Chip buffer modeling method, system, device and circuit

Abstract

The application discloses a chip buffer modeling method, system, device and circuit, obtains a measured output waveform of a chip to be modeled, and takes the measured output waveform as a simulation voltage source; obtains an actual output impedance of the chip to be modeled, and takes the actual output impedance as an impedance value of a simulation output resistance; establishes a buffer model of the chip to be modeled according to the simulation voltage source and the simulation output resistance; and the simulation output resistance in the buffer model is connected to an output end of the simulation voltage source. It can be seen that the application can establish a chip buffer model based on chip measured parameters in the case of lacking a chip model, thereby ensuring that simulation work is smoothly carried out, and helping to improve the PCB design effect; moreover, the chip buffer model established based on the chip measured parameters has a smaller difference from an actual chip buffer and higher accuracy; in addition, the chip buffer model has a simple structure and is easy to obtain, and compared with a complex model provided by a manufacturer, the complexity of model verification is lower.

Description

Technical Field

[0001] This invention relates to the field of PCB simulation, and in particular to a chip buffer modeling method, system, device and circuit. Background Technology

[0002] With the increase in signal speed, signal integrity has become an essential aspect of PCB (Printed Circuit Board) design. Currently, PCB simulation technology is commonly used to determine the signal integrity of PCB designs. Specifically, after the PCB design is completed, various models corresponding to the PCB design are added and simulated to generate signal waveforms. By measuring these waveforms, it is determined whether the PCB design meets signal integrity requirements.

[0003] In the simulation phase, various models of active and passive components are usually required. Passive components can be modeled using test modeling or 3D software, while active components such as chips usually require chip models to be provided by the manufacturer. However, in some cases, the manufacturer cannot provide chip models, which makes the simulation work impossible due to the lack of models, thus affecting the PCB design results.

[0004] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that those skilled in the art need to solve at present. Summary of the Invention

[0005] The purpose of this invention is to provide a chip buffer modeling method, system, device, and circuit. In the absence of a chip model, a buffer model of the chip to be modeled can be automatically established based on the measured parameters of the chip to be modeled, thereby ensuring the smooth progress of simulation and helping to improve the PCB design effect. Moreover, the chip buffer model established based on the measured parameters of the chip has little difference from the actual chip buffer and has high accuracy. In addition, the chip buffer model of this application has a simple structure, is easy to obtain, and has lower model verification complexity compared to the complex models provided by manufacturers.

[0006] To address the aforementioned technical problems, this invention provides a chip buffer modeling method, comprising:

[0007] Obtain the measured output waveform of the chip to be modeled, and use the measured output waveform as the simulation voltage source;

[0008] Obtain the actual output impedance of the chip to be modeled, and use the actual output impedance as the impedance value of the simulated output resistance;

[0009] A buffer model of the chip to be modeled is established based on the simulated voltage source and the simulated output resistor; wherein, in the buffer model, the simulated output resistor is connected to the output terminal of the simulated voltage source. Preferably, the process of obtaining the measured output waveform of the chip to be modeled and using the measured output waveform as the simulated voltage source includes:

[0010] The output voltage of the chip to be modeled is measured with the first grounding resistor connected to the output terminal to obtain the output voltage waveform of the chip to be modeled; wherein, the resistance value of the first grounding resistor is greater than a preset open circuit resistance threshold.

[0011] Each voltage value of the output voltage waveform is saved with a certain step size, and the saved output voltage waveform is used as a simulation voltage source.

[0012] Preferably, the process of obtaining the actual output impedance of the chip to be modeled includes:

[0013] The output voltage of the chip to be modeled, which has a second grounding resistor connected to its output terminal, is measured to obtain the voltage value Vx;

[0014] According to the preset pressure division relationship Vx=R GND *Vh / (R+R GND The output impedance R of the chip to be modeled is obtained; where Vh is the supply voltage of the chip to be modeled; R GND The value of the second grounding resistor is given.

[0015] Preferably, the buffer model of the chip to be modeled further includes an RLC circuit connected to the output terminal of the simulated output resistor;

[0016] Accordingly, the chip buffer modeling method further includes:

[0017] The initial values ​​of each circuit parameter in the RLC circuit are determined according to the range of values ​​of each circuit parameter in the RLC circuit.

[0018] Based on the initial values ​​of each circuit parameter of the RLC circuit, the buffer model of the chip to be modeled is simulated to obtain the simulation waveform of the chip to be modeled.

[0019] The circuit parameter values ​​of the RLC circuit are optimized based on the fitting error between the simulated waveform and the measured output waveform, and the final optimized circuit parameter values ​​are used as the simulated values ​​of the circuit parameters of the RLC circuit.

[0020] Preferably, the process of optimizing the circuit parameter values ​​of the RLC circuit based on the fitting error between the simulated waveform and the measured output waveform, and using the final optimized circuit parameter values ​​as the simulated values ​​of the circuit parameters of the RLC circuit, includes:

[0021] Determine whether the fitting error between the simulated waveform and the measured output waveform is less than a preset error threshold;

[0022] If the error is less than the preset error threshold, the current circuit parameter values ​​of the RLC circuit will be used as the simulation values ​​of the circuit parameters of the RLC circuit.

[0023] If the error is not less than the preset error threshold, then it is determined whether all circuit parameters of the RLC circuit have been traversed within their value range.

[0024] If not all circuit parameters are traversed, the values ​​of each circuit parameter in the RLC circuit are reselected within the range of values ​​of each circuit parameter in the RLC circuit. Based on the reselected circuit parameter values, the buffer model of the chip to be modeled is simulated. Then, the step of judging whether the fitting error between the simulated waveform and the measured output waveform is less than the preset error threshold is re-executed.

[0025] If all iterations are completed, the circuit parameter values ​​of the RLC circuit corresponding to the simulation waveform with the smallest fitting error are taken as the simulation values ​​of the circuit parameters of the RLC circuit.

[0026] Preferably, before optimizing the circuit parameter values ​​of the RLC circuit based on the fitting error between the simulated waveform and the measured output waveform, the chip buffer modeling method further includes:

[0027] The measured output waveform is subjected to median filtering so that the filtered measured output waveform can be used as the measured output waveform for calculating the fitting error with the simulated waveform.

[0028] To address the aforementioned technical problems, the present invention also provides a chip buffer modeling system, comprising:

[0029] The waveform acquisition module is used to acquire the measured output waveform of the chip to be modeled, and use the measured output waveform as a simulation voltage source;

[0030] The impedance acquisition module is used to acquire the actual output impedance of the chip to be modeled and use the actual output impedance as the impedance value of the simulated output resistance.

[0031] A model building module is used to build a buffer model of the chip to be modeled based on the simulated voltage source and the simulated output resistor; wherein, in the buffer model, the simulated output resistor is connected to the output terminal of the simulated voltage source. To solve the above technical problems, the present invention also provides a chip buffer modeling device, comprising:

[0032] Memory, used to store computer programs;

[0033] A processor for implementing the steps of any of the above-described chip buffer modeling methods when executing the computer program.

[0034] To address the aforementioned technical problems, the present invention also provides a chip buffer modeling circuit, comprising:

[0035] Simulated voltage source;

[0036] The simulated output resistor is connected to the output terminal of the simulated voltage source;

[0037] An RLC circuit is connected to the output terminal of the simulated output resistor; wherein, the circuit parameter values ​​of the chip buffer modeling circuit are set using the chip buffer modeling method described above.

[0038] This invention provides a chip buffer modeling method. The method involves acquiring the measured output waveform of the chip to be modeled and using it as a simulated voltage source; acquiring the actual output impedance of the chip to be modeled and using it as the impedance value of the simulated output resistance; and establishing a buffer model of the chip to be modeled based on the simulated voltage source and simulated output resistance. In the buffer model, the simulated output resistance is connected to the output terminal of the simulated voltage source. Therefore, even in the absence of a chip model, this invention can automatically establish a buffer model of the chip to be modeled based on the measured parameters of the chip, thus ensuring the smooth progress of simulation and improving PCB design. Furthermore, the chip buffer model established based on the measured parameters of the chip has minimal difference from the actual chip buffer and high accuracy. In addition, the chip buffer model of this invention has a simple structure, is easy to obtain, and has lower model verification complexity compared to complex models provided by manufacturers.

[0039] The present invention also provides a chip buffer modeling system, apparatus and circuit, which have the same beneficial effects as the chip buffer modeling method described above. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A flowchart illustrating a chip buffer modeling method provided in an embodiment of the present invention;

[0042] Figure 2a A schematic diagram of a simplified chip buffer circuit for high-level output provided in an embodiment of the present invention;

[0043] Figure 2bA schematic diagram of a simplified chip buffer circuit for low-level output provided in an embodiment of the present invention;

[0044] Figure 3 A simplified diagram of a chip buffer model provided in an embodiment of the present invention;

[0045] Figure 4 A schematic diagram of a simplified circuit based on a chip buffer for obtaining the output impedance of a chip, provided for an embodiment of the present invention;

[0046] Figure 5 A simplified diagram of another chip buffer model provided in an embodiment of the present invention;

[0047] Figure 6 A flowchart illustrating optimized circuit parameters for an RLC circuit, provided as an embodiment of the present invention;

[0048] Figure 7 A comparison diagram of the simulated waveform and the measured output waveform of a chip buffer model before adding an RLC circuit, provided for an embodiment of the present invention;

[0049] Figure 8 This is a comparison diagram of the simulation waveform and the measured output waveform of a chip buffer model after adding an RLC circuit, provided in an embodiment of the present invention. Detailed Implementation

[0050] The core of this invention is to provide a chip buffer modeling method, system, device, and circuit. In the absence of a chip model, a buffer model of the chip to be modeled can be automatically established based on the measured parameters of the chip to be modeled, thereby ensuring the smooth progress of simulation and helping to improve the PCB design effect. Moreover, the chip buffer model established based on the measured parameters of the chip has little difference from the actual chip buffer and has high accuracy. In addition, the chip buffer model of this application has a simple structure, is easy to obtain, and has lower model verification complexity compared to the complex models provided by manufacturers.

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] Please refer to Figure 1 , Figure 1 This is a flowchart of a chip buffer modeling method provided in an embodiment of the present invention.

[0053] The chip buffer modeling method includes:

[0054] Step S1: Obtain the measured output waveform of the chip to be modeled, and use the measured output waveform as the simulation voltage source;

[0055] Step S2: Obtain the actual output impedance of the chip to be modeled, and use the actual output impedance as the impedance value of the simulated output resistance;

[0056] Step S3: Establish a buffer model of the chip to be modeled based on the simulated voltage source and simulated output resistance.

[0057] It should be noted that the order of steps S1 and S2 can be interchanged, and this application does not impose any special restrictions on this.

[0058] Specifically, please refer to Figure 2a and Figure 2b , Figure 2a A schematic diagram of a simplified chip buffer circuit for high-level output provided in an embodiment of the present invention; Figure 2b This invention provides a schematic diagram of a simplified chip buffer circuit for low-level output. Analyzing the chip's physical structure, the simplified chip buffer circuit consists of an upper switch M1 (such as a MOSFET) and a lower switch M2. By controlling the on / off state of the upper and lower switches M1 and M2, the chip output can switch between high and low levels, thus enabling signal transmission. Specifically, when the upper switch M1 is on and the lower switch M2 is off, current flows from the chip's power supply to the chip's output terminal, switching the chip's output level from low to high, thus achieving a rising edge effect. When the upper switch M1 is off and the lower switch M2 is on, current flows from the chip's output terminal to the ground plane, switching the chip's output level from high to low, thus achieving a falling edge effect. From the perspective of the transmission line, the chip buffer output is similar to a signal source with an output impedance. To ensure signal integrity, the chip's output impedance must be equal to the characteristic impedance of the transmission line to achieve impedance matching. From the perspective of output impedance, the chip buffer is similar to a voltage source with an output resistor.

[0059] Based on the above assumptions, this application specifically represents the buffer model of the chip to be modeled as a voltage source plus an output resistor, such as... Figure 3 As shown, these are referred to as the simulation voltage source V and the simulation output resistor R, respectively. Next, we need to determine the specific parameter values ​​of the simulation voltage source V and the simulation output resistor R in order to simulate the output characteristics of the chip to be modeled.

[0060] More specifically, the specific parameter values ​​of the simulated voltage source V and the simulated output resistor R are determined as follows: The actual output waveform of the chip to be modeled is measured to obtain the measured output waveform of the chip. This measured output waveform can then be used as the simulated voltage source V within the buffer model of the chip to be modeled. Based on the voltage divider principle, the actual output impedance of the chip to be modeled can be calculated. This actual output impedance can then be used as the impedance value of the simulated output resistor R within the buffer model of the chip to be modeled. Based on this, after determining the specific parameter values ​​of the simulated voltage source V and the simulated output resistor R, the buffer model of the chip to be modeled can be obtained.

[0061] This invention provides a chip buffer modeling method. The method involves acquiring the measured output waveform of the chip to be modeled and using it as a simulated voltage source; acquiring the actual output impedance of the chip to be modeled and using it as the impedance value of the simulated output resistance; and establishing a buffer model of the chip to be modeled based on the simulated voltage source and simulated output resistance. In the buffer model, the simulated output resistance is connected to the output terminal of the simulated voltage source. Therefore, even in the absence of a chip model, this invention can automatically establish a buffer model of the chip to be modeled based on the measured parameters of the chip, thus ensuring the smooth progress of simulation and improving PCB design. Furthermore, the chip buffer model established based on the measured parameters of the chip has minimal difference from the actual chip buffer and high accuracy. In addition, the chip buffer model of this invention has a simple structure, is easy to obtain, and has lower model verification complexity compared to complex models provided by manufacturers.

[0062] Based on the above embodiments:

[0063] As an optional embodiment, the process of acquiring the measured output waveform of the chip to be modeled and using the measured output waveform as a simulation voltage source includes:

[0064] The output voltage of the chip to be modeled is measured with the first grounding resistor connected to the output terminal to obtain the output voltage waveform of the chip to be modeled; wherein, the resistance value of the first grounding resistor is greater than the preset open circuit resistance threshold.

[0065] Each voltage value of the output voltage waveform is saved with a certain step size, and the saved output voltage waveform is used as a simulation voltage source.

[0066] Specifically, the method used in this application to measure the actual output waveform of the chip to be modeled is as follows: a first grounding resistor (meg ohm level) with a resistance value greater than a preset open-circuit resistance threshold is connected to the output terminal of the chip to be modeled. In other words, the output terminal of the chip to be modeled is equivalent to an open circuit. Then, the output voltage at the output terminal of the chip to be modeled is measured using a voltage measurement tool, thereby obtaining the actual output voltage waveform of the chip to be modeled. At the same time, each voltage value of the actual output voltage waveform of the chip to be modeled is saved with a certain step size. That is, the currently measured output voltage of the chip to be modeled is saved at regular intervals, thereby using the saved output voltage waveform as the simulation voltage source V inside the buffer model of the chip to be modeled.

[0067] As an optional embodiment, the process of obtaining the actual output impedance of the chip to be modeled includes:

[0068] The output voltage of the chip to be modeled, which has a second grounding resistor connected to its output terminal, is measured to obtain the voltage value Vx;

[0069] According to the preset pressure division relationship Vx=R GND *Vh / (R+R GND The output impedance R of the chip to be modeled is obtained; where Vh is the supply voltage of the chip to be modeled; R GND This is the resistance value of the second grounding resistor.

[0070] Specifically, this application obtains the actual output impedance of the chip to be modeled in the following way: Figure 4 As shown, a second grounding resistor R with a small resistance is connected to the output terminal of the chip to be modeled. GND (e.g., 50 ohms), and then use a voltage measuring tool to measure the output voltage at the output terminal of the chip to be modeled, to obtain the voltage value Vx, which is also the second grounding resistance R. GND The voltage across the two ends. According to the voltage divider principle, (supply voltage Vh of the chip to be modeled - voltage value Vx) / output impedance R of the chip to be modeled = voltage value Vx / resistance value R of the second grounding resistor. GND It is understandable that the output impedance R of the chip to be modeled is the on-resistance of the switching transistor M1 on the chip, based on the supply voltage Vh, voltage value Vx, and resistance R of the second grounding resistor of the chip to be modeled. GND All of these are known quantities. The output impedance R of the chip to be modeled can be calculated based on the above relationship, which gives the impedance value of the simulated output resistance inside the buffer model of the chip to be modeled.

[0071] As an optional embodiment, the buffer model of the chip to be modeled also includes an RLC circuit connected to the output terminal of the simulated output resistor;

[0072] Correspondingly, chip buffer modeling methods also include:

[0073] Determine the initial values ​​of each circuit parameter in the RLC circuit based on the range of values ​​of each circuit parameter in the RLC circuit;

[0074] Based on the initial values ​​of each circuit parameter of the RLC circuit, the buffer model of the chip to be modeled is simulated to obtain the simulation waveform of the chip to be modeled.

[0075] The circuit parameter values ​​of the RLC circuit are optimized based on the fitting error between the simulated waveform and the measured output waveform, and the final optimized circuit parameter values ​​are used as the simulated values ​​of the circuit parameters of the RLC circuit.

[0076] Furthermore, chip packaging can also cause changes in output parameters, requiring a more accurate chip buffer model in addition to... Figure 3 The simulation voltage source V shown here, along with a simulation output resistor R, should also include an RLC circuit, as shown below. Figure 5 As shown, the RLC circuit includes capacitor C_comp, resistor R_pkg, inductor L_pkg, and capacitor C_pkg. Next, it is necessary to determine the specific parameter values ​​of each circuit parameter of the RLC circuit in order to more accurately simulate the output characteristics of the chip to be modeled.

[0077] Specifically, the specific parameter values ​​of each circuit parameter in the RLC circuit are determined as follows: 1) A value range is set in advance for each circuit parameter in the RLC circuit. For example, the value range of capacitor C_comp is 0.5pF–15pF, the value range of resistor R_pkg is 50mohm–1000mohm, the value range of inductor L_pkg is 0.5nH–20nH, and the value range of capacitor C_pkg is 0.5pF–10pF. 2) From the value range of each circuit parameter in the RLC circuit, an initial value is selected for each circuit parameter of the RLC circuit. Then, based on the initial values ​​of each circuit parameter of the RLC circuit and the specific parameter values ​​of the simulation voltage source V and the simulation output resistor R determined in the above embodiment, the buffer model of the chip to be modeled is simulated to obtain the simulation waveform of the chip to be modeled. 3) It is understood that the measured output waveform of the chip to be modeled is the target waveform that the simulated waveform of the chip to be modeled needs to achieve. In other words, the closer the simulated waveform of the chip to be modeled is to the measured output waveform of the chip to be modeled, the higher the accuracy of the buffer model of the chip to be modeled. Therefore, this application optimizes the circuit parameter values ​​of the RLC circuit based on the fitting error between the simulated waveform and the measured output waveform of the chip to be modeled, with the aim of improving the accuracy of the buffer model of the chip to be modeled. Then, the final optimized circuit parameter values ​​are used as the simulated values ​​of the circuit parameters of the RLC circuit.

[0078] As an optional embodiment, the process of optimizing the circuit parameter values ​​of the RLC circuit based on the fitting error between the simulated waveform and the measured output waveform, and using the final optimized circuit parameter values ​​as the simulated values ​​of the circuit parameters of the RLC circuit, includes:

[0079] Determine whether the fitting error between the simulated waveform and the measured output waveform is less than a preset error threshold;

[0080] If the error is less than the preset error threshold, the current circuit parameter values ​​of the RLC circuit will be used as the simulation values ​​of the circuit parameters of the RLC circuit.

[0081] If the error is not less than the preset error threshold, then determine whether all circuit parameters of the RLC circuit have been traversed within their value range.

[0082] If not all circuit parameters are traversed, the values ​​of each circuit parameter in the RLC circuit are reselected within the range of values ​​of each circuit parameter in the RLC circuit. Based on the reselected circuit parameter values, the buffer model of the chip to be modeled is simulated. Then, the step of judging whether the fitting error between the simulated waveform and the measured output waveform is less than the preset error threshold is re-executed.

[0083] If all iterations are completed, the circuit parameter values ​​of the RLC circuit corresponding to the simulation waveform with the smallest fitting error will be used as the simulation values ​​of the circuit parameters of the RLC circuit.

[0084] Specifically, please refer to Figure 6 , Figure 6This document provides a flowchart for optimizing the circuit parameters of an RLC circuit according to an embodiment of the present invention. The specific optimization process for the RLC circuit parameters is as follows: 1) Import the measured output waveform of the chip to be modeled. 2) Select an initial value for each circuit parameter of the RLC circuit from the range of values ​​of each circuit parameter in the RLC circuit. Then, based on the initial values ​​of each circuit parameter of the RLC circuit and the specific parameter values ​​of the simulation voltage source V and the simulation output resistance R determined in the above embodiment, simulate the buffer model of the chip to be modeled to obtain the simulation waveform of the chip to be modeled. 3) Use the least squares method to fit the simulation waveform of the chip to be modeled and its measured output waveform to obtain the fitting error between the simulation waveform and the measured output waveform of the chip to be modeled. 4) Determine if the fitting error between the simulated waveform and the measured output waveform of the chip to be modeled is less than a preset error threshold (e.g., 0.05). If it is less than the preset error threshold, it means that the accuracy of the buffer model of the chip to be modeled meets the requirements under this condition. Then, use the current circuit parameter values ​​of the RLC circuit as the simulated values ​​of each circuit parameter of the RLC circuit, i.e., the optimization of the circuit parameters of the RLC circuit is complete. If it is not less than the preset error threshold, it means that the accuracy of the buffer model of the chip to be modeled still does not meet the requirements under this condition. Then, determine if all circuit parameters of the RLC circuit have been traversed within their value range. If not... Once the traversal is complete, within the range of values ​​for each circuit parameter in the RLC circuit, the values ​​of each circuit parameter in the RLC circuit are reselected. Based on the reselected circuit parameter values, the buffer model of the chip to be modeled is simulated to obtain the simulation waveform of the chip to be modeled. Then, the least squares method is used again to fit the simulation waveform and the actual measured output waveform of the chip to be modeled, and subsequent steps are performed. If the traversal is complete, the circuit parameter values ​​of the RLC circuit corresponding to the simulation waveform with the smallest fitting error are taken as the simulation values ​​of each circuit parameter of the RLC circuit, that is, the optimization of the circuit parameters of the RLC circuit is completed.

[0085] As an optional embodiment, before optimizing the circuit parameter values ​​of the RLC circuit based on the fitting error between the simulated waveform and the measured output waveform, the chip buffer modeling method further includes:

[0086] The measured output waveform is subjected to median filtering so that the filtered measured output waveform can be used as the measured output waveform for calculating the fitting error with the simulated waveform.

[0087] Furthermore, such as Figure 6 As shown, this application can first perform median filtering on the measured output waveform before obtaining the fitting error between the simulation waveform and the measured output waveform of the chip to be modeled, so as to filter out the noise signal doped during the measurement process. Then, the fitting error between the filtered measured output waveform and the simulation waveform is calculated, thereby improving the accuracy of parameter optimization of RLC circuit.

[0088] In summary, please refer to Figure 7, Figure 7 This image shows a comparison of the simulated waveform and the measured output waveform of a chip buffer model provided in an embodiment of the present invention before the addition of an RLC circuit. Figure 7 It can be seen that for the chip buffer model without RLC circuitry, the simulation waveform and the measured output waveform have poor amplitude matching at the waveform edges for overshoot. Please refer to... Figure 8 , Figure 8 This image shows a comparison between the simulated and measured output waveforms of a chip buffer model provided in an embodiment of the present invention after adding an RLC circuit. Figure 8 It can be seen that the chip buffer model with added RLC circuitry shows better fit between the simulated and measured output waveforms at the edges compared to the previous model without RLC circuitry. Therefore, to improve the accuracy of the chip buffer model, RLC circuitry needs to be considered. It should be noted that... Figure 8 The simulated waveforms were obtained after RLC parameter optimization, and they show a high degree of agreement with the measured output waveforms, meeting the accuracy requirements of engineering design. Moreover, the chip buffer modeling method of this application not only has a certain theoretical basis, but also proves to be practically feasible from a practical perspective.

[0089] This application also provides a chip buffer modeling system, including:

[0090] The waveform acquisition module is used to acquire the measured output waveform of the chip to be modeled and use the measured output waveform as the simulation voltage source.

[0091] The impedance acquisition module is used to acquire the actual output impedance of the chip to be modeled and use the actual output impedance as the impedance value of the simulated output resistance.

[0092] The model building module is used to build a buffer model of the chip to be modeled based on the simulated voltage source and the simulated output resistor; wherein, the simulated output resistor in the buffer model is connected to the output terminal of the simulated voltage source.

[0093] For a description of the chip buffer modeling system provided in this application, please refer to the embodiments of the chip buffer modeling method described above; further details will not be repeated here.

[0094] This application also provides a chip buffer modeling apparatus, including:

[0095] Memory, used to store computer programs;

[0096] A processor is used to implement the steps of any of the above-described chip buffer modeling methods when executing a computer program.

[0097] For a description of the chip buffer modeling apparatus provided in this application, please refer to the embodiments of the chip buffer modeling method described above; further details will not be repeated here.

[0098] This application also provides a chip buffer modeling circuit, including:

[0099] Simulated voltage source;

[0100] The simulated output resistor connected to the output terminal of the simulated voltage source;

[0101] An RLC circuit is connected to the output terminal of the simulation output resistor; wherein, the circuit parameter values ​​of the chip buffer modeling circuit are set using the chip buffer modeling method described above.

[0102] For a description of the chip buffer modeling circuit provided in this application, please refer to the embodiments of the chip buffer modeling method described above; further details will not be repeated here.

[0103] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0104] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip buffer modeling method, characterized in that, include: The process of obtaining the measured output waveform of the chip to be modeled and using the measured output waveform as a simulation voltage source includes: measuring the output voltage of the chip to be modeled with a first grounding resistor connected to its output terminal to obtain the output voltage waveform of the chip to be modeled; wherein the resistance value of the first grounding resistor is greater than a preset open-circuit resistance threshold; saving each voltage value of the output voltage waveform with a certain step size, and using the saved output voltage waveform as a simulation voltage source. The actual output impedance of the chip to be modeled is obtained, and this actual output impedance is used as the impedance value of the simulated output resistance. The process of obtaining the actual output impedance of the chip to be modeled includes: measuring the output voltage of the chip to be modeled with a second grounding resistor connected to its output terminal, obtaining a voltage value Vx; where Vx is the voltage across the second grounding resistor; and applying the preset voltage divider formula Vx=R... GND *Vh / (R+R GND The output impedance R of the chip to be modeled is obtained; where Vh is the supply voltage of the chip to be modeled; R GND The resistance value of the second grounding resistor; A buffer model of the chip to be modeled is established based on the simulated voltage source and the simulated output resistor; wherein, in the buffer model, the simulated output resistor is connected to the output terminal of the simulated voltage source.

2. The chip buffer modeling method as described in claim 1, characterized in that, The buffer model of the chip to be modeled also includes an RLC circuit connected to the output terminal of the simulated output resistor. Accordingly, the chip buffer modeling method further includes: The initial values ​​of each circuit parameter in the RLC circuit are determined according to the range of values ​​of each circuit parameter in the RLC circuit. Based on the initial values ​​of each circuit parameter of the RLC circuit, the buffer model of the chip to be modeled is simulated to obtain the simulation waveform of the chip to be modeled. The circuit parameter values ​​of the RLC circuit are optimized based on the fitting error between the simulated waveform and the measured output waveform, and the final optimized circuit parameter values ​​are used as the simulated values ​​of the circuit parameters of the RLC circuit.

3. The chip buffer modeling method as described in claim 2, characterized in that, The process of optimizing the circuit parameter values ​​of the RLC circuit based on the fitting error between the simulated waveform and the measured output waveform, and using the final optimized circuit parameter values ​​as the simulated circuit parameter values ​​of the RLC circuit, includes: Determine whether the fitting error between the simulated waveform and the measured output waveform is less than a preset error threshold; If the error is less than the preset error threshold, the current circuit parameter values ​​of the RLC circuit will be used as the simulation values ​​of the circuit parameters of the RLC circuit.

4. The chip buffer modeling method as described in claim 3, characterized in that, Determining whether the fitting error between the simulated waveform and the measured output waveform is less than a preset error threshold further includes: If the error is not less than the preset error threshold, then it is determined whether all circuit parameters of the RLC circuit have been traversed within their value range. If not all circuit parameters are traversed, the values ​​of each circuit parameter in the RLC circuit are reselected within the range of values ​​of each circuit parameter in the RLC circuit. Based on the reselected circuit parameter values, the buffer model of the chip to be modeled is simulated. Then, the step of judging whether the fitting error between the simulated waveform and the measured output waveform is less than the preset error threshold is re-executed. If all iterations are completed, the circuit parameter values ​​of the RLC circuit corresponding to the simulation waveform with the smallest fitting error are taken as the simulation values ​​of the circuit parameters of the RLC circuit.

5. The chip buffer modeling method as described in claim 2, characterized in that, Before optimizing the circuit parameter values ​​of the RLC circuit based on the fitting error between the simulated waveform and the measured output waveform, the chip buffer modeling method further includes: The measured output waveform is subjected to median filtering so that the filtered measured output waveform can be used as the measured output waveform for calculating the fitting error with the simulated waveform.

6. A chip buffer modeling system, characterized in that, include: The waveform acquisition module is used to acquire the measured output waveform of the chip to be modeled, and use the measured output waveform as a simulation voltage source; The process of obtaining the measured output waveform of the chip to be modeled and using the measured output waveform as a simulation voltage source includes: measuring the output voltage of the chip to be modeled with a first grounding resistor connected to its output terminal to obtain the output voltage waveform of the chip to be modeled; wherein the resistance value of the first grounding resistor is greater than a preset open circuit resistance threshold; saving each voltage value of the output voltage waveform with a certain step size, and using the saved output voltage waveform as a simulation voltage source; An impedance acquisition module is used to acquire the actual output impedance of the chip to be modeled and use the actual output impedance as the impedance value of the simulated output resistance. Specifically, the impedance acquisition module is used to: measure the output voltage of the chip to be modeled with a second grounding resistor connected to its output terminal, obtaining a voltage value Vx; Vx is the voltage across the second grounding resistor; according to a preset voltage divider relationship Vx=R... GND *Vh / (R+R GND The output impedance R of the chip to be modeled is obtained; where Vh is the supply voltage of the chip to be modeled; R GND The resistance value of the second grounding resistor; The model building module is used to build a buffer model of the chip to be modeled based on the simulated voltage source and the simulated output resistor; wherein, in the buffer model, the simulated output resistor is connected to the output terminal of the simulated voltage source.

7. A chip buffer modeling apparatus, characterized in that, include: Memory, used to store computer programs; A processor for implementing the steps of the chip buffer modeling method as described in any one of claims 1-5 when executing the computer program.

8. A chip buffer modeling circuit, characterized in that, include: Simulated voltage source; The simulated output resistor is connected to the output terminal of the simulated voltage source; An RLC circuit connected to the output terminal of the simulated output resistor; wherein, the circuit parameter values ​​of the chip buffer modeling circuit are set using the chip buffer modeling method as described in any one of claims 2-5.

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