A layout and routing method, device, equipment and readable storage medium

Abstract

The present application discloses a layout and routing method, apparatus, device, and readable storage medium. For a functional module whose data processing logic matches the star topology structure, the present application can use constraint methods with different constraint capabilities to constrain each sub-module in the functional module to perform layout and routing according to the star topology structure, obtain various layout and routing results, and then select a layout and routing result that meets the requirements of preset indicators from the various layout and routing results as the layout and routing scheme of the functional module, which can simplify the layout and routing inside the module, reduce the probability of problems such as wire congestion, short circuit, time delay, and functional errors, save wire resources, chip power consumption, and chip area, and can also select a layout and routing scheme that meets the requirements of preset indicators. Therefore, it can improve the performance, manufacturability, and timing convergence effect of the chip. Correspondingly, a layout and routing apparatus, device, and readable storage medium provided by the present application also have the above technical effects.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly to a layout and routing method, device, equipment, and readable storage medium. Background Art

[0002] Currently, the routing method for functional modules with complex data interaction logic usually has the following problems: The wire winding inside the module is congested, and problems such as short circuits and time delays are likely to occur, and the line resources are tense. Therefore, it is easy to cause functional errors and increase the chip power consumption. If an EDA tool is used to solve the wire winding problem, a certain chip area will be sacrificed.

[0003] Therefore, how to simplify the layout and routing of functional modules with complex data interaction logic is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a layout and routing method, device, equipment, and readable storage medium to simplify the layout and routing of functional modules with complex data interaction logic. The specific solutions are as follows:

[0005] In the first aspect, this application provides a layout and routing method, including:

[0006] Determine the data processing logic between each sub-module in any functional module in the chip;

[0007] If the data processing logic matches the star topology structure, use constraint methods with different constraint capabilities to constrain each sub-module in the functional module to perform layout and routing according to the star topology structure, and obtain the layout and routing results corresponding to each constraint method;

[0008] Select the layout and routing result that meets the preset index requirements from each layout and routing result as the layout and routing scheme of the functional module.

[0009] Preferably, the step of using constraint methods with different constraint capabilities to constrain each sub-module in the functional module to perform layout and routing according to the star topology structure, and obtaining the layout and routing results corresponding to each constraint method includes:

[0010] According to the data processing logic, determine the target sub-module that needs to be set at the center position of the star topology structure and other sub-modules that need to be set around the center position among each sub-module in the functional module;

[0011] Based on each constraint method, constrain the target sub-module at the center position, constrain the other sub-modules around the center position, and perform wiring between each sub-module to obtain the layout and routing result corresponding to each constraint method.

[0012] Preferably, before constraining the target sub-module at the central position and constraining the other sub-modules around the central position, the method further includes:

[0013] Allocating corresponding layout spaces of appropriate sizes to the sub-modules in the functional module according to the number of units included in each sub-module in the functional module.

[0014] Preferably, the constraint methods with different constraint capabilities are: soft bound, bound, hard bound and / or exclude bound in the EDA tool.

[0015] Preferably, the step of selecting a layout and routing result that meets the preset index requirements from each layout and routing result as the layout and routing scheme of the functional module includes:

[0016] Testing the timing information and / or routing congestion degree of each layout and routing result respectively;

[0017] If the timing information and / or routing congestion degree of any layout and routing result meets the preset index requirements, then using this layout and routing result as the layout and routing scheme of the functional module.

[0018] Preferably, the method further includes:

[0019] If there are multiple layout and routing results that meet the preset index requirements, then selecting the layout and routing result with the optimal timing information and / or routing congestion degree from the multiple layout and routing results that meet the preset index requirements as the layout and routing scheme of the functional module.

[0020] Preferably, after selecting a layout and routing result that meets the preset index requirements from each layout and routing result as the layout and routing scheme of the functional module, the method further includes:

[0021] Visualizing and displaying the layout and routing scheme by using an EDA tool.

[0022] In a second aspect, the present application provides a layout and routing device, including:

[0023] A determination module, configured to determine the data processing logic between the sub-modules in any functional module in the chip;

[0024] A layout and routing module, configured to, if the data processing logic matches the star topology structure, use constraint methods with different constraint capabilities to constrain the sub-modules in the functional module to perform layout and routing according to the star topology structure, and obtain layout and routing results respectively corresponding to each constraint method;

[0025] A selection module, configured to select a layout and routing result that meets the requirements of a preset metric from each layout and routing result as the layout and routing scheme of the functional module.

[0026] In a third aspect, the present application provides an electronic device, including:

[0027] A memory, configured to store a computer program;

[0028] A processor, configured to execute the computer program to implement the layout and routing method disclosed above.

[0029] In a fourth aspect, the present application provides a readable storage medium, configured to save a computer program, wherein the computer program, when executed by a processor, implements the layout and routing method disclosed above.

[0030] As can be seen from the above solutions, the present application provides a layout and routing method, including: determining the data processing logic between each sub-module in any functional module in a chip; if the data processing logic matches a star topology structure, using constraint methods with different constraint capabilities to constrain each sub-module in the functional module to perform layout and routing according to the star topology structure to obtain layout and routing results respectively corresponding to each constraint method; selecting a layout and routing result that meets the requirements of a preset metric from each layout and routing result as the layout and routing scheme of the functional module.

[0031] It can be seen that for such a functional module whose data processing logic matches a star topology structure, the present application can use constraint methods with different constraint capabilities to constrain each sub-module in the functional module to perform layout and routing according to the star topology structure to obtain layout and routing results respectively corresponding to each constraint method, and then select a layout and routing result that meets the requirements of a preset metric from each layout and routing result as the layout and routing scheme of the functional module. This can not only simplify the layout and routing according to the star topology structure, but also select a layout and routing scheme with better performance that meets the requirements of a preset metric from multiple layout and routing results, thus ensuring the usability of the layout and routing scheme. Since the star topology structure matches the data processing logic between each sub-module in the functional module, layout and routing based on this can reduce wire routing, solve the problem of wire routing congestion inside the module, reduce the probability of problems such as short circuits, time delays, and functional errors, and also save wire resources, chip power consumption, and chip area, and can improve the performance, manufacturability, and timing convergence effect of the chip.

[0032] Correspondingly, a layout and routing device, device, and readable storage medium provided by the present application also have the above technical effects. Description of the Drawings

[0033] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0034] Figure 1 It is a flowchart of a layout and routing method disclosed in the present application;

[0035] Figure 2 It is a schematic diagram of the result of a layout and routing disclosed in the present application;

[0036] Figure 3 It is another schematic diagram of the result of a layout and routing disclosed in the present application;

[0037] Figure 4 It is a schematic diagram of a layout and routing device disclosed in the present application;

[0038] Figure 5 It is a schematic diagram of an electronic device disclosed in the present application. Specific embodiments

[0039] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of them. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0040] To introduce the present application more clearly, the following is the technical background of the present application.

[0041] The present application optimizes the chip design layout. The physical implementation of chip design is usually simply referred to as layout and routing (P&R, Place-and-Route). After layout and routing, continue with steps such as timing convergence, power consumption analysis, and manufacturability analysis of the chip, and finally convert the integrated netlist into a file format for production and manufacturing. Among them, timing convergence can ensure that the chip can achieve the ideal performance in the required working environment. It predicts the working frequency of the chip under various conditions through means such as static timing analysis, and at the same time achieves path optimization with the help of constraint and optimization engines, ultimately realizing the increase of the main frequency so that the chip can work at the required frequency. The result of power consumption analysis reflects the power consumption of the chip, the distribution of voltage drop and current inside the chip, and also reflects the stability of the chip's operation.

[0042] Of course, only by controlling parameters such as the power consumption, voltage drop, and electromigration of the chip within a certain range can a manufacturable chip be designed, which plays a certain positive role in improving the yield rate, reducing production costs, and increasing product profits.

[0043] In the physical design of a chip, floorplanning and placement play an important role in chip design. Whether it is reasonable or not directly affects timing convergence, smooth routing, power supply stability, and yield rate. In the entire chip design process, from floorplanning to completing placement generally takes about one-third of the entire physical implementation time. The quality of floorplanning and placement directly determines the quality of the chip.

[0044] In some individual modules in the chip (such as the switch module of a server chip), the data interaction is complex, and the data flow shuttles back and forth due to functional requirements, making it inevitable to have wire routing detours. As Figure 2 shown, A1 - A8 are scattered in various places within the module, and the wire routing will shuttle around according to the positions of A1 - A8, which will inevitably occupy a large amount of wire routing resources, causing a shortage of wire routing resources and a large number of short circuits.

[0045] If we rely on EDA tools to handle the wire routing congestion problem, we need to sacrifice area. And if we increase the area occupied by the module in the chip, it will increase timing violations and power consumption, bringing unpredictable risks and iteration time to both timing convergence and manufacturability.

[0046] It can be seen that the wire routing method for functional modules with complex data interaction logic usually has the following problems: severe wire routing congestion inside the module, prone to problems such as short circuits and delays, and tight wire resources. Therefore, it is easy to cause functional errors, resulting in increased chip power consumption. If we use EDA tools to solve the wire routing problem, it will sacrifice a certain amount of chip area. For this reason, this application provides a floorplanning and wire routing scheme, which can simplify the floorplanning and wire routing of functional modules with complex data interaction logic, reduce the probability of problems such as wire routing congestion, short circuits, delays, and functional errors, save wire resources and chip power consumption, and can also select a floorplanning and wire routing scheme that meets the preset index requirements. Therefore, it can improve the performance, manufacturability, and timing convergence effect of the chip.

[0047] See Figure 1 shown, the embodiment of this application discloses a floorplanning and wire routing method, including:

[0048] S101. Determine the data processing logic between each sub-module in any functional module of the chip.

[0049] In this embodiment, the data processing logic between each sub-module in any functional module can be obtained by a technician based on the design logic of the functional module.

[0050] Suppose a functional module includes nine sub-modules A1 - A8 and C, and the data processing logic among these sub-modules is as follows: A1 sends data to C, and after C receives and processes it, C returns the processing result to A1 - A8. Correspondingly, A2 also sends data to C, and after C processes the data sent by A2, C returns the result to A1 - A8. Similarly, there is the above logic between A3 - A8 and C respectively.

[0051] For the layout and wiring of the above functional module, there may be a layout and wiring scheme as Figure 2 shown. Figure 2 Only the lines from A1 - A8 to C are shown. In the case where data can only be transmitted unidirectionally on this line, wiring is also required from C to A1 - A8 respectively. As Figure 2 shown, the wiring in this scheme is complex, with many wire windings, and more chip space is required.

[0052] S102. If the data processing logic matches the star topology structure, then use constraint methods with different constraint capabilities to constrain each sub-module in the functional module to be laid out and wired according to the star topology structure, and obtain the layout and wiring results corresponding to each constraint method.

[0053] Taking the Figure 2 shown functional module as an example, there is an interaction logic between A1 - A8 and C in this module. Then it can be considered that this data processing logic matches the star topology structure. That is: C can be regarded as the central point, and A1 - A8 surround C. Accordingly, re-arrange the wire layout of the Figure 2 shown functional module according to the method provided in this embodiment, and the layout and wiring result as Figure 3 shown can be obtained.

[0054] Comparing Figure 2 and Figure 3 it can be seen that Figure 3 the wiring is more concise. Figure 3 For the line between A1 and C and the line between A2 and C in , they will not cross, and the same is true for other lines. This not only saves line resources but also solves the problem of wire winding.

[0055] If there are multiple functional modules as Figure 3 shown, and the data processing logic between these functional modules also matches the star topology structure, then these functional modules can also be laid out and wired according to the star topology structure.

[0056] It should be noted that Figure 2 and Figure 3Only the positions and connections of different sub - modules are illustrated. In fact, not all the units that make up a sub - module are set inside the sub - module. They may also be scattered in the adjacent positions near the edge of the sub - module. As for whether the units that make up a sub - module are set inside the sub - module or scattered in the adjacent positions near the edge of the sub - module, this depends on the constraint ability of the constraint method. Generally, the stronger the constraint ability of the constraint method, the more it will limit the units inside the sub - module as much as possible, while the weaker the constraint ability of the constraint method, the more it will allow the units to be distributed at the edge of the sub - module. Among them, the unit is: the standard cell.

[0057] Among them, the relationship between the strength of the constraint ability and the routing complexity of the placement and routing result is not easy to estimate and determine. Therefore, constraint methods with different constraint abilities can be used to perform placement and routing on each sub - module in the same functional module, and then compare the obtained placement and routing results. In this way, it can be clearly known which constraint method is better.

[0058] In a specific implementation manner, the constraint methods with different constraint abilities are: softbound, bound, hard bound, and / or exclude bound in the EDA tool. Of course, other constraint methods can also be used.

[0059] Among them, the constraint ability of soft bound (soft constraint) is the weakest, the constraint ability of bound (boundary) is relatively weak, the constraint ability of hard bound (hard constraint) is relatively strong, and the constraint ability of exclude bound (exclusion constraint) is the strongest.

[0060] Among them, soft bound is also called soft guide. It does not set a fixed position, but only serves as a guide to place the module (such as Figure 3 sub - module C) or cell (standard cell). If problems such as timing violations occur, it will place the module or cell according to its own needs. It is the least strictly constrained one. The cell can enter or exit according to requirements such as timing violations. Its definition method is similar to that of a virtual clock. It does not need to specify the pin (the interface between the cell and the outside) / port (the interface between the module and the outside), does not need coordinates, or coordinates can also be given.

[0061] Bound, also known as guide, has a slightly stricter constraint ability than soft bound. It requires specifying coordinates to place cells or modules on the basis of soft bound. Bound still only serves to guide the placement of cells and modules and does not make mandatory requirements. Therefore, cells can enter or exit. The specified cells may be placed outside the module, and the unspecified cells may be placed inside the module, but fixed coordinates need to be specified.

[0062] Hard bound, also known as region, has a stricter constraint ability than bound. It not only serves to guide the placement of modules or cells, but must place cells or modules according to the constraints required by humans. At this time, cells can enter but not exit. The specified cells cannot be placed outside the module, and the unspecified cells may be placed inside the module.

[0063] Exclude bound, also known as fence, has the strictest constraint ability and requires placing cells or modules strictly according to the constraints required by humans. This type of constraint condition is the same as that of region and must be satisfied, not just serving as a guide anymore. Cells cannot enter or exit. The specified cells cannot be placed outside the module, and the unspecified cells cannot be placed inside the module.

[0064] Through experimental comparison, it is finally found that the layout and routing result corresponding to the exclude bound with the strongest constraint ability is the best (i.e., the result shown in Figure 3 ), which can ensure that the data routing between each sub-module is clear.

[0065] S103. Select the layout and routing results that meet the preset index requirements from each layout and routing result as the layout and routing scheme for the functional module.

[0066] In this embodiment, constraint methods with different constraint abilities are used to constrain each sub-module in the same functional module to be laid out and routed according to the star topology structure, so as to obtain the layout and routing results corresponding to each constraint method respectively. In this way, it can be known which constraint method has the best layout and routing effect when combined with the star topology structure.

[0067] Of course, among the multiple layout and routing results obtained in this embodiment, there may be more than one that meets the preset index requirements. That is: multiple layout and routing results are both practical and feasible, then one with the best effect can be selected from them, or one can be randomly selected. Among them, the preset index requirements can be set based on the timing convergence effect and / or the routing congestion degree.

[0068] In a specific embodiment, after selecting the layout and routing result that meets the preset index requirements from each layout and routing result as the layout and routing scheme of the functional module, it further includes: visually displaying the layout and routing scheme using an EDA tool. Of course, the layout and routing results corresponding to each constraint method can also be visually displayed using an EDA tool. For example: highlighting the layout and routing situation in this functional module in the EDA tool.

[0069] In this embodiment, for a functional module where the data processing logic matches the star topology structure, constraint methods with different constraint capabilities can be used to constrain each sub-module in the functional module to perform layout and routing according to the star topology structure, obtaining the layout and routing results corresponding to each constraint method respectively. Then, select the layout and routing result that meets the preset index requirements from each layout and routing result as the layout and routing scheme of the functional module. This can not only simplify the layout and routing according to the star topology structure, but also select a layout and routing scheme with better performance that meets the preset index requirements from multiple layout and routing results, thus ensuring the usability of the layout and routing scheme.

[0070] It can be seen that if the star topology structure matches the data processing logic between each sub-module in the functional module, then performing layout and routing inside the module according to the star topology structure can reduce wire routing, solve the problem of wire routing congestion inside the module, reduce the probability of problems such as short circuits, time delays, and functional errors, and also save wire resources, chip power consumption, and chip area, and can improve the performance, manufacturability, and timing convergence effect of the chip.

[0071] Based on the above embodiment, it should be noted that in a specific embodiment, using constraint methods with different constraint capabilities to constrain each sub-module in the functional module to perform layout and routing according to the star topology structure, obtaining the layout and routing results corresponding to each constraint method respectively, includes: determining, according to the data processing logic, the target sub-module that needs to be set at the center position of the star topology structure and the other sub-modules that need to be set around the center position among the sub-modules in the functional module; based on each constraint method, constraining the target sub-module at the center position, constraining the other sub-modules around the center position, and performing wire routing between each sub-module to obtain the layout and routing result corresponding to each constraint method.

[0072] Among them, before constraining the target sub-module at the center position and the other sub-modules around the center position, it further includes: allocating corresponding layout spaces of appropriate sizes to each sub-module in the functional module according to the number of units included in each sub-module in the functional module.

[0073] Please refer to Figure 3, if the number of cells in A1 - A8 varies, then relatively larger areas can be allocated to those with more cells and relatively smaller areas to those with fewer cells. That is: when constraining other sub - modules around the central position, the area around the target sub - module can be equally divided, or divided one by one according to the number of cells included in each sub - module. Both of these methods can fix A1 - A8 in a specific area, and such an arrangement will no longer cause the crossing of data streams, fundamentally solving the short - circuit problem.

[0074] Of course, Figure 3 The proportion of the entire module area occupied by the central C can also be adjusted according to the number of cells in C.

[0075] It should be noted that there are limitations on the areas that each functional module can occupy in the chip. In this application, the sub - modules within the functional module are restricted to a star - shaped topology structure, which has a certain dependence on the overall shape of the module. When the overall shape of the module is rectangular, the results are relatively good. At the same time, there are also certain restrictions on the shapes of other modules in the chip.

[0076] In a specific implementation manner, the method of selecting a layout and routing result that meets the preset index requirements from each layout and routing result as the layout and routing scheme of the functional module includes: respectively testing the timing information and / or routing congestion degree of each layout and routing result; if the timing information and / or routing congestion degree of any layout and routing result meets the preset index requirements, then use this layout and routing result as the layout and routing scheme of the functional module.

[0077] If there are multiple layout and routing results that meet the preset index requirements, then select the layout and routing result with the optimal timing information and / or routing congestion degree from the multiple layout and routing results that meet the preset index requirements as the layout and routing scheme of the functional module.

[0078] Next, a layout and routing device provided by an embodiment of the present application will be introduced. The layout and routing device described below can be referred to in mutual reference with the layout and routing method described above.

[0079] See Figure 4 As shown, an embodiment of the present application discloses a layout and routing device, including:

[0080] A determination module 401, configured to determine the data - processing logic between each sub - module in any functional module in the chip;

[0081] A layout and routing module 402, configured to, if the data - processing logic matches the star - shaped topology structure, use constraint methods with different constraint capabilities to constrain each sub - module in the functional module to perform layout and routing according to the star - shaped topology structure, and obtain layout and routing results corresponding to each constraint method respectively;

[0082] A selection module 403 is configured to select a layout and routing result that meets the requirements of a preset metric from each layout and routing result as the layout and routing scheme of the functional module.

[0083] In a specific embodiment, the layout and routing module includes:

[0084] A determination unit is configured to determine, in each sub-module of the functional module according to the data processing logic, a target sub-module to be set at the central position of the star topology structure and other sub-modules to be set around the central position.

[0085] A constraint unit is configured to, based on each constraint method, constrain the target sub-module at the central position, constrain the other sub-modules around the central position, and perform routing between the sub-modules to obtain a layout and routing result corresponding to each constraint method.

[0086] In a specific embodiment, the layout and routing module further includes:

[0087] An allocation unit is configured to allocate corresponding layout spaces of appropriate sizes to the sub-modules in the functional module according to the number of units included in each sub-module in the functional module.

[0088] In a specific embodiment, the constraint methods with different constraint capabilities are: softbound, bound, hard bound, and / or exclude bound in the EDA tool.

[0089] In a specific embodiment, the selection module includes:

[0090] A test unit is configured to respectively test the timing information and / or routing congestion degree of each layout and routing result.

[0091] A selection unit is configured to, if the timing information and / or routing congestion degree of any layout and routing result meets the requirements of the preset metric, use the layout and routing result as the layout and routing scheme of the functional module.

[0092] In a specific embodiment, the selection unit is further configured to:

[0093] If there are multiple layout and routing results that meet the requirements of the preset metric, select the layout and routing result with the optimal timing information and / or routing congestion degree from the multiple layout and routing results that meet the requirements of the preset metric as the layout and routing scheme of the functional module.

[0094] In a specific embodiment, it further includes:

[0095] A display module is configured to visually display the layout and routing scheme by using the EDA tool.

[0096] Among them, the more specific working processes of each module and sub-module in this embodiment can refer to the corresponding content disclosed in the foregoing embodiments, and will not be elaborated here.

[0097] It can be seen that this embodiment provides a layout and routing device, which can simplify the layout and routing inside the module, reduce the probability of problems such as wire congestion, short circuit, time delay, and functional error, save wire resources, chip power consumption, and chip area, and can also select a layout and routing scheme that meets the requirements of preset indicators. Therefore, it can improve the performance, manufacturability, and timing convergence effect of the chip.

[0098] Next, an electronic device provided by an embodiment of the present application will be introduced. The electronic device described below can be referred to in mutual reference with the layout and routing method and device described above.

[0099] See Figure 5 As shown, an embodiment of the present application discloses an electronic device, including:

[0100] A memory 501 for storing a computer program;

[0101] A processor 502 for executing the computer program to implement the method disclosed in any of the foregoing embodiments.

[0102] Next, a readable storage medium provided by an embodiment of the present application will be introduced. The readable storage medium described below can be referred to in mutual reference with the layout and routing method, device, and equipment described above.

[0103] A readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the layout and routing method disclosed in the foregoing embodiments. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and will not be elaborated here.

[0104] The "first", "second", "third", "fourth", etc. (if any) involved in the present application are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments described here can be implemented in an order other than that illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, or device that includes a series of steps or sub-modules does not necessarily have to be limited to those steps or sub-modules clearly listed, but may include other steps or sub-modules that are not clearly listed or are inherent to these processes, methods, or devices.

[0105] It should be noted that the descriptions involving "first", "second", etc. in this application are only for descriptive purposes and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. Additionally, the technical solutions between various embodiments may be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0106] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0107] The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of readable storage medium known in the technical field.

[0108] Specific examples are used in this article to elaborate on the principles and implementation manners of this application. The descriptions of the above embodiments are only for helping to understand the method and its core idea of this application. At the same time, for those of ordinary skill in the art, based on the idea of this application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A layout and routing method, characterized in that, Including: Determine the data processing logic between each sub-module in any functional module in the chip; If the data processing logic matches the star topology, use constraint methods with different constraint capabilities to constrain each sub-module in the functional module to be laid out and routed according to the star topology, and obtain the layout and routing results corresponding to each constraint method; Select the layout and routing result that meets the preset index requirements from each layout and routing result as the layout and routing scheme of the functional module; The preset index requirements are set based on the timing convergence effect and / or the routing congestion degree; Among them, the constraint methods with different constraint capabilities are: soft bound, bound, hard bound, and / or exclude bound in the EDA tool.

2. The layout and wiring method according to claim 1, wherein The step of using constraint methods with different constraint capabilities to constrain each sub-module in the functional module to be laid out and routed according to the star topology and obtain the layout and routing results corresponding to each constraint method includes: According to the data processing logic, determine the target sub-module that needs to be set at the center position of the star topology and other sub-modules that need to be set around the center position in each sub-module of the functional module; Based on each constraint method, constrain the target sub-module at the center position, constrain the other sub-modules around the center position, and route between each sub-module to obtain the layout and routing result corresponding to each constraint method.

3. The layout and wiring method according to claim 2, wherein Before constraining the target sub-module at the center position and constraining the other sub-modules around the center position, it further includes: Allocate corresponding layout spaces of appropriate sizes to each sub-module in the functional module according to the number of units included in each sub-module in the functional module.

4. The layout and wiring method according to any one of claims 1 to 3, characterized in that The step of selecting the layout and routing result that meets the preset index requirements from each layout and routing result as the layout and routing scheme of the functional module includes: Test the timing information and / or the routing congestion degree of each layout and routing result respectively; If the timing information and / or the routing congestion degree of any layout and routing result meet the preset index requirements, use this layout and routing result as the layout and routing scheme of the functional module.

5. The layout and wiring method according to claim 4, wherein It further includes: If there are multiple layout and routing results that meet the preset index requirements, select the layout and routing result with the optimal timing information and / or the routing congestion degree from the multiple layout and routing results that meet the preset index requirements as the layout and routing scheme of the functional module.

6. The layout and wiring method according to any one of claims 1 to 3, characterized in that, After selecting the layout and routing result that meets the preset index requirements from each layout and routing result as the layout and routing scheme of the functional module, it further includes: Visually display the layout and routing scheme using the EDA tool.

7. A layout and wiring device, characterized in that, Including: A determination module for determining the data processing logic between each sub-module in any functional module in the chip; A layout and routing module, which is configured to, if the data processing logic matches the star topology, use constraint methods with different constraint capabilities to constrain each sub-module in the functional module to perform layout and routing according to the star topology, and obtain layout and routing results corresponding to each constraint method respectively; A selection module, which is configured to select a layout and routing result that meets the preset index requirements from each layout and routing result as the layout and routing scheme of the functional module; The preset index requirements are set based on the timing convergence effect and / or the routing congestion degree; Among them, the constraint methods with different constraint capabilities are: soft bound, bound, hard bound, and / or exclude bound in the EDA tool.

8. An electronic device, characterized in that, It includes: A memory, which is configured to store a computer program; A processor, which is configured to execute the computer program to implement the layout and routing method according to any one of claims 1 to 6.

9. A readable storage medium, characterized in that, For saving a computer program, wherein the computer program, when executed by a processor, implements the layout and routing method according to any one of claims 1 to 6.

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