For enhancing deposition of a patterned stop-etch layer

Abstract

Methods, systems, and computer programs are presented for selectively depositing an etch stop layer to enhance patterning during semiconductor manufacturing. One method includes the operations of: adding a photoresist material (M2) on top of a substrate's base material (M1), where M2 defines a pattern for etching M1 in areas where M2 is absent above M1. The method also includes the operations of: conformally covering the substrate with an oxide material (M3) after adding M2; and performing a gap fill on the substrate with a fill material M4 after the conformal covering. Additionally, after the gap fill, an etch stop material (M5) is selectively grown on the exposed surface of M3 and not on the surface of M4. Further, the method also includes the operations of: removing M4 from the substrate after selectively growing M5; and etching the substrate after removing M4 to transfer the pattern into M1. M5 adds etch protection, enabling deeper etching into M1.

Description

[0001] This application is a divisional application of a PCT application that entered the Chinese national stage, with an international filing date of May 6, 2019, a PCT application number of PCT / US2019 / 030929, and an applicant of "Lam Research Corporation" (national application number: 201980031248.5, invention title: "Enhanced Patterning Stop Etch Layer Deposition").

[0002] Priority Claim

[0003] This application claims the priority benefit of U.S. Patent Application No. 15 / 972,918, filed on May 7, 2018, the entire content of which is incorporated herein by reference. Technical Field

[0004] The subject matter disclosed herein generally relates to methods, systems, and procedures for semiconductor etching in semiconductor manufacturing apparatuses. In some examples, deposition control and semiconductor etching are provided during the operation of a semiconductor manufacturing apparatus. Background Art

[0005] Semiconductor manufacturing has seen a reduction in critical dimension (CD) and an exponential increase in the cost of multiple patterning. The semiconductor manufacturing industry is transitioning to extreme ultraviolet lithography (EUV) patterning to achieve smaller CD features with fewer processing steps. In many cases, EUV photoresist (PR) materials are patterned onto silicon-based materials with an aspect ratio of approximately 2:1.

[0006] During the EUV process, undesirable effects can occur when non-uniformities cause aspect ratio variations across the wafer. Another problem can occur during the EUV semiconductor manufacturing process when transferring the pattern to the underlying layer, which is limited by the ability of the EUV PR to withstand the etching process that defines the pattern. As a result, the EUV PR is quickly consumed and cannot be effectively used to define deep patterns within the underlying layer.

[0007] Another problem is that since EUV may not always penetrate to the bottom of the line, a very thick EUV PR is required to successfully transfer the pattern to the underlying layer, but this can lead to line bending (e.g., EUV PR line collapse) or poor selectivity (CD loss).

[0008] The background description provided here is for the purpose of presenting the background of the present disclosure in general. The work of the currently designated inventors is neither expressly nor implicitly admitted to be prior art to the present disclosure to the extent described in this background art section and in the aspects of the description that cannot be determined to be prior art at the time of filing the application. Summary of the Invention

[0009] Exemplary methods, systems, and computer programs are directed to the selective deposition of an etch stop layer to enhance patterning during semiconductor manufacturing. In some embodiments, the semiconductor manufacturing process includes an extreme ultraviolet lithography (EUV) photoresist (PR) material, but the same principles can be used with other patterning techniques. The examples are only representative of possible variations.

[0010] In some implementations, an etch stop layer in the form of a metal oxide (e.g., zirconium oxide ZrO x , aluminum oxide AlO x , hafnium oxide HfO x ) is deposited on the EUV PR pattern to protect the pattern during the etch step. Additionally, a CHx surface relative to a carbon-based gap fill material can be selectively deposited on other examples of hard masks on SiO 2 . Other examples of hard masks on SiO 2 include aluminum nitride A1N, aluminum oxynitride AlON, yttrium oxide Y 3 O x , yttrium nitride YNx, and yttrium oxynitride YO y . The etch stop layer enables the pattern to be transferred deeper into the underlying layer without sacrificing critical dimension (CD) or causing other problems related to line bending, such as those encountered when using elongated PR lines.

[0011] In one implementation, a method is provided. The method includes the operations of: adding a photoresist material (M2) on top of a substrate's base material (M1), where M2 defines a pattern for etching M1 in an area where M2 is absent above M1. The method further includes the operations of: conformally covering the substrate with an oxide material (M3) after adding M2; and gap filling the substrate with a fill material M4 after the conformally covering operation. Additionally, after the gap filling, an etch stop material (M5) is selectively grown on the exposed surface of M3 and not on the surface of M4. Further, the method also includes the operations of: removing M4 from the substrate after selectively growing M5; and etching the substrate after removing M4 to transfer the pattern into M1. M5 adds etch protection, enabling deeper etching into M1.

[0012] In one example, etching the substrate after removing M4 further includes: etching the exposed surface of M3 in the substrate; and continuing to etch the substrate to transfer the pattern into M1.

[0013] In one example, M2 is a carbon-based material.

[0014] In one example, M3 is one of silicon dioxide or aluminum oxide.

[0015] In one example, M4 is a carbon-based sacrificial material.

[0016] In one example, M5 is a metal oxide.

[0017] In one example, conformally covering the substrate with M3 further includes: performing low-damage plasma-enhanced atomic layer deposition.

[0018] In one example, gap filling the substrate with the filler material M4 further includes: alternately depositing M4 and etching M4 to fill the gaps in the substrate.

[0019] In one example, selectively growing M5 further includes: depositing M5 using an atomic layer deposition process.

[0020] In one example, removing M4 from the substrate further includes: performing plasma ashing to remove M4.

[0021] In another implementation, a semiconductor manufacturing apparatus includes a processing chamber and a controller for controlling the processing of a substrate within the processing chamber. The controller causes the processing chamber to perform the following operations: adding a photoresist material (M2) on top of a substrate base material (M1), where M2 defines a pattern for etching M1 in an area where M2 is absent above M1; after adding M2, conformally covering the substrate with an oxide material (M3); and after the conformally covering operation, gap filling the substrate with a filler material M4; after the gap filling, selectively growing a stop etch material (M5) on the exposed surface of M3 and not on the surface of M4; after selectively growing M5, removing M4 from the substrate; and after removing M4, etching the substrate to transfer the pattern into M1, where M5 adds etch protection such that etching can be deeper into M1 than when using M2 without M5.

[0022] In one example, etching the substrate after removing M4 further includes: etching the exposed surface of M3 in the substrate; and continuing to etch the substrate to transfer the pattern into M1.

[0023] In one example, M2 is a carbon-based material.

[0024] In one example, M3 is one of silicon dioxide or aluminum oxide.

[0025] In one example, M4 is carbon.

[0026] In one example, M5 is a metal oxide.

[0027] In one example, conformally covering the substrate with M3 further includes: performing low-damage plasma-enhanced atomic layer deposition.

[0028] In one example, gap filling the substrate with the fill material M4 further includes: alternately depositing M4 and etching M4 to fill the gaps in the substrate.

[0029] In one example, selectively growing M5 further includes: depositing M5 using an atomic layer deposition process.

[0030] In one example, removing M4 from the substrate further includes: performing plasma ashing to remove M4. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Each of the drawings in the figures only shows exemplary embodiments of the present disclosure and should not be considered as limiting its scope.

[0032] Figure 1 is an etching chamber according to some exemplary embodiments.

[0033] Figures 2 - 10 shows a series of operations for etching a substrate in a semiconductor processing apparatus according to some exemplary embodiments.

[0034] Figure 11 is a flowchart of a method for processing a substrate in a semiconductor processing apparatus according to some exemplary embodiments.

[0035] Figures 12 - 14 shows a second operation sequence for etching a substrate in a semiconductor processing apparatus according to some exemplary embodiments.

[0036] Figure 15 is a flowchart of a second method for processing a substrate in a semiconductor processing apparatus according to some exemplary embodiments.

[0037] Figures 16 - 20 shows a third sequence for etching a substrate in a semiconductor processing apparatus according to some exemplary embodiments.

[0038] Figure 21 is a flowchart of a third method for processing a substrate in a semiconductor processing apparatus according to some exemplary embodiments.

[0039] Figure 22 is a block diagram showing an example of a machine on which one or more exemplary embodiments can be implemented or by which one or more exemplary embodiments can be controlled. DETAILED DESCRIPTION

[0040] In some examples, selective deposition of an etch stop layer for enhancing patterning during semiconductor manufacturing is presented. Unless otherwise explicitly stated, components and functions are optional, can be combined or subdivided, and operations can vary in order or be combined or subdivided. In the following description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the exemplary embodiments. However, it will be apparent to those skilled in the art that the subject matter may be practiced without these specific details.

[0041] The presented embodiments can provide several benefits. First, when using an etch stop layer, while using the same EUV PR thickness as in previous implementations, the pattern can be extended deeper into the underlying layer. This means that no other changes are required to the existing EUV process. Second, a combination of process steps (including adding conformal silicon oxide (SiO x )) and gap filling of uneven surfaces on the substrate surface) is used to enable selective growth of the etch stop layer onto the EUV PR.

[0042] Third, when the pattern is extended deeper into the underlying layer, there is no (or very little) line bending or CD loss. Fourth, compared to open space regions used for enhancing patterning, the presented embodiments can be applied to any structured substrate that requires selective growth of an etch stop layer on the etch line. These are just some of the benefits that can be obtained using the described method. Other benefits are possible.

[0043] Figure 1 An etch chamber 100 according to one embodiment is shown. Exciting an electric field between two electrodes is one of the methods for obtaining a radio frequency (RF) gas discharge in an etch chamber. When an oscillating voltage is applied between the electrodes, the resulting discharge is called a capacitively coupled plasma (CCP) discharge.

[0044] The plasma 102 can be generated using a stable feed gas to obtain various chemical reaction by-products, which are produced by dissociation of various molecules caused by electron-neutral collisions. The chemical aspect of etching involves the reaction of neutral gas molecules and their dissociated by-products with the molecules on the surface to be etched, and produces volatile molecules that can be pumped away. When the plasma is generated, positive ions are accelerated from the plasma through the space charge sheath that separates the plasma from the chamber wall, and thus strike the wafer surface with sufficient energy to remove material from the wafer surface. This is called ion bombardment or ion sputtering. However, some industrial plasmas cannot produce ions with sufficient energy to effectively etch the surface by purely physical means.

[0045] The controller 116 manages the operation of the chamber 100 through different components in the control chamber, such as the RF generator 118, the gas source 122, and the gas pump 120. In one embodiment, a fluorocarbon gas (e.g., CF 4 and C-C 4 F 8 is used in the dielectric etching process due to its anisotropic and selective etching capabilities, but the principles described herein can be applied to other plasma-generating gases. Fluorocarbon gases readily decompose into chemical reaction by-products with smaller molecules and atomic radicals. These chemical reaction by-products etch away the dielectric material, which in one embodiment can be SiO 2 or SiOCH used for low-k devices.

[0046] Chamber 100 shows a processing chamber having a top electrode 104 and a bottom electrode 108. The top electrode 104 can be grounded or coupled to an RF generator (not shown), and the bottom electrode 108 is coupled to the RF generator 118 via a matching network 114. The RF generator 118 provides RF power at one, two, or three different RF frequencies. At least one of the three RF frequencies can be turned on or off depending on the desired configuration of the chamber 100 for a particular operation. In Figure 1 the embodiment shown, the RF generator 118 provides frequencies of 2 MHz, 27 MHz, and 60 MHz, but other frequencies are possible.

[0047] Chamber 100 includes a gas showerhead on the top electrode 104 for introducing the gas provided by the gas source 122 into the chamber 100; and a perforated seal ring 112 that allows the gas to be pumped out of the chamber 100 through the gas pump 120. In some exemplary embodiments, the gas pump 120 is a turbomolecular pump, but other types of gas pumps can be used.

[0048] When a substrate 106 is present in the chamber 100, the silicon focus ring 110 is located beside the substrate 106 so that a uniform RF field exists on the bottom surface of the plasma 102 for uniform etching on the surface of the substrate 106. Figure 1 The embodiment of

[0049] shows a triode reactor configuration where the top electrode 104 is surrounded by a symmetric RF ground electrode 124. The insulator 126 is a dielectric that isolates the ground electrode 124 from the top electrode 104. Figure 1In the example of [[ID=]], RF powers of 2 MHz, 27 MHz, and 60 MHz are provided. The 2 MHz RF power provides ion energy control, while the 27 MHz and 60 MHz powers provide control over plasma density and the dissociation mode of chemical species. This configuration where each RF power supply can be turned on or off enables certain processes that use ultra-low ion energy on a substrate or wafer, as well as certain processes that require low ion energy (less than 100 or 200 eV), such as the gentle etching of low-k materials.

[0050] In another embodiment, 60 MHz RF power is used on the top electrode 104 to obtain ultra-low energy and very high density. This configuration enables chamber cleaning with a high-density plasma when the substrate is not in chamber 100 while minimizing sputtering on the electrostatic chuck (ESC) surface. When the substrate is absent, the ESC surface is exposed, and any ion energy on the surface should be avoided, which is why the bottom 2 MHz and 27 MHz power supplies may be turned off during the cleaning process.

[0051] Figures 2 - 10 A sequence of operations for etching a substrate in a semiconductor processing apparatus according to some exemplary embodiments is shown. This sequence of operations illustrates how an etch stop layer is added to provide additional protection from the etching operation, enabling the pattern to be transferred further down to the underlying layer compared to using only EUV PR alone.

[0052] Figure 2 Operation 202 is shown, where a PR material (M2 206) is patterned onto a substrate (M1 204), resulting in structure 200. In some exemplary embodiments, the M1 204 material is silicon oxide or silicon nitride (Si x N y ) type of material, but other materials can be used. In some embodiments, the aspect ratio of M1 204 is about 2:1, plus or minus 10%, but other aspect ratios can be used. The aspect ratio defines the relationship between different dimensions (in this case, the height of the feature relative to the width of the feature).

[0053] M2 206 can be a carbon-based material with some embedded dopants. EUV (also known as EUVL) is a lithography technology that uses extreme ultraviolet wavelengths (e.g., 13.5 nm). In some implementations, the EUV tool is a laser-driven tin (Sn) plasma light source, where the reflective optics include multilayer mirrors that are contained in a hydrogen environment.

[0054] The resulting structure 200 has some dense regions (e.g., on the left above M1 204) and some isolated regions (e.g., in the central region above M1 204). The goal of the etching process is to transfer the pattern onto M1 204 by etching downward the regions of M1 204 not covered by M2 206. In some cases, EUV is used in this process, but EUV PRs are prone to damage because they tend to lack the stability to resist strong etching.

[0055] For structure 200, to pattern M1 204 with PR M2 206, it is possible to etch into M1 204, but not very deep. Some applications require deeper etching, which may etch into more than one layer, and PR M2 206 is not sufficient for this application because M2 206 may wear out and stop protecting M1 204.

[0056] The following reference Figures 3 - 10 The operations described below show how to add protection to M2 206 to enable deeper etching of M1 204. This protection includes adding an etch stop layer above M2 206 to enable deeper etching without completely wearing out M2 206. The etch stop layer is a material layer located above PR M2 206 that protects M2 206 during the etching process. Although the term "stop" is used, those skilled in the art should understand that the etch stop layer may not completely avoid some etching on M2 206, but the etch stop layer provides sufficient protection for M2 206 to avoid completely wearing out M2 206 during deep etching. That is, the etch stop layer provides at least sufficient protection for M2 206 to avoid etching the M1 204 material under PR M2 206.

[0057] One method might simply be to add an etch stop layer above M2 206, but this would also mean placing the etch stop layer above the uncovered regions of M1 204, which would be ineffective. The goal is to place the etch stop layer above M2 206 without directly adding the etch stop layer to the top of M1 204.

[0058] Figure 3 Operation 302 is shown, where material M3 304 is deposited to conformally cover structure 200 with material M3 304, resulting in structure 300. When structure 200 is conformally covered with M3 304, the angles and proportions are preserved; that is, M3 forms a uniform layer on both M1 204 and M2 206.

[0059] The purpose of M3 304 is to provide a surface for the etch stop layer to grow on. In some exemplary embodiments, M3 304 is an oxide, such as an atomic layer deposition (ALD) oxide. In some exemplary embodiments, M3 304 is silicon dioxide SiO 2 or aluminum oxide Al 2 O 3 , but other materials can also be used.

[0060] In some exemplary embodiments, operation 302 for placing M3 304 is performed by low-damage plasma-enhanced atomic layer deposition (PEALD). ALD is a vapor-phase thin film deposition technique that is typically carried out in a heated reactor maintained below atmospheric pressure. The substrate to be coated with the ALD film is placed in the reactor and brought to thermal equilibrium with the reactor temperature before starting the ALD process.

[0061] PEALD is an energy-enhanced ALD method in which, during the reaction step, the surface of the substrate is exposed to species generated by a plasma. Typical plasmas used during PEALD are plasmas generated in O 2 , N 2 and H 2 reaction gases or combinations thereof. Such plasmas can replace the typical ligand exchange reactions in water H 2 O or ammonia NH 3 and can be used to deposit metal oxides, metal nitrides, and metal films.

[0062] Figure 4 Operation 402 is shown, in which the open area is filled with material M4 404, resulting in structure 400. In some exemplary embodiments, M4 404 (also referred to herein as the fill material) is amorphous carbon, but other materials are possible. After adding M4 404, the top of the feature of M3 304 is exposed, while the other surfaces of the feature will be covered by M4 404.

[0063] M4 404 serves as a sacrificial material, as discussed in more detail below, to enable the etch stop layer to grow on the top surface of M3 304 but not on the other surfaces. In some exemplary embodiments, operation 402 is performed in an etching environment where hydrogen is added in the process, and along with the deposition, the process also etches the material (e.g., etching and deposition are carried out simultaneously). In this way, the open area can be filled by gap filling. In a narrow space, etching is only performed at the top and not at the bottom, so gap filling can be achieved.

[0064] The reason for using M4 404 is that this carbon-based filler enables the selective growth of a stop-etching layer over regions where M4 404 is not present. That is, the stop-etching layer grows over regions not exposed to M4 404 and does not grow over regions exposed to M4 404. In this way, M3 304 can be exposed to the stop-etching layer.

[0065] Figure 5 Operation 502 is shown, in which a stop-etching layer (material M5 504) is grown over the exposed M3 304, resulting in structure 500. In some exemplary embodiments, operation 502 is an ALD process to selectively deposit M5 504 on M3 304. In some exemplary embodiments, ALD includes alternating a first precursor and a second precursor for a layer-by-layer growth method.

[0066] In some exemplary embodiments, M5 504 is a metal oxide (MO x ) that does not grow on M4 404 due to the presence of carbon (e.g., zirconium oxide ZrO x , aluminum oxide AlO x , hafnium oxide HfO x ). (For example, M4 404 can be CH x -terminated). For example, M5 504 can be aluminum oxide. However, M5 504 will grow on M3 304, which can be an OH-terminated SiO x surface.

[0067] Figure 6 Operation 602 is shown, in which M4 404 is removed, resulting in structure 600. As described above, the purpose of filling the gap with M4 404 is to allow for the selective growth of M5 504. After the stop-etching layer M5 504 has been added, M4 404 can be removed.

[0068] In some exemplary embodiments, M4 404 can be removed by ashing, which is a straightforward operation since carbon is easily removed. For example, M4 404 can be removed using a hydrogen plasma.

[0069] Plasma ashing is a process for removing material from a substrate. Using a plasma source, single-atom species called reactive species are generated. Oxygen or fluorine are common reactive species. The reactive species combine with the material to be removed to form an ash, which is removed using a vacuum pump.

[0070] Figure 7Operation 702 is shown, where M3 304 on the exposed surface is removed, resulting in structure 700. After removing M4 404, the etching process can continue to transfer the pattern defined by M2 206 into M1 204. In some exemplary embodiments, operation 602 is performed by etching to remove M3 304.

[0071] At this time, a portion of the top surface of M1 204 is uncovered, and since M2 206 is covered by M5 504, the pattern defined by M2 206 has additional protection against etching. Deep etching of M1 204 can now be performed, as described below.

[0072] Figure 8 Operation 802 is shown, which is for etching the unexposed surface of M1 204, resulting in structure 800. The etching is performed to transfer the pattern into M1 204. As M1 204 is etched, M5 504 is also removed until M5 504 is completely removed, but the etching can continue because M2 206 still remains.

[0073] Structure 800 shows the progressive etching of M1 204 and the wear of M5 504. Due to the presence of M5 504, it is possible to etch deeper into M1 204.

[0074] Figure 9 Operation 902 is shown, where the etching continues to etch into M1 204 while etching away M3 304, resulting in structure 900. At the end of operation 902, M3 304 (not shown) has been etched away, or at least mostly etched, but M2 206 still continues to provide protection for M1 204 to transfer the pattern and etch deeper into M1 204.

[0075] Figure 10 Operation 1002 is shown, where M5 504 and M3 304 have been removed, and a portion of M2 206 has also been etched away, resulting in structure 1000. At the end of operation 1002, the desired portion of M1 204 has been etched away, while some of M2 206 remains, resulting in maintaining the desired CD.

[0076] As shown in structure 1000, due to the etching, some edges of M2 206 have been rounded. Those skilled in the art will readily understand that Figures 2 - 10 an ideal representation of the material is shown, which includes perfect straight lines. However, during different operations, deposition and etching may cause minor variations in the material (e.g., thickness and uneven corners).

[0077] In summary, by filling the gap with M4 404, M5 504 can be selectively grown over M2 206. M3 304 enables M5 504 to grow on a consistent surface.

[0078] Figure 11 is a flowchart of a method for processing a substrate in a semiconductor processing apparatus according to some exemplary embodiments. Although the various operations in the flowchart are presented and described in sequence, those of ordinary skill in the art will understand that some or all of the operations may be performed in a different order, may be combined or omitted, or may be performed in parallel. Figure 11 summarizes Figures 2 - 10 the process shown in

[0079] At operation 202, a pattern M2 206 is created over a material M1 204. In some exemplary embodiments, EUV is utilized to create the pattern, but other lithography methods may also be utilized.

[0080] The method proceeds from operation 202 to operation 302, in which M2 206 is conformally covered with M3 304. At operation 402, the gap is filled with a material M4 404 while preserving the top surface of M3 304 that is located over the pattern defined by M2 206.

[0081] The method proceeds from operation 402 to operation 502. Once M4 404 is added, M5 504 can be selectively grown on top of M3 304 rather than on top of M4 404.

[0082] The method proceeds from operation 502 to operation 602. Once M4 404 has served its purpose, i.e., enabling the selective growth of M5 504, M4 404 is removed.

[0083] The method proceeds from operation 602 to operation 702, in which the portion of M3 304 that is not protected by M5 504 is etched away.

[0084] The method proceeds from operation 702 to operation 802, in which etching of the underlying layer of M1 202 is started. As M1 202 is etched away, the top surface of M5 504 is also etched away, but still provides protection for the pattern defined by M2 206.

[0085] The method proceeds from operation 802 to operation 902, in which etching of M1 continues while also etching away M3 304.

[0086] The method proceeds from operation 902 to operation 1002. After M3 304 has been etched away, etching of M1 204 continues, which means that the pattern of M2 206 is also being gradually etched away. However, M2 206 is not completely etched away, thus ensuring that the pattern is transferred into M1 204.

[0087] Figures 12 - 14 A second operation sequence for etching a substrate in a semiconductor processing apparatus according to some exemplary embodiments is shown. The second sequence may also use EUV PR to transfer the pattern lower to the underlying layer, which is not possible with EUVPR alone.

[0088] The second sequence also includes operations 202, 302, and 402, as referred to above Figures 2 - 4 as shown. However, starting from operation 402, the second sequence proceeds from operation 402 to Figure 12 operation 1202.

[0089] Figure 12 Operation 1202 is shown, in which M4 404 is transformed into material M4-2 1204, resulting in structure 1200. In some exemplary embodiments, M4 402 is CH x surface, which is transformed into CF x surface M4-2 1204. Compared with the CH x surface, this surface can provide a more non-wetting surface for the desired chemical substances, thus improving the selectivity of depositing M5 504. In some exemplary embodiments, M4 402 is converted into M4-2 1204 by fluorinating M4 402.

[0090] Fluorination of the carbon film (CH x ) can be performed by capacitively coupled plasma or a remote plasma-assisted process capable of fluorinating the carbon surface.

[0091] Figure 13 Operation 1302 is shown, in which a stop-etching layer (material M5 504) is grown over the exposed M3 304, resulting in structure 1300. As in operation 502, M5 504 is selectively deposited on M3 304 using an ALD process. Metal oxide (MO x ) will not grow on the CF x terminated surface (M4-2 1204), thus enabling selective growth on the SiO x surface (M3 304).

[0092] Figure 14 Operation 1402 is shown, in which M4-2 1204 is removed, resulting in structure 1400, which is similar to Figure 6Structure 600. In some exemplary embodiments, M4-2 1204 can be removed by ashing, which is a simple operation because carbon is easy to remove. For example, M4-2 1204 can be removed using a hydrogen plasma.

[0093] The method proceeds from operation 1402 to Figure 7 operation 702, and the remaining operations in the second sequence are the same as the operations after operation 702 in the first sequence.

[0094] Figure 15 is a flowchart of a second method for processing a substrate in a semiconductor processing apparatus according to some exemplary embodiments. Although the various operations in this flowchart are presented and described sequentially, those of ordinary skill in the art will understand that some or all of the operations can be performed in a different order, can be combined or omitted, or can be performed in parallel.

[0095] Operations 202, 302, and 402 are the same as those described above with reference to Figure 11 In operation 1202, material M4 404 (e.g., by fluorination) is transformed into a different type of material M4-2 1204.

[0096] The method proceeds from operation 1202 to operation 1302, in which material M5 504 is selectively grown on M3 304 rather than on M4-2 1204.

[0097] The method proceeds from operation 1302 to operation 1402, in which material M4-2 1204 is removed, for example, by ashing or other types of etching processes.

[0098] The method proceeds from operation 1402 to operation 702, and the remaining steps are the same as those described above with reference to Figure 11 described.

[0099] Figures 16 - 20 illustrates a third sequence for etching a substrate in a semiconductor processing apparatus according to some exemplary embodiments. The third sequence is a hybrid method in which a new material M6 1604 is added on top of M3 304 before gap filling with M4 404 to improve the selectivity when growing M5 504.

[0100] The third sequence includes operations 202 and 302 as described above. Starting from operation 302, the third sequence continues at operation 1602. Figure 16 Illustrates operation 1602, in which M3 304 is covered with a conformal layer of material M6 1604, resulting in structure 1600.

[0101] In some exemplary embodiments, M6 1604 is a fluorocarbon CFx. In some exemplary embodiments, the operation 1602 for placing M6 1604 is performed by low-damage plasma-enhanced atomic layer deposition (PEALD).

[0102] Figure 17 Operation 1702 is shown, in which the open area is filled with material M4 404, resulting in structure 1700. Operation 1702 is similar to operation 402 described above, except that M6 1604 is present on the top surface. Figure 4 The difference is that M6 1604 is present on the top surface.

[0103] Figure 18 Operation 1802 is shown, in which, before growing M5 504, the top surface of M6 1604 associated with the pattern to be transferred is removed to expose M3 304. The result is structure 1800. In some exemplary embodiments, the top surface of M6 1604 is removed. A photoetching operation is used to expose the oxide surface, but other removal operations are also possible.

[0104] Figure 19 Operation 1902 is shown, in which a stop-etch layer (material M5 504) is grown over the exposed M3 304, resulting in structure 1900. Since M6 1604 provides a separation between M3 304 and M4 4041, the presence of M6 1604 improves the selectivity when growing M5 504; thus, the selectivity is increased. A metal oxide can be deposited by MOCVD (metal-organic CVD), and the metal oxide does not grow on the CF x or CH x surface. This will enable the selective growth of MO x on the SiOx surface, which can be -OH terminated.

[0105] Figure 20 Operation 2002 is shown, in which M4 404 and M6 1604 are removed, resulting in structure 2000. As described above, the purpose of gap filling with M4 404 is to enable the selective growth of M5 504. After the stop-etch layer M5 504 has been added, M4 404 and M6 1604 can be removed.

[0106] In some exemplary embodiments, M4 404 and M6 1604 can be removed by ashing, which is a simple operation because carbon is easy to remove. For example, M4 404 can be removed using a hydrogen plasma.

[0107] After operation 2002, the third sequence continues at operation 702, as Figure 7 shown, and the remaining operations are the same as Figure 11is the same as the first sequence described in

[0108] Figure 21 is a flowchart of a third method for processing a substrate in a semiconductor processing apparatus according to some exemplary embodiments. Although the various operations in this flowchart are presented and described sequentially, those of ordinary skill in the art should understand that some or all of the operations may be performed in a different order, may be combined or omitted, or may be performed in parallel.

[0109] Operations 202 and 302 are the same as those described above with reference to Figure 11 described. At operation 1602, a conformal material layer M6 1604 is grown over M3 304.

[0110] The method proceeds from operation 1602 to operation 1702, in which the opening region is gap-filled with M4 404. The method proceeds from operation 1702 to operation 1802, in which the top surfaces of M4 404 and M6 1604 are removed to expose M3 304.

[0111] The method proceeds from operation 1802 to operation 1902, in which M5 504 is selectively grown on M3 304. The method proceeds from operation 1902 to operation 2002, in which M4 404 and M6 1604 are removed.

[0112] The method proceeds from operation 2002 to operation 702, as described above with reference to Figure 7 described, and the remaining operations are the same as those described above with reference to Figure 11 described.

[0113] Figure 22 is a block diagram illustrating an example of a machine 2200, by or on which one or more example process embodiments described herein may be implemented or controlled. In alternative embodiments, the machine 2200 may operate as a stand-alone device or may be connected (e.g., network-connected) to other machines. In a networked arrangement, the machine 2200 may operate in the capacity of a server machine, a client machine, or both in a server-client network environment. In one example, the machine 2200 may act as a peer machine in a peer-to-peer (P2P) network (or other distributed network) environment. Further, although only a single machine 2200 is shown, the term "machine" shall also be taken to include any collection of machines (these machines individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods described herein, e.g., via cloud computing, software as a service (SaaS), or other computer cluster configurations).

[0114] Examples described herein may include logic, several components, or mechanisms, or may operate through logic, several components, or mechanisms. A circuitry is a collection of circuits implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). Circuitry components may have flexibility over time and due to basic hardware variability. A circuitry includes components that can perform specified operations when operating, either individually or in combination. In one example, the hardware of a circuitry may be designed in a fixed and immutable manner to perform a particular operation (e.g., hardwired). In one example, the hardware of a circuitry may include variable connection entity components (e.g., execution units, transistors, simple circuits, etc.) that include a computer-readable medium modified physically (e.g., magnetically, electrically, by a movable arrangement of invariant mass particles, etc.) to encode instructions for a particular operation. When the entity components are connected, the basic electrical properties of the hardware components change (e.g., from an insulator to a conductor, or vice versa). The instructions enable an embedded hardware (e.g., an execution unit or a loading mechanism) to generate components of the circuitry in the hardware via variable connections to perform parts of a particular operation when operating. Thus, when the device operates, the computer-readable medium is communicatively coupled to other components of the circuit. In one example, any of the entity components may be used in more than one component of more than one circuitry. For example, in operation, an execution unit may be used in a first circuit of a first circuitry at one point in time and reused by a second circuit of the first circuitry or by a third circuit of a second circuitry at a different time.

[0115] A machine (e.g., a computer system) 2200 may include a hardware processor 2202 (e.g., a central processing unit (CPU), a hardware processor core, or any combination thereof), a graphics processing unit (GPU) 2203, a main memory 2204, and a static memory 2206, some or all of which may communicate with each other via an interconnection (e.g., a bus) 2208. The machine 2200 may also include a display device 2210, an alphanumeric input device 2212 (e.g., a keyboard), and a user interface (UI) navigation device 2214 (e.g., a mouse). In one example, the display device 2210, the alphanumeric input device 2212, and the UI navigation device 2214 may be a touch screen display. The machine 2200 may additionally include a mass storage device (e.g., a drive unit) 2216, a signal generation device 2218 (e.g., a speaker), a network interface device 2220, and one or more sensors 2221, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 2200 may include an output controller 2228 (e.g., a serial (e.g., universal serial bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection) to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0116] The mass storage device 2216 may include a machine-readable medium 2222, on which one or more sets of data structures or instructions 2224 (e.g., software) may be stored, and these data structures or instructions 2224 implement any one or more of the techniques or functions described herein, or are used by any one or more of the techniques or functions described herein. The instructions 2224 may also be present, in whole or at least in part, within the main memory 2204, the static memory 2206, the hardware processor 2202, or the GPU 2203 during execution thereof by the machine 2200. In one example, one or any combination of the hardware processor 2202, the GPU 2203, the main memory 2204, the static memory 2206, or the mass storage device 2216 may constitute a machine-readable medium.

[0117] Although the machine-readable medium 2222 is shown as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) configured to store one or more instructions 2224.

[0118] The term "machine-readable medium" can include: any medium that can store, encode, or carry instructions 2224 for causing a machine 2200 to perform and causing the machine 2200 to perform any one or more of the techniques of the present disclosure; or any medium that can store, encode, or carry data structures used by or associated with such instructions 2224. Non-limiting machine-readable media can exemplarily include solid-state memories and optical and magnetic media. In one example, a mass machine-readable medium includes a machine-readable medium 2222 having a plurality of particles having an invariant mass (e.g., rest mass). Thus, a mass machine-readable medium is not an instantaneous propagated signal. Specific examples of mass machine-readable media can include non-volatile memories such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory devices); magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0119] Instructions 2224 can be further sent or received via a network interface device 2220 using a transmission medium over a communication network 2226.

[0120] Throughout the specification, multiple instances can implement components, operations, or structures described as a single instance. Although the separate operations of one or more methods are shown and described as separate operations, one or more of the separate operations can be performed simultaneously, and the operations need not be performed in the order shown. Structures and functions that are represented as separate components in an example configuration can be implemented as a combined structure or component. Similarly, structures and functions presented as a single component can be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter herein.

[0121] The embodiments shown herein are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments can be used and other embodiments can be derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of the present disclosure. Thus, this detailed description is not to be considered limiting, and the scope of the various embodiments is defined only by the appended claims and the full scope of equivalents given by those claims.

[0122] As used herein, the term "or" may be interpreted in an inclusive or exclusive sense. In addition, multiple instances may be provided for resources, operations, or structures described herein as a single instance. Further, the boundaries between various resources, operations, modules, engines, and data stores are somewhat arbitrary, and particular operations are illustrated in the context of a particular illustrative configuration. Other allocations of functionality are contemplated and may fall within the scope of various embodiments of the present disclosure. Generally, structures and functions that are represented as separate resources in an example configuration may be implemented as a combined structure or resource. Similarly, structures and functions presented as a single resource may be implemented as separate resources. These and other variations, modifications, additions, and improvements fall within the scope of the embodiments of the present disclosure as expressed in the appended claims. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A method for processing a substrate, the method comprises: adding a photoresist material M2 on top of a substrate base material M1, M2 defining a pattern for etching M1 in an area where M2 is absent above M1; after adding M2, conformally covering the substrate with an oxide material M3; after the conformal covering, gap-filling the substrate with a filling material M4; transforming the filling material M4 into a filling material M4-2; after the transformation, enabling a stop-etching material M5 to selectively grow on the exposed surface of M3 and not on the surface of M4-2; after selectively growing M5, removing M4-2 from the substrate; and after removing M4-2, etching the substrate to transfer the pattern into M1.

2. The method according to claim 1, wherein etching the substrate after removing M4-2 further comprises: etching the exposed surface of M3 in the substrate; and continuing to etch the substrate to transfer the pattern into M1.

3. The method according to claim 1, wherein M2 is a carbon-based material.

4. The method according to claim 1, wherein M3 is one of silicon dioxide or aluminum oxide.

5. The method according to claim 1, wherein M4 is CH x surface, wherein M4-2 is CF x surface.

6. The method according to claim 1, wherein transforming the filling material M4 comprises: transforming M4 into M4-2 by fluorinating M4.

7. The method according to claim 1, wherein M5 is a metal oxide or an oxynitride.

8. The method according to claim 1, wherein conformally covering the substrate with M3 further comprises: performing low-damage plasma-enhanced atomic layer deposition.

9. The method according to claim 1, wherein gap-filling the substrate with a filling material M4 further comprises: alternately depositing M4 and etching M4 to fill the gaps in the substrate.

10. The method according to claim 1, wherein selectively growing M5 further comprises: depositing M5 using an atomic layer deposition process.

11. The method according to claim 1, wherein removing M4-2 from the substrate further comprises: performing plasma ashing to remove M4-2.

12. A semiconductor manufacturing apparatus, which comprises: a processing chamber; and a controller for controlling the processing of a substrate in the processing chamber, wherein the controller causes the processing chamber to perform operations, the operations including: adding a photoresist material M2 on top of a substrate base material M1, M2 defining a pattern for etching M1 in an area where M2 is absent above M1; after adding M2, conformally covering the substrate with an oxide material M3; after the conformal covering, gap-filling the substrate with a filling material M4; transforming the filling material M4 into a filling material M4-2; after the transformation, enabling a stop-etching material M5 to selectively grow on the exposed surface of M3 and not on the surface of M4-2; after selectively growing M5, removing M4-2 from the substrate; and after removing M4-2, etching the substrate to transfer the pattern into M1.

13. A method for processing a substrate, the method comprises: A photoresist material M2 is added on top of the substrate base material M1, and M2 defines a pattern for etching M1 in an area where M2 does not exist above M1; After adding M2, the substrate is conformally covered with an oxide material M3; After conformally covering the substrate, a layer of conformal material M6 is deposited; After depositing M6, the substrate is gap-filled with a filling material M4; After the gap filling, the top surface of M6 is removed from the substrate; After removing the top surface of M6, a stop-etching material M5 is selectively grown on the exposed surface of M3 and not on the surface of M4; After selectively growing M5, M4 is removed from the substrate; and After removing M4, the substrate is etched to transfer the pattern into M1.

14. The method according to claim 13, wherein, etching the substrate after removing M4 further includes: etching the exposed surface of M3 in the substrate; and continuing to etch the substrate to transfer the pattern into M1.

15. The method according to claim 13, wherein depositing the layer of M6 includes performing low-damage plasma-enhanced atomic layer deposition (PEALD).

16. The method according to claim 13, wherein removing the top surface of M6 from the substrate after the gap filling includes performing a photo-etching operation to expose the surface of the oxide material.

17. The method according to claim 13, wherein the selective growth of M5 is performed by metal-organic chemical vapor deposition (CVD).

18. The method according to claim 13, wherein after selectively growing M5, removing M4 from the substrate includes removing it by ashing.

19. The method according to claim 13, wherein conformally covering the substrate with M3 includes: performing low-damage plasma-enhanced atomic layer deposition.

20. The method according to claim 13, wherein, M2 is a carbon-based material.

21. The method according to claim 13, wherein, M3 is one of silicon dioxide or aluminum oxide.

22. The method according to claim 13, wherein M4 is CH x Surface.

23. The method according to claim 13, wherein M6 is a fluorocarbon.

24. The method according to claim 13, wherein M5 is a metal oxide or an oxynitride.

25. A semiconductor manufacturing apparatus, which comprises: a processing chamber; and a controller for controlling the processing of a substrate in the processing chamber, wherein the controller causes the processing chamber to perform operations, and the operations include: adding a photoresist material M2 on top of the substrate base material M1, and M2 defines a pattern for etching M1 in an area where M2 does not exist above M1; after adding M2, conformally covering the substrate with an oxide material M3; after conformally covering the substrate, depositing a layer of conformal material M6; after depositing M6, gap-filling the substrate with a filling material M4; after the gap filling, removing the top surface of M6 from the substrate; after removing the top surface of M6, selectively growing a stop-etching material M5 on the exposed surface of M3 and not on the surface of M4; After selectively growing M5, M4 is removed from the substrate; and After removing M4, the substrate is etched to transfer the pattern into M1.

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