Method for preparing semiconductor device

Abstract

The present disclosure provides a method for fabricating a semiconductor device. The method for fabricating the semiconductor device includes providing a target layer; forming a first hard mask layer on the target layer; forming a plurality of second hard mask layers on the first hard mask layer; performing a first inclined etching process on the first hard mask layer to form a plurality of first openings at respective first sides along the first hard mask and adjacent to the second hard mask layers; and performing a second inclined etching process on the first hard mask layer to form a plurality of second openings at respective second sides along the first hard mask layer and adjacent to the second hard mask layers. The first inclined etching process and the second inclined etching process use the second hard mask layers as pattern guides, and the first hard mask layer is transformed into a patterned first hard mask layer through the first openings and the second openings.

Description

Technical Field

[0001] This application claims the priority and benefit of U.S. Formal Application No. 17 / 014,432, filed on September 8, 2020, the content of which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates to a method for manufacturing a semiconductor device. In particular, it relates to a method for manufacturing a semiconductor device using an inclined etching process. Background Art

[0003] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually decreasing to meet the increasing demand for computing power. However, during the process of reducing the size, different problems are increasing, and such problems continue to increase in number and complexity. Therefore, there are still challenges in achieving improved quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of the "prior art" is only provided for background information and does not admit that the above description of the "prior art" discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the "prior art" above should not be taken as any part of this case. Summary of the Invention

[0005] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a target layer; forming a first hard mask layer on the target layer; forming a plurality of second hard mask layers on the first hard mask layer; performing a first inclined etching process on the first hard mask layer to form a plurality of first openings at each first side along the first hard mask layer and adjacent to the second hard mask layer; and performing a second inclined etching process on the first hard mask layer to form a plurality of second openings at each second side along the first hard mask layer and adjacent to the second hard mask layer. The first inclined etching process and the second inclined etching process use the second hard mask layer as a pattern guide, and the first hard mask layer is transformed into a patterned first hard mask layer through the first openings and the second openings.

[0006] In some embodiments, a ratio of a width of the second hard mask layer to a horizontal distance between adjacent pairs of second hard mask layers is approximately 1:2.

[0007] In some embodiments, an incident angle of the first inclined etching process is between approximately 10 degrees and approximately 80 degrees.

[0008] In some embodiments, an incident angle of the second inclined etching process is opposite to that of the first inclined etching process, and a width of the first opening is equal to a width of the second opening.

[0009] In some embodiments, a ratio of the width of the first opening to a horizontal distance between one of the first openings and an adjacent one of the second openings is approximately 1:2.

[0010] In some embodiments, the method for manufacturing the semiconductor device further includes a step of removing the second hard mask.

[0011] In some embodiments, the method for manufacturing the semiconductor device further includes a step of using the patterned first hard mask layer as a mask to pattern the target layer.

[0012] In some embodiments, the target layer includes semiconductor material.

[0013] In some embodiments, the target layer is formed on an isolation layer and includes semiconductor material.

[0014] In some embodiments, the target layer includes conductive material.

[0015] In some embodiments, the target layer includes insulating / isolation material.

[0016] In some embodiments, the method for manufacturing the semiconductor device further includes a step of forming the target layer on an etch stop layer.

[0017] In some embodiments, the etch stop layer includes the following materials: carbon-doped oxide, carbon-incorporated silicon oxide, or nitrogen-doped silicon carbide.

[0018] In some embodiments, the first hard mask layer includes the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, silicon boron nitride, phosphorus boron nitride, boron carbon silicon nitride, or a carbon film.

[0019] In some embodiments, the second hard mask layer includes the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, silicon boron nitride, phosphorus boron nitride, boron carbon silicon nitride, or a carbon film.

[0020] In some embodiments, for the first inclined etching process, the etching rate of the second hard mask layer with respect to the first hard mask layer is between about 1:10 and about 1:100.

[0021] In some embodiments, the ratio of the width of the second hard mask layer to the height of the second hard mask layer is between about 1:1 and about 1:12.

[0022] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The manufacturing method includes: providing a target layer; forming a first hard mask layer on the target layer; forming a plurality of second hard mask layers on the first hard mask layer; performing a first inclined etching process on the first hard mask layer to form a plurality of first openings at respective first sides along the first hard mask layer and adjacent to the second hard mask layers; performing a 180-degree rotation to the target layer; and performing a third inclined etching process on the first hard mask layer to form a plurality of third openings at respective second sides along the first hard mask layer and adjacent to the second hard mask layers. The incident angle of the first inclined etching process is equal to the incident angle of the third inclined etching process.

[0023] In some embodiments, the incident angle of the first inclined etching process is between about 10 degrees and about 80 degrees.

[0024] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The manufacturing method includes: providing a target layer; forming a first hard mask layer on the target layer; forming a plurality of second hard mask layers on the first hard mask layer; and performing a first inclined etching process on the first hard mask layer to form a plurality of first openings at respective first sides along the first hard mask layer and adjacent to the second hard mask layers. The first inclined etching process uses the second hard mask layer as a pattern guide.

[0025] By using the first inclined etching process and the second inclined etching process, the present disclosure can form the first openings and the second openings on the first hard mask layer without an additional lithography process. Therefore, the manufacturing complexity of the semiconductor device can be reduced. In addition, the narrower first openings and the narrower second openings are formed using the second hard mask layer having a plurality of wider hard mask openings. That is, the requirements of the lithography process for forming the narrower first openings and the narrower second openings can be alleviated. Therefore, the yield of the semiconductor device can be improved.

[0026] The technical features and advantages of the present disclosure have been outlined quite extensively above, enabling a better understanding of the following detailed description of the present disclosure. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those having ordinary skill in the art to which the present disclosure pertains should understand that the concepts disclosed below and specific embodiments can be quite easily utilized as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those having ordinary skill in the art to which the present disclosure pertains should also understand that such equivalent constructs cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Referring to the embodiments and considering the drawings in combination with the claims, a more comprehensive understanding of the disclosure of the present application can be obtained. The same reference numerals in the drawings refer to the same elements.

[0028] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0029] Figures 2 to 6 A cross-sectional schematic view illustrating a process of a method for fabricating the semiconductor device according to an embodiment of the present disclosure.

[0030] Figures 7 to 11 A cross-sectional schematic view illustrating a process of a method for fabricating a semiconductor device according to another embodiment of the present disclosure.

[0031] Figures 12 to 16 A cross-sectional schematic view illustrating a process of a method for fabricating a semiconductor device according to another embodiment of the present disclosure.

[0032] Figures 17 to 21 A cross-sectional schematic view illustrating a process of a method for fabricating a semiconductor device according to another embodiment of the present disclosure.

[0033] Figures 22 to 26 A cross-sectional schematic view illustrating a process of a method for fabricating a semiconductor device according to another embodiment of the present disclosure.

[0034] Figure 27 And Figure 28 A cross-sectional schematic view illustrating a process of a method for fabricating a semiconductor device according to another embodiment of the present disclosure.

[0035] Figures 29 to 31 A cross-sectional schematic view illustrating a process of a method for fabricating a semiconductor device according to another embodiment of the present disclosure.

[0036] Figure 32 A top view schematic diagram of an intermediate semiconductor device according to another embodiment of the present disclosure.

[0037] Figure 33Schematic cross-sectional view along cutting line A-A' of a part of the manufacturing method of a semiconductor device according to another embodiment of the present disclosure. Figure 32 of the semiconductor device according to another embodiment of the present disclosure.

[0038] Figure 34 Schematic cross-sectional view of a part of the manufacturing process of the semiconductor device according to another embodiment of the present disclosure.

[0039] Among them, the reference numerals are explained as follows:

[0040] 10: Manufacturing method

[0041] 1A: Semiconductor device

[0042] 1B: Semiconductor device

[0043] 1C: Semiconductor device

[0044] 1D: Semiconductor device

[0045] 1E: Semiconductor device

[0046] 1F: Semiconductor device

[0047] 1G: Semiconductor device

[0048] 1H: Semiconductor device

[0049] 101: Substrate

[0050] 101’: Patterned first substrate

[0051] 103: Etch stop layer

[0052] 105: Disposed substrate

[0053] 107: Isolation layer

[0054] 109: Top semiconductor layer

[0055] 109’: Patterned top semiconductor layer

[0056] 111: Conductive layer

[0057] 111’: Patterned conductive layer

[0058] 113: Dielectric layer

[0059] 113’: Patterned dielectric layer

[0060] 201: First hard mask layer

[0061] 201’: Patterned first hard mask layer

[0062] 201TS: Upper surface

[0063] 301: Second hard mask layer

[0064] 401: First opening

[0065] 403: Second opening

[0066] 405: Third opening

[0067] 407: First contact opening

[0068] 409: Intermediate contact opening

[0069] 411: Second contact opening

[0070] 501: First inclined etching process

[0071] 503: Second inclined etching process

[0072] 505: Third inclined etching process

[0073] 601: Hard mask opening

[0074] D1: Horizontal distance

[0075] D2: Horizontal distance

[0076] FS: First side

[0077] H1: Height

[0078] S11: Step

[0079] S13: Step

[0080] S15: Step

[0081] S17: Step

[0082] S19: Step

[0083] SS: Second side

[0084] W1: Width

[0085] W2: Width

[0086] W3: Width

[0087] W4: Width

[0088] Z: Direction

[0089] α: Angle of incidence

[0090] β: Angle of incidence

[0091] γ: Angle of incidence Detailed implementation manners

[0092] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. For example, when it is described that a first component is formed on a second component, it may include embodiments where the first and second components are in direct contact, or it may also include embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, embodiments of the present disclosure may repeat reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between various embodiments and / or the configurations being discussed.

[0093] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0094] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments where these components are in direct contact, and it may also include embodiments where additional components are formed between these components such that these components are not in direct contact.

[0095] It should be understood that although terms such as first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Thus, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0096] Unless otherwise indicated in the context, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as "same", "equal", "planar", or "coplanar" as used herein do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but rather mean within acceptable variations that include nearly identical orientation, layout, location, shape, size, amount, or other measure, and for example, such acceptable variations can occur due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, substantially the same, substantially equal, or substantially planar means exactly the same, equal, or planar, or that it is the same, equal, or planar within acceptable variations, and for example, such acceptable variations can occur due to manufacturing processes.

[0097] In the present disclosure, a semiconductor element generally means an element that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of semiconductor elements.

[0098] It should be understood that in the description of the present disclosure, "above" (or "up") corresponds to the direction of the Z-direction arrow, and "below" (or "down") corresponds to the opposite direction of the Z-direction arrow.

[0099] Figure 1 Schematic flowchart of a method 10 for preparing a semiconductor element 1A illustrating an embodiment of the present disclosure. Figures 2 to 6 Cross-sectional schematic view of a process of the method for preparing the semiconductor element 1A illustrating an embodiment of the present disclosure. Please refer to Figure 1 andFigure 2 In step S11, a substrate 101 can be provided, a first hard mask layer 201 can be formed on the substrate 101, and a plurality of second hard mask layers 301 can be formed on the first hard mask layer 201.

[0100] Please refer to Figure 2 In some embodiments, the substrate 101 can be a bulk semiconductor substrate, which is entirely composed of at least one semiconductor material; the bulk semiconductor substrate does not contain any dielectric, isolation layer, or conductive feature. For example, the bulk semiconductor substrate includes elemental semiconductors, compound semiconductors, non-semiconductor materials, other suitable materials, or combinations thereof; the elemental semiconductor is, for example, silicon or germanium; the compound semiconductor is, for example, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors; the non-semiconductor material is, for example, soda-lime glass, fused silica, fused quartz, calcium fluoride.

[0101] Please refer to Figure 2 In some embodiments, for example, the first hard mask layer 201 can include the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, analogs, or combinations thereof. The first hard mask layer 201 can be formed by a plurality of deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or similar processes.

[0102] It should be understood that in the description of the present disclosure, silicon oxynitride represents a substance that contains silicon, nitrogen, and oxygen, and in which the ratio of oxygen is greater than the ratio of nitrogen. Silicon nitride oxide represents a substance that contains silicon, oxygen, and nitrogen, and in which the ratio of nitrogen is greater than the ratio of oxygen.

[0103] Alternatively, in some embodiments, for example, the first hard mask layer 201 may comprise the following materials: boron nitride, silicon boron nitride, phosphorus boron nitride, or boron carbon silicon nitride. The first hard mask layer 201 may be formed by a film formation process and a treatment process. In particular, in the film formation process, a plurality of first precursors, which may be boron-based precursors, may be introduced onto the substrate 101 to form a boron layer. Next, in the treatment process, a plurality of second precursors, which may be nitrogen-based precursors, may be introduced to react with the boron layer and transform the boron layer into the first hard mask layer 201.

[0104] In some embodiments, for example, the first precursor may be diborane, borazine, or an alkyl-substituted derivative of borazine. In some embodiments, the first precursor may be introduced at a flow rate that is between approximately 5 sccm (standard cubic centimeter per minute) and approximately 50 slm (standard liter per minute); in particular, between approximately 10 sccm and approximately 1 slm. In some embodiments, the first precursor may be introduced through a dilution gas, such as nitrogen, hydrogen, argon, or a combination thereof. The dilution gas may be introduced at a flow rate that is between approximately 5 sccm and approximately 50 slm; in particular, between approximately 1 slm and approximately 10 slm.

[0105] In some embodiments, the film formation process may be performed without the assistance of plasma. In this case, the substrate temperature of the film formation process may be between approximately 100 °C and approximately 1000 °C. For example, the substrate temperature of the film formation process may be between approximately 300 °C and approximately 500 °C. The process pressure of the film formation process may be between approximately 10 mTorr and approximately 760 Torr. For example, the process pressure of the film formation process may be between approximately 2 Torr and approximately 10 Torr.

[0106] In some embodiments, the film forming process can be carried out in the presence of plasma. In this case, a substrate temperature of the film forming process can be between about 100 °C and about 1000 °C. For example, the substrate temperature of the film forming process can be between about 300 °C and about 500 °C. A process temperature of the film forming process can be between about 10 mTorr and about 760 Torr. For example, the process temperature of the film forming process can be between about 2 Torr and about 10 Torr. The plasma is provided by a radio frequency power (RF power) between 30 W and 1000 W.

[0107] In some embodiments, for example, the second precursor can be ammonia or hydrazine. In some embodiments, the second precursor can be introduced at a flow rate that is between about 5 sccm and about 50 slm; in particular, between about 10 sccm and about 1 slm.

[0108] In some embodiments, a plurality of oxygen-based precursors can be introduced together with the second precursor in the processing process. For example, the oxygen-based precursor can be oxygen, nitric oxide, nitrous oxide, carbon dioxide or water.

[0109] In some embodiments, a plurality of silicon-based precursors can be introduced together with the second precursor in the processing process. For example, the silicon-based precursor can be silane, trisilylamine, trimethylsilane, and silazanes (such as hexamethylcyclotrisilazane).

[0110] In some embodiments, a plurality of phosphorus-based precursors can be introduced together with the second precursor in the processing process. For example, the phosphorus-based precursor can be phosphine.

[0111] In some embodiments, the oxygen-based precursor, the silicon-based precursor or the phosphorus-based precursor can be introduced together with the second precursor in the processing process. In some embodiments, the processing process can be performed with the assistance of a plasma process, an ultraviolet curing (UV cure) process, a thermal annealing (thermal anneal) process, or a combination thereof.

[0112] When the process is performed with a plasma process as an aid, the plasma of the plasma process can be provided by radio frequency power (RF power). In some embodiments, at a single low frequency between approximately 100 kHz and approximately 1 MHz, the RF power can be between approximately 2 W and approximately 5000 W. In some embodiments, at a single high frequency greater than approximately 13.6 MHz, the RF power can be between approximately 30 W and approximately 1000 W. In this case, a substrate temperature of the processing can be between approximately 20°C and approximately 1000°C. A process pressure of the processing can be between approximately 10 mTorr and approximately 760 Torr.

[0113] When the process is performed with an ultraviolet curing process as an aid, in this case, a substrate temperature of the processing can be between approximately 20°C and approximately 1000°C. A process temperature of the processing can be between approximately 10 mTorr and approximately 760 Torr. Ultraviolet curing can be provided by any ultraviolet source, such as a mercury microwave arc, pulsed xenon flash lamps, or high-efficiency UV light emitting diode arrays. The ultraviolet source can have a wavelength between approximately 170 nm and approximately 400 nm. The ultraviolet source can provide a photon energy between approximately 0.5 eV and approximately 10 eV; in particular, between approximately 1 eV and approximately 6 eV. The aid of the ultraviolet curing process can remove hydrogen from the first hard mask layer 201. When hydrogen can diffuse into other regions of the semiconductor element 1A and may reduce the reliability of the semiconductor element 1A, the removal of hydrogen by the aid of the ultraviolet curing process can improve the reliability of the semiconductor element 1A. In addition, the ultraviolet curing process can increase the density of the first hard mask layer 201.

[0114] When the process is performed with a thermal annealing process as an aid, in this situation, a substrate temperature of the processing can be between approximately 20°C and approximately 1000°C. A process pressure of the processing can be between approximately 10 mTorr and approximately 760 Torr.

[0115] In some embodiments, for example, the first hard mask layer 201 may comprise a carbon film. As used herein, the term "carbon film" is defined primarily by a plurality of carbon atoms, or its physical and chemical properties depend on its carbon content. The term "carbon film" refers to materials that exclude materials that are simple mixtures or compounds containing carbon. For example, materials containing carbon compounds are dielectric materials, such as silicon oxynitride doped with carbon, silicon oxide doped with carbon, or polysilicon doped with carbon. For example, these terms do include graphite, charcoal, and halocarbons.

[0116] In some embodiments, the carbon film is deposited by a process that includes introducing a process gas mixture into a process chamber, the process gas mixture being composed of one or more hydrocarbon compounds. The hydrocarbon compound has a chemical formula C x H y , where x has a range between 2 and 4, and y has a range between 2 and 10. For example, the hydrocarbon compound can be propylene (C3H6), propyne (C3H4), propane (C3H8), butane (C4H 10 ), butylene (C4H8), butadiene (C4H6), acetylene (C2H2), or a combination thereof.

[0117] In some embodiments, partially or fully fluorinated derivatives of hydrocarbon compounds can be used. Doped derivatives include boron-containing derivatives of hydrocarbon compounds and their fluorinated derivatives. The fluorinated hydrocarbon compound has a chemical formula C x H y F z , where x has a range between 2 and 4, y has a range between 0 and 10, z has a range between 0 and 10, and y + z is greater than or equal to 2, or less than or equal to 10. Some examples include fully fluorinated hydrocarbons, such as C3F8 or C4F8, which can be used to deposit a fluorocarbon film. In addition, the hydrocarbon compound may contain nitrogen, or be deposited with a nitrogen-containing gas, such as ammonia.

[0118] In some embodiments, a combination of a hydrocarbon compound and a fluorinated derivative of the hydrocarbon compound can be used together to deposit a carbon film. In some embodiments, the hydrocarbon compound and its fluorinated derivative can be used to deposit a carbon film, and the hydrocarbon compound includes alkanes, alkenes, alkynes, cyclic compounds, and aromatic compounds, which have five or more carbons, such as pentane, benzene, and toluene.

[0119] In some embodiments, the carbon film is deposited from a process gas mixture by maintaining a substrate temperature between about 100 °C and about 700 °C; in particular, between about 350 °C and 550 °C. In some embodiments, the carbon film is deposited from a process gas mixture by maintaining a chamber pressure between about 1 Torr and about 20 Torr. The carbon film can be deposited from the process gas mixture by introducing a hydrocarbon gas and any inert or reactive gas at a flow rate between about 50 sccm and about 2000 sccm. In some embodiments, the carbon film can be deposited with plasma assistance, and the plasma is generated by applying an RF power between about 0.03 W / cm 2 and about 20 W / cm 2 or between 10 W and about 6000 W, for example, between about 0.3 W / cm 2 and about 3 W / cm 2 or between 100 W and about 1000 W.

[0120] In some embodiments, a dual-frequency system can be provided to deposit a carbon film. A dual-frequency source that mixes RF power provides a high-frequency power and a low-frequency power. The high-frequency power can be in a range between about 10 MHz and about 30 MHz, for example, about 13.56 MHz. The low-frequency power can be in a range between about 100 KHz and about 500 KHz, for example, about 350 KHz.

[0121] In some embodiments, the process gas mixture may further include an inert gas, such as argon. However, other inert gases may be used, such as nitrogen or other noble gases, and the noble gas may be, for example, helium. The inert gas can be used to control the density and deposition rate of the carbon film. In addition, a variety of different gases can be added to the process gas mixture to change the characteristics of the carbon film. The gas can be a reactive gas, such as hydrogen, ammonia, a mixture of hydrogen and nitrogen, or a combination thereof. The addition of hydrogen or ammonia can be used to control the hydrogen ratio of the carbon film, thereby controlling layer characteristics, such as etch selectivity, chemical mechanical polishing resistance characteristics, and reflectivity. In some embodiments, a mixture of the reactive gas and the inert gas can be added to the process gas mixture to deposit the carbon film.

[0122] The carbon film may include carbon and hydrogen atoms, and it can have an adjustable carbon:hydrogen ratio, which is between about 10% hydrogen and about 60% hydrogen. Controlling the hydrogen proportion of the carbon film can adjust the corresponding etch selectivity and chemical mechanical polishing resistance characteristics. When the hydrogen content decreases, the etch resistance and selectivity of the carbon film increase. When an etching process is performed to transfer a desired pattern to the underlying layer, the reduction in the carbon film removal rate can make the carbon film suitable as a mask layer.

[0123] Please refer to Figure 2 , in some embodiments, for example, the second hard mask layer 301 may include the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or a combination thereof. The second hard mask layer 301 can be formed by a plurality of deposition processes, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, or the like.

[0124] Alternatively, in some embodiments, for example, the second hard mask layer 301 may include the following materials: boron nitride, boron silicon nitride, boron phosphorus nitride, or boron carbon silicon nitride. The second hard mask layer 301 can be formed by a film formation process and a treatment process similar to those of the first hard mask layer 201.

[0125] In some embodiments, for example, the second hard mask layer 301 may include a carbon film. The second hard mask layer 301 can be formed by a process similar to that of the first hard mask layer 201 using a process gas mixture.

[0126] The second hard mask layer 301 and the first mask layer 201 may include different materials; in particular, during the subsequent processes, the second hard mask layer 301 and the first mask layer 201 can be formed of materials having etch selectivity with respect to each other.

[0127] Please refer to Figure 2, in a cross-sectional view, each second hard mask layer 301 has a rectangular cross-sectional profile. For ease of description, only one second hard mask layer 301 is described. The second hard mask layer 301 may include two sides, namely a first side FS and a second side SS. The first side FS and the second side SS are disposed opposite to each other. The first side FS and the second side SS are perpendicular to the upper surface 201TS of the first hard mask layer 201.

[0128] Please refer to Figure 2 , the spaces between adjacent pairs of second hard mask layers 301 can be regarded as a plurality of hard mask openings 601. In some embodiments, the ratio of the width W1 of the second hard mask layer 301 to the horizontal distance D1 between adjacent pairs of second hard mask layers 301 may be between approximately 1:3 and approximately 2:3. In some embodiments, the ratio of the width W1 of the second hard mask layer 301 to the horizontal distance D1 between adjacent pairs of second hard mask layers 301 may be approximately 1:2. It should be understood that the horizontal distance D1 between adjacent pairs of second hard mask layers 301 may be the same as the width W2 of the hard mask opening 601, or the same as the horizontal distance between the first side FS of one second hard mask layer 301 and the second side SS of an adjacent second hard mask layer 301. In some embodiments, a ratio of the width W1 of the second hard mask layer 301 to the height H1 of the hard mask opening 601 (e.g., the height of the second hard mask layer 301) may be between approximately 3:1 and approximately 1:12, between approximately 1:1 and approximately 1:12, between approximately 1:1 and approximately 1:8, or between approximately 1:2 and approximately 1:6.

[0129] Refer to Figure 1 and Figure 3 , in step S13, a first inclined etching process 501 may be performed on the first hard mask layer 201 to form a plurality of first openings 401, and the first openings 401 are disposed along the first hard mask layer 201.

[0130] Please refer to Figure 3, the first inclined etching process 501 can use the second hard mask layer 301 as pattern guides to remove some parts of the first hard mask layer 201 and simultaneously form the first opening 401 at each first side FS along the first hard mask 201 and adjacent to the second hard mask layer 301. In some embodiments, the incident angle α of the first inclined etching process 501 can be defined by the width W2 and the height H1 of the hard mask opening 601. In some embodiments, the incident angle α of the first inclined etching process 501 can be between about 10 degrees and about 80 degrees. In some embodiments, the incident angle α of the first inclined etching process 501 can be between about 20 degrees and about 60 degrees. In some embodiments, the incident angle α of the first inclined etching process 501 can be between about 20 degrees and about 40 degrees.

[0131] In some embodiments, the first inclined etching process 501 can be an anisotropic etching process, such as a reactive ion etching process. The reactive ion etching process can include a plurality of etchant gases and a plurality of passivation gases, which may inhibit the isotropic effect to limit the removal of materials in the horizontal direction. The etchant gases can include chlorine gas and boron trichloride. The passivation gases can include fluoroform or other suitable halocarbons. In some embodiments, the second hard mask layer 301 containing a carbon film can serve as a source of a halocarbon for the passivation gas in the reactive ion etching process.

[0132] In some embodiments, the etching rate of the first hard mask layer 201 in the first inclined etching process 501 may be faster than the etching rate of the second hard mask layer 301 in the first inclined etching process 501. For example, during the first inclined etching process 501, the etching rate ratio of the first hard mask layer 201 to the second hard mask layer 301 may be between approximately 100:1 and approximately 1.05:1, between approximately 100:1 and approximately 10:1, between approximately 50:1 and approximately 10:1, between approximately 30:1 and approximately 10:1, between approximately 20:1 and approximately 10:1, or between approximately 15:1 and approximately 10:1. In some embodiments, during the first inclined etching process 501, the etching rate ratio of the first hard mask layer 201 to a substrate 101 may be between approximately 100:1 and approximately 1.05:1, between approximately 100:1 and approximately 10:1, between approximately 50:1 and approximately 10:1, between approximately 30:1 and approximately 10:1, between approximately 20:1 and approximately 10:1, or between approximately 15:1 and approximately 10:1.

[0133] In some embodiments, a ratio of a width W3 of the first opening 401 to a width W1 of the second hard mask layer 301 may be between approximately 1:3 and approximately 2:3. In some embodiments, a ratio of the width W3 of the first opening 401 to the width W1 of the second hard mask layer 301 may be approximately 1:2. In some embodiments, a ratio of the width W3 of the first opening 401 to a width W2 of a hard mask opening 601 may be between approximately 1:5 and approximately 2:5. In some embodiments, a ratio of the width W3 of the first opening 401 to the width W2 of the hard mask opening 601 may be approximately 1:4.

[0134] Please refer to Figure 1 and Figure 4 , in step S15, a second inclined etching process 503 may be performed on the first hard mask layer 201 to form a plurality of second openings 403, and the second openings 403 are disposed along the first hard mask layer 201.

[0135] Please refer to Figure 4 , the second inclined etching process 503 may use the second hard mask layer 301 as a plurality of pattern guides to remove some portions of the first hard mask layer 201 and simultaneously form the second openings 403, and the second openings 403 are at respective second sides SS along the first hard mask layer 201 and adjacent to the second hard mask layer 301.

[0136] In some embodiments, the incident angle β of the second inclined etching process 503 can be defined by the width W2 of the hard mask opening 601 and the height of the hard mask opening 601. In some embodiments, the incident angle β of the second inclined etching process can have the same value as the incident angle α of the first inclined etching process, but the incident direction of the second inclined etching process 503 can be opposite to that of the first inclined etching process 501. In other words, the incident angle β of the second inclined etching process is opposite to the incident angle α of the first inclined etching process. In this case, the width W4 of the second opening 403 can be equal to the width W3 of the first opening 401. The ratio of the width W3 of the first opening 401 (or the width W4 of the second opening 403) to a horizontal distance D2 between one of the first openings 401 and an adjacent one of the second openings 403 can be between about 1:3 and about 2:3, or can be 1:2.

[0137] In some embodiments, the second inclined etching process 503 can be an anisotropic etching process, such as a reactive ion etching process. The process parameters of the second inclined etching process 503 can be the same as those of the first inclined etching process 501, except for the incident angle. In some embodiments, the incident angle β of the second inclined etching process 503 can be between about -10 degrees and about -80 degrees. In some embodiments, the incident angle β of the second inclined etching process 503 can be between about -20 degrees and about -60 degrees. In some embodiments, the incident angle β of the second inclined etching process 503 can be between about -20 degrees and about -40 degrees.

[0138] In some embodiments, the ratio of the width W4 of the two openings 403 to the width W1 of the second hard mask layer 301 can be between about 1:3 and about 2:3. In some embodiments, the ratio of the width W4 of the two openings 403 to the width W1 of the second hard mask layer 301 can be approximately 1:2. In some embodiments, the ratio of the width W4 of the two openings 403 to the width W2 of the hard mask opening 601 can be between about 1:5 and about 2:5. In some embodiments, the ratio of the width W4 of the two openings 403 to the width W2 of the hard mask opening 601 can be approximately 1:4.

[0139] In some embodiments, between the second inclined etching processes 503, an etching rate ratio of the first hard mask layer 201 to the second hard mask layer 301 may be between approximately 100:1 and approximately 1.05:1, between approximately 100:1 and approximately 10:1, between approximately 50:1 and approximately 10:1, between approximately 30:1 and approximately 10:1, between approximately 20:1 and approximately 10:1, or between approximately 15:1 and approximately 10:1. In some embodiments, between the second inclined etching processes 503, an etching rate ratio of the first hard mask layer 201 to the substrate 101 may be between approximately 100:1 and approximately 1.05:1, between approximately 100:1 and approximately 10:1, between approximately 50:1 and approximately 10:1, between approximately 30:1 and approximately 10:1, between approximately 20:1 and approximately 10:1, or between approximately 15:1 and approximately 10:1.

[0140] Please refer to Figure 4 , after the first inclined etching process 501 and the second inclined etching process 503, through the first opening 401 and the second opening 403, the first hard mask layer 201 can be patterned into a patterned first hard mask layer 201'.

[0141] Please refer to Figure 1 and Figure 5 , in step S17, the second hard mask layer 301 can be removed.

[0142] Please refer to Figure 5 , a hard mask etching process can be performed to remove the second hard mask layer 301. In some embodiments, between the hard mask etching processes, an etching rate ratio of the second hard mask layer 301 to the patterned first hard mask layer 201' may be between approximately 100:1 and approximately 1.05:1, between approximately 100:1 and approximately 10:1, between approximately 50:1 and approximately 10:1, between approximately 30:1 and approximately 10:1, between approximately 20:1 and approximately 10:1, or between approximately 15:1 and approximately 10:1. In some embodiments, between the hard mask etching processes, an etching rate ratio of the second hard mask layer 301 to the substrate 101 may be between approximately 100:1 and approximately 1.05:1, between approximately 100:1 and approximately 10:1, between approximately 50:1 and approximately 10:1, between approximately 30:1 and approximately 10:1, between approximately 20:1 and approximately 10:1, or between approximately 15:1 and approximately 10:1. In some embodiments, the hard mask etching process can be an isotropic etching process or an anisotropic etching process.

[0143] Please refer to Figure 1 andFigure 6 In step S19, the substrate 101 may be patterned using the patterned first hard mask layer 201’ as a mask.

[0144] Please refer to Figure 6 An etch process for a target layer may be performed to remove some portions of the substrate 101. After the etch process for the target layer, the substrate 101 may be transformed into a patterned first substrate 101’. In some embodiments, during the etch process for the target layer, the etch rate ratio of the substrate 101 to the patterned first hard mask layer 201’ may be between about 100:1 and about 1.05:1, between about 100:1 and about 10:1, between about 50:1 and about 10:1, between about 30:1 and about 10:1, between about 20:1 and about 10:1, or between about 15:1 and about 10:1. The protrusion portions of the patterned first substrate 101’ may be used as fin structures of the semiconductor element 1A. After the patterned first substrate 101’ is formed, the patterned first hard mask layer 201’ may be removed.

[0145] By employing the first inclined etch process 501 and the second inclined etch process 503 using the second hard mask layer 301 as a pattern guide, the first opening 401 and the second opening 403 may be formed on the first hard mask layer 201 without an additional lithography process. Therefore, the manufacturing complexity of the semiconductor element 1A can be reduced. In addition, the narrower first opening 401 and the narrower second opening 403 may be formed using the second hard mask layer 301 having the wider hard mask opening 601. That is, the requirements for the lithography process for forming the narrower first opening 401 and the narrower second opening 403 can be alleviated. Therefore, the yield of the semiconductor element 1A can be improved.

[0146] Figures 7 to 11 A cross-sectional schematic diagram of a process flow for manufacturing a semiconductor element 1B according to another embodiment of the present disclosure. Please refer to Figure 7 which shows an intermediate semiconductor element having a structure that is similar to the structure of the intermediate semiconductor element illustrated in Figure 2 and is formed by a process similar to the process of the intermediate semiconductor element illustrated in Figure 2 . Elements that are the same or similar in Figure 7 and Figure 2 have been labeled with similar element numbers, and repeated descriptions have been omitted.

[0147] Please refer to Figure 7, in some embodiments, an etch stop layer 103 may be formed on a substrate 101, and a first hard mask layer 201 may be formed on the etch stop layer 103. For example, the etch stop layer 103 may include the following materials: carbon-doped oxide, carbon incorporated silicon oxide, or nitrogen-doped silicon carbide.

[0148] Please refer to Figure 8 , a process similar to that exemplified in Figure 3 may be performed. In some embodiments, during a first angled etch process 501, an etch rate ratio of the first hard mask layer 201 to the etch stop layer 103 may be between approximately 100:1 and approximately 10:1 or between approximately 15:1 and approximately 10:1. During the first angled etch process 501, the etch stop layer 103 may provide additional protection to the underlying substrate 101.

[0149] Please refer to Figure 9 , a process similar to that exemplified in Figure 4 may be performed. In some embodiments, during a second angled etch process 503, an etch rate ratio of the first hard mask layer 201 to the etch stop layer 103 may be between approximately 100:1 and approximately 10:1 or between approximately 15:1 and approximately 10:1. During the second angled etch process 503, the etch stop layer 103 may provide additional protection to the underlying substrate 101.

[0150] Please refer to Figure 10 , a process similar to that exemplified in Figure 5 may be performed. In some embodiments, during a hard mask etch process, an etch rate ratio of the second hard mask layer 301 to the etch stop layer 103 may be between approximately 100:1 and approximately 10:1 or between approximately 15:1 and approximately 10:1. During the hard mask etch process, the etch stop layer 103 may provide additional protection to the underlying substrate 101.

[0151] Please refer to Figure 11 , a process similar to that exemplified in Figure 6 may be performed. In some embodiments, during a target layer etch process, an etch rate ratio of the etch stop layer 103 to the patterned first hard mask layer 201' may be between approximately 100:1 and approximately 10:1 or between approximately 15:1 and approximately 10:1.

[0152] Figures 12 to 16A cross-sectional schematic view of a process for manufacturing a semiconductor device 1C illustrating another embodiment of the present disclosure. Please refer to Figure 12 which shows an intermediate semiconductor device having a structure similar to that of the intermediate semiconductor device illustrated in Figure 2 and formed by a process similar to that of the intermediate semiconductor device illustrated in Figure 2 . Components that are the same or similar in Figure 12 and Figure 2 have been labeled with similar component numbers, and repeated descriptions have been omitted.

[0153] Please refer to Figure 12 where a handle substrate 105 can be provided. An isolation layer 107 can be formed on the handle substrate 105. A top semiconductor layer 109 can be formed on the isolation layer 107. The handle substrate 105, the isolation layer 107, and the top semiconductor layer 109 together form a semiconductor-on-insulator structure. The handle substrate 105 and the top semiconductor layer 109 can comprise the same material as the substrate 101 illustrated in Figure 2 . The isolation layer can be a crystalline or non-crystalline dielectric material, such as an oxide and / or a nitride. The isolation layer can have a thickness ranging from about 10 nm to about 200 nm. A first hard mask layer 201 can be formed on the top semiconductor layer 109. The second hard mask layer 301 can be formed on the first hard mask layer 201.

[0154] Please refer to Figure 13 where a process similar to that illustrated in Figure 3 can be performed. In some embodiments, during the first inclined etching process 501, the etching rate ratio of the first hard mask layer 201 to the top semiconductor layer 109 can be between about 100:1 and about 10:1 or between about 15:1 and about 10:1.

[0155] Please refer to Figure 14 where a process similar to that illustrated in Figure 4 can be performed. In some embodiments, during the second inclined etching process 503, the etching rate ratio of the first hard mask layer 201 to the top semiconductor layer 109 can be between about 100:1 and about 10:1 or between about 15:1 and about 10:1.

[0156] Please refer to Figure 15 where a process similar to that illustrated in Figure 5An exemplary process. In some embodiments, during the hard mask etching process, the etching rate ratio of the second hard mask layer 301 to the top semiconductor layer 109 may be between approximately 100:1 and approximately 10:1 or between approximately 15:1 and approximately 10:1.

[0157] Please refer to Figure 16 , a process similar to that exemplified in Figure 6 may be performed. In some embodiments, during the target layer etching process, the etching rate ratio of the top semiconductor layer 109 to the patterned first hard mask layer 201' may be between approximately 100:1 and approximately 10:1 or between approximately 15:1 and approximately 10:1. In some embodiments, during the target layer etching process, the etching rate ratio of the top semiconductor layer 109 to the isolation layer 107 may be between approximately 100:1 and approximately 10:1 or between approximately 15:1 and approximately 10:1. After the target layer etching process, the top semiconductor layer 109 may be patterned into a patterned top semiconductor layer 109' and may serve as the fin structures of the semiconductor device 1C.

[0158] Figures 17 to 21 A cross-sectional schematic view of a process flow for manufacturing a semiconductor device 1D according to another embodiment of the present disclosure.

[0159] Please refer to Figure 17 , which shows an intermediate semiconductor device having a structure similar to that of the intermediate semiconductor device exemplified in Figure 2 and is formed by a process similar to that of the intermediate semiconductor device exemplified in Figure 2 . Elements that are the same or similar in Figure 17 and Figure 2 are labeled with similar element numbers, and repeated descriptions are omitted.

[0160] Please refer to Figure 17, a conductive layer 111 may be formed on a substrate 101, and a first hard mask layer 201 may be formed on the conductive layer 111. The substrate 101 may include a plurality of dielectrics, a plurality of isolation layers, or a plurality of conductive features disposed on a bulk semiconductor substrate. For example, the dielectric or the isolation layer may include the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, analogs, or combinations thereof. Each dielectric or each isolation layer may have a thickness between about 0.5 μm and about 3.0 μm. The low-k dielectric material may have a dielectric constant less than 3.0, or even less than 2.5. The conductive features may be conductive lines, conductive vias, conductive contacts, or the like. For example, the conductive layer 111 may include the following materials: copper, aluminum, titanium, tungsten, analogs, or combinations thereof.

[0161] Please refer to Figure 18 , a process similar to that exemplified in Figure 3 may be performed. In some embodiments, during the first inclined etching process 501, the etching rate ratio of the first hard mask layer 201 to the conductive layer 111 may be between about 100:1 and about 10:1 or between about 15:1 and about 10:1.

[0162] Please refer to Figure 19 , a process similar to that exemplified in Figure 4 may be performed. In some embodiments, during the second inclined etching process 503, the etching rate ratio of the first hard mask layer 201 to the conductive layer 111 may be between about 100:1 and about 10:1 or between about 15:1 and about 10:1.

[0163] Please refer to Figure 20 , a process similar to that exemplified in Figure 3 may be performed. In some embodiments, during the hard mask etching process, the etching rate ratio of the second hard mask layer 301 to the conductive layer 111 may be between about 100:1 and about 10:1 or between about 15:1 and about 10:1.

[0164] Please refer to Figure 21 , a process similar to that exemplified in Figure 6An illustrated process. In some embodiments, during the target layer etching process, the etching rate ratio of the conductive layer 111 to the patterned first hard mask layer 201' can be between approximately 100:1 and approximately 10:1 or between approximately 15:1 and approximately 10:1. After the target layer etching process, the conductive layer 111 can be patterned into a patterned conductive layer 111' and can serve as the conductive lines of the semiconductor element 1D.

[0165] Figures 22 to 26 A cross-sectional schematic diagram of a process flow for manufacturing a semiconductor element 1E according to another embodiment of the present disclosure.

[0166] Please refer to Figure 22 , which shows an intermediate semiconductor element having a structure similar to that of the intermediate semiconductor element illustrated in Figure 2 and is formed by a process similar to that of the intermediate semiconductor element illustrated in Figure 2 . Elements that are the same as or similar to those in Figure 22 and Figure 2 are labeled with similar element numbers, and repeated descriptions are omitted.

[0167] Please refer to Figure 22 , a dielectric layer 113 can be formed on the substrate 101, and a first hard mask layer 201 can be formed on the dielectric layer 113. For example, the dielectric layer 113 can include the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, analogs, or combinations thereof.

[0168] Please refer to Figure 23 , a process similar to that illustrated in Figure 3 can be performed. In some embodiments, during the first inclined etching process 501, the etching rate ratio of the first hard mask layer 201 to the dielectric layer 113 can be between approximately 100:1 and approximately 10:1 or between approximately 15:1 and approximately 10:1.

[0169] Please refer to Figure 24 , a process similar to that illustrated in Figure 4 can be performed. In some embodiments, during the second inclined etching process 503, the etching rate ratio of the first hard mask layer 201 to the dielectric layer 113 can be between approximately 100:1 and approximately 10:1 or between approximately 15:1 and approximately 10:1.

[0170] Please refer to Figure 25 , a process similar to that exemplified by Figure 5 can be performed. In some embodiments, during the hard mask etching process, the etching rate ratio of the second hard mask layer 301 to the dielectric layer 113 can be between approximately 100:1 and approximately 10:1 or between approximately 15:1 and approximately 10:1.

[0171] Please refer to Figure 26 , a process similar to that exemplified by Figure 6 can be performed. In some embodiments, during the target layer etching process, the etching rate ratio of the dielectric layer 113 to the patterned first hard mask layer 201' can be between approximately 100:1 and approximately 10:1 or between approximately 15:1 and approximately 10:1. After the target layer etching process, the dielectric layer 113 can be patterned into a patterned dielectric layer 113'. A conductive material can be deposited on the patterned dielectric layer 113', and then a planarization process, such as chemical mechanical polishing, can be performed to form multiple conductive features of the semiconductor element 1E in the patterned dielectric layer 113'.

[0172] Figure 27 and Figure 28 A cross-sectional schematic diagram of a process flow for manufacturing a semiconductor element 1F according to another embodiment of the present disclosure.

[0173] Please refer to Figure 27 , an intermediate semiconductor structure and a process similar to that exemplified by Figure 3 can be provided and performed. Please refer to Figure 28 , the second hard mask layer 301 can be removed in a process similar to that exemplified by Figure 5 , and the substrate 101 can be patterned using the first hard mask layer 201 having the first opening 401 as a mask and in a process similar to that exemplified by Figure 6 . After the target layer etching process, the substrate 101 can be transformed into a patterned first substrate 101'. It should be understood that in the embodiment, only the first inclined etching process 501 is performed.

[0174] Figures 29 to 31 A cross-sectional schematic diagram of a process flow for manufacturing a semiconductor element 1G according to another embodiment of the present disclosure.

[0175] Please refer to Figure 29 , an intermediate semiconductor structure and a process similar to that exemplified by Figure 3 can be provided and performed. Please refer to Figure 30 , the intermediate semiconductor can be rotated 180 degrees by rotating the substrate 101.

[0176] Please refer toFigure 31 , a third inclined etching process 505 can be performed on the first hard mask layer 201 to form a plurality of third openings 405, and the third openings 405 are at each second side along the first hard mask layer 201 and adjacent to the second hard mask layer 301. The third inclined etching process 505 can have the same parameters as the first inclined etching process 501. For example, the incident angle γ of the third inclined etching process 505 can be the same as the incident angle α of the first inclined etching process 501. The dimension of the third opening 405 can be the same as the dimension of the first opening 501. The first hard mask layer 201 can be patterned through the first opening 401 and the second opening 405.

[0177] By rotating the intermediate semiconductor element, the settings of the equipment for performing the first inclined etching process 501 can continue to be used to perform the third inclined etching process 505. The deviation of changing the settings (such as the incident angle) of the equipment can be reduced. Therefore, the quality of the semiconductor element 1G can be improved.

[0178] Figure 32 A top view schematic diagram of an intermediate semiconductor element illustrating another embodiment of the present disclosure. Figure 33 An example of a cross-sectional schematic diagram along the cutting line A-A' of a part of the process flow of a method for manufacturing a semiconductor element 1H according to another embodiment of the present disclosure. Figure 32 A cross-sectional schematic diagram of a part of the process flow of the method for manufacturing the semiconductor element 1H according to another embodiment of the present disclosure. Figure 34 A cross-sectional schematic diagram of a part of the process flow of the method for manufacturing the semiconductor element 1H according to another embodiment of the present disclosure.

[0179] Please refer to Figure 33 and Figure 34 , the space between the second hard mask layers 301 can be regarded as a first contact opening 407. In a top view, the first contact opening 407 can have a circular shape. The first inclined etching process 501 can be performed using the second hard mask layer 301 as a pattern guide to remove a part of the first hard mask layer 201, thereby forming an intermediate contact opening 409 therein. When performing the first inclined etching process 501, the substrate 101 can be rotated to perform a 360-degree rotation on the intermediate semiconductor element.

[0180] Please refer to Figure 33, other portions of the first hard mask layer 201 can also be removed via the first inclined etching process 501 and by rotation. The intermediate contact opening 409 can be extended into a second contact opening 411. A conductive material can be filled in the second contact opening 411 to form a conductive contact of the semiconductor element 1H, and the conductive material is, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (such as tantalum carbide, titanium carbide, magnesium carbide), metal nitrides (such as titanium nitride), transition metal aluminides or a combination thereof.

[0181] An embodiment of the present disclosure provides a method for manufacturing a semiconductor element, including providing a target layer; forming a first hard mask layer on the target layer; forming a plurality of second hard mask layers on the first hard mask layer; performing a first inclined etching process on the first hard mask layer to form a plurality of first openings at each first side along the first hard mask layer and adjacent to the second hard mask layers; and performing a second inclined etching process on the first hard mask layer to form a plurality of second openings at each second side along the first hard mask layer and adjacent to the second hard mask layers. The first inclined etching process and the second inclined etching process use the second hard mask layer as a pattern guide, and the first hard mask layer is transformed into a patterned first hard mask layer through the first openings and the second openings.

[0182] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor element. The manufacturing method includes: providing a target layer; forming a first hard mask layer on the target layer; forming a plurality of second hard mask layers on the first hard mask layer; performing a first inclined etching process on the first hard mask layer to form a plurality of first openings at each first side along the first hard mask layer and adjacent to the second hard mask layers; performing a 180-degree rotation on the target layer; and performing a third inclined etching process on the first hard mask layer to form a plurality of third openings at each second side along the first hard mask layer and adjacent to the second hard mask layers. An incident angle of the first inclined etching process is equal to an incident angle of the third inclined etching process.

[0183] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor element. The manufacturing method includes: providing a target layer; forming a first hard mask layer on the target layer; forming a plurality of second hard mask layers on the first hard mask layer; and performing a first inclined etching process on the first hard mask layer to form a plurality of first openings at each first side along the first hard mask layer and adjacent to the second hard mask layers. The first inclined etching process uses the second hard mask layer as a pattern guide.

[0184] The present disclosure forms the first opening 401 and the second opening 403 on the first hard mask layer 201 by using a first inclined etching process 501 and a second inclined etching process 503, without an additional lithography process. Therefore, the manufacturing complexity of the semiconductor device 1A can be reduced. In addition, the narrower first opening 401 and the narrower second opening 403 are formed by using the second hard mask layer 301 having a plurality of wider hard mask openings 601. That is, the requirements of the lithography process for forming the narrower first opening 401 and the narrower second opening 403 can be alleviated. Therefore, the yield of the semiconductor device 1A can be improved.

[0185] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0186] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A method for fabricating a semiconductor device, comprising: providing a target layer; forming a first hard mask layer on the target layer; forming a plurality of second hard mask layers on the first hard mask layer; performing a first inclined etching process on the first hard mask layer to form a plurality of first openings at respective first sides along the first hard mask layer and adjacent to the second hard mask layers; and performing a second inclined etching process on the first hard mask layer to form a plurality of second openings at respective second sides along the first hard mask layer and adjacent to the second hard mask layers; wherein the first inclined etching process and the second inclined etching process use the second hard mask layer as a pattern guide, and the first hard mask layer is transformed into a patterned first hard mask layer through the first openings and the second openings; wherein a ratio of a width of the second hard mask layer to a horizontal distance between a pair of adjacent second hard mask layers is 1:

2.

2. The method for fabricating a semiconductor device according to claim 1, wherein an incident angle of the first inclined etching process is between 10 degrees and 80 degrees.

3. The method for fabricating a semiconductor device according to claim 2, wherein an incident angle of the second inclined etching process is opposite to the incident angle of the first inclined etching process, and a width of the first opening is equal to a width of the second opening.

4. The method for fabricating a semiconductor device according to claim 3, wherein a ratio of the width of the first opening to a horizontal distance between one of the first openings and an adjacent one of the second openings is 1:

2.

5. The method for fabricating a semiconductor device according to claim 4, further comprising a step of removing the second hard mask.

6. The method for fabricating a semiconductor device according to claim 5, further comprising a step of using the patterned first hard mask layer as a mask to pattern the target layer.

7. The method for fabricating a semiconductor device according to claim 6, wherein the target layer comprises a semiconductor material.

8. The method for fabricating a semiconductor device according to claim 6, wherein the target layer is formed on an isolation layer and comprises a semiconductor material.

9. The method for fabricating a semiconductor device according to claim 6, wherein the target layer comprises a conductive material.

10. The method for fabricating a semiconductor device according to claim 6, wherein the target layer comprises an insulating or isolating material.

11. The method for fabricating a semiconductor device according to claim 6, further comprising a step of forming the target layer on an etch stop layer.

12. The method for fabricating a semiconductor device according to claim 11, wherein the etch stop layer comprises the following materials: carbon-doped oxide, carbon-incorporated silicon oxide, or nitrogen-doped silicon carbide.

13. The method for fabricating a semiconductor device according to claim 6, wherein the first hard mask layer comprises the following materials: silicon oxide, silicon nitride, silicon oxynitride, oxynitride silicon, boron nitride, silicon boron nitride, phosphorus boron nitride, boron carbon silicon nitride, or a carbon film.

14. The method for manufacturing a semiconductor device according to claim 6, wherein the second hard mask layer comprises the following materials: silicon oxide, silicon nitride, silicon oxynitride, oxynitride silicon, boron nitride, boron silicon nitride, boron phosphorus nitride, boron carbon silicon nitride or a carbon film.

15. The method for manufacturing a semiconductor device according to claim 6, wherein for the first inclined etching process, an etching rate of the second hard mask layer with respect to the first hard mask layer is between 1:10 and 1:

100.

16. The method for manufacturing a semiconductor device according to claim 1, wherein a ratio of a width of the second hard mask layer to a height of the second hard mask layer is between 1:1 and 1:

12.

17. A method for manufacturing a semiconductor device, comprising: providing a target layer; forming a first hard mask layer on the target layer; forming a plurality of second hard mask layers on the first hard mask layer; performing a first inclined etching process on the first hard mask layer to form a plurality of first openings at respective first sides along the first hard mask layer and adjacent to the second hard mask layers; performing a 180-degree rotation to the target layer; and performing a third inclined etching process on the first hard mask layer to form a plurality of third openings at respective second sides along the first hard mask layer and adjacent to the second hard mask layers; wherein an incident angle of the first inclined etching process is equal to an incident angle of the third inclined etching process.

18. The method for manufacturing a semiconductor device according to claim 17, wherein the incident angle of the first inclined etching process is between 10 degrees and 80 degrees.

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