Methods for forming semiconductor devices

Abstract

The present invention discloses a method for forming a semiconductor device, comprising: providing a substrate on which a plurality of discretely arranged initial fins are formed; forming an isolation structure on the substrate; forming a connection layer on the sidewalls of the initial fins and between adjacent initial fins; forming a dummy gate structure on the substrate spanning the initial fins and the connection layer, the dummy gate structure covering the sidewalls of the connection layer and a portion of the top surface of the initial fins; forming grooves in the initial fins on both sides of the dummy gate structure, and forming source / drain doped layers in the grooves; forming a dielectric layer on the substrate, the dielectric layer covering the dummy gate structure and the source / drain doped layers, the top surface of the dielectric layer being flush with the top surface of the dummy gate structure; and removing the dummy gate structure to form a gate structure. The present invention helps to improve the quality of the finally formed semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more particularly to a method for forming a semiconductor device. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are among the most important components in modern integrated circuits. The basic structure of a MOSFET includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the gate structure including: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; and source and drain doped regions located in the semiconductor substrate on both sides of the gate structure.

[0003] With the development of semiconductor technology, traditional planar MOSFETs have become less capable of controlling channel current, resulting in severe leakage current. FinFETs are a new type of multi-gate device that typically includes fins protruding from the surface of a semiconductor substrate, a gate structure covering part of the top surface and sidewalls of the fins, and source / drain doped regions located in the fins on both sides of the gate structure. Compared to planar MOSFETs, finFETs have stronger short-channel rejection and higher operating current.

[0004] With the further development of semiconductor technology, traditional fin field-effect transistors (FETs) face limitations in increasing their operating current. Specifically, because only the area near the top surface and sidewalls of the fin is used as the channel region, the volume of the channel region within the fin is relatively small, which limits the increase in the operating current of the FET. Therefore, a gate-all-around (GAA) MOSFET structure has been proposed, which increases the volume of the channel region and further increases the operating current of the GAA structure MOSFET.

[0005] However, the electrical performance of GAA structure MOSFETs still needs to be improved in the current technology. Summary of the Invention

[0006] The problem solved by this invention is to provide a method for forming a semiconductor device, thereby improving the performance of the semiconductor device.

[0007] To address the aforementioned problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate on which a plurality of discretely arranged initial fins are formed; forming an isolation structure on the substrate; forming a connection layer on the sidewalls of the initial fins and between adjacent initial fins; forming a dummy gate structure on the substrate spanning the initial fins and the connection layer, the dummy gate structure covering the sidewalls of the connection layer and a portion of the top surface of the initial fins; forming grooves in the initial fins on both sides of the dummy gate structure, and forming source / drain doped layers in the grooves; forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the dummy gate structure and the source / drain doped layers, the top surface of the dielectric layer being flush with the top surface of the dummy gate structure; and removing the dummy gate structure to form a gate structure.

[0008] Optionally, the material of the connecting layer is silicon germanium, amorphous carbon, or amorphous germanium.

[0009] Optionally, the process for forming the connecting layer is chemical vapor deposition, atomic layer deposition, physical vapor deposition, or epitaxial growth.

[0010] Optionally, the step of forming the interconnect layer includes: forming an initial interconnect layer on the substrate, on the sidewalls and top of the initial fin, and between adjacent initial fins; and etching back the initial interconnect layer to expose the substrate and the top surface of the initial fin to form the interconnect layer.

[0011] Optionally, the step of forming a plurality of discretely arranged initial fins on the substrate includes: forming a patterned layer on the substrate; using the patterned layer as a mask, etching a portion of the substrate thickness to form a plurality of discretely arranged initial fins on the substrate.

[0012] Optionally, the step of forming a plurality of discretely arranged initial fins on the substrate includes: forming alternating layers of sacrificial film and channel film on the substrate, wherein the channel film is located between two adjacent layers of sacrificial film and on the top layer of sacrificial film; forming a patterned layer on the top layer of channel film; using the patterned layer as a mask, etching the channel film, the sacrificial film, and a portion of the substrate to form the initial fins on the substrate, wherein the initial fins include alternating layers of sacrificial film and channel film along the normal direction of the substrate surface, wherein the channel film is located between two adjacent layers of sacrificial film and on the top layer of sacrificial film.

[0013] Optionally, the step of removing the dummy gate structure and forming a gate structure includes: removing the dummy gate structure, the sacrificial layer at the bottom of the dummy gate structure, and the interconnect layer to form a gate opening and a channel, wherein the channel is located between adjacent channel layers and between the channel layer and the substrate; forming a gate structure within the gate opening and the channel, wherein the gate structure fills the gate opening and the channel and surrounds the channel layer.

[0014] Optionally, before forming the connecting layer, a hard mask layer is further formed on top of the initial fin.

[0015] Optionally, before forming the source / drain doped layer, the method further includes: etching a portion of the sacrificial layer on the sidewall of the groove, and forming a barrier layer on the sidewall of the etched sacrificial layer.

[0016] Optionally, the top surface of the isolation structure is flush with the bottom surface of the bottommost sacrificial layer.

[0017] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0018] After forming several discretely arranged initial fins on the substrate, a connecting layer is formed on the sidewalls of the initial fins and between adjacent initial fins. The connecting layer connects the discretely arranged initial fins into a whole. A dummy gate structure is formed on the substrate, spanning the initial fins and the connecting layer. The dummy gate structure covers the sidewalls of the connecting layer and part of the top surface of the initial fins. That is, the dummy gate structure spans the entire connected initial fins, rather than spanning several discretely arranged initial fins separately. This avoids the formation of dummy gate structures between the initial fins. On the one hand, this facilitates the removal of dummy gate structures during the removal process, reduces the residue of dummy gate structures, and thus improves the quality of the formed gate structure. On the other hand, since several discretely arranged initial fins are connected into a whole, sidewall material will not form between the initial fins during the formation of the gate structure sidewalls. The process of etching back the sidewall material to form the sidewalls reduces the difficulty of forming the gate structure sidewalls and improves the formation quality of the gate structure sidewalls, thereby helping to improve the quality of the final semiconductor device. Attached Figure Description

[0019] Figures 1 to 3 It is a schematic diagram of the process of forming a graphic structure;

[0020] Figures 4 to 18 This is a schematic diagram of the semiconductor device formation process in one embodiment of the present invention. Detailed Implementation

[0021] As semiconductor device dimensions shrink, the spacing between fins also becomes smaller. However, this shrinking spacing presents challenges in forming GAA (Glass-Apartment) structure MOSFETs. For details, please refer to [link / reference needed]. Figures 1 to 3 .

[0022] Figures 1 to 3 This is a schematic diagram of the semiconductor device formation process.

[0023] refer to Figure 1 A substrate 100 is provided, on which a plurality of discretely arranged initial fins are formed. The initial fins include sacrificial layers 101 and channel layers 102 alternately stacked along the normal direction of the surface of the substrate 100. The channel layers 102 are located between two adjacent sacrificial layers 101 and on the top sacrificial layer 101.

[0024] refer to Figure 2 An isolation structure 103 is formed on the substrate 100, the isolation structure 103 covering part of the sidewall of the initial fin. A pseudo gate structure 104 is formed on the substrate 100, spanning a plurality of discretely arranged initial fins, the pseudo gate structure 104 covering part of the sidewall and part of the top of the initial fins.

[0025] refer to Figure 3 Remove the dummy gate structure 104 and the sacrificial layer 101 covered by the dummy gate structure 104 to form a gate structure 105, which surrounds the channel layer 102.

[0026] After forming the dummy gate structure 104, the process also includes forming a gate sidewall on the sidewall of the dummy gate structure 104, and then forming source / drain doped layers in the initial fins on both sides of the dummy gate structure 104, etc., which are not shown here.

[0027] The inventors discovered that, in the process of removing the pseudo-gate structure to form the gate structure 105 after forming the pseudo-gate structure 104, the above method has several drawbacks. First, the small spacing between the initial fins makes it easy for pseudo-gate structure residues to remain during the removal process. Second, the reduced spacing between the initial fins increases the difficulty of forming the gate sidewalls. Third, the different spacing between the initial fins results in different stresses that the initial fins can withstand during the formation of the isolation structure, which can lead to bending of some initial fins and thus affect the quality and performance of the final semiconductor device.

[0028] The inventors discovered that after forming several discretely arranged initial fins on a substrate, a connecting layer is formed on the sidewalls of the initial fins and between adjacent initial fins. The connecting layer connects the discretely arranged initial fins into a fin with a width. This facilitates the removal of dummy gate structures during the subsequent formation of the gate structure, reduces the residue of dummy gate structures, and thus improves the quality of the formed gate structure. Furthermore, since several discretely arranged initial fins are connected to form a fin with a width, the formation difficulty of the gate structure sidewalls is reduced during the formation process, improving the formation quality of the gate structure sidewalls, thereby contributing to the improvement of the quality of the final semiconductor device.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figures 4 to 18 This is a schematic diagram of the semiconductor device formation process in one embodiment of the present invention.

[0031] Please refer to Figure 4 Substrate 200 is provided.

[0032] In this embodiment, the substrate 200 is made of single-crystal silicon.

[0033] In other embodiments, the substrate 200 may also be polycrystalline silicon or amorphous silicon. In other embodiments, the material of the substrate 200 may also be semiconductor materials such as germanium, silicon germanide, gallium arsenide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or multi-element semiconductor materials composed of group III-V elements, including: InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0034] Please refer to Figure 5 and Figure 6 , Figure 5 yes Figure 6 Top view, Figure 6 yes Figure 5 A cross-sectional schematic diagram along line AA shows that several initial fins are formed in parallel on the substrate 200. The initial fins include several sacrificial layers 201 that overlap along the normal direction of the surface of the substrate 200, and a channel layer 202 located between two adjacent sacrificial layers 201.

[0035] exist Figure 5 and Figure 6 In the illustration, the number of fins is three; the number of layers of the sacrificial layer 201 is three; and the number of layers of the channel layer 202 is three.

[0036] In this embodiment, the step of forming a plurality of discretely arranged initial fins on the substrate 200 includes: forming alternately stacked sacrificial layer films (not shown in the figure) and channel layer films (not shown in the figure) on the substrate, wherein the channel layer films are located between two adjacent sacrificial layer films and on the top sacrificial layer film; forming a patterned layer (not shown in the figure) on the top channel layer film; using the patterned layer as a mask, etching the channel layer film, the sacrificial layer film, and a portion of the substrate thickness; and forming the initial fins on the substrate, wherein the initial fins include a plurality of sacrificial layers 201 overlapping along the normal direction of the surface of the substrate 200, and channel layers 202 located between two adjacent sacrificial layers 201 and on the top sacrificial layer 201.

[0037] In this embodiment, alternating layers of sacrificial and channel layers are formed on the substrate. A patterned layer is formed on the top channel layer. Using the patterned layer as a mask, the channel layer, the sacrificial layer, and a portion of the substrate are etched to form the initial fin on the substrate. The purpose of the initial fin including the sacrificial layer 201 and the channel layer 202 is that the sacrificial layer 201 needs to be removed during the subsequent formation of the gate structure, so that the gate structure can occupy the position of the sacrificial layer 201. This allows the gate structure to surround the four sidewalls of the channel layer 202, thereby enhancing the effective width of the gate structure and the control over the channel layer 202, which helps to improve the quality of the formed semiconductor device.

[0038] In other embodiments, the step of forming a plurality of parallel initial fins on the substrate 200 includes: forming a patterned layer on the substrate; using the patterned layer as a mask, etching a portion of the substrate thickness to form a plurality of discretely arranged initial fins on the substrate.

[0039] In this embodiment, the sacrificial layer 201 and the channel layer 202 are made of different materials. The purpose is that the sacrificial layer 201 needs to be removed when the gate structure is subsequently formed. Therefore, by using different materials, the sacrificial layer 201 and the channel layer 202 have a larger etching selectivity, reducing the damage to the channel layer 202 during the removal of the sacrificial layer 201.

[0040] In this embodiment, the sacrificial layer 201 is made of silicon-germanium; the channel layer 202 is made of monocrystalline silicon.

[0041] In other embodiments, the materials of the sacrificial layer 201 and the channel layer 202 may also be silicon carbide, gallium arsenide, indium gallium arsenide, or III-V semiconductor materials.

[0042] In this embodiment, an epitaxial growth process is used to form the sacrificial material film for the fins. The process parameters for the epitaxial growth include: the gases used include hydrogen (H2), hydrogen chloride (HCl), DCS gas, GeH4 gas, and B2H6 gas, wherein the gas flow rate of hydrogen (H2) is 10–3000 sccm; the gas flow rate of hydrogen chloride (HCl) is 10–200 sccm; the gas flow rate of DCS gas is 20–2000 sccm; the gas flow rate of GeH4 is 10–500 sccm; the gas flow rate of B2H6 gas is 5–600 sccm; the temperature range is 600–850°C; and the pressure range is 8–300 mTorr.

[0043] In this embodiment, an epitaxial growth process is used to form the initial channel material film. The process parameters for epitaxial growth include: the gases used include hydrogen (H2), hydrogen chloride (HCl), DCS gas, SiH4 gas, and B2H6 gas; wherein the flow rate of hydrogen (H2) is 10–3000 sccm; the flow rate of hydrogen chloride (HCl) gas is 10–250 sccm; the flow rate of DCS gas is 20–2500 sccm; the flow rate of SiH4 gas is 10–700 sccm; the flow rate of B2H6 gas is 5–400 sccm; the pressure range is 8–300 mTorr; and the temperature range is 600–850 °C.

[0044] In this embodiment, the reason for using epitaxial growth to form the fin sacrificial material film and the initial channel material film is that epitaxial growth can obtain P-type and N-type materials with high conductivity, thereby obtaining a sacrificial layer and a channel layer with good integrity, which is conducive to forming a high-quality semiconductor device.

[0045] In other embodiments, the fin sacrificial material film and the initial channel material film may also be formed using ion doping or chemical vapor deposition.

[0046] In this embodiment, an isolation structure 203 is formed on the substrate 200, and the top surface of the isolation structure 203 is not higher than (i.e., flush with or lower than) the top surface of the substrate 200.

[0047] In this embodiment, the top surface of the isolation structure 203 is flush with the bottom surface of the bottommost sacrificial layer 201.

[0048] In this embodiment, the material of the isolation structure 203 is silicon nitride.

[0049] In other embodiments, the material of the isolation structure 203 may also include one or more combinations of insulating materials such as silicon oxide, silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon oxycarbonate (SiOCN), and silicon boron carbonitride (SiCBN).

[0050] In this embodiment, the isolation structure 203 serves to form electrical isolation.

[0051] In this embodiment, a hard mask layer 204 is also formed on the top surface of the initial fin.

[0052] In this embodiment, the material of the hard mask layer 204 is silicon nitride; in other embodiments, the material of the hard mask layer 204 may also be a dielectric material such as silicon oxide or silicon carbide.

[0053] In this embodiment, the purpose of forming the hard mask layer 204 on the top surface of the initial fin is twofold: firstly, to facilitate the protection of the top of the initial fin and prevent damage to the initial fin in subsequent processes; secondly, due to the presence of the hard mask layer 204, the pattern is accurately transferred during the formation of the initial fin, thereby forming a high-quality initial fin.

[0054] Please refer to Figures 7 to 8 A connecting layer 206 is formed on the sidewall of the initial fin and between adjacent initial fins.

[0055] Please refer to Figure 7 An initial connection layer 205 is formed on the substrate 200, on the sidewalls and top of the initial fin, and between adjacent initial fins.

[0056] In this embodiment, the material of the initial connection layer 205 is silicon germanium; in other embodiments, the material of the initial connection layer 205 may also be amorphous carbon or amorphous germanium.

[0057] When selecting the initial interconnect layer 205, ensure that the etching rate of the initial interconnect layer 205 material is close to that of the sacrificial layer 201 material, and that the etching rate of the initial interconnect layer 205 is greater than that of the channel layer 202. This ensures that the channel layer 202 is minimized during the removal of the initial interconnect layer 205, thereby guaranteeing the quality of the channel.

[0058] In this embodiment, the process for forming the initial interconnect layer 205 is chemical vapor deposition; in other embodiments, the process for forming the initial interconnect layer 205 may also be atomic layer deposition, physical vapor deposition, or epitaxial growth, etc.

[0059] Please refer to Figure 8 The initial interconnect layer 205 is etched back until the top surface of the substrate 200 and the initial fin is exposed, forming the interconnect layer 206.

[0060] In this embodiment, the initial interconnect layer 205 is etched back until the top surface of the substrate 200 and the hard mask layer 204 is exposed, forming the interconnect layer 206.

[0061] In this embodiment, the process of etching back the initial interconnect layer 205 to form the interconnect layer 206 is a dry etching process; in other embodiments, the process of etching back the initial interconnect layer 205 to form the interconnect layer 206 can also be a wet etching process.

[0062] In this embodiment, the dry etching process is chosen because it has good etching directionality, with a higher etching rate in the longitudinal direction than in the lateral direction. This reduces damage to the channel layer 202 in the lateral direction during the re-etching of the initial interconnect layer 205, thereby reducing damage to the channel layer 202.

[0063] In this embodiment, since the initial fins arranged separately are connected by the connecting layer 206, the initial fins arranged separately can be regarded as a whole. This ensures that during the subsequent removal of the pseudo gate structure, there will be no problem of pseudo gate structure residue due to the small spacing between adjacent initial fins, thereby ensuring the quality of pseudo gate structure removal and improving the quality of the final gate structure.

[0064] In this embodiment, since the connecting layer 206 connects the discretely arranged initial fins into a whole, there are no gaps between the initial fins during the subsequent sidewall formation process. Therefore, sidewalls will not be formed on the sidewalls of the initial fins, thereby reducing the formation of sidewalls on the sidewalls of the initial fins and reducing the difficulty of sidewall formation, thus preparing for the formation of high-quality semiconductor devices.

[0065] In this embodiment, after the connection layer 206 is formed, the hard mask layer 204 is removed.

[0066] Please refer to Figures 9 to 10 , Figure 10 yes Figure 9 Please refer to the cross-sectional view along section AA. Figure 9 A pseudo-gate structure 207 is formed on the substrate 200, spanning the initial fin and the connection layer 206.

[0067] In this embodiment, the hard mask layer 204 on top of the initial fin is removed before the pseudo gate structure 207 is formed.

[0068] In this embodiment, the dummy gate structure 207 includes: a dummy gate dielectric layer 208 located on the connection layer 206 and the top channel layer 202, a dummy gate layer 209 located on the dummy gate dielectric layer 208, and a protective layer 210 located on the dummy gate layer 209.

[0069] In this embodiment, the pseudo-gate layer 209 is made of silicon.

[0070] In this embodiment, the protective layer 210 is made of silicon nitride; in other embodiments, the protective layer 210 may also be made of one or more of the following insulating materials: silicon oxide, silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon oxycarbonate (SiOCN), and silicon boron carbonitride (SiCBN).

[0071] In this embodiment, a sidewall 211 is formed on the sidewalls of the pseudo-gate layer 209 and the protective layer 210.

[0072] In this embodiment, the sidewall 211 is made of silicon nitride; in other embodiments, the sidewall 211 may also be made of one or more of the following insulating materials: silicon oxide, silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon oxycarbonate (SiOCN), and silicon boron carbonitride (SiCBN).

[0073] In this embodiment, the sidewall 211 is used to define the location of the subsequent source / drain doped layers.

[0074] The method for forming the sidewall 211 includes: forming a sidewall material layer (not shown) on the top surface of the dummy gate dielectric layer 208, the sidewall of the dummy gate layer 209, and the sidewall and top surface of the protective layer 210; and etching the sidewall material layer back until the protective layer 210 and the top surface of the dummy gate dielectric layer 208 are exposed to form the sidewall 211.

[0075] The sidewall material layer can be formed by one or more of the following processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or heat treatment.

[0076] In this embodiment, the sidewall material layer is formed using atomic layer deposition (ALD).

[0077] In this embodiment, since the initial fins arranged separately are connected into a whole by the connecting layer 206 before the sidewall 211 is formed, the formation of sidewall material on the sidewall of the initial fin can be avoided, and the sidewall material between the initial fins can be reduced. This not only reduces the difficulty of sidewall formation, but also reduces the sidewall material remaining on the initial fin, thus preparing for the formation of a high-quality semiconductor device.

[0078] Please refer to Figure 11 , Figure 11 and Figure 10 With the view orientation consistent, grooves 212 are formed in the initial fins on both sides of the pseudo-gate structure 207.

[0079] In this embodiment, the groove 212 serves two purposes: firstly, it provides space for the subsequently formed source / drain doped layers; secondly, it prepares for the subsequent etching of the sacrificial layer 201 covered by the dummy gate structure 207.

[0080] The process of etching the initial fin to form the groove 212 includes: an anisotropic dry etching process or an anisotropic wet etching process.

[0081] In this embodiment, the etching process for the initial fin is an anisotropic dry etching process. The parameters of the dry etching process include: the etching gases used include HBr and Ar, wherein the gas flow rate of HBr is 10 sccm to 1000 sccm, and the gas flow rate of Ar is 10 sccm to 1000 sccm.

[0082] In this embodiment, the initial fin is etched to form the groove 212, and the bottom surface of the groove 212 exposes the top surface of the substrate 200.

[0083] Please refer to Figure 12 A portion of the sacrificial layer 201 on the sidewall of the groove 212 is etched, and a barrier layer 213 is formed on the sidewall of the etched sacrificial layer 201.

[0084] In this embodiment, the barrier layer 213 is made of a material with a low dielectric constant, including at least one of SiOCN, SiOC, and SiON.

[0085] The sidewall of the barrier layer 213 is flush with the sidewall of the channel layer 202.

[0086] In this embodiment, the barrier layer 213 is made of silicon nitride.

[0087] In this embodiment, the purpose of forming the barrier layer 213 is to form an electrical isolation between the subsequently formed source / drain doped layer and the gate structure, preventing punch-through between the two during use, thereby ensuring the electrical performance of the formed semiconductor device.

[0088] Please refer to Figure 13 A source / drain doped layer 214 is formed within the groove 212.

[0089] In this embodiment, the formation process of the source / drain doped layer 214 includes an epitaxial growth process; the process of doping the source / drain ions in the source / drain doped layer 214 includes an in-situ doping process.

[0090] When the semiconductor structure is a P-type device, the material of the source / drain doped layer 214 includes silicon, germanium, or silicon-germanium; the source / drain ions are P-type ions, including boron ions and BF ions. 2- The source / drain doped layer 214 is made of silicon, gallium arsenide, or indium gallium arsenide when the semiconductor structure is an N-type device; the source / drain ions are N-type ions, including phosphorus ions or arsenic ions.

[0091] Please refer to Figure 14 A dielectric layer 215 is formed on the substrate 200, the dielectric layer 215 covers the sidewalls of the dummy gate structure 207 and the source / drain doped layer 214, and the top surface of the dielectric layer 215 is flush with the top surface of the dummy gate structure 207.

[0092] In this embodiment, after the source / drain doped layer 214 is formed, a dielectric layer 215 is formed on the substrate 200 and the isolation structure 203. The dielectric layer 215 is located on the sidewall of the sidewall 211 and on the top surface of the protective layer 210.

[0093] In this embodiment, the dielectric layer 215 is specifically formed on the isolation structure 203, and the dielectric layer 215 also covers the source / drain doped layer 214.

[0094] In this embodiment, the method for forming the dielectric layer 215 includes: forming an initial dielectric layer (not shown) on the substrate 200 and the isolation structure 203, the initial dielectric layer covering the top surface and sidewall surface of the protective layer 210; planarizing the initial dielectric layer until the top surface of the protective layer 210 is exposed, thereby forming the dielectric layer 215.

[0095] In this embodiment, the dielectric layer 215 is made of silicon oxide.

[0096] Please refer to Figures 15 to 16 , Figure 16 View direction and Figure 9 The view directions are the same. Figure 15 yes Figure 16 In the cross-sectional view along line AA, the dummy gate structure 207, the sacrificial layer 201 at the bottom of the dummy gate structure 207, and the interconnect layer 206 are removed to form a gate opening 216 and a channel 217. The channel 217 is located between adjacent channel layers 202 and between the channel layer 202 and the substrate 200.

[0097] In this embodiment, the dummy gate structure 207 is removed, and a gate opening 216 is formed in the dielectric layer 219.

[0098] In this embodiment, the process for removing the pseudo gate structure 207 is a wet etching process, specifically using tetramethylammonium hydroxide (TMAH) as the etching solution.

[0099] In this embodiment, the dummy gate structure 207 is removed to form a gate opening 216, exposing the sacrificial layer 201 and the interconnect layer 206 covered by the dummy gate structure 207.

[0100] In this embodiment, the process for removing the sacrificial layer 201 and the interconnect layer 206 covered by the dummy gate structure 207 is a wet etching process. The specific process parameters include: a temperature of 25°C to 300°C and HCl gas with a volume percentage of 20% to 90%.

[0101] In this embodiment, the dummy gate structure 207 and the sacrificial layer 201 and the connection layer 206 covered by the dummy gate structure 207 are removed in preparation for the subsequent formation of the gate structure.

[0102] In this embodiment, due to the presence of the connecting layer 206, no pseudo-gate structure 207 is formed between adjacent initial fins. Thus, during the removal of the pseudo-gate structure, the pseudo-gate structure 207 will not remain due to the small spacing between the initial fins, thereby reducing the difficulty of removing the pseudo-gate structure 207 and improving the quality of removing the pseudo-gate structure 207, thus preparing for the formation of a high-quality gate structure.

[0103] In this embodiment, since the initial fins arranged separately are connected by the connecting layer 206, the multiple separate initial fins are regarded as a whole. There is no need to consider the impact of the spacing between the initial fins on subsequent processes, which reduces the difficulty of subsequent processes and has a wide range of applications. It is also more adaptable to the manufacturing of smaller semiconductor devices.

[0104] Please refer to Figures 17 to 18A gate structure 218 is formed within the gate opening 216 and the channel 217, the gate structure 218 filling the gate opening 216 and the channel 217 and surrounding the channel layer 202.

[0105] In this embodiment, the gate structure 218 includes a gate dielectric layer 219 and a gate electrode layer 220 located on the gate dielectric layer.

[0106] In this embodiment, the gate dielectric layer 219 is a high-k dielectric material (dielectric coefficient k is greater than 3.9); the high-k dielectric material includes at least one of hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.

[0107] In this embodiment, the gate electrode layer 220 is made of metal, and the metal material includes one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum.

[0108] In this embodiment, the gate structure 218 surrounds the channel layer 202, thereby enhancing the gate structure 218's control over the channel, ensuring the maximum effective width of the gate structure 218, and improving the performance of the formed semiconductor device.

[0109] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A substrate is provided on which a plurality of discretely arranged initial fins are formed; An isolation structure is formed on the substrate; A connecting layer is formed on the sidewall of the initial fin and between adjacent initial fins; A pseudo-gate structure is formed on the substrate, spanning the initial fin and the interconnect layer. The pseudo-gate structure covers the sidewall of the interconnect layer and part of the top surface of the initial fin. No pseudo-gate structure is formed between adjacent initial fins. Grooves are formed in the initial fins on both sides of the pseudo-gate structure, and source / drain doped layers are formed in the grooves; A dielectric layer is formed on the substrate, the dielectric layer covering the sidewalls of the dummy gate structure and the source / drain doped layer, and the top surface of the dielectric layer is flush with the top surface of the dummy gate structure; Remove the dummy gate structure and the interconnect layer covered by the dummy gate structure to form a gate structure.

2. The method for forming a semiconductor device as described in claim 1, characterized in that, The material of the connecting layer is silicon germanium, amorphous carbon, or amorphous germanium.

3. The method for forming a semiconductor device as described in claim 1, characterized in that, The process for forming the connecting layer is chemical vapor deposition, atomic layer deposition, physical vapor deposition, or epitaxial growth.

4. The method for forming a semiconductor device as described in claim 1, characterized in that, The steps for forming the connection layer include: An initial connection layer is formed on the substrate, on the sidewalls and top of the initial fin, and between adjacent initial fins; The initial interconnect layer is etched back until the top surface of the substrate and the initial fin is exposed, forming the interconnect layer.

5. The method for forming a semiconductor device as described in claim 1, characterized in that, The step of forming a plurality of discretely arranged initial fins on the substrate includes: A patterned layer is formed on the substrate; Using the patterned layer as a mask, a portion of the substrate is etched to form a plurality of discretely arranged initial fins on the substrate.

6. The method for forming a semiconductor device as described in claim 1, characterized in that, The step of forming a plurality of discretely arranged initial fins on the substrate includes: Alternating layers of sacrificial film and channel film are formed on the substrate, wherein the channel film is located between two adjacent sacrificial film layers and on the top sacrificial film layer; A patterned layer is formed on the top channel layer film; Using the patterned layer as a mask, the channel layer film, the sacrificial layer film, and a portion of the substrate are etched to form the initial fin on the substrate. The initial fin includes sacrificial layers and channel layers that are alternately stacked along the normal direction of the substrate surface. The channel layer is located between two adjacent sacrificial layers and on the top sacrificial layer.

7. The method for forming a semiconductor device as described in claim 6, characterized in that, The step of removing the dummy gate structure and forming the gate structure includes: Remove the dummy gate structure, the sacrificial layer at the bottom of the dummy gate structure, and the interconnect layer to form a gate opening and a channel, the channel being located between adjacent channel layers and between the channel layer and the substrate; A gate structure is formed within the gate opening and the channel, the gate structure filling the gate opening and the channel, and surrounding the channel layer.

8. The method for forming a semiconductor device as described in claim 1, characterized in that, Before forming the connecting layer, the method further includes forming a hard mask layer on top of the initial fin.

9. The method for forming a semiconductor device as described in claim 6, characterized in that, Before forming the source / drain doped layer, the method further includes: etching a portion of the sacrificial layer on the sidewall of the groove, and forming a barrier layer on the sidewall of the etched sacrificial layer.

10. The method for forming a semiconductor device as described in claim 6, characterized in that, The top surface of the isolation structure is flush with the bottom surface of the bottommost sacrificial layer.

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