Semiconductor Structure and Method for Forming the Same

Abstract

A semiconductor structure and a method for forming the same, wherein the method includes: providing a substrate; forming a first dielectric layer and a plurality of gate structures on the substrate, source-drain doping regions are formed in the substrate on both sides of the gate structures, and source-drain plugs are formed on the top surfaces of the source-drain doping regions, and the first dielectric layer is located on the surfaces of the gate structures, the source-drain doping regions, and the source-drain plugs; forming a first plug in the first dielectric layer, the first plug is in contact with the top surface of the source-drain plug or the top surface of the gate structure; forming a second dielectric layer on the surface of the first dielectric layer, and the second dielectric layer covers the surface of the first plug; forming a second plug material film in the first dielectric layer and the second dielectric layer, the second plug material film is in contact with the top surface of the source-drain plug or the top surface of the gate structure. The method is beneficial to improving the performance of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the key dimensions of components are constantly decreasing, and the circuit density inside the integrated circuit is increasing. This development makes it impossible for the wafer surface to provide enough area to make the required interconnection lines.

[0003] The connection plugs in the transistor structure include connection plugs located on the surface of the gate structure, which are used to connect the gate structure with an external circuit; and connection plugs located on the surface of the source and drain doping regions, which are used to connect the source region or drain region of the transistor with an external circuit. In order to further meet the demand for improving integration, the area can be further saved by transferring the connection plugs on the gate structure in the isolation region to the gate structure in the active region. In addition, the performance of the connection plug formed by the selective metal growth process is better, for example, the resistivity of the connection plug is lower, which is conducive to improving the conductivity of the transistor structure.

[0004] However, there are problems with the existing selective metal growth process for forming the connection plug, resulting in poor performance of the semiconductor structure. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first dielectric layer and a plurality of gate structures on the substrate, wherein the substrate on both sides of the gate structure has source-drain doped regions, and the top surfaces of the source-drain doped regions have source-drain plugs, and the first dielectric layer is located on the surfaces of the gate structure, the source-drain doped regions, and the source-drain plugs; forming a first plug in the first dielectric layer, wherein the first plug is in contact with the top surface of the source-drain plug or the top surface of the gate structure; forming a second dielectric layer on the surface of the first dielectric layer, wherein the second dielectric layer covers the surface of the first plug; forming a second plug material film in the first dielectric layer and the second dielectric layer, wherein the second plug material film is in contact with the top surface of the source-drain plug or the top surface of the gate structure; planarizing the second plug material film until the surface of the first dielectric layer and the top surface of the first plug are exposed, and forming a second plug in the first dielectric layer, wherein the second plug is in contact with the top surface of the source-drain plug or the top surface of the gate structure.

[0007] Optionally, the method for forming the first plug includes: forming a first opening in the first dielectric layer, the first opening exposing the top surface of the source / drain plug or the top surface of the gate structure; forming a first plug material film in the first opening and on the surface of the first dielectric layer; planarizing the first plug material film until the surface of the first dielectric layer is exposed, and forming the first plug in the first opening.

[0008] Optionally, the method for forming the first opening includes: forming a first patterned layer on the surface of the first dielectric layer, the first patterned layer exposing a portion of the surface of the first dielectric layer; using the first patterned layer as a mask, etching the first dielectric layer until the top surface of the source and drain plug or the top surface of the gate structure is exposed to form the first opening.

[0009] Optionally, the formation process of the first plug material film includes: a selective metal growth process, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0010] Optionally, when the first opening exposes the top surface of the source / drain plug, the formation process of the first plug material film is a selective metal growth process; the parameters of the selective metal growth process include: the gases used include tungsten fluoride and hydrogen, the flow rate of tungsten fluoride is 20 standard ml / min to 150 standard ml / min, the flow rate of hydrogen is 5000 standard ml / min to 8000 standard ml / min, and the temperature is 200 degrees Celsius to 400 degrees Celsius.

[0011] Optionally, a material of the first plug includes: one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0012] Optionally, the material of the second plug material film includes: one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0013] Optionally, the second plug material film is also located on the surface of the second dielectric layer; the method for forming the second plug material film includes: forming a second opening in the first dielectric layer and the second dielectric layer, and the second opening exposes the top surface of the source and drain plug or the top surface of the gate structure; forming the second plug material film in the second opening and on the surface of the second dielectric layer.

[0014] Optionally, the method for forming the second opening includes: forming a second patterned layer on the surface of the second dielectric layer, the second patterned layer exposing a portion of the surface of the second dielectric layer; using the second patterned layer as a mask, etching the first dielectric layer and the second dielectric layer until the top surface of the source and drain plug or the top surface of the gate structure is exposed to form the second opening.

[0015] Optionally, the formation process of the second plug material film is a selective metal growth process; the parameters of the selective metal growth process include: the gases used include tungsten fluoride and hydrogen, the flow rate of tungsten fluoride is 20 standard ml / min to 150 standard ml / min, the flow rate of hydrogen is 5000 standard ml / min to 8000 standard ml / min, and the temperature is 200 degrees Celsius to 400 degrees Celsius.

[0016] Optionally, the first plug is in contact with a top surface of the gate structure; and the second plug material film is in contact with a top surface of the source / drain plug.

[0017] Optionally, the first plug is in contact with a top surface of the source / drain plug; and the second plug material film is in contact with a top surface of the gate structure.

[0018] Optionally, the material of the first dielectric layer is a dielectric material, and the dielectric material includes: a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbon nitride.

[0019] Optionally, the material of the second dielectric layer is a dielectric material, and the dielectric material includes: one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0020] Optionally, the source-drain plug includes: an isolation layer and a conductive layer located on the surface of the isolation layer; the material of the isolation layer includes: titanium silicide, tantalum silicide or tungsten nitride; the material of the conductive layer includes: a combination of one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0021] Optionally, the gate structure includes: a gate dielectric layer and a work function layer located on the surface of the gate dielectric layer, and a gate layer located on the surface of the work function layer; the material of the gate dielectric layer includes: silicon oxide or high-K dielectric material; the material of the work function layer includes: one or more combinations of TiN, TaN, TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN; the material of the gate layer includes: one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0022] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate; a first dielectric layer and a plurality of gate structures located on the substrate, wherein the substrate on both sides of the gate structure has source-drain doped regions, and the top surfaces of the source-drain doped regions have source-drain plugs, the first dielectric layer is located on the gate structure, the source-drain doped regions, and the source-drain plug surfaces; a first plug located in the first dielectric layer, the first plug is in contact with the top surface of the source-drain plug or the top surface of the gate structure; a second dielectric layer located on the surface of the first dielectric layer, and the second dielectric layer covers the surface of the first plug.

[0023] Optionally, a second plug material film is located in the first dielectric layer and the second dielectric layer, and the second plug material film is in contact with a top surface of the source / drain plug or a top surface of the gate structure.

[0024] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0025] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first plug is first formed; and then a second dielectric layer covering the surface of the first plug is formed. Since the second dielectric layer covers the surface of the first plug, the first plug can be protected from being affected by subsequent processes, so that in the subsequent process of forming a second plug material film in the first dielectric layer and the second dielectric layer, material will not be deposited on the surface exposed by the first plug, thereby reducing the impact on the second plug material film, which is beneficial to improving the morphology of the formed second plug material film, thereby improving the performance of the formed semiconductor structure.

[0026] Furthermore, the second plug material film is formed by a selective metal growth process. Since the selective metal growth process has different deposition rates on different material surfaces, the second plug material film can be directly deposited on the surface of the metal material. The second plug material film has good adhesion, so there is no need to additionally form a film layer for increasing the adhesion of the second plug material film, which is beneficial to improving the conductivity of the first plug material film, thereby improving the performance of the formed semiconductor structure.

[0027] Furthermore, when the first plug material film adopts a selective metal growth process, since the selective metal growth process has different deposition rates on different material surfaces, the first plug material film can be directly deposited on the surface of the metal material, and the first plug material film has good adhesion, so there is no need to additionally form a film layer for increasing the adhesion of the first plug material film, which is beneficial to improving the conductivity of the first plug material film, thereby improving the performance of the formed semiconductor structure.

[0028] In the semiconductor structure provided by the technical solution of the present invention, since the second dielectric layer covers the surface of the first plug, the first plug can be protected from being affected by subsequent processes, so that in the subsequent process of forming the second plug material film in the first dielectric layer and the second dielectric layer, material will not be deposited on the exposed surface of the first plug, thereby reducing the impact on the second plug material film, which is beneficial to improving the morphology of the formed second plug material film, thereby improving the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 4 It is a structural schematic diagram of each step of a method for forming a conventional semiconductor structure;

[0030] Figures 5 to 12 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0031] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0032] First, the reasons why the performance of the existing semiconductor structure is poor are described in detail with reference to the accompanying drawings. Figures 1 to 4 The present invention is a structural schematic diagram of each step of a method for forming a conventional semiconductor structure.

[0033] Please refer to Figure 1 A substrate 100 is provided, on which a dielectric layer 120 and a plurality of gate structures 110 are provided, source-drain doped regions 130 are provided in the substrate 100 on both sides of the gate structure 110, and source-drain plugs 140 are provided on the top surfaces of the source-drain doped regions 130, and the dielectric layer 120 is located on the surfaces of the gate structure 110, the source-drain doped regions 130 and the source-drain plugs 140.

[0034] Please refer to Figure 2 , a first opening (not shown in the figure) is formed in the dielectric layer 120, and the bottom of the first opening exposes the top surface of the gate structure 110; a first plug 150 is formed in the first opening, and the first plug 150 is in contact with the top surface of the gate structure 110.

[0035] Please refer to Figure 3 , a second opening 160 is formed in the dielectric layer 120 , and the second opening 160 exposes the top surface of the source-drain plug 140 .

[0036] Please refer to Figure 4 , a second plug 170 is formed in the second opening 160 by using a selective metal growth process.

[0037] In the above method, since the selective metal growth process can have different deposition rates on the surfaces of different materials, the second plug 170 can be directly deposited on the surface of the metal material, and the adhesion of the second plug 170 is good, so there is no need to additionally form a film layer for increasing the adhesion of the second plug 170, which is beneficial to improving the performance of the formed semiconductor structure.

[0038] However, in the process of forming the second plug 170 by adopting the selective metal growth process, the top surface of the first plug 150 is exposed, resulting in the formation of material growing not only on the top surface of the source-drain plug 140 exposed by the second opening 160, but also on the surface of the first plug 150. Furthermore, since the distance between the gate structure 120 and the source-drain plug 140 is relatively close, and thus the distance between the first plug 150 and the second opening 160 is relatively close, the material grown on the surface of the first plug 150 is likely to extend to the second opening 160, which is likely to cause the second opening 160 to close prematurely, resulting in a void in the second opening 160, and thus the second plug 170 formed has a poor morphology and is likely to be disconnected.

[0039] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: forming a first plug in the first dielectric layer, the first plug being in contact with the top surface of the source / drain plug or the top surface of the gate structure; forming a second dielectric layer on the surface of the first dielectric layer, and the second dielectric layer covering the surface of the first plug; forming a second plug material film in the first dielectric layer and the second dielectric layer, the second plug material film being in contact with the top surface of the source / drain plug or the top surface of the gate structure, since the second dielectric layer covers the surface of the first plug, the first plug can be protected from being affected by subsequent processes, so that in the subsequent process of forming the second plug material film in the first dielectric layer and the second dielectric layer, material will not be deposited on the surface exposed by the first plug, thereby reducing the impact on the second plug material film.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 5 to 12 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0042] Please refer to Figure 5 , providing a substrate 200.

[0043] In this embodiment, the base 200 includes: a substrate (not shown in the figure) and a fin portion (not shown in the figure) located on the surface of the substrate.

[0044] The materials of the substrate and the fins may be single crystal silicon, polycrystalline silicon, or silicon or silicon germanium with an amorphous structure, or silicon on insulator (SOI), or may include other materials (eg, Group III-V compounds such as gallium arsenide).

[0045] The method for forming the base 200 includes: providing an initial substrate; and patterning the initial substrate to form a substrate and a fin located on the substrate.

[0046] In other embodiments, the base is a planar substrate.

[0047] Please refer to Figure 6 A first dielectric layer 220 and a plurality of gate structures 210 are formed on the substrate 200. Source-drain doped regions 230 are provided in the substrate 200 on both sides of the gate structure 210, and source-drain plugs 240 are provided on the top surfaces of the source-drain doped regions 230. The first dielectric layer 220 is located on the surfaces of the gate structure 210, the source-drain doped regions 230, and the source-drain plugs 240.

[0048] The method for forming the plurality of gate structures 210, the first dielectric layer 220 and the source-drain doped region 230 includes: forming a plurality of dummy gate structures (not shown in the figure) on the substrate 200; forming source-drain doped regions 230 in the substrate 200 on both sides of the dummy gate structure; forming a first dielectric portion (not shown in the figure) on the substrate 200, wherein the first dielectric portion covers the side wall surface of the dummy gate structure; removing the dummy gate structure and forming a gate opening in the first dielectric portion; forming a gate structure 210 in the gate opening; forming a second dielectric portion on the surface of the first dielectric portion, wherein the top surface of the second dielectric portion is higher than the top surface of the gate structure 210, and the first dielectric portion and the second dielectric portion constitute the first dielectric layer 220.

[0049] The material of the first dielectric layer 220 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride.

[0050] The method for forming the source-drain plug 240 includes: forming a third patterned layer (not shown in the figure) on the surface of the first dielectric layer 220, wherein the third patterned layer exposes the surface of the first dielectric layer 220 on the source-drain doped region 230; using the third patterned layer as a mask, etching the first dielectric layer 220 until the top surface of the source-drain doped region 230 is exposed, and forming a source-drain opening (not shown in the figure) in the first dielectric layer 220; and forming the source-drain plug 240 in the source-drain opening.

[0051] The source-drain plug 240 includes an isolation layer (not shown in the figure) and a conductive layer (not shown in the figure) located on the surface of the isolation layer.

[0052] Specifically, the isolation layer is located at the bottom and side wall surfaces of the source / drain openings.

[0053] The material of the isolation layer includes: titanium silicide, tantalum silicide or tungsten nitride.

[0054] The isolation layer has the following functions: on the one hand, it increases the adhesion of the conductive layer, thereby improving the performance of the source-drain plug 240; on the other hand, it blocks atoms or ions in the conductive layer from diffusing into the first dielectric layer 220 to avoid leakage, thereby improving the performance of the semiconductor structure.

[0055] The material of the conductive layer includes one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0056] The gate structure 210 includes: a gate dielectric layer (not shown in the figure), a work function layer (not shown in the figure) located on the surface of the gate dielectric layer, and a gate layer (not shown in the figure) located on the surface of the work function layer.

[0057] The material of the gate dielectric layer includes: silicon oxide or high-K dielectric material; the material of the work function layer includes: one or more combinations of TiN, TaN, TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN; the material of the gate layer includes: one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0058] The high-K dielectric material refers to a material with a dielectric constant greater than 3.9.

[0059] Specifically, the gate dielectric layer is located at the bottom and side wall surfaces of the gate opening.

[0060] Since the gate structure 210 includes a gate dielectric layer, a work function layer and a gate layer, and the source-drain plug 240 includes an isolation layer and a conductive layer, the material composition of the gate structure 210 is relatively complex, while the material composition of the source-drain plug 240 is relatively simple. If a selective metal growth process is adopted, the film layers formed on the top surface of the gate structure 210 and the top surface of the source-drain plug 240 are quite different.

[0061] In this embodiment, the top surface of the source-drain plug 240 has a first protective layer (not shown in the figure), thereby preventing over-etching from occurring when an electrical connection structure is subsequently formed on the top of the source-drain plug 240, thereby causing a short circuit between the source-drain plug 240 and the gate structure 210, or between the source-drain plug 240 and the electrical connection structure.

[0062] In this embodiment, the top surface of the gate structure 210 has a second protective layer (not shown in the figure), so as to avoid over-etching when an electrical connection structure is subsequently formed on the top of the gate structure 210, which may cause a short circuit between the gate structure 210 and the source / drain plug 240, or between the gate structure 210 and the electrical connection structure.

[0063] Next, a first plug is formed in the first dielectric layer 220, and the first plug is in contact with the top surface of the source / drain plug 240 or the top surface of the gate structure 210. For the specific process of forming the first plug, please refer to Figures 7 and 8 .

[0064] Please refer to Figure 7 , a first opening 251 is formed in the first dielectric layer 220 , and the first opening 251 exposes the top surface of the source / drain plug 240 or the top surface of the gate structure 210 .

[0065] The first opening 251 provides a space for subsequently forming a first plug.

[0066] The method for forming the first opening 251 includes: forming a first patterned layer 221 on the surface of the first dielectric layer 220, wherein the first patterned layer 221 exposes a portion of the surface of the first dielectric layer 220; using the first patterned layer 221 as a mask, etching the first dielectric layer 220 until the top surface of the source / drain plug 240 or the top surface of the gate structure 210 is exposed, thereby forming the first opening 251.

[0067] The process of etching the first dielectric layer 220 includes: a dry etching process and a wet etching process, or a combination of the two.

[0068] In this embodiment, the first dielectric layer 220 is etched using a dry etching process, which is beneficial to improving the morphology of the formed first opening 251, thereby improving the performance of the formed semiconductor structure.

[0069] In this embodiment, the first opening 251 exposes the top surface of the gate structure 210 .

[0070] In other embodiments, the first opening exposes top surfaces of the source / drain plugs.

[0071] Please refer to Figure 8 , forming a first plug material film (not shown in the figure) in the first opening 251 and on the surface of the first dielectric layer 220 ; planarizing the first plug material film until the surface of the first dielectric layer 220 is exposed, and forming the first plug 260 in the first opening 251 .

[0072] In this embodiment, since the first opening 251 exposes the top surface of the gate structure 210 , the first plug 260 formed in the first opening 251 is located on the top surface of the gate structure 210 .

[0073] The formation process of the first plug material film includes: a selective metal growth process, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0074] In this embodiment, the process of forming the first plug material film is a chemical vapor deposition process.

[0075] In other embodiments, when the first opening exposes the top surface of the source / drain plug, the formation process of the first plug material film is a selective metal growth process; the parameters of the selective metal growth process include: the gases used include tungsten fluoride and hydrogen, the flow rate of tungsten fluoride is 20 standard ml / min to 150 standard ml / min, the flow rate of hydrogen is 5000 standard ml / min to 8000 standard ml / min, and the temperature is 200 degrees Celsius to 400 degrees Celsius.

[0076] Since the selective metal growth process can have different deposition rates on different material surfaces, and the material composition of the source-drain plug is simple, the first plug material film can be directly deposited on the surface of the source-drain plug, and the first plug material film has good adhesion, so there is no need to additionally form a film layer for increasing the adhesion of the first plug material film, which is beneficial to improving the performance of the formed semiconductor structure.

[0077] In other embodiments, when the first opening exposes the top surface of the source / drain plug, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process may also be used.

[0078] The material of the first plug material film includes: one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum. In this embodiment, the material of the first plug material film is tungsten, and the material of the first plug 260 formed by the first plug material film is tungsten.

[0079] Please refer to Fig. 9 , a second dielectric layer 270 is formed on the surface of the first dielectric layer 220 , and the second dielectric layer 270 covers the surface of the first plug 260 .

[0080] Specifically, the second dielectric layer 270 covers the top surface of the first plug 260 .

[0081] The material of the second dielectric layer 270 is a dielectric material, and the dielectric material includes: one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the second dielectric layer 270 is silicon oxide.

[0082] By first forming the first plug 260 and then forming the second dielectric layer 270 covering the surface of the first plug 260, since the second dielectric layer 270 covers the surface of the first plug 260, the first plug 260 can be protected from being affected by subsequent processes, so that in the subsequent process of forming the second plug material film in the first dielectric layer 220 and the second dielectric layer 270, no material will be deposited on the exposed surface of the first plug 260, thereby reducing the impact on the second plug material film, which is beneficial to improving the morphology of the formed second plug material film, thereby improving the performance of the formed semiconductor structure.

[0083] Next, a second plug material film is formed in the first dielectric layer 220 and the second dielectric layer 270. The second plug material film is in contact with the top surface of the source / drain plug 240 or the top surface of the gate structure 210. For details on the process of forming the second plug material film, please refer to Figure 10 to Figure 11 .

[0084] Please refer to Fig.10 , a second opening 252 is formed in the first dielectric layer 260 and the second dielectric layer 270 , and the second opening 252 exposes the top surface of the source / drain plug 240 or the top surface of the gate structure 210 .

[0085] The second opening 252 provides a space for subsequently forming a second plug.

[0086] The method for forming the second opening 252 includes: forming a second patterned layer 271 on the surface of the second dielectric layer 270, wherein the second patterned layer 271 exposes a portion of the surface of the second dielectric layer 270; using the second patterned layer 271 as a mask, etching the first dielectric layer 220 and the second dielectric layer 270 until the top surface of the source / drain plug 240 or the top surface of the gate structure 210 is exposed to form the second opening 252.

[0087] The process of etching the first dielectric layer 220 and the second dielectric layer 270 includes: a dry etching process and a wet etching process, or a combination of the two.

[0088] In this embodiment, the first dielectric layer 220 and the second dielectric layer 270 are etched using a dry etching process, which is beneficial to improving the morphology of the formed second opening 252, thereby improving the performance of the formed semiconductor structure.

[0089] In this embodiment, the second opening 252 exposes the top surface of the source / drain plug 240 .

[0090] In other embodiments, the second opening exposes a top surface of the gate structure.

[0091] Please refer to Fig.11 , the second plug material film 280 is formed in the second opening 252 and on the surface of the second dielectric layer 270 .

[0092] The formation process of the second plug material film 280 is a selective metal growth process; the parameters of the selective metal growth process include: the gases used include tungsten fluoride and hydrogen, the flow rate of tungsten fluoride is 20 standard ml / min to 150 standard ml / min, the flow rate of hydrogen is 5000 standard ml / min to 8000 standard ml / min, and the temperature is 200 degrees Celsius to 400 degrees Celsius.

[0093] The second plug material film 280 is formed by a selective metal growth process. Since the selective metal growth process has different deposition rates on different material surfaces, the second plug material film 280 can be directly deposited on the surface of the metal material. The second plug material film 280 has good adhesion, so there is no need to additionally form a film layer for increasing the adhesion of the second plug material film 280, which is beneficial to improving the conductivity of the first plug material film 280, thereby improving the performance of the formed semiconductor structure.

[0094] In this embodiment, the second opening 252 exposes the top surface of the source-drain plug 240. Since the material composition of the source-drain plug 240 is simple, the selective metal growth process is further beneficial to improve the adhesion of the second plug material film formed on the top surface of the source-drain plug 240, thereby helping to improve the conductivity of the second plug material film 280, thereby improving the performance of the formed semiconductor structure.

[0095] The material of the second plug material film 280 includes: one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum. In this embodiment, the material of the second plug material film 280 is tungsten.

[0096] In this embodiment, the first plug 260 is in contact with the top surface of the gate structure 210 ; and the second plug material film 280 is in contact with the top surface of the source-drain plug 240 .

[0097] In other embodiments, the first plug is in contact with a top surface of the source / drain plug; and the second plug material film is in contact with a top surface of the gate structure.

[0098] Please refer to Fig.12 , planarizing the second plug material film 280 until the surface of the first dielectric layer 220 and the top surface of the first plug 260 are exposed, forming a second plug 290 in the first dielectric layer 220, and the second plug 290 is in contact with the top surface of the source / drain plug 240 or the top surface of the gate structure 210.

[0099] The process of planarizing the second plug material film 280 includes a chemical mechanical polishing process.

[0100] In this embodiment, the first plug 260 is in contact with the top surface of the gate structure 210 ; and the second plug 290 is in contact with the top surface of the source-drain plug 240 .

[0101] In other embodiments, the first plug is in contact with a top surface of the source / drain plug; and the second plug is in contact with a top surface of the gate structure.

[0102] Accordingly, the present invention provides a semiconductor structure. Fig.11 , comprising: a substrate 200; a first dielectric layer 220 and a plurality of gate structures 210 located on the substrate 200, wherein the substrate 200 on both sides of the gate structure 210 has source-drain doped regions 230, and the top surfaces of the source-drain doped regions 230 have source-drain plugs 240, and the first dielectric layer 220 is located on the surfaces of the gate structure 210, the source-drain doped regions 230, and the source-drain plugs 240; a first plug 260 located in the first dielectric layer 230, and the first plug 260 is in contact with the top surface of the source-drain plug 240 or the top surface of the gate structure 210; and a second dielectric layer 270 located on the surface of the first dielectric layer 220, and the second dielectric layer 270 covers the surface of the first plug 260.

[0103] In this embodiment, the first plug 260 is in contact with the top surface of the source / drain plug 240 .

[0104] In other embodiments, the first plug contacts a top surface of the gate structure.

[0105] The semiconductor structure further includes a second plug material film 280 located in the first dielectric layer 220 and the second dielectric layer 270 , and the second plug material film 280 is in contact with the top surface of the source / drain plug 240 or the top surface of the gate structure 210 .

[0106] In this embodiment, the second plug material film 280 is in contact with the top surface of the gate structure 210 .

[0107] In other embodiments, the second plug material film is in contact with top surfaces of the source / drain plugs.

[0108] Specifically, in this embodiment, the second plug material film 280 is also located on the surface of the second dielectric layer 270 .

[0109] In other embodiments, the second plug material film is only located in the first dielectric layer and the second dielectric layer.

[0110] Since the second dielectric layer 270 covers the surface of the first plug 260, the first plug 260 can be protected from being affected by subsequent processes, so that in the subsequent process of forming the second plug material film 280 in the first dielectric layer 220 and the second dielectric layer 270, no material will be deposited on the exposed surface of the first plug 260, thereby reducing the impact on the second plug material film 280, which is beneficial to improving the morphology of the formed second plug material film 280, thereby improving the performance of the formed semiconductor structure.

[0111] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, comprising: providing a substrate; forming a first dielectric layer and a plurality of gate structures on the substrate, source-drain doping regions are formed in the substrate on both sides of the gate structures, and source-drain plugs are formed on the top surfaces of the source-drain doping regions, and the first dielectric layer is located on the surfaces of the gate structures, source-drain doping regions, and source-drain plugs; forming a first plug in the first dielectric layer, the first plug being in contact with the top surface of the source-drain plug or the top surface of the gate structure; forming a second dielectric layer on the surface of the first dielectric layer, and the second dielectric layer covering the surface of the first plug; forming a second plug material film in the first dielectric layer and the second dielectric layer, the second plug material film being in contact with the top surface of the source-drain plug or the top surface of the gate structure; planarizing the second plug material film until the surface of the first dielectric layer and the top surface of the first plug are exposed, forming a second plug in the first dielectric layer, and the second plug being in contact with the top surface of the source-drain plug or the top surface of the gate structure; The method for forming the first plug includes: forming a first opening in the first dielectric layer, the first opening exposing the top surface of the source-drain plug or the top surface of the gate structure; forming a first plug material film in the first opening and on the surface of the first dielectric layer; planarizing the first plug material film until the surface of the first dielectric layer is exposed, and forming the first plug in the first opening.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The method for forming the first opening includes: forming a first patterned layer on the surface of the first dielectric layer, the first patterned layer exposing a part of the surface of the first dielectric layer; using the first patterned layer as a mask to etch the first dielectric layer until the top surface of the source-drain plug or the top surface of the gate structure is exposed, and forming the first opening.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The forming process of the first plug material film includes: selective metal growth process, physical vapor deposition process, chemical vapor deposition process or atomic layer deposition process.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, When the first opening exposes the top surface of the source-drain plug, the forming process of the first plug material film is a selective metal growth process; the parameters of the selective metal growth process include: the gases used include tungsten fluoride and hydrogen, the flow rate of tungsten fluoride is 20 standard milliliters per minute to 150 standard milliliters per minute, the flow rate of hydrogen is 5000 standard milliliters per minute to 8000 standard milliliters per minute, and the temperature is 200 degrees Celsius to 400 degrees Celsius.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the first plug includes: one or a combination of more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the second plug material film includes one or a combination of more than one of: tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

7. The method for forming a semiconductor structure as described in claim 1, wherein, the second plug material film is also located on the surface of the second dielectric layer; the method for forming the second plug material film includes: forming a second opening in the first dielectric layer and the second dielectric layer, and the second opening exposes the top surface of the source / drain plug or the top surface of the gate structure; forming the second plug material film in the second opening and on the surface of the second dielectric layer.

8. The method for forming a semiconductor structure as described in claim 7, wherein, the method for forming the second opening includes: forming a second patterned layer on the surface of the second dielectric layer, and the second patterned layer exposes a part of the surface of the second dielectric layer; using the second patterned layer as a mask to etch the first dielectric layer and the second dielectric layer until the top surface of the source / drain plug or the top surface of the gate structure is exposed, thereby forming the second opening.

9. The method for forming a semiconductor structure as described in claim 1, wherein, the forming process of the second plug material film is a selective metal growth process, and the parameters of the selective metal growth process include: the gases used include tungsten fluoride and hydrogen, the flow rate of tungsten fluoride is 20 standard milliliters per minute to 150 standard milliliters per minute, the flow rate of hydrogen is 5000 standard milliliters per minute to 8000 standard milliliters per minute, and the temperature is 200 degrees Celsius to 400 degrees Celsius.

10. The method for forming a semiconductor structure as described in claim 1, wherein, the first plug is in contact with the top surface of the gate structure; the second plug material film is in contact with the top surface of the source / drain plug.

11. The method for forming a semiconductor structure as described in claim 1, wherein, the first plug is in contact with the top surface of the source / drain plug; the second plug material film is in contact with the top surface of the gate structure.

12. The method for forming a semiconductor structure as described in claim 1, wherein, the material of the first dielectric layer is a dielectric material, and the dielectric material includes one or a combination of more than one of: silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.

13. The method for forming a semiconductor structure as described in claim 1, wherein, the material of the second dielectric layer is a dielectric material, and the dielectric material includes one or a combination of more than one of: silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.

14. The method for forming a semiconductor structure as described in claim 1, wherein, the source / drain plug includes: an isolation layer and a conductive layer located on the surface of the isolation layer; the material of the isolation layer includes: titanium silicide, tantalum silicide, or tungsten nitride; the material of the conductive layer includes one or a combination of more than one of: tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

15. The method for forming a semiconductor structure according to claim 1, wherein, the gate structure includes: a gate dielectric layer, a work function layer on the surface of the gate dielectric layer, and a gate layer on the surface of the work function layer; the material of the gate dielectric layer includes: silicon oxide or a high-K dielectric material; the material of the work function layer includes: one or more combinations of TiN, TaN, TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN; the material of the gate layer includes: one or more combinations of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

16. A semiconductor structure formed by using the method for forming a semiconductor structure according to any one of claims 1 to 15, wherein, it includes: a substrate; a first dielectric layer and a plurality of gate structures on the substrate, source-drain doping regions are formed in the substrate on both sides of the gate structure, and source-drain plugs are formed on the top surfaces of the source-drain doping regions, and the first dielectric layer is on the surfaces of the gate structures, source-drain doping regions, and source-drain plugs; a first plug in the first dielectric layer, the first plug is in contact with the top surface of the source-drain plug or the top surface of the gate structure; a second dielectric layer on the surface of the first dielectric layer, and the second dielectric layer covers the surface of the first plug.

17. The method for forming a semiconductor structure according to claim 16, wherein, a second plug material film in the first dielectric layer and the second dielectric layer, the second plug material film is in contact with the top surface of the source-drain plug or the top surface of the gate structure.

Images