Semiconductor device and method for forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same, the method comprising: providing a substrate, wherein a contact hole is formed in the substrate, wherein the bottom surface of the contact hole exposes the top surface of a source-drain doped layer in the substrate; forming an initial barrier layer on the bottom and sidewalls of the contact hole; forming a metal layer on the initial barrier layer, wherein the metal layer covers a portion of the sidewalls of the initial barrier layer; forming a sealing layer on the metal layer; etching away the portion of the initial barrier layer not covered by the metal layer to form the barrier layer; after the sealing layer is formed on the metal layer, the sealing layer well protects the metal layer, so that in the process of etching away the portion of the initial barrier layer not covered by the metal layer to form the barrier layer, due to the protective effect of the sealing layer, the metal layer will not be damaged in the etching process, thereby improving the formation quality of the metal layer and contributing to improving the quality and yield of the formed semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration. As the most basic semiconductor device, the device is currently being widely used. However, the control ability of traditional planar devices for channel current has weakened, resulting in short channel effects and leakage current, which ultimately affects the electrical performance of semiconductor devices.

[0003] During the fabrication of semiconductor devices, current conduction is typically achieved through metal interconnects, thereby enabling specific semiconductor device functions. Typically, metal plugs are connected between different semiconductor devices, connecting the gate and source / drain regions, respectively. However, the quality of currently formed metal plugs is poor, resulting in poor electrical performance in the resulting semiconductor devices.

[0004] How to form high-quality metal plugs to ensure that the formed semiconductor devices have good performance is a problem that urgently needs to be solved. Summary of the Invention

[0005] The problem solved by the present invention is to provide a semiconductor device and a method for forming the same, so that the formed metal plug has good forming quality and ensures that the formed semiconductor device has good performance and yield.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, wherein a contact hole is formed in the substrate, and the bottom surface of the contact hole exposes the top surface of the source-drain doped layer in the substrate; forming an initial barrier layer on the bottom and sidewalls of the contact hole; forming a metal layer on the initial barrier layer, wherein the metal layer covers a portion of the sidewalls of the initial barrier layer; forming a sealing layer on the metal layer; and etching away the portion of the initial barrier layer not covered by the metal layer to form the barrier layer.

[0007] Optionally, the step of forming the metal layer includes: forming a metal seed layer on the bottom and side walls of the initial barrier layer; forming an electroplated metal layer on the metal seed layer using a chemical electroplating process, wherein the electroplated metal layer covers a portion of the side walls of the metal seed layer; etching back the metal seed layer not covered by the electroplated metal layer until the side wall surface of the initial barrier layer is exposed, thereby forming the metal layer on the initial barrier layer.

[0008] Optionally, the method of etching back the metal seed layer not covered by the electroplated metal layer includes: continuing the chemical electroplating process, using a current of 0.17 mA to 0.3 mA, and continuing for 0 seconds to 35 seconds.

[0009] Optionally, the step of forming the sealing layer includes: forming an initial sealing layer on the metal layer; annealing the initial sealing layer, and introducing oxygen during the annealing process to form the sealing layer on the metal layer.

[0010] Optionally, the initial sealing layer is formed by a selective growth process.

[0011] Optionally, the portion of the initial barrier layer not covered by the metal layer is etched away, and the method for forming the barrier layer includes: introducing hydrogen peroxide and ammonia water, the reaction temperature is 65° C. to 75° C., the concentration of the hydrogen peroxide is 0.1% to 6%, and the concentration of the ammonia water is 0.1% to 6%.

[0012] Optionally, the thickness of the sealing layer is

[0013] Optionally, the etching rate of the sealing layer is lower than the etching rate of the barrier layer.

[0014] Optionally, the sealing layer has a higher density than the metal layer.

[0015] Optionally, after forming the barrier layer, the method further includes: forming a cap layer on the sealing layer, wherein the top surface of the cap layer is flush with the top surface of the contact hole.

[0016] Correspondingly, the present invention also provides a semiconductor device, comprising: a substrate; a source-drain doped layer located in the substrate; a contact hole located in the substrate and with the bottom exposing the top surface of the source-drain doped layer; a barrier layer located at the bottom and part of the side wall of the contact hole; a metal layer located on the barrier layer; and a sealing layer located on the metal layer.

[0017] Optionally, the method further includes: a cap layer, wherein the cap layer is located on the sealing layer, and the top surface of the cap layer is flush with the top surface of the contact hole.

[0018] Optionally, the thickness of the sealing layer is

[0019] Optionally, the etching rate of the sealing layer is lower than the etching rate of the barrier layer.

[0020] Optionally, the sealing layer has a higher density than the metal layer.

[0021] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0022] In the formation method of the present invention, after the sealing layer is formed on the metal layer, the sealing layer protects the metal layer very well. In this way, in the process of etching and removing the part of the initial barrier layer not covered by the metal layer to form the barrier layer, due to the protective effect of the sealing layer, the metal layer will not be damaged in the etching process, thereby improving the formation quality of the metal layer and helping to improve the quality and yield of the formed semiconductor device.

[0023] In the device of the present invention, a sealing layer is formed on the metal layer, and the top surface of the metal layer is protected by the sealing layer and the sealing pillar. In this way, the surface of the metal layer will not be damaged in any subsequent process due to the protective effect of the sealing layer, thereby ensuring the quality of the metal layer and preparing for the formation of high-quality and high-yield semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figures 1 to 6 is a structural schematic diagram of a semiconductor device forming process in one embodiment;

[0025] Figures 7 to 13 It is a structural schematic diagram of a semiconductor device forming process in one embodiment of the present invention. DETAILED DESCRIPTION

[0026] Currently, in the process of forming metal plugs using metal layers, the quality of the metal plugs is poor and they are prone to defects, which results in poor quality of the formed metal plugs, affecting the electrical performance and usability of semiconductor devices and limiting the use of semiconductor devices. For the specific formation process, please refer to Figures 1 to 6 .

[0027] First reference Figure 1 , providing a substrate 100, the substrate 100 includes a substrate 101, a gate structure 102 located on the substrate 101, a source-drain doped layer 103 located on both sides of the gate structure 102, and a dielectric layer 104 located on top of the substrate 101, the gate structure 102 and the source-drain doped layer 103.

[0028] Please refer to Figure 2 , etching the dielectric layer 104 to form a contact hole 105 in the dielectric layer 104 , wherein the bottom of the contact hole 105 exposes the top surface of the source / drain doped layer 103 .

[0029] Please refer to Figure 3 An initial barrier layer 106 is formed on the bottom and sidewalls of the contact hole 105 and the surface of the dielectric layer 104 , and an initial metal layer 107 is formed on the initial barrier layer 106 .

[0030] Please refer to Figure 4, the initial metal layer 107 is planarized until the top surface of the dielectric layer 104 is exposed, and an intermediate barrier layer 108 and an intermediate metal layer 109 are formed on the bottom and sidewalls of the contact hole 105, and the intermediate metal layer 109 fills the contact hole 105.

[0031] Please refer to Figure 5 , partially etching back the intermediate metal layer 109 to form a metal layer 110 , wherein the metal layer 110 fills a portion of the contact hole 105 and covers a portion of the sidewall of the intermediate barrier layer 108 .

[0032] The metal layer 110 serves as a metal plug to achieve electrical connection between the source / drain doped layer 103 and the outside.

[0033] Please refer to Figure 6 , the intermediate barrier layer 108 not covered by the metal layer 110 is etched away to form a barrier layer 111 , wherein the top surface of the barrier layer 111 is flush with the top surface of the metal layer 110 .

[0034] After forming the barrier layer 111 , a sealing layer is formed on the surface of the metal layer 110 , and then a cap layer is formed on the sealing layer. The top surface of the cap layer is flush with the top surface of the contact hole 105 .

[0035] The inventors have discovered that semiconductor devices formed using this method suffer from poor performance stability and are prone to failure, limiting their use. This is because the process of etching away the intermediate barrier layer 108 not covered by the metal layer 110 to form the barrier layer 111 results in the loss of the metal layer 110, resulting in poor formation quality of the metal layer 110, which affects the quality and yield of the resulting semiconductor device.

[0036] The inventors have discovered that a sealing layer is formed on the metal layer, which protects the metal layer very well. In this way, in the process of etching away the part of the initial barrier layer not covered by the metal layer to form a barrier layer, due to the protective effect of the sealing layer, the metal layer will not be damaged during the etching process, thereby improving the formation quality of the metal layer and helping to improve the quality and yield of the formed semiconductor devices.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 7 to 13 It is a structural schematic diagram of a semiconductor device forming process in one embodiment of the present invention.

[0039] First reference Figure 7, providing a substrate 200 , wherein a contact hole 201 is formed in the substrate 200 , and the bottom surface of the contact hole 201 exposes the top surface of the source-drain doped layer 202 in the substrate 200 .

[0040] In this embodiment, the base 200 includes a substrate 203 , a gate structure 204 on the substrate 203 , the source / drain doped layers 202 on both sides of the gate structure 204 , and a dielectric layer 208 covering the substrate 203 , the gate structure 204 , and the source / drain doped layers 202 .

[0041] In this embodiment, a plurality of fins (not shown) arranged in parallel are further formed on the substrate 203 , and the gate structure 204 spans across the fins and covers part of the sidewalls and bottom surfaces of the fins.

[0042] In other embodiments, the fin may not be formed on the substrate 203 .

[0043] In this embodiment, the substrate 203 is made of single crystal silicon.

[0044] In other embodiments, the substrate 203 may be polycrystalline silicon or amorphous silicon. The substrate 201 may also be made of semiconductor materials such as germanium, silicon germanium, gallium arsenide, silicon on insulator (SOI), and germanium on insulator (GOI).

[0045] In this embodiment, an isolation structure (not shown in the figure) is further formed on the substrate 203 , and the isolation structure covers a portion of the sidewall of the fin.

[0046] In this embodiment, the isolation structure functions to form electrical isolation.

[0047] In this embodiment, the gate structure 204 includes a gate dielectric layer (not shown in the figure), a gate layer 205 located on the gate dielectric layer, a protective layer 206 located on the gate layer 205, and sidewalls 207 located on the side walls of the gate layer 205 and the protective layer 206.

[0048] In this embodiment, the material of the gate dielectric layer includes a high-K dielectric material, such as oxides such as Al2O3, HfO2, Ta2O5, TiO2, and ZrO2.

[0049] In other embodiments, the material of the gate dielectric layer may further include other dielectric materials with a dielectric constant higher than 3.9.

[0050] In this embodiment, the gate layer 205 is made of metal, and the metal material includes one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum.

[0051] In this embodiment, the material of the protective layer 206 includes silicon nitride or silicon oxide. In other embodiments, the material of the protective layer 206 may also be one or more combinations of materials such as silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron carbonitride (SiCBN).

[0052] In this embodiment, the material of the side wall 207 is silicon oxide; in other embodiments, the material of the side wall 207 can also be one or more combinations of materials such as silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron carbonitride (SiCBN).

[0053] The sidewall spacers 207 are used to define the positions of the source and drain doping layers.

[0054] In this embodiment, the process for forming the gate structure 204 is a gate-last process, that is, a dummy gate structure is first formed on the substrate 203, and after forming the source and drain doping layers, the dummy gate structure is removed and the gate structure 204 is formed in its place.

[0055] In other embodiments, a gate-first process may be used, that is, the gate structure 204 is formed directly on the substrate 203 without using a dummy gate structure in advance.

[0056] In this embodiment, the process of forming the source / drain doping layer 202 includes an epitaxial growth process.

[0057] In this embodiment, before forming the gate structure 204 , the source-drain doped layer 202 is formed in the substrate 203 .

[0058] In this embodiment, only one source-drain doped layer 202 is shown.

[0059] In this embodiment, the dielectric layer 208 is used as an interlayer dielectric isolation material, and the material used is silicon carbide.

[0060] In other embodiments, the material of the dielectric layer 208 may also be one or a combination of silicon carbide, silicon oxide, or silicon nitride.

[0061] In this embodiment, the process parameters for forming the dielectric layer 208 include: the gases used include hydrogen, HCl gas, SiH2Cl2 and PH3, the flow rate of hydrogen is 2000sccm~20000sccm, the flow rate of HCl gas is 30sccm~150sccm, the flow rate of SiH2Cl2 is 50sccm~1000sccm, the flow rate of PH3 is 10sccm~2000sccm, the chamber pressure is 10torr~600torr, and the temperature is 650 degrees Celsius~850 degrees Celsius.

[0062] In this embodiment, the dielectric layer 208 is formed by a chemical vapor deposition process; in other embodiments, the dielectric layer 208 may be formed by physical vapor deposition or atomic layer vapor deposition.

[0063] In this embodiment, a patterned layer (not shown in the figure) is formed on the surface of the dielectric layer 208. The patterned layer is used as a mask to etch the dielectric layer 208, and a contact hole 201 is formed in the dielectric layer 208. The bottom surface of the contact hole 201 exposes the top surface of the source-drain doped layer 202.

[0064] In this embodiment, the process of forming the contact hole 201 is a dry etching process; in other embodiments, the process of forming the contact hole 201 is a wet etching process, a dry etching process, or a combination of a wet etching process and a dry etching process.

[0065] In this embodiment, dry etching is used to form the contact hole 201 because dry etching has a strong etching directionality, and the etching rate of the dry etching process in the vertical direction is greater than the etching rate in the horizontal direction. This ensures that no damage is caused to surrounding devices during the process of forming the contact hole 201.

[0066] In this embodiment, the specific parameters of the dry etching process include: the gases used include CF4 gas, CH3F gas and O2, the flow rate of CF4 gas is 5sccm~100sccm, the flow rate of CH3F gas is 8sccm~50sccm, the flow rate of O2 is 10sccm~100sccm, the chamber pressure is 10mtorr~2000mtorr, the RF power is 50W~300W, the bias voltage is 30V~100V, and the time is 4 seconds~50 seconds.

[0067] Please refer to Figure 8 , forming an initial barrier layer 209 on the bottom and sidewalls of the contact hole 201 .

[0068] In this embodiment, the material of the initial barrier layer 209 is TiN.

[0069] In other embodiments, the material of the initial barrier layer 209 may also be Ti, TiN or TaN, or a combination thereof.

[0070] In this embodiment, the process for forming the initial barrier layer 209 is an atomic layer deposition process; in other embodiments, the process for forming the initial barrier layer 209 may also be a chemical vapor deposition process, a physical vapor deposition process, etc.

[0071] In this embodiment, the reason why the atomic layer deposition process is used to form the initial barrier layer 209 is that the atomic layer deposition process can form the initial barrier layer 209 with good density and good coverage gradient, so that the initial barrier layer 209 and the contact hole 201 have good formation quality and will not have defects such as holes and uneven coverage.

[0072] In this embodiment, the initial barrier layer 209 serves as an adhesion layer between the subsequently formed metal layer and the contact hole 201, which can improve the formation quality of the metal layer in the contact hole 201; the initial barrier layer 209 also serves as a barrier layer, preventing the diffused ions in the blocking metal layer from damaging the source-drain doping layer 202 during the process of forming the metal layer.

[0073] A metal layer is formed on the initial barrier layer, and the metal layer covers a portion of the sidewall of the initial barrier layer. For a detailed formation process, please refer to Figures 9 and 10 .

[0074] Please refer to Figure 9 , forming a metal seed layer 210 on the bottom and sidewalls of the initial barrier layer 209 ; forming an electroplated metal layer 211 on the metal seed layer 210 by a chemical electroplating process, wherein the electroplated metal layer 211 covers a portion of the sidewalls of the metal seed layer 210 .

[0075] In this embodiment, a metal seed layer 210 is formed on the surface of the initial barrier layer 209 on the dielectric layer 208 and on the bottom and sidewalls of the contact hole 201 .

[0076] In this embodiment, the material of the metal seed layer 210 is a cobalt metal seed layer; in other embodiments, the material of the metal seed layer 210 may also be copper, tungsten, etc.

[0077] In this embodiment, the metal seed layer 210 is deposited by ionized plasma.

[0078] In this embodiment, the process parameters for forming the metal seed layer 210 include: using CCTBA as the organic source, the reaction gases include hydrogen (H2) and argon (Ar), wherein the flow rate of hydrogen (H2) is 1000-8000 sccm, and the flow rate of argon (Ar) is 10-500 sccm; the source RF power is 100-2000 W, the temperature is 100-400° C., and the pressure is 10-40 Torr.

[0079] In this embodiment, the reason for first forming the metal seed layer 210 on the bottom and side walls of the initial barrier layer 209 is that it provides good interface conditions for the subsequent formation of the metal layer, ensures good bonding quality between the formed metal layer and the initial barrier layer 209, and improves the interface formation quality between the metal layer and the initial barrier layer 209.

[0080] In this embodiment, the material of the electroplated metal layer 211 is cobalt (Co); in other embodiments, the material of the electroplated metal layer 211 may also be copper (Cu), tungsten (W), etc.

[0081] In this embodiment, a chemical electroplating process is used to form an electroplated metal layer 211 on the metal seed layer 210, and the electroplated metal layer 211 covers a portion of the side wall of the metal seed layer 210. Since the chemical electroplating process is essentially to connect the wafer to the cathode and place it in an acidic solution containing metal ions to be deposited, and the cobalt connected to the anode is also placed in the solution, the current flows from the cobalt electrode at the anode to the wafer at the cathode, and the ionized ions nucleate on the metal seed layer 210, eventually forming the electroplated metal layer 211.

[0082] In this embodiment, the purpose of the electroplated metal layer 211 covering part of the side wall of the metal seed layer 210 is to reduce the subsequent back-etching process. If the electroplated metal layer 211 fills the contact hole 201, the electroplated metal layer 211 needs to be back-etched to fill only part of the contact hole 201. The use of a chemical electroplating process can control the height of the formed electroplated metal layer 211, thereby avoiding damage to the device caused by subsequent multiple etchings.

[0083] Please refer to Figure 10 , the metal seed layer 210 not covered by the electroplated metal layer 211 is etched back until the sidewall surface of the initial barrier layer 209 is exposed, and the metal layer 212 is formed on the initial barrier layer 209 .

[0084] In this embodiment, the method for etching back the metal seed layer 210 not covered by the electroplated metal layer 211 includes: continuing the chemical electroplating process with a current of 0.17 mA to 0.3 mA for 0 seconds to 35 seconds.

[0085] In this embodiment, in an acidic reaction environment, under the action of low current, the formation speed of the electroplated metal layer 211 is lower than the consumption speed of the metal seed layer 210. After 0 to 35 seconds, the metal seed layer 210 not covered by the electroplated metal layer 211 is removed. This can avoid damage to other devices caused by dry etching or wet etching, and help improve the quality of the semiconductor device finally formed.

[0086] In this embodiment, after the electroplated metal layer 211 is deposited on the metal seed layer 210, the metal seed layer 210 and the electroplated metal layer 211 are fused together. Figure 10 In the figure, the metal seed layer 210 and the electroplated metal layer 211 finally in the contact hole 201 are collectively referred to as a metal layer 212 .

[0087] In this embodiment, the metal layer 212 serves as a metal plug for the source and drain, and is used to achieve electrical connection between the source and drain doped layer 202 and the outside.

[0088] Please refer to Figure 11 , forming a sealing layer 213 on the metal layer 212 .

[0089] In this embodiment, the step of forming the sealing layer 213 includes: forming an initial sealing layer on the metal layer 212 ; annealing the initial sealing layer, while introducing oxygen during the annealing process, to form the sealing layer 213 on the metal layer 212 .

[0090] In this embodiment, the initial sealing layer is formed by a selective growth process; in other embodiments, an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process may also be used.

[0091] In this embodiment, the initial sealing layer is made of cobalt; in other embodiments, other metal materials such as tungsten and copper may also be used.

[0092] In this embodiment, the material of the initial sealing layer is the same as that of the metal layer 212. This has the following advantages: during the annealing process, the initial sealing layer is oxidized into the sealing layer 213. Since the sealing layer 213 is an oxide, it has greater electrical insulation. In the subsequent process of forming interconnect lines, the sealing layer 213 can be reduced to the initial sealing layer by a reduction reaction, thereby reducing the influence of the insulating material on the resistance Rc / Rs. At the same time, since the metal layer 212 is made of the same material as that of the initial sealing layer, the differences between different metal materials are also avoided, which helps to reduce the differences in electrical properties caused by the differences between metal materials and improve the coordination of the electrical properties of the formed semiconductor device.

[0093] In this embodiment, the reason for using a selective growth process to form the initial sealing layer is that the initial sealing layer formed by the selective growth process grows upward from the surface of the metal layer 212, has good directionality, and the initial sealing layer formed has good density and coverage.

[0094] In this embodiment, process parameters for annealing the initial sealing layer include: an oxygen gas flow rate of 800 sccm to 3000 sccm, an annealing temperature of 350° C. to 450° C., and a pressure of 2 Torr to 40 Torr.

[0095] In this embodiment, when the oxygen gas flow rate is less than 800 sccm, there is not enough oxygen, so that the density and thickness of the formed sealing layer 213 cannot effectively seal the metal layer 212; when the oxygen gas flow rate is greater than 3000 sccm, there is too much oxygen, and over-oxidation is likely to occur, affecting the quality of the semiconductor device finally formed.

[0096] In this embodiment, the annealing temperature is 350°C to 450°C. When the annealing temperature is less than 350°C, the temperature is too low, resulting in a slow reaction rate or no reaction; when the annealing temperature is greater than 450°C, sintering occurs due to the excessively high temperature.

[0097] In this embodiment, the pressure is 2 torr to 40 torr; when the pressure is less than 2 torr, the reaction pressure is too small, resulting in a too slow reaction rate, or even failure of chemical reaction; when the pressure is greater than 40 torr, the reaction pressure is too large, resulting in an overly fast reaction rate, and overreaction is likely to occur.

[0098] In this embodiment, oxygen is introduced during the annealing process, so that the initial sealing layer is oxidized during the annealing process, thereby making the formed sealing layer 213 highly dense and having enhanced etching resistance.

[0099] In this embodiment, the sealing layer 213 is made of cobalt oxide.

[0100] In this embodiment, the thickness of the sealing layer 213 is When the thickness of the sealing layer 213 is less than The thickness of the sealing layer 213 formed at this time is too thin, resulting in poor sealing and failure to protect the metal layer 212 below. As a result, the thickness of the sealing layer 213 is too thick. In the subsequent process of forming interconnect lines, the sealing layer 213 cannot be completely reduced to its original metal state. As a result, in the process of forming interconnect lines, there is insulating material between the metal layer 212 and the connection layer, causing Rc / Rs to be too large, which affects the electrical performance of the final semiconductor device.

[0101] In this embodiment, the density of the sealing layer 213 is greater than that of the metal layer 212 . The sealing layer 213 can effectively protect the metal layer 212 and prevent defects such as missing of the metal layer 212 in subsequent processes.

[0102] Please refer to Figure 12 , etching away the portion of the initial barrier layer 209 not covered by the metal layer 212 to form the barrier layer 214 .

[0103] In this embodiment, the method for etching away the portion of the initial barrier layer 209 not covered by the metal layer 212 to form the barrier layer 214 includes: introducing hydrogen peroxide and ammonia water, the reaction temperature is 65° C. to 75° C., the concentration of the hydrogen peroxide is 0.1% to 6%, and the concentration of the ammonia water is 0.1% to 6%.

[0104] In this embodiment, after the sealing layer 213 is formed on the metal layer 212, the sealing layer 213 protects the metal layer 212 very well. In this way, in the process of etching away the portion of the initial barrier layer 209 not covered by the metal layer 212 to form the barrier layer 214, due to the protective effect of the sealing layer 213, the metal layer 212 will not be damaged during the etching process, thereby improving the formation quality of the metal layer 212 and helping to improve the quality and yield of the formed semiconductor device.

[0105] In this embodiment, the etching rate of the sealing layer 213 is lower than the etching rate of the barrier layer 214 , ensuring that the sealing layer 213 is not easily etched under the same etching environment, so that the sealing layer 213 can play a good protective role for the metal layer 212 .

[0106] Please refer to Figure 13 After forming the barrier layer 214 , the method further includes: forming a cap layer 215 on the sealing layer 213 , wherein the top surface of the cap layer 215 is flush with the top surface of the contact hole 201 .

[0107] In this embodiment, the material of the cap layer 215 is silicon carbide; in other embodiments, the material of the cap layer 215 may also be silicon nitride, silicon oxide, silicon oxycarbide, or the like.

[0108] In this embodiment, the step of forming the cap layer 215 includes: forming an initial cap layer on the surface of the dielectric layer 208, the surface of the sealing layer 213, and the surface of the barrier layer 214, planarizing the initial cap layer until the surface of the protective layer 206 is exposed, and forming a cap layer 215 on the sealing layer 213, wherein the top surface of the cap layer 215 is flush with the top surface of the contact hole 201.

[0109] Correspondingly, the present invention also provides a semiconductor device, comprising: a substrate 200; a source-drain doped layer 202, located in the substrate 200; a contact hole 201, located in the substrate 200 and with the top surface of the source-drain doped layer 202 exposed at the bottom; a barrier layer 214, located at the bottom and part of the sidewall of the contact hole 201; a metal layer 212, located on the barrier layer 214; and a sealing layer 213, located on the metal layer 212.

[0110] In this embodiment, the sealing layer 213 is formed on the metal layer 212, and the top surface of the metal layer 212 is provided with a sealing column by the sealing layer 213. In this way, the surface of the metal layer 212 will not be damaged in any subsequent process due to the protective effect of the sealing layer 213, thereby ensuring the quality of the metal layer 212 and preparing for the formation of high-quality and high-yield semiconductor devices.

[0111] The system further includes a cap layer 215 , which is located on the sealing layer, and a top surface of the cap layer is flush with a top surface of the contact hole.

[0112] In this embodiment, the material of the cap layer 215 is silicon carbide; in other embodiments, the material of the cap layer 215 may also be silicon nitride, silicon oxide, silicon oxycarbide, or the like.

[0113] In this embodiment, the step of forming the cap layer 215 includes: forming an initial cap layer on the surface of the dielectric layer 208, the surface of the sealing layer 213, and the surface of the barrier layer 214, planarizing the initial cap layer until the surface of the protective layer 206 is exposed, and forming a cap layer 215 on the sealing layer 213, wherein the top surface of the cap layer 215 is flush with the top surface of the contact hole 201.

[0114] In this embodiment, the thickness of the sealing layer 213 is When the thickness of the sealing layer 213 is less than The thickness of the sealing layer 213 formed at this time is too thin, resulting in poor sealing and failure to protect the metal layer 212 below. As a result, the thickness of the sealing layer 213 is too thick. In the subsequent process of forming interconnect lines, the sealing layer 213 cannot be completely reduced to its original metal state. As a result, in the process of forming interconnect lines, there is insulating material between the metal layer 212 and the connection layer, causing Rc / Rs to be too large, which affects the electrical performance of the final semiconductor device.

[0115] In this embodiment, the etching rate of the sealing layer 213 is lower than the etching rate of the barrier layer 214 , ensuring that the sealing layer 213 is not easily etched under the same etching environment, so that the sealing layer 213 can play a good protective role for the metal layer 212 .

[0116] In this embodiment, the density of the sealing layer 213 is greater than that of the metal layer 212 . The sealing layer 213 can effectively protect the metal layer 212 and prevent defects such as missing of the metal layer 212 in subsequent processes.

[0117] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, wherein a contact hole is formed in the substrate, and the bottom surface of the contact hole exposes the top surface of the source-drain doped layer in the substrate; forming an initial barrier layer on the bottom and sidewalls of the contact hole; forming a metal layer on the initial barrier layer, wherein the metal layer covers a portion of a sidewall of the initial barrier layer; forming a sealing layer on the metal layer; Etching and removing the portion of the initial barrier layer not covered by the metal layer to form the barrier layer; The step of forming the sealing layer comprises: forming an initial sealing layer on the metal layer; The initial sealing layer is annealed, and oxygen is introduced during the annealing process to form the sealing layer on the metal layer.

2. The forming method according to claim 1, wherein: The steps of forming the metal layer include: forming a metal seed layer on the bottom and sidewalls of the initial barrier layer; forming an electroplated metal layer on the metal seed layer by a chemical electroplating process, wherein the electroplated metal layer covers a portion of the sidewall of the metal seed layer; The metal seed layer not covered by the electroplated metal layer is etched back until the sidewall surface of the initial barrier layer is exposed, thereby forming the metal layer on the initial barrier layer.

3. The forming method according to claim 2, wherein: The method for etching back the metal seed layer not covered by the electroplated metal layer includes: continuing the chemical electroplating process, using a current of 0.17 mA to 0.3 mA, and continuing for 0 seconds to 35 seconds.

4. The forming method according to claim 1, wherein: The initial sealing layer is formed by a selective growth process.

5. The forming method according to claim 1, wherein: The portion of the initial barrier layer not covered by the metal layer is removed by etching. The method for forming the barrier layer includes: introducing hydrogen peroxide and ammonia water, the reaction temperature is 65° C. to 75° C., the concentration of the hydrogen peroxide is 0.1% to 6%, and the concentration of the ammonia water is 0.1% to 6%.

6. The forming method according to claim 1, wherein: The thickness of the sealing layer is 15Å~30Å.

7. The forming method according to claim 1, wherein: The etching rate of the sealing layer is lower than the etching rate of the barrier layer.

8. The forming method according to claim 1, wherein: The sealing layer has a higher density than the metal layer.

9. The forming method according to claim 1, wherein: After forming the barrier layer, the method further includes forming a cap layer on the sealing layer, wherein the top surface of the cap layer is flush with the top surface of the contact hole.

10. A semiconductor device formed by the forming method according to any one of claims 1 to 9, characterized in that: include: substrate; a source-drain doped layer, located in the substrate; a contact hole, located in the substrate and having a bottom portion exposing a top surface of the source-drain doped layer; a barrier layer, located on the bottom and a portion of the sidewall of the contact hole; a metal layer located on the barrier layer; The sealing layer is located on the metal layer.

11. The semiconductor device according to claim 10, wherein Also includes: A cap layer is located on the sealing layer, and a top surface of the cap layer is flush with a top surface of the contact hole.

12. The semiconductor device according to claim 10, wherein The thickness of the sealing layer is 15Å~30Å.

13. The semiconductor device according to claim 10, wherein The etching rate of the sealing layer is lower than the etching rate of the barrier layer.

14. The semiconductor device according to claim 10, wherein The sealing layer has a higher density than the metal layer.

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