An SOC integrated packaging structure based on an LTCC substrate and a manufacturing method thereof

Abstract

The application discloses a kind of SOC integrated packaging structure and manufacturing method based on LTCC substrate, the packaging structure contains a system level chip SOC with more than 600 pins, uses low temperature co-fired ceramic (LTCC) as packaging carrier substrate, multiple layers of cavities are arranged in the substrate, SOC chip is adhered in the cavity using conductive glue, and the interconnection of SOC chip and packaging substrate is carried out using high-purity gold wire.Metalized via and conductor are arranged inside the multilayer ceramic substrate to interconnect the input / output terminals of the SOC chip with the leads on the back surface of the substrate, and solder balls are planted on the back surface of the substrate to form a ball grid array (BGA).The application realizes the integrated packaging of large-scale SOC chips, has high packaging density, small packaging volume, and can withstand high overload.The application uses 3 layers of cavities, 4 layers of bonding areas, and staggered bonding wires to realize the small size packaging of large-scale fine-pitch chips.

Description

TECHNICAL FIELD

[0001] The application discloses an SOC integrated packaging structure based on an LTCC substrate and a manufacturing method thereof, and belongs to the technical field of semiconductor packaging. BACKGROUND

[0002] Conventional SOC packaging usually adopts high-temperature ceramics as a shell or a plastic packaging structure. The plastic packaging shell cannot meet the application of high reliability, and the packaging adopting high-temperature ceramics as a shell material is not suitable for the application of high-frequency high-speed devices due to the high dielectric constant of the material and the low conductivity of the conductor material. SUMMARY

[0003] The application aims to provide an SOC integrated packaging structure based on an LTCC substrate and a manufacturing method thereof, which has high packaging density, small packaging volume and can withstand high overload.

[0004] To achieve the above-mentioned purpose, the application adopts the following technical scheme:

[0005] The application provides an SOC integrated packaging structure based on an LTCC substrate, which comprises an integrated packaging shell formed by an LTCC substrate with multiple cavities and a metal frame, a SOC chip is adhered in the middle of the bottom cavity by conductive adhesive, the metal frame is welded on the film-forming substrate, the inside of the substrate is provided with a metallized through hole, and the input / output end of the SOC chip is interconnected with the through hole of the substrate through a bonding wire.

[0006] The back surface of the substrate is provided with solder balls to form a ball grid array.

[0007] Further, the substrate is provided with 3 cavities, and the cavity depth is 0.2 mm.

[0008] Further, the interval between the bonding areas of the substrate is designed to be 50-58 microns.

[0009] Further, the substrate and the cavities therein form 1, 2, 3 and 4 layers from top to bottom.

[0010] The chip bonding area is double-layer arranged, the inner bonding area of the chip is interconnected with the 1st layer and the 2nd layer of the substrate, and the outer bonding area is interconnected with the 3rd layer and the 4th layer of the substrate.

[0011] Further, the bonding wire connected with the 4th layer bonding area of the substrate has the lowest arc height, and the remaining bonding wires are sequentially raised.

[0012] The application further provides a manufacturing method of the SOC integrated packaging structure based on the LTCC substrate, which comprises the following steps:

[0013] (1) manufacturing a substrate;

[0014] (2) welding the metal frame on the film-forming substrate by means of vacuum eutectic welding;

[0015] (3) implanting soldering balls on the back of the substrate;

[0016] (4) mounting the system-level SOC chip in the middle of the cavity of the substrate bottom layer by means of conductive adhesive;

[0017] (5) connecting the SOC chip and the substrate by means of bonding wires;

[0018] (6) testing the finished SOC packaging structure;

[0019] (7) sealing the metal frame by covering a cover plate.

[0020] Further, the manufacturing substrate comprises the following steps:

[0021] (11) forming green ceramic pieces, punching holes on the green ceramic pieces, and printing conductors to fill the holes;

[0022] (12) performing pattern printing and laser etching to form a bonding area;

[0023] (13) forming a plurality of cavities by cavityizing and cutting the substrate;

[0024] (14) inserting laminated pieces into the cavities, laminating, and then sintering at 850 DEG C to complete the substrate processing.

[0025] Further,

[0026] The conductor material printed on the surface layer of the substrate is any one of gold and palladium silver;

[0027] The conductor material printed on the inner layer of the substrate is silver;

[0028] The conductor film printed on the substrate has a thickness of 5-12 microns, the minimum width of the conductor is 4 mils, and the minimum interval of the conductor is 2 mils;

[0029] Further,

[0030] The cover plate is welded by means of parallel seam welding or laser welding.

[0031] Further, high-purity gold wires are used as the bonding wires.

[0032] The present application has the following advantages:

[0033] 1) The present application uses a low-temperature ceramic co-firing (LTCC) substrate with a plurality of cavities, and forms an integrated packaging shell by welding the frame through vacuum eutectic welding, thereby realizing integrated packaging of large-scale SOC chips, having high packaging density, small packaging volume, and being able to withstand high overload.

[0034] 2) The application adopts LTCC as a packaging carrier, has the advantages of low dielectric constant and low conductor resistivity, and realizes low-loss transmission of high-frequency and high-speed signals.

[0035] 3) The application adopts 3-layer cavities and 4-layer bonding area layout, and the bonding wires are arranged in an interleaved manner, so that large-scale fine-pitch chip small-size packaging is realized.

[0036] 4) The application adopts BGA packaging form, and meets a large number of input / output terminals.

[0037] 5) After the assembly and testing of the device are completed, a cover plate is added to the metal frame, parallel seam welding or laser welding is adopted, air-tight packaging is realized, and high reliability is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 The LTCC substrate structure with a cavity in the application; Figure 1 (a) is a top view, Figure 1 (b) is a front view; Figure 1 (c) is a schematic view of the back of the substrate;

[0039] Figure 2 The front view of the SOC integrated packaging structure in the application;

[0040] Figure 3 The laser etching example in the substrate manufacturing process of the application;

[0041] Figure 4 The schematic view of the bonding interconnection multi-layer interleaved layout in the application;

[0042] Figure 5 The 3D schematic view of the bonding interconnection multi-layer interleaved layout in the application;

[0043] Figure 6 The schematic view of the SOC chip and the substrate interconnection in the application;

[0044] Figure 7 The substrate processing flowchart in the application;

[0045] Figure 8 The assembly flowchart of the SOC integrated packaging structure in the application. DETAILED DESCRIPTION

[0046] The application will be further described below. The following examples are only used to more clearly illustrate the technical solutions of the application, and cannot be used to limit the protection scope of the application.

[0047] The application provides an SOC integrated packaging structure based on an LTCC substrate, as shown in Figure 2The integrated package shell 1 is formed by a low-temperature ceramic co-firing (LTCC) substrate with multiple layers of cavities and a metal frame, the metal frame is welded on the film-forming substrate by vacuum eutectic welding, the system-level SOC chip is adhered in the cavity by conductive adhesive, and the SOC chip and the package substrate are interconnected by high-purity gold wires.

[0048] Referring to Figure 1 (a), the LTCC substrate is used to manufacture a two-piece MEMS gyroscope package, a temperature feedback channel is added between the MEMS gyroscope and the ASIC during the conventional electrical interconnection design, and temperature compensation is realized by a specific programming algorithm of the ASIC.

[0049] In the present application, the metalized through holes and conductors in the substrate interconnect the input / output terminals of the SOC chip with the leads on the back of the substrate.

[0050] Referring to Figure 1 (c), the solder balls are planted on the back of the substrate to form a ball grid array (BGA).

[0051] Referring to Figure 1 (b), the laser is used to cut the cavity pattern in the substrate, and the cavity is filled with a laminated sheet.

[0052] Preferably, three layers of cavities are arranged in the substrate.

[0053] In the present application, the chip is adhered in the middle of the bottom cavity by conductive adhesive. The present application supports system-level chips (SOC) with more than 600 pins.

[0054] In the present application, the spacing between the bonding areas of the substrate is designed to be 50-58 microns.

[0055] Referring to Figure 4 , Figure 5 and Figure 6 , the chip bonding area 2 is arranged in two layers. When the bonding interconnection is performed, every four bonding wires 3 on the chip bonding area are sequentially bonded with the bonding areas of the four layers of the substrate, the inner chip bonding area is interconnected with the first and second layers of the substrate, and the outer bonding area is interconnected with the third and fourth layers of the substrate. By controlling the arc height and direction of the bonding wires, the three-dimensional interlacing of the multi-layer bonding wires is realized. The arc height control principle is that the arc height of the bonding wire connected with the fourth layer (the bottom layer) of the substrate is the lowest, the arc heights of the remaining bonding wires connected with the layers are sequentially increased in descending order, and the arc height of the first layer bonding wire is the highest. Finally, the interconnection between the chip and the substrate is shown in Figure 6 .

[0056] The present application also provides a manufacturing method of the SOC integrated package structure based on the LTCC substrate, referring to Figure 8 , comprising:

[0057] manufacturing a substrate;

[0058] welding the substrate and the metal frame into one body;

[0059] implanting solder balls on the back of the substrate;

[0060] mounting the system-level SOC chip in the substrate;

[0061] connecting the SOC chip and the lead of the packaging substrate;

[0062] testing the finished SOC packaging structure;

[0063] sealing the metal frame by covering it with a cover plate.

[0064] Referring to Figure 7 , the manufacturing of the substrate comprises the following steps:

[0065] forming a green sheet, punching holes in the green sheet and printing conductive material to fill the holes for connecting the leads;

[0066] forming a bonding area by graphic printing and laser etching;

[0067] cavitation cutting the substrate to form multiple layers of cavities, inserting the laminated sheet into the cavities and sintering the substrate at 850 DEG C to complete the manufacturing of the substrate.

[0068] In the present application, laser is used to punch holes in the green sheet.

[0069] In the present application, the surface of the substrate and the interlayer printed conductive material are gold, silver, palladium silver, etc.

[0070] Referring to Figure 3 , the high-precision conductive material with a distance of 50 microns between the conductors is processed by laser etching process, that is, the whole surface of the conductor is printed in the area where the conductor of the bonding area is needed, and then the laser is used to strip off the excess part according to the actual design of the conductor pattern, and finally the required pattern is etched.

[0071] In the present application, laser is used to cut the cavity pattern.

[0072] In the present application, the metal frame is welded on the film-forming substrate by vacuum eutectic welding.

[0073] In the present application, the SOC chip is bonded in the middle of the bottom cavity by conductive adhesive.

[0074] In the present application, Figure 4 and Figure 5 are used to connect the SOC chip and the lead of the packaging substrate;

[0075] In the present application, the cover plate is welded by parallel seam welding or laser welding.

[0076] The process parameters are designed as follows:

[0077] 1) Substrate type: low temperature ceramic co-fired LTCC;

[0078] 3) Substrate conductive band: surface layer conductor material: gold, palladium silver, inner layer conductor material: silver, printed film, conductor film thickness 5-12 microns, minimum conductor width: 4 mils (0.1 mm), minimum conductor spacing: 2 mils (50 microns);

[0079] 4) Through hole diameter: electrical interconnection through hole: 4 mils (0.1 mm), heat conducting metal column through hole: ≥10 mils (0.25 mm);

[0080] 5) Interlayer metal strip; material: gold, film thickness: 10-15 microns.

[0081] 6) Cavity layer number: 3 layers; cavity depth: 0.2 mm;

[0082] 7) Minimum bonding point center distance: 52 microns, bonding point number: >600;

[0083] 8) BGA solder ball diameter: Φ0.4 mm; solder ball number: >600.

[0084] The above only describes the preferred embodiments of the present application, and it should be noted that for those skilled in the art, without departing from the technical principles of the present application, a number of improvements and modifications can be made, and these improvements and modifications should be considered as the protection scope of the present application.

Claims

1. An SOC-integrated package structure based on an LTCC substrate, characterized in that, The integrated package shell is formed by a LTCC substrate with multi-layer cavities and a metal frame, a SOC chip is adhered to the center of the bottom cavity by conductive adhesive, the metal frame is welded on the substrate, the substrate is internally provided with metallized through holes, and the input / output terminals of the SOC chip are interconnected with the substrate through holes by bonding wires; Three layers of cavities are arranged in the substrate, and the substrate and the cavities therein form 1, 2, 3 and 4 layers from top to bottom; The bonding areas of the SOC chip are arranged in double layers, the inner bonding areas of the SOC chip are interconnected with the 1st and 2nd layers of the substrate, and the outer bonding areas are interconnected with the 3rd and 4th layers of the substrate; The bonding wires connected with the 4th layer of the substrate have the lowest arc height, and the other bonding wires are arranged in ascending order; The solder balls are planted on the back of the substrate to form a ball grid array.

2. The LTCC substrate-based SOC-integrated package structure according to claim 1, characterized in that, The depth of the cavity is 0.2mm.

3. The LTCC substrate-based SOC-integrated package structure according to claim 1, characterized in that, The interval between the bonding areas of the substrate is designed to be 50-58μm.

4. The manufacturing method of the LTCC substrate-based SOC-integrated package structure according to any one of claims 1 to 3, characterized by, The method comprises the following steps: (1) manufacturing the substrate; (2) welding the metal frame on the substrate by vacuum eutectic welding; (3) planting solder balls on the back of the substrate; (4) adhering the system-level SOC chip to the center of the bottom cavity of the substrate by conductive adhesive; (5) connecting the SOC chip and the substrate by bonding wires; (6) testing the manufactured SOC package structure; (7) sealing the metal frame by covering a cover plate.

5. The production method according to claim 4, wherein The manufacturing of the substrate comprises the following steps: (11) green ceramic sheeting, punching and printing conductors for filling holes; (12) pattern printing and laser etching to form bonding areas; (13) cavity cutting to form multi-layer cavities; (14) inserting laminated sheets in the cavities, laminating and then sintering at 850℃ to complete the substrate processing.

6. The manufacturing method according to claim 5, wherein, the conductor material printed on the surface layer of the substrate is any one of gold and palladium silver; the conductor material printed on the inner layer of the substrate is silver; the conductor film thickness of the printed substrate is 5-12μm, the minimum width of the conductor is 4mils, and the minimum interval of the conductor is 2mils.

7. The manufacturing method according to claim 5, wherein, the cover plate is welded by parallel seam welding or laser welding.

8. The production method according to claim 4, wherein high-purity gold wires are used as the bonding wires.

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