Packaging substrate interconnection structure capable of reducing warping probability

Abstract

A packaging substrate interconnection structure capable of reducing the warping probability comprises a first substrate set and a second substrate set, and the first substrate set comprises a first substrate and a first chip; the second substrate group comprises a second substrate and a plurality of second chips and solder ball groups; the bottom surface of the first substrate is connected with the top surface of the second substrate through a plurality of connecting point structures; a plurality of grooves are formed in the bottom surface of the second substrate, and the second chip is connected to the inner side circuit layer; the connection point structure comprises a first groove, a second groove, a first welding ball, a conductive part and a conductive column, the first groove and the second groove are oppositely arranged, one of the first groove and the second groove is arranged on the first substrate, the other of the first groove and the second groove is arranged on the second substrate, the first welding ball is arranged on the bottom surface of the first groove and protrudes out of the first groove, and the conductive part is arranged on the bottom surface of the second groove. The conductive parts are filled outside the first solder balls, and the conductive columns are connected to the conductive parts and are filled in the second grooves. The device is high in practicability and has high popularization significance.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of packaging substrate, and specifically relates to a packaging substrate interconnection structure capable of reducing warping probability. BACKGROUND

[0002] In order to meet the requirements of multifunction and integration, electronic components (such as chips) are usually arranged on the substrate and packaged. Integrated circuit chips develop towards high integration and small feature size, and the chips of the existing packaging substrate are usually integrated on the front surface. As the number of interconnected chips increases, the mismatched stress and abnormal warping of the substrate during high-temperature packaging process will be greater, thereby reducing the reliability of packaging. SUMMARY

[0003] Therefore, the purpose of the utility model is to provide a packaging substrate interconnection structure capable of reducing warping probability to solve the problems in the background art.

[0004] A packaging substrate interconnection structure capable of reducing warping probability comprises a first substrate group and a second substrate group. The first substrate group comprises a first substrate and a plurality of first chips arranged on the outer surface of the first substrate. The second substrate group comprises a second substrate, a plurality of second chips arranged on the bottom surface of the second substrate, and a solder ball group. The bottom surface of the first substrate is connected to the top surface of the second substrate through a plurality of connection point structures. A plurality of grooves are arranged on the bottom surface of the second substrate, and an inner circuit layer is arranged on the bottom surface of the groove. The second chips are connected to the inner circuit layer through solder balls. The connection point structure comprises a first groove, a second groove, a first solder ball, a conductive part, and a conductive column. The first groove and the second groove are arranged oppositely, and one of them is arranged on the first substrate, and the other is arranged on the second substrate. The first solder ball is arranged on the bottom surface of the first groove and protrudes outward from the first groove. The conductive part is filled on the outer side of the first solder ball, and the conductive column is connected to the conductive part and filled in the second groove.

[0005] Further, an upper circuit layer is arranged on the top surface of the first substrate, and an upper conductive layer is arranged on the bottom surface. A plurality of chip pre-arrangement areas are arranged on the upper circuit layer, and the first chips are connected to the chip pre-arrangement areas through solder balls.

[0006] Further, a lower conductive layer is arranged on the top surface of the second substrate, and a lower circuit layer is arranged on the bottom surface. The upper conductive layer is connected to the lower circuit layer.

[0007] Further, the solder ball group comprises a plurality of solder balls arranged on the lower circuit layer.

[0008] Further, the bottom of the first chip and the second chip is further provided with filling glue, and the filling glue is filled between the circuit layer, the chip, and the solder ball.

[0009] Further, the connection point structures are arranged in a staggered manner, wherein the first recess of one connection point structure is arranged on the first substrate, and the first recess of the adjacent connection point structure is arranged on the second substrate.

[0010] Further, the first chip and the second chip are arranged in a staggered manner.

[0011] Further, the first substrate is provided with an encapsulation layer on the outer surface, and the encapsulation layer is provided with an external circuit layer on the outer surface.

[0012] Further, the second substrate is also provided with an encapsulation layer and a circuit layer corresponding to the outer surface of the second chip, and the circuit layer is connected to the lower circuit layer of the second substrate.

[0013] In summary, the present application forms a multi-layer board structure by arranging the connection point structures to connect the board bodies, increases the thickness of the board body, and has good uniformity in overall layout, thereby reducing the warping probability to a certain extent. In addition, the symmetric structure is arranged on the overall board layer, so that the upper and lower stress effects tend to be balanced, thereby reducing the warping probability caused by the stress effect. The present application has strong practicability and strong popularization significance. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 FIG. 1 is a structural schematic diagram of a first embodiment of the packaging substrate interconnection structure capable of reducing warping probability according to the present application;

[0015] Figure 2 FIG. 2 is a structural schematic diagram of a second embodiment of the packaging substrate interconnection structure capable of reducing warping probability according to the present application. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0017] As shown in FIG. 1, the packaging substrate interconnection structure capable of reducing warping probability according to the present application comprises a first substrate 1, a second substrate 2, a first chip 3 and a second chip 4. Figure 1As shown, this is a first embodiment of a packaging substrate interconnect structure that can reduce the probability of warpage provided by this utility model. The packaging substrate interconnect structure that can reduce the probability of warpage includes a first substrate group 10 and a second substrate group 20. The first substrate group 10 includes a first substrate 11 and a plurality of first chips 12 disposed on the outer surface of the first substrate 11. The second substrate group 20 includes a second substrate 21 and a plurality of second chips 22 and solder ball groups 23 disposed on the bottom surface of the second substrate 21; the bottom surface of the first substrate 11 is connected to the top surface of the second substrate 21.

[0018] The first substrate 11 has an upper circuit layer 111 on its top surface and an upper conductive layer 112 on its bottom surface. The upper circuit layer 111 has several chip pre-mount areas, and the first chip 12 is connected to these chip pre-mount areas via solder balls. The second substrate 21 has a lower conductive layer 211 on its top surface and a lower circuit layer 212 on its bottom surface. The bottom surface of the second substrate 21 has several grooves 213, and the bottom surface of each groove 213 has an inner circuit layer 214. The second chip 22 is connected to the inner circuit layer 214 via solder balls. Furthermore, the solder ball group 23 includes several solder balls disposed on the lower circuit layer 212, and the upper conductive layer 112 is connected to the lower circuit layer 212. Additionally, a filler adhesive 14 is provided at the bottom of the first chip 12 and the second chip 22. The filler adhesive 14 fills the space between the circuit layer / conductive layer and the chip / solder ball, providing stress buffering and protection.

[0019] The upper conductive layer 112 and the lower conductive layer 211 are provided with a plurality of connection point structures 30. Each connection point structure 30 includes a first groove 31, a second groove 32, a first solder ball 33, a conductive portion 34, and a conductive post 35. The first groove 31 and the second groove 32 are arranged opposite to each other, with one of them disposed on the first substrate 11 and the other disposed on the second substrate 21. The first solder ball 33 is disposed on the bottom surface of the first groove 31 and protrudes outside the first groove 31. The conductive portion 34 fills the outside of the first solder ball 33. The conductive post 35 is connected to the conductive portion 34 and fills the second groove 32. The conductive portion 34 can be conductive adhesive or conductive paste.

[0020] In this embodiment, the connection point structures 30 are staggered, meaning that the first groove 31 of one connection point structure 30 is located on the first substrate 11, while the first groove 31 of its adjacent connection point structure 30 is located on the second substrate 21. This staggered arrangement not only makes the connection between the two more compact but also improves the overall uniformity. Furthermore, the first chip 12 and the second chip 22 are approximately staggered, resulting in better overall uniformity and mitigating the problem of warping in some areas caused by uneven distribution.

[0021] like Figure 2 As shown in the figure, it is the second embodiment of the utility model, the structure of this embodiment is basically same with the first embodiment, the difference is that the outer surface of the first substrate 11 is provided with the packaging layer 15, the outer surface of the packaging layer 15 is provided with the outer circuit layer 16.The second substrate 21 is also provided with the packaging layer 15 and the circuit layer on the outer surface corresponding to the second chip 22, and the circuit layer is connected to the lower circuit layer 212 of the second substrate.In this embodiment, the overall hierarchical symmetry of the plate body can improve the stress effect to a certain extent and reduce the warping probability.

[0022] In summary, the utility model discloses a connection point structure 30 is set up to connect the plate body and form multilayer plate body structure, increase the thickness of plate body, and the overall layout uniformity is good, and the warping probability is reduced to a certain extent;And the plate body can integrate more chips or other electronic components.In addition, the symmetrical structure is arranged on the overall plate layer, so that the stress effect of upper and lower sides tends to balance, and the warping probability caused by stress effect is reduced.The utility model has strong practicability and strong popularization significance.

[0023] The above-mentioned embodiment only expresses part of the embodiment of the utility model, and the description is more specific and detailed, but it can not be understood as the limitation of the patent range of the utility model.Therefore, it should be pointed out that for ordinary skilled person in the art, without departing from the concept of the utility model, a number of modifications and improvements can be made, which belong to the protection range of the utility model.Therefore, the protection range of the utility model patent should be according to the attached claims.

Claims

1. A packaging substrate interconnect structure that reduces the probability of warpage, characterized in that: The system includes a first substrate group and a second substrate group. The first substrate group includes a first substrate and a plurality of first chips disposed on the outer surface of the first substrate. The second substrate group includes a second substrate and a plurality of second chips and a solder ball group disposed on the bottom surface of the second substrate. The bottom surface of the first substrate and the top surface of the second substrate are connected by a plurality of connection point structures. A plurality of grooves are provided on the bottom surface of the second substrate, and an inner circuit layer is provided on the bottom surface of the grooves. The second chips are connected to the inner circuit layer by solder balls. The connection point structure includes a first groove, a second groove, a first solder ball, a conductive part, and a conductive post. The first groove and the second groove are arranged opposite to each other, and one of them is disposed on the first substrate and the other is disposed on the second substrate. The first solder ball is disposed on the bottom surface of the first groove and protrudes out of the first groove. The conductive part fills the outside of the first solder ball, and the conductive post is connected to the conductive part and filled in the second groove.

2. The packaging substrate interconnect structure with reduced warpage probability as described in claim 1, characterized in that: An upper circuit layer is provided on the top surface of the first substrate, and an upper conductive layer is provided on the bottom surface; a plurality of chip pre-assembly areas are provided on the upper circuit layer, and the first chip is connected to the chip pre-assembly areas by solder balls.

3. The packaging substrate interconnect structure with reduced warpage probability as described in claim 2, characterized in that: The second substrate has a lower conductive layer on its top surface and a lower circuit layer on its bottom surface, and the upper conductive layer is connected to the lower circuit layer.

4. The packaging substrate interconnect structure with reduced warpage probability as described in claim 3, characterized in that: The solder ball group comprises several solder balls, which are disposed on the lower circuit layer.

5. The packaging substrate interconnect structure with reduced warpage probability as described in claim 1, characterized in that: The bottom of the first chip and the second chip is also provided with filler glue, which fills the space between the circuit layer and the chip and solder balls.

6. The packaging substrate interconnect structure with reduced warpage probability as described in claim 1, characterized in that: The connection point structure is staggered, wherein the first groove of one connection point structure is disposed on the first substrate, and the first groove of the adjacent connection point structure is disposed on the second substrate.

7. The packaging substrate interconnect structure with reduced warpage probability as described in claim 1, characterized in that: The first chip and the second chip are staggered.

8. The packaging substrate interconnect structure with reduced warpage probability as described in claim 1, characterized in that: An encapsulation layer is disposed on the outer surface of the first substrate, and an external circuit layer is disposed on the outer surface of the encapsulation layer.

9. The packaging substrate interconnect structure with reduced warpage probability as described in claim 8, characterized in that: The second substrate also has an encapsulation layer and a circuit layer on its outer surface corresponding to the second chip, and the circuit layer is connected to the lower circuit layer of the second substrate.

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