Display panel manufacturing method and display panel

Abstract

The present invention relates to a method for manufacturing a display panel and the display panel. Compared with the existing method in which an undercut structure is formed through two processes of photolithography and wet etching, the manufacturing method of the present invention can form an undercut structure on a passivation layer through a single etching process, thereby saving production capacity. In addition, a double-layer support for an organic light-emitting layer and a cathode is formed by the cooperation of a planarization layer and an anode layer, thereby enhancing the support strength of the cathode and the organic light-emitting layer and avoiding the risk of collapse.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a method for manufacturing a display panel and the display panel. Background Art

[0002] Due to light transmission requirements, the transparent cathode of self-luminous organic light-emitting diode (OLED) displays is manufactured to a relatively thin thickness. This results in a large square resistance and a severe panel current voltage drop (IR drop). This leads to significant brightness unevenness on the display panel, seriously affecting the display performance of the OLED display device. Currently, large-scale OLED panel designs generally use a backplane-assisted cathode introduction method, which mainly reduces IR drop by forming an undercut structure to connect the cathode. However, in the existing OLED display panel manufacturing process, the support layer serving as the cathode will retreat during the undercut formation process, resulting in a decrease in the support layer's support effectiveness and the risk of collapse. Summary of the Invention

[0003] The present invention aims to solve the problem of cathode collapse risk in the existing undercut process.

[0004] To achieve the above object, the present invention provides a method for manufacturing a display panel, comprising:

[0005] providing a substrate;

[0006] forming a thin film transistor layer, an auxiliary electrode layer, a passivation layer and a planarization layer in sequence on the base substrate;

[0007] forming a first contact hole on the surface of the planarization layer, penetrating the planarization layer and the passivation layer to expose at least a portion of the source electrode of the thin film transistor layer;

[0008] forming a second contact hole on the surface of the planarization layer, penetrating the planarization layer and the passivation layer to expose a portion of the auxiliary electrode layer;

[0009] forming an anode layer on the surface of the planarization layer, wherein the anode layer is electrically connected to the source electrode through a first contact hole, and the anode layer is deposited onto the surface of the auxiliary electrode layer through a second contact hole;

[0010] forming a photoresist layer on the surface of the anode layer, and forming a first opening corresponding to the second contact hole on the surface of the photoresist layer;

[0011] Etching and removing the anode layer deposited on the surface of the auxiliary electrode layer to form a second opening corresponding to the first opening on the surface of the anode layer;

[0012] etching at least a portion of the passivation layer covering the auxiliary electrode layer to form an undercut cavity exposing at least a portion of the auxiliary electrode layer;

[0013] removing the photoresist layer;

[0014] etching the anode layer to form an anode;

[0015] The remaining anode layer is removed.

[0016] Optionally, the step of removing the remaining anode layer includes retaining the anode layer deposited on the inner wall of the second contact hole.

[0017] Optionally, the second contact hole includes a groove formed on the surface of the planarization layer and a first through hole formed on the bottom of the groove and connected to the bottom cut cavity, the inner diameter of the groove gradually decreases from one end away from the auxiliary electrode layer to one end close to the auxiliary electrode layer, the anode layer is deposited on the inner wall of the groove, and the inner diameter of the second opening on the anode layer is greater than or equal to the inner diameter of the first through hole.

[0018] Optionally, an orthographic projection area of ​​the first through hole on the surface of the auxiliary electrode layer is smaller than an orthographic projection area of ​​the undercut cavity on the surface of the auxiliary electrode layer.

[0019] Optionally, the step of sequentially forming a thin film transistor layer, an auxiliary electrode layer, a passivation layer and a planarization layer on the base substrate also includes: forming a second supporting layer on the surface of the passivation layer; the planarization layer covers the second supporting layer, and the second supporting layer is located above the auxiliary electrode layer; the second contact hole passes through the planarization layer, the second supporting layer and the passivation layer.

[0020] Optionally, the second contact hole includes a second through hole formed in the planarization layer and a third through hole formed in the second support layer and connected to the second through hole, the inner diameter of the second through hole gradually decreases from the end away from the auxiliary electrode layer to the end close to the auxiliary electrode layer, and the inner diameter of the third through hole is smaller than the inner diameter of the second through hole close to the end of the auxiliary electrode layer.

[0021] Optionally, an orthographic projection area of ​​the third through hole on the surface of the auxiliary electrode layer is smaller than an orthographic projection area of ​​the undercut cavity on the surface of the auxiliary electrode layer.

[0022] Optionally, the second supporting layer located outside the third through hole covers a portion of the undercut cavity.

[0023] Optionally, after the step of removing the remaining anode layer, the method further comprises:

[0024] forming a pixel definition layer on the surface of the planarization layer;

[0025] forming a first via hole on the surface of the pixel definition layer exposing at least a portion of the anode;

[0026] forming a second via hole exposing the second contact hole on the surface of the pixel definition layer;

[0027] forming an organic light-emitting layer by evaporation on the surface of the pixel definition layer, wherein the organic light-emitting layer is deposited on the surface of the anode through the first via hole, and the organic light-emitting layer is deposited on the surface of the auxiliary electrode layer through the second via hole and the second contact hole;

[0028] A cathode is formed by evaporation on the surface of the organic light-emitting layer, and the cathode is overlapped with the auxiliary electrode layer through the second via hole and the second contact hole.

[0029] To achieve the above object, the present invention further provides a display panel, which is manufactured by the manufacturing method as described above.

[0030] The beneficial effect of the present invention is that the present invention provides a method for manufacturing a display panel and a display panel. Compared with the existing method of forming an under-cut structure through two processes of photolithography and wet etching, the manufacturing method of the present invention can form an under-cut structure on a passivation layer through a single etching process, saving production capacity, and forming a double-layer support for the organic light-emitting layer and the cathode through the cooperation of the planarization layer and the anode layer, thereby enhancing the support strength of the cathode and the organic light-emitting layer and avoiding the risk of collapse. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic structural diagram of a display panel according to an exemplary embodiment of the present invention;

[0032] Figure 2 is a flow chart of a method for manufacturing a display panel according to an exemplary embodiment of the present invention;

[0033] Figure 3a to Figure 3j is a schematic flow chart of a method for manufacturing a display panel according to an exemplary embodiment of the present invention;

[0034] Figure 4 is a schematic structural diagram of a display panel according to another exemplary embodiment of the present invention;

[0035] Figure 5a to Figure 5i is a schematic flow chart of a method for manufacturing a display panel according to another exemplary embodiment of the present invention;

[0036] The parts numbers in the figure are as follows:

[0037] 100, 100', display panel, 100a, undercut region, 100b, driving region, 100c, capacitor region, 100d, bonding region, 110, substrate, 111, buffer layer, 112, interlayer insulating layer, 113, auxiliary electrode layer, 120, thin film transistor layer, 121, light shielding layer, 122, first electrode plate, 123, semiconductor layer, 124, gate insulating layer, 125, gate, 126, second electrode plate, 127, drain, 128, source, 129, source and drain, 130, passivation layer, 131, undercut cavity, 132, bonding opening, 133. Binding metal layer, 140. Planarization layer, 141. First contact hole, 141a, 141a', second contact hole, 142. Groove, 143. First through hole, 1431. Protrusion, 1432. First supporting layer, 150. Pixel definition layer, 151. First via hole, 152. Second via hole, 160. Light-emitting functional layer, 161. Anode, 161a. Anode layer, 161b. Photoresist layer, 161c. First opening, 161d. Second opening, 162. Organic photoresist layer, 163. Cathode, 170. Second supporting layer, 171. Second through hole. DETAILED DESCRIPTION

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0039] Compared to existing methods that use two processes, photolithography and wet etching, to form an undercut structure, the fabrication method described herein utilizes a single etching process to form an undercut structure on the passivation layer, saving production capacity. Furthermore, the planarization layer and the anode layer form a dual-layer support for the organic light-emitting layer and cathode, enhancing the support strength of the cathode and organic light-emitting layer and reducing the risk of collapse. As a typical application, the display panel can be applied to large-scale OLED panels, including mobile phones, tablets, televisions, monitors, laptops, and the like.

[0040] In one embodiment of the present invention, referring to Figure 1The display panel 100 provided by the present invention includes a base substrate 110, a thin film transistor layer 120 formed on the base substrate 110, a passivation layer 130 formed on the thin film transistor layer 120, a planarization layer 140 formed on the passivation layer 130, a pixel definition layer 150 formed on the planarization layer 140, and a light-emitting functional layer 160 formed on the pixel definition layer 150, wherein the light-emitting functional layer 160 includes a stacked anode 161, an organic light-emitting layer 162, and a cathode 163.

[0041] The display panel 100 includes an undercut region 100 a , a driving region 100 b , a capacitor region 100 c , and a bonding region 100 d , which are arranged at intervals.

[0042] The thin film transistor layer 120 includes a light-shielding layer 121 and a first electrode plate 122 arranged on the same layer on the base substrate 110, the light-shielding layer 121 corresponds to the driving area 100b, and the first electrode plate 122 corresponds to the capacitor area 100c. A buffer layer 111 is provided on the base substrate 110, and the buffer layer 111 covers the light-shielding layer 121 and the first electrode plate 122. The light-shielding layer 121 is a metal layer, and the light-shielding layer 121 and the first electrode plate 122 form a first metal layer M1 on the same layer; a semiconductor layer 123 is provided on the surface of the buffer layer 111 located above the light-shielding layer 121, and a gate insulating layer 124 and a gate 125 are stacked on the surface of the semiconductor layer 123; a second electrode plate 126 is provided on the surface of the buffer layer 111 located above the first electrode plate 122, and the first electrode plate 122 and the second electrode plate 126 form a capacitor structure. An interlayer insulating layer 112 is formed on the buffer layer 111, and a drain 127, a source 128 and a source-drain 129 are provided on the surface of the interlayer insulating layer 112. The drain 127 and the source 128 correspond to the driving area 100b, and the source-drain 129 corresponds to the capacitor area 100c. The drain 127 and the source 128 are electrically connected to the semiconductor layer 123 respectively, and the source 128 is electrically connected to the light shielding layer 121.

[0043] An auxiliary electrode layer 113 is arranged on the interlayer insulating layer 112 corresponding to the bottom cut area 100a, and a bonding electrode layer 114 is arranged on the interlayer insulating layer 112 corresponding to the bonding area 100d. The auxiliary electrode layer 113, the drain 127, the source 128, the source and drain 129 and the bonding electrode layer 114 are arranged on the same layer to form a second metal layer M2.

[0044] Passivation layer 130 covers auxiliary electrode layer 113, drain electrode 127, source electrode 128, source-drain electrode 129, and bonding electrode layer 114. An undercut cavity 131 is formed on the surface of passivation layer 130 corresponding to auxiliary electrode layer 113. Undercut cavity 131 exposes at least a portion of auxiliary electrode layer 113. A bonding opening 132 is formed on the surface of passivation layer 130 corresponding to bonding region 100d, exposing at least a portion of bonding electrode layer 114. A bonding metal layer 133 is provided on the surface of passivation layer 130 corresponding to bonding opening 132. Bonding metal layer 133 is electrically connected to bonding electrode layer 114 through bonding opening 132. Bonding metal layer 133 forms third metal layer M3.

[0045] The planarization layer 140 is disposed on the surface of the passivation layer 130 corresponding to the undercut region 100a, the driving region 100b, and the capacitor region 100c. The planarization layer 140 does not cover the surface of the passivation layer 130 corresponding to the bonding region 100d. A first contact hole 141 is provided on the surface of the planarization layer 140 to expose at least a portion of the source electrode 128. A groove 142 is provided on the surface of the planarization layer 140 corresponding to the auxiliary electrode layer 113. A first contact hole 141 is provided on the bottom surface of the groove 142 to penetrate the planarization layer 140 and communicate with the undercut cavity 131. The inner diameter of the groove 142 gradually decreases from the end away from the auxiliary electrode layer 113 to the end close to the auxiliary electrode layer 113, forming an inverted trapezoidal cross-sectional structure of the groove 142. The passivation layer 130 located outside the first through hole 143 forms an annular protrusion 1431. The protrusion 1431 partially blocks the undercut cavity 131, so that the orthographic projection area of ​​the first through hole 143 on the surface of the auxiliary electrode layer 113 is smaller than the orthographic projection area of ​​the undercut cavity 131 on the surface of the auxiliary electrode layer 113. In this embodiment, a first supporting layer 1432 is respectively provided on the upper surface of at least two protrusions 1431, that is, the first supporting layer 1432 covers at least the inner bottom surface of the groove 142. In another embodiment, in addition to covering the protrusion 1431, the first supporting layer 1432 also covers the inner surface of the sidewall of the groove 142 adjacent to the protrusion 1431.

[0046] An anode 161 is disposed on the surface of the planarization layer 140 corresponding to the first contact hole 141 and electrically connected to the source electrode 128 through the first contact hole 141. The first supporting layer 1432 and the anode 161 are made of the same material: a deposited structure of IZO (indium zinc oxide) and an APC alloy (silver-palladium-copper alloy), i.e., IZO / APC / IZO. A pixel definition layer 150 is disposed on the surface of the planarization layer 140. A first via 151 is defined on the surface of the pixel definition layer 150, exposing at least a portion of the anode 161. A second via 152 is defined on the surface of the pixel definition layer 150, communicating with the recess 142. An organic light-emitting layer 162 is disposed on the surface of the pixel definition layer 150 and electrically connected to the anode 161 through the first via 151. The organic light-emitting layer 162 extends through the second via 152, the recess 142, and the first through-hole 143 to the interior of the undercut cavity 131 and covers a portion of the surface of the auxiliary electrode layer 113. The cathode 163 is disposed on the surface of the organic light-emitting layer 162. The cathode 163 extends through the second via 152, the groove 142, and the first through-hole 143 into the undercut cavity 131 and is electrically connected to the auxiliary electrode layer 113 not covered by the organic light-emitting layer 162. Under the conduction of current and voltage, the holes in the anode 161 and the electrons in the cathode 163 meet and combine in the organic light-emitting layer 162, thereby exciting the light-emitting material in the organic light-emitting layer 162 to emit light.

[0047] In this embodiment, the groove 142 on the planarization layer 140 cooperates with the first supporting layer 1432 to form a double-layer support structure for the organic light-emitting layer 162 and the cathode 163, thereby ensuring the support strength and support stability of the organic light-emitting layer 162 and the cathode 163 and avoiding the risk of collapse. Moreover, the protrusion 1431 located on the outside of the first through hole 143 forms a partial shielding of the bottom cut cavity 131, so that when the organic light-emitting layer 162 is formed by vapor deposition, the organic light-emitting layer 162 can only cover a portion of the auxiliary electrode layer 113. When the cathode 163 is formed by vapor deposition, the cathode 163 can be electrically connected to the auxiliary electrode layer 113 not covered by the organic light-emitting layer 162.

[0048] Reference Figure 2 as well as Figure 3a to Figure 3j The manufacturing method of the display panel 100 according to this embodiment includes the following steps:

[0049] S1, providing a base substrate 110;

[0050] S2, reference Figure 3a , sequentially forming a thin film transistor layer 120 , an auxiliary electrode layer 113 , a passivation layer 130 and a planarization layer 140 on the base substrate 110 ;

[0051] S3. Reference Figure 3a, forming a first contact hole 141 on the surface of the planarization layer 140 , penetrating the planarization layer 140 and the passivation layer 130 to expose at least a portion of the source electrode 128 of the thin film transistor layer 120 ;

[0052] S4, reference Figure 3a , forming a second contact hole 141 a on the surface of the planarization layer 140 , penetrating the planarization layer 140 and the passivation layer 130 to expose a portion of the auxiliary electrode layer 113 ;

[0053] S5. Reference Figure 3b , forming an anode layer 161a on the surface of the planarization layer 140, the anode layer 161a is electrically connected to the source electrode 128 through the first contact hole 141, and the anode layer 161a is deposited on the surface of the auxiliary electrode layer 113 through the second contact hole 141a;

[0054] S6, reference Figure 3b , forming a photoresist layer 161b on the surface of the anode layer 161a, and forming a first opening 161c corresponding to the second contact hole 141a on the surface of the photoresist layer 161b;

[0055] S7, reference Figure 3c , etching and removing the anode layer 161a deposited on the surface of the auxiliary electrode layer 113 to form a second opening 161d corresponding to the first opening 161c on the surface of the anode layer 161a;

[0056] S8. Reference Figure 3d , etching at least a portion of the passivation layer 130 covering the auxiliary electrode layer 113 to form an undercut cavity 131 exposing at least a portion of the auxiliary electrode layer 113 ;

[0057] S9, reference Figure 3e and Figure 3f , removing the photoresist layer 161b;

[0058] S10, reference Figure 3g , etching the anode layer 161a to form the anode 161;

[0059] S11 , removing the remaining anode layer 161 a .

[0060] Preferably, in step S11, referring to Figure 3g The anode layer 161a deposited on the inner wall of the second contact hole 141a is retained. The second contact hole 141a includes a groove 142 and a first through hole 143 opened at the bottom surface of the groove 142. The anode layer 161a deposited on the inner wall of the second contact hole 141a is the first supporting layer 1432 described above.

[0061] In step S6, the photoresist layer 161b covers the anode layer 161a and the bonding metal layer 133, and a photolithography (PH) process is used to form the first opening 161c on the surface of the photoresist layer 161b. The mask used in the photolithography process is such that the mask area corresponding to the first through hole 143 is a fully transparent area, the mask area corresponding to the anode 161 is a fully black area, and the mask area corresponding to the other areas of the photoresist layer 161b is a semi-transparent area. In step S7, the anode layer 161a deposited on the surface of the auxiliary electrode layer 113 is removed by wet etching to form the second opening 161d. In step S8, a portion of the passivation layer 130 is removed by wet etching, and the etching solution is hydrofluoric acid to form the undercut cavity 131. In step S9, dry ash (DRY-ASH) is used to remove the photoresist layer 161b, but the photoresist layer 161b corresponding to the undercut area 100a and the photoresist layer 161b corresponding to the anode 161 are retained. In step S10 , wet etching is used to form the anode 161 and remove the remaining photoresist layer 161 b in step S9 .

[0062] The method for manufacturing the display panel 100 further includes:

[0063] S12. Reference Figure 3h , forming a pixel definition layer 150 on the surface of the planarization layer 140;

[0064] S13. Reference Figure 3h , forming a first via hole 151 on the surface of the pixel definition layer 150 to expose at least a portion of the anode 161;

[0065] S14. Reference Figure 3h , forming a second via hole 152 exposing the second contact hole 141 a on the surface of the pixel definition layer 150;

[0066] S15. Reference Figure 3i , forming an organic light-emitting layer 162 by evaporation on the surface of the pixel definition layer 150, the organic light-emitting layer 162 is deposited on the surface of the anode 161 through the first via hole 151, and the organic light-emitting layer 162 is deposited on the surface of the auxiliary electrode layer 113 through the second via hole 152 and the second contact hole 141a;

[0067] S16, reference Figure 3j A cathode 163 is formed by evaporation on the surface of the organic light-emitting layer 162 , and the cathode 163 is overlapped with the auxiliary electrode layer 113 through the second via hole 152 and the second contact hole 141 a .

[0068] The evaporation angle for forming the organic light-emitting layer 162 is different from the evaporation angle for forming the cathode 163. For example, the evaporation angle for the organic light-emitting layer 162 is 0 to 45 degrees, while the evaporation angle for the cathode 163 is -45 to 0 degrees. Due to the different evaporation angles, combined with the shielding of the auxiliary electrode layer 113 by the protrusions 1431 and the first supporting layer 1432, the organic light-emitting layer 162 only partially covers the auxiliary electrode layer 113. This allows the cathode 163 to cover both the organic light-emitting layer 162 and the auxiliary electrode layer 113, thus achieving electrical connection between the cathode 163 and the auxiliary electrode layer 113 and reducing voltage drop.

[0069] The manufacturing method of the display panel provided in this embodiment can form an undercut cavity 131 exposing at least a portion of the auxiliary electrode layer 113 on the passivation layer 130 through a single etching process. Compared with the existing process of forming the undercut cavity through two processes of photolithography and etching, this method saves photolithography production capacity and avoids waste.

[0070] In another embodiment, referring to Figure 4 The display panel 100' includes a base substrate 110, a thin film transistor layer 120 formed on the base substrate 110, a passivation layer 130 formed on the thin film transistor layer 120, a planarization layer 140 formed on the passivation layer 130, a pixel definition layer 150 formed on the planarization layer 140, and a light-emitting functional layer 160 formed on the pixel definition layer 150, wherein the light-emitting functional layer 160 includes a stacked anode 161, an organic light-emitting layer 162, and a cathode 163.

[0071] The display panel 100' includes an undercut area 100a, a driving area 100b, a capacitor area 100c and a bonding area 100d arranged at intervals. A second supporting layer 170 is provided on the surface of the passivation layer 130 corresponding to the undercut area 100a. The second supporting layer 170 is a metal layer. The second supporting layer 170 and the bonding metal layer 133 are arranged on the same layer to form a third metal layer M3.

[0072] The second supporting layer 170 has a second through hole 171 formed on its surface, corresponding to the first through hole 143. The inner diameter of the first through hole 143 is the same as that of the second through hole 171. Protrusions 1431 are provided on the second supporting layer 170 on either side of the second through hole 171. The grooves 142 on the planarization layer 140 cooperate with the second supporting layer 170 to form a double-layer support structure for the organic light-emitting layer 162 and the cathode 163. This ensures the support strength and stability of the organic light-emitting layer 162 and the cathode 163, and prevents the risk of collapse. Furthermore, the second supporting layer 170 located outside the second through hole 171 partially blocks the undercut cavity 131, ensuring that when the organic light-emitting layer 162 is formed by vapor deposition, the organic light-emitting layer 162 only covers a portion of the auxiliary electrode layer 113. When the cathode 163 is formed by vapor deposition, the cathode 163 can be electrically connected to the auxiliary electrode layer 113 not covered by the organic light-emitting layer 162.

[0073] Reference Figure 5a to Figure 5i The method for manufacturing the display panel 100' provided in this embodiment includes the following steps:

[0074] S1, providing a base substrate 110;

[0075] S2', reference Figure 5a , sequentially forming a thin film transistor layer 120 , an auxiliary electrode layer 113 , a passivation layer 130 , a second supporting layer 170 and a planarization layer 140 on the base substrate 110 ;

[0076] S3', reference Figure 5a , forming a first contact hole 141 on the surface of the planarization layer 140 , penetrating the planarization layer 140 and the passivation layer 130 to expose at least a portion of the source electrode 128 of the thin film transistor layer 120 ;

[0077] S4', reference Figure 5a , forming a second contact hole 141 a ′ on the surface of the planarization layer 140 , penetrating the planarization layer 140 , the second supporting layer 170 and the passivation layer 130 to expose a portion of the auxiliary electrode layer 113 ;

[0078] S5', reference Figure 5b , forming an anode layer 161a on the surface of the planarization layer 140, the anode layer 161a is electrically connected to the source electrode 128 through the first contact hole 141, and the anode layer 161a is deposited on the surface of the auxiliary electrode layer 113 through the second contact hole 141a';

[0079] S6', reference Figure 5b , forming a photoresist layer 161b on the surface of the anode layer 161a, and forming a first opening 161c corresponding to the second contact hole 141a' on the surface of the photoresist layer 161b;

[0080] S7, reference Figure 5c , etching and removing the anode layer 161a deposited on the surface of the auxiliary electrode layer 113 to form a second opening 161d corresponding to the first opening 161c on the surface of the anode layer 161a;

[0081] S8. Reference Figure 5d , etching at least a portion of the passivation layer 130 covering the auxiliary electrode layer 113 to form an undercut cavity 131 exposing at least a portion of the auxiliary electrode layer 113 ;

[0082] S9, reference Figure 5e , removing the photoresist layer 161b;

[0083] S10, reference Figure 5f , etching the anode layer 161a to form the anode 161;

[0084] S11 , removing the remaining anode layer 161 a .

[0085] The second contact hole 141 a ′ in this embodiment includes a groove 142 , a first through hole 143 formed on the bottom surface of the groove 142 , and a second through hole 171 formed on the second supporting layer 170 .

[0086] In step S6', the photoresist layer 161b covers the anode layer 161a and the bonding metal layer 133. A photolithography (PH) process is used to form the first opening 161c on the surface of the photoresist layer 161b. The photomask used in the PH process is designed such that the area corresponding to the first through hole 143 is fully transparent, the area corresponding to the anode 161 is fully black, and the areas corresponding to the rest of the photoresist layer 161b are semi-transparent. In step S9, dry ash (DRY-ASH) is used to remove the photoresist layer 161b, but the photoresist layer 161b corresponding to the anode 161 is retained. In step S10, wet etching is used to form the anode 161 and remove the remaining photoresist layer 161b from step S9.

[0087] The manufacturing method of the display panel 100' further includes:

[0088] S12. Reference Figure 5g , forming a pixel definition layer 150 on the surface of the planarization layer 140;

[0089] S13. Reference Figure 5g , forming a first via hole 151 on the surface of the pixel definition layer 150 to expose at least a portion of the anode 161;

[0090] S14. Reference Figure 5g , forming a second via hole 152 exposing the second contact hole 141 a on the surface of the pixel definition layer 150;

[0091] S15. Reference Figure 5h , forming an organic light-emitting layer 162 by evaporation on the surface of the pixel definition layer 150, the organic light-emitting layer 162 is deposited on the surface of the anode 161 through the first via hole 151, and the organic light-emitting layer 162 is deposited on the surface of the auxiliary electrode layer 113 through the second via hole 152 and the second contact hole 141a;

[0092] S16, reference Figure 5i A cathode 163 is formed by evaporation on the surface of the organic light-emitting layer 162 , and the cathode 163 is overlapped with the auxiliary electrode layer 113 through the second via hole 152 and the second contact hole 141 a .

[0093] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make multiple improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for manufacturing a display panel, characterized in that: include: providing a substrate; forming a thin film transistor layer, an auxiliary electrode layer, a passivation layer and a planarization layer in sequence on the base substrate; forming a first contact hole on the surface of the planarization layer, penetrating the planarization layer and the passivation layer to expose at least a portion of the source electrode of the thin film transistor layer; forming a second contact hole on the surface of the planarization layer, penetrating the planarization layer and the passivation layer to expose a portion of the auxiliary electrode layer; wherein the second contact hole comprises a groove formed on the surface of the planarization layer and a first through hole formed at the bottom of the groove, and the inner diameter of the groove gradually decreases from an end away from the auxiliary electrode layer to an end close to the auxiliary electrode layer; forming an anode layer on the surface of the planarization layer, wherein the anode layer is electrically connected to the source electrode through a first contact hole, and the anode layer is deposited onto the surface of the auxiliary electrode layer through a second contact hole; forming a photoresist layer on the surface of the anode layer, and forming a first opening corresponding to the second contact hole on the surface of the photoresist layer; Etching and removing the anode layer deposited on the surface of the auxiliary electrode layer to form a second opening corresponding to the first opening on the surface of the anode layer; etching at least a portion of the passivation layer covering the auxiliary electrode layer to form an undercut cavity exposing at least a portion of the auxiliary electrode layer; wherein the undercut cavity is connected to the first through hole, and the planarization layer located outside the first through hole forms an annular protrusion, and the protrusion partially shields the undercut cavity; removing the photoresist layer; etching the anode layer to form an anode; The remaining anode layer is removed, and the anode layer deposited on the inner wall of the groove is retained as a first supporting layer.

2. The method for manufacturing a display panel according to claim 1, wherein The anode layer is deposited on the inner wall of the groove, and the inner diameter of the second opening on the anode layer is greater than or equal to the inner diameter of the first through hole.

3. The method for manufacturing a display panel according to claim 2, wherein: An orthographic projection area of ​​the first through hole on the surface of the auxiliary electrode layer is smaller than an orthographic projection area of ​​the undercut cavity on the surface of the auxiliary electrode layer.

4. The method for manufacturing a display panel according to claim 1, wherein: The step of sequentially forming a thin film transistor layer, an auxiliary electrode layer, a passivation layer and a planarization layer on the base substrate further comprises: forming a second supporting layer on the surface of the passivation layer; The planarization layer covers the second supporting layer, and the second supporting layer is located above the auxiliary electrode layer; The second contact hole passes through the planarization layer, the second supporting layer, and the passivation layer.

5. The method for manufacturing a display panel according to claim 4, wherein: The second contact hole includes a second through hole formed in the planarization layer and a third through hole formed in the second supporting layer and connected to the second through hole. The inner diameter of the second through hole gradually decreases from the end away from the auxiliary electrode layer to the end close to the auxiliary electrode layer, and the inner diameter of the third through hole is smaller than the inner diameter of the second through hole close to the end of the auxiliary electrode layer.

6. The method for manufacturing a display panel according to claim 5, wherein: An orthographic projection area of ​​the third through hole on the surface of the auxiliary electrode layer is smaller than an orthographic projection area of ​​the undercut cavity on the surface of the auxiliary electrode layer.

7. The method for manufacturing a display panel according to claim 6, wherein: The second supporting layer located outside the third through hole covers a portion of the undercut cavity.

8. The method for manufacturing a display panel according to claim 1 or 5, wherein: After the step of removing the remaining anode layer, the method further comprises: forming a pixel definition layer on the surface of the planarization layer; forming a first via hole on the surface of the pixel definition layer exposing at least a portion of the anode; forming a second via hole exposing the second contact hole on the surface of the pixel definition layer; forming an organic light-emitting layer by evaporation on the surface of the pixel definition layer, wherein the organic light-emitting layer is deposited on the surface of the anode through the first via hole, and the organic light-emitting layer is deposited on the surface of the auxiliary electrode layer through the second via hole and the second contact hole; A cathode is formed by evaporation on the surface of the organic light-emitting layer, and the cathode is overlapped with the auxiliary electrode layer through the second via hole and the second contact hole.

9. A display panel, characterized in that: include: substrate; A thin film transistor layer is provided on the surface of the base substrate; An auxiliary electrode layer is provided on one side of the surface of the thin film transistor; a passivation layer disposed on a surface of the thin film transistor layer, wherein an undercut cavity is formed on a surface of the passivation layer corresponding to the auxiliary electrode layer, and the undercut cavity exposes at least a portion of the auxiliary electrode layer; a planarization layer disposed on the surface of the passivation layer, wherein a groove is defined on the surface of the planarization layer corresponding to the auxiliary electrode layer, wherein the inner diameter of the groove gradually decreases from an end away from the auxiliary electrode layer to an end close to the auxiliary electrode layer; a first through hole communicating with the undercut cavity is defined on the bottom surface of the groove, and an annular protrusion is formed on the planarization layer outside the first through hole, wherein the protrusion partially shields the undercut cavity; a first supporting layer, disposed on the inner wall of the groove, wherein the first supporting layer at least covers the inner bottom surface of the groove located outside the first through hole; an anode, disposed on the surface of the planarization layer, the anode being electrically connected to the source electrode of the thin film transistor layer; a pixel definition layer disposed on the surface of the planarization layer, wherein the surface of the pixel definition layer is provided with a first via hole exposing at least a portion of the anode, and the surface of the pixel definition layer is provided with a second via hole communicating with the groove; an organic light-emitting layer disposed on a surface of the pixel definition layer, the organic light-emitting layer being electrically connected to the anode through a first via hole, the organic light-emitting layer extending through the second via hole, the groove, and the first through hole to the inside of the undercut cavity and covering a portion of the surface of the auxiliary electrode layer; A cathode is provided on the surface of the organic light-emitting layer, and the cathode extends into the undercut cavity through the second via hole, the groove and the first through hole and is electrically connected to the auxiliary electrode layer.

10. A display panel, characterized in that: include: substrate; A thin film transistor layer is provided on the surface of the base substrate; An auxiliary electrode layer is provided on one side of the surface of the thin film transistor; a passivation layer disposed on a surface of the thin film transistor layer, wherein an undercut cavity is formed on a surface of the passivation layer corresponding to the auxiliary electrode layer, and the undercut cavity exposes at least a portion of the auxiliary electrode layer; a second supporting layer, disposed on a surface of the passivation layer corresponding to the undercut cavity, wherein a second through hole exposing a portion of the undercut cavity is opened on the surface of the second supporting layer; a planarization layer disposed on the surface of the passivation layer, wherein a groove is formed on the surface of the planarization layer corresponding to the auxiliary electrode layer, a first through hole communicating with the second through hole is formed on the bottom surface of the groove, and an annular protrusion is formed on the planarization layer outside the first through hole, wherein the protrusion and the second supporting layer partially shield the undercut cavity; an anode, disposed on the surface of the planarization layer, the anode being electrically connected to the source electrode of the thin film transistor layer; a pixel definition layer disposed on the surface of the planarization layer, wherein the surface of the pixel definition layer is provided with a first via hole exposing at least a portion of the anode, and the surface of the pixel definition layer is provided with a second via hole communicating with the groove; an organic light-emitting layer disposed on a surface of the pixel definition layer, the organic light-emitting layer being electrically connected to the anode through a first via hole, the organic light-emitting layer extending through the second via hole, the groove, the first through hole, and the second through hole to the inside of the undercut cavity and covering a portion of the surface of the auxiliary electrode layer; A cathode is provided on the surface of the organic light-emitting layer, and extends into the undercut cavity through the second via hole, the groove, the first through hole, and the second through hole, and is electrically connected to the auxiliary electrode layer.

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