Operational amplifier

Abstract

The present disclosure relates to operational amplifiers. In an embodiment, a differential pair for an input stage includes: two identical branches connected in parallel, each branch including a first MOS transistor and a second MOS transistor arranged in series, wherein the first transistor and the second transistor have channels of the same type, and wherein each of the first transistor and the second transistor has a gate coupled to the same corresponding input of the differential pair; and a circuit configured to apply a potential difference between the source and the channel formation region of the first transistor to each first transistor.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of French Patent Application No. 2009059, filed on September 7, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to operational amplifiers and, more particularly, to the input stage of operational amplifiers. Background Art

[0004] Operational amplifiers are currently used in electronic devices or circuits. An operational amplifier typically includes an input stage, one or more gain stages, an output stage, and possibly one or more intermediate stages.

[0005] Particularly considered here are operational amplifiers having an input stage that includes at least one differential pair in CMOS ("complementary metal oxide semiconductor") technology, e.g., a rail-to-rail operational amplifier whose input stage includes a differential pair of P-channel MOS transistors or PMOS transistors in parallel with a differential pair of N-channel MOS transistors or NMOS transistors.

[0006] Such known differential pairs of operational amplifiers have an undesirable input offset. Summary of the Invention

[0007] There is a need to overcome all or part of the drawbacks of known operational amplifiers and, in particular, of known differential pairs for the input stage of operational amplifiers. Specifically, it is desirable to make a differential pair suitable for use in the input stage of an operational amplifier whose input offset does not vary with the common-mode value between the inputs of the differential pair.

[0008] Thus, embodiments overcome all or part of the drawbacks of known operational amplifiers.

[0009] For example, embodiments overcome all or part of the drawbacks of the input stage of known operational amplifiers.

[0010] For example, embodiments overcome all or part of the drawbacks of known differential pairs suitable for use in the input stage of operational amplifiers.

[0011] For example, embodiments provide a differential pair that can be used in the input stage of an operational amplifier and that has an input offset that is independent of the common-mode value applied between the inputs of the differential pair.

[0012] One embodiment provides a differential pair for the input stage of an operational amplifier, comprising:

[0013] Two identical parallel branches, each branch including a first MOS transistor and a second MOS transistor having the same type of channel, these branches being cascode-assembled, and each branch having a gate coupled to the same corresponding input of a differential pair; and

[0014] A circuit configured to apply a potential difference between the source and the channel formation region of each first transistor.

[0015] According to an embodiment, the size ratio of each first transistor is X times the size ratio of each second transistor.

[0016] According to an embodiment, X is in the range of 4 to 10, preferably in the range of 5 to 6.

[0017] According to an embodiment, the potential difference is configured to increase the conduction threshold of the first transistor in absolute value.

[0018] According to an embodiment, the potential difference is configured to bring the first transistor into a saturation state.

[0019] According to an embodiment, the potential difference is configured to make the absolute value of the drain-source voltage of each first transistor greater than the absolute value of the gate-source voltage of the first transistor minus the absolute value of the conduction threshold of the first transistor.

[0020] According to an embodiment:

[0021] In each branch, the first transistor has a source coupled to the first end of the branch.

[0022] In each branch, the second transistor has a drain coupled to the second end of the branch through the active load of the branch.

[0023] The first end of the branch is coupled to a first node to which a DC potential is applied by a current source; and

[0024] The second end of the branch is coupled to a second node to which a second DC voltage is applied.

[0025] According to an embodiment, the active load of each branch includes a resistor in series with a third MOS transistor having a channel of a type opposite to the type of the channels of the first and second transistors, the resistor being coupled to the second end of the branch, the drain of the third transistor being coupled to the drain of the second transistor of the branch, and the third transistor being a mirror image of a fourth MOS transistor.

[0026] According to an embodiment, the current source includes a MOS transistor having a channel of the same type as the channels of the first and second transistors, the transistor having a gate configured to receive a bias potential.

[0027] According to an embodiment, the circuit includes:

[0028] A MOS transistor having a channel of the same type as the channels of the first and second transistors, the transistor having a source coupled to a first node and a drain connected to the channel formation region of each first transistor, and the drain of the transistor being further coupled to the source of each first transistor through a resistor.

[0029] According to an embodiment, in each branch, the second transistor includes a conductive terminal (preferably its source) connected to the drain of the first transistor, and a conductive terminal forming the output of the differential pair.

[0030] Another embodiment provides an operational amplifier including an input stage composed of the above differential pair.

[0031] According to an embodiment, the first and second transistors of the differential pair have P-channels.

[0032] According to an embodiment, the input stage further includes the above another differential pair connected in parallel with the differential pair, the first and second transistors of the another differential pair having N-channels, and the amplifier being of rail-to-rail type.

[0033] According to an embodiment, the output of each differential pair is coupled to a corresponding folded cascode stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other features and advantages will be described in detail below with reference to the accompanying drawings in a manner of illustration rather than limitation for specific embodiments, where:

[0035] Figure 1 An example of a differential pair of the input stage of an operational amplifier is schematically shown.

[0036] Figure 2 An embodiment of a differential pair of the input stage of an operational amplifier is schematically shown.

[0037] Figure 3 Shows for Figure 2 of the differential pair and Figure 1 an example of a differential pair of type, an example of the input offset varying as a function of the input common mode.

[0038] Figure 4 Another embodiment of a differential pair of the input stage of an operational amplifier is schematically shown; and

[0039] Figure 5 An embodiment of the input stage of an operational amplifier is schematically shown in the form of a block diagram. DETAILED DESCRIPTION

[0040] In the various figures, similar features have been designated with similar reference numerals. Specifically, structural and / or functional features common to the embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0041] For clarity, only the steps and elements useful for understanding the embodiments described herein have been described in detail. Specifically, the input stage of the operational amplifier and the other stages of the operational amplifier (intermediate stage, gain stage, and output stage) have not been described in detail, as these are known to those skilled in the art.

[0042] Unless otherwise stated, when referring to two elements being connected together, this means a direct connection without any intermediate element other than a conductor, and when referring to two elements being coupled together, this means that the two elements may be connected or they may be coupled through one or more other elements.

[0043] In the following disclosure, unless otherwise specified, when referring to absolute position qualifiers such as the terms "front", "rear", "top", "bottom", "left", "right", etc., or relative position qualifiers such as the terms "above", "below", "higher", "lower", etc., or direction qualifiers such as "horizontal", "vertical", etc., it refers to the direction shown in the figure.

[0044] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "approximate to" mean within 10%, preferably within 5%.

[0045] Figure 1 An example of a differential pair 100 of the input stage IN of an operational amplifier is schematically shown. In Figure 1 only a part of the input stage IN of the operational amplifier and a part of an example of the gain stage G are shown.

[0046] The differential pair 100 includes two identical branches 101 and 102, which are connected in parallel between a node or rail 104 to which a DC potential Vcc is applied and a node or rail 106 to which a DC potential GND is applied. The potential Vdd is the supply potential of the operational amplifier. The potential Vdd is positive and is referenced to another supply potential of the operational amplifier, or a reference potential here, which is the potential GND.

[0047] Each branch 101, 102 includes a P-channel MOS or PMOS transistor T1. The source of the transistor T1 of each branch 101 and 102 is connected to the first end of the branch, its drain is coupled to the second end of the branch through an active load 108 (a current source in this example), and its gate is connected to the corresponding input in_n or in_p of the differential pair 100, or rather, the input stage IN. In Figure 1In the example, the gate of transistor T1 in branch 101 is connected to input in_n, and the gate of transistor T1 in branch 102 is connected to input in_p.

[0048] The first ends of branches 101 and 102 are interconnected, or rather, mixed together. The first ends of branches 101 and 102 are further coupled to node 104 through the same current source 110, which is configured to provide a bias current I0. In addition, the second end of each of branches 101 and 102 is connected to node 106.

[0049] The drains of transistors T1 in each of branches 101 and 102 form the corresponding output terminals out_n or out_p of differential pair 100, or in other words, the output terminals of input stage IN. In Figure 1 the example, the drain of transistor T1 in branch 101 forms output terminal out_n, and the drain of transistor T1 in branch 102 forms output terminal out_p.

[0050] In Figure 1 the example, the gain stage G connected after input stage IN includes a folded cascode circuit 111, and circuit 111 has an input connected to output out_n and an input connected to output out_p.

[0051] More specifically, in Figure 1 the example, circuit 111 includes two identical circuits 112 and 114. Each of circuits 112 and 114 includes a MOS transistor T2, whose channel type is opposite to that of transistor T1, that is, having an N-channel in this example. The sources of transistors T2 in circuits 112 and 114 respectively form the input terminals of circuit 111, which are respectively coupled to the output terminals out_n and out_p of stage IN. Each of circuits 112 and 114 further includes a circuit 116 for controlling its transistor T2, which is schematically shown as an operational amplifier here. Each circuit 116 is configured to provide a control potential to the gate of the transistor T2 it controls, so that in the steady state, a potential Vref (such as a positive potential and referenced to ground GND) is applied to the corresponding output out_n or out_p of stage IN. Therefore, each circuit 116 includes an input coupled to the corresponding output out_n or out_p, an input coupled to potential Vref, and an output coupled to the gate of the transistor T2 it controls. Each circuit 116 is implemented by an operational amplifier, for example, an operational amplifier having a non-inverting input receiving potential Vref and an inverting input coupled (preferably connected) to the corresponding output out_n or out_p.

[0052] Figure 1The case where the operational amplifier represented in the middle part is of the rail-to-rail type is taken as an example here. In this case, although not shown, stage IN includes an additional differential pair connected in parallel with differential pair 100. This additional differential pair is supplementary to differential pair 100. Specifically, the transistor T1 of the complementary differential pair is of the N-channel type.

[0053] In this example, differential pair 100 is configured to operate within a common-mode input value range, for example, a range value from -200 mV to Vdd - 1.5V. Therefore, the drain-source voltage of each transistor T1 is within the absolute value range, from Vdd - 1.5 + Vgs - Vref to -0.2 + Vgs - Vref in this example, where Vgs is the absolute value of the gate-source voltage of the transistor, and Vref is equal to 0.3V, for example. Thus, the drain-source voltage of each transistor T1 varies with the common-mode value of inputs in_n and in_p.

[0054] The inventor has observed that the input offset of differential pair 100 varies with the drain-source voltage of transistor T1, and thus with the common-mode input value of differential pair 100, which is not desirable.

[0055] Therefore, the inventor provides to keep the drain-source voltage of transistor T1 constant while ensuring that the latter operates in the saturation state. To this end, the inventor provides to place each transistor T1 in a cascode configuration, or in other words, by interconnecting the gates of the transistors assembled in cascode, in series with a MOS transistor of the same type but with a smaller channel size. Thus, the drain-source voltage of each transistor T1 is constant and is set by the gate-source voltage of transistor T1 and the gate-source voltage of the transistor assembled in cascode therewith. In addition, to ensure that each transistor T1 remains in the saturation state, or in other words, remains saturated throughout the common-mode input value range providing differential pair operation, the inventor provides to apply a non-zero voltage between the source of transistor T1 and the channel formation or body region, which voltage is configured to increase the absolute value of transistor T1, thereby increasing its gate-source voltage when transistor T1 operates in the saturation state. In the provided solution, transistor T1 ensures the amplification function and thus determines the input offset of the differential pair, and the transistors assembled in cascode are used to keep the drain-source voltage of transistor T1 constant.

[0056] Figure 2 An embodiment of such a differential pair 200 is schematically shown, and differential pair 200 is suitable for use in the input stage of an operational amplifier (e.g., a rail-to-rail amplifier).

[0057] Differential pair 200 includes two identical branches 201 and 202, connected in parallel with each other.

[0058] Each branch 201, 202 includes a MOS transistor (or PMOS transistor) T1 having a P-type channel and a MOS transistor T3 having a P-type channel.

[0059] In each branch 201, 202, the transistors T1 and T3 are cascode-assembled. In other words, the source or first conductive terminal of the transistor T3 is connected to the drain of the transistor T1.

[0060] Further, in each branch 201, 202, the gates of the transistors T1 and T3 are interconnected and coupled, preferably connected to the corresponding input in_n or in_p of the differential pair 200. In Figure 2 the example of, the gates of the transistors T1 and T3 of the branch 201 are coupled, preferably connected to the input in_n of the differential pair 200, and the gates of the transistors T1 and T3 of the branch 202 are coupled, preferably connected to the input in_p of the differential pair 200.

[0061] Thus, in each branch 201, 202, the drain-source voltage of the transistor T1 is equal to the gate-source voltage of the transistor T1 minus the gate-source voltage of the transistor T3. This drain-source voltage is thus constant because when modifying the gate potential of the cascode-assembled transistors T1 and T3, the modification of the gate-source voltage of the transistor T1 is offset by the modification of the gate-source voltage of the transistor T3.

[0062] As an example, in each branch 201, 202, the drain or second conductive terminal of the transistor T3 forms or corresponds to the output out_n or out_p of the differential pair 200. In Figure 2 the example of, the drain of the transistor T3 of the branch 201 forms the output terminal out_n, and the drain of the transistor T3 of the branch 202 forms the output terminal out_p. Although this is not illustrated in Figure 2 when the differential pair 200 is implemented in the input stage of an operational amplifier, each output out_p, out_n of the differential pair 200 is coupled, preferably connected to the corresponding input of the gain stage. For example, the outputs out_n and out_p are connected to the respective input terminals of a folded cascode circuit, preferably related to Figure 1 the circuit 111.

[0063] The differential pair 200 further includes a circuit 204 (delineated by a dashed line in Figure 2 ). The circuit 204 is configured to apply a non-zero voltage between the transistor source and the body region of each transistor T1. In other words, the circuit 204 is configured to apply a non-zero source-body voltage to each transistor T1.

[0064] According to an embodiment, the source-body voltage is configured to increase the turn-on threshold of transistor T1 in absolute value, while in the normal case, the body region of each transistor T1 is connected to the source of that transistor T1, as Figure 1 in the case of. This enables, when the transistors T1 of the differential pair 200 are operating in the saturation state, an increase in their gate-source voltage, and thus an increase in the drain-source voltage of these transistors T1.

[0065] More particularly, according to an embodiment, the source-body voltage is configured to keep the transistor T1 in saturation over the entire common-mode input value range provided for the operation of the differential pair 200.

[0066] Thus, according to an embodiment, the source-body voltage is configured to make the absolute value of the drain-source voltage of each transistor T1 greater than the absolute value of the gate-source voltage of the transistor T1 minus the absolute value of the turn-on threshold of that transistor T1, over the entire common-mode input value range provided for the operation of the differential pair 200.

[0067] According to an embodiment, the size ratio of each transistor T1 is X times greater than the size ratio of each transistor T3. Preferably, the factor X is less than or equal to 10, still more preferably less than or equal to 6, so that the gate-source voltage of transistor T3 is not too high. In fact, the higher the gate-source voltage of transistor T3, the higher the source-body voltage applied to transistor T1 to provide the operation of transistor T1 in the saturation state. In addition, preferably, the factor X is greater than 4, or even 5. In fact, the lower the factor X, the higher the stray capacitance of transistor T3, which is not desirable. In particular, the higher the input capacitance of transistor T3, the greater the input capacitance of the operational amplifier including the pair 200 as the input stage, while preferably the input capacitance of the operational amplifier is as low as possible.

[0068] In Figure 2 each of the transistors T1 of branches 201, 202 has its source coupled, preferably to the first end 206 of the branch. The two ends 206 of branches 201 and 202 are confused here. In addition, the drains of the transistors T3 of branches 201 and 202 are coupled to the second ends 208 and 209 of the branches respectively through the active loads 210 of the branches.

[0069] In this embodiment, transistors T1 and T3 have P channels, and the first ends 206 of branches 201 and 202 are coupled to the rail or node 212 through the current source 214, and the node 212 is configured to receive the DC power supply potential Vdd. The current source 214 provides a constant current I0'.

[0070] Furthermore, in this embodiment where transistors T1 and T3 are P-channel, the second ends 208 and 209 of branches 201 and 202 are coupled, preferably connected, to a rail or node 216 configured to receive a DC reference potential GND. The potential Vdd is positive and referenced to the potential GND. When the differential pair 200 is implemented in the input stage of the operational amplifier, the latter is preferably supplied with the difference between the potentials Vdd and GND.

[0071] According to an example of the implementation mode, the current source 214 is a P-channel MOS transistor, whose source is coupled, preferably connected, to the rail 212; whose drain is coupled, preferably connected, to the ends 206 of branches 201 and 202, and whose gate receives a bias potential Vb.

[0072] According to the embodiment, the load 210 of each of the branches 201, 202 includes a resistor R1 in series with an N-channel MOS transistor T4. The resistors R1 of the branches 201, 202 are respectively on one side of the ends 208, 209 of the said branches, and are respectively coupled, e.g., connected, to the ends 208, 209 of the said branches. The transistors T4 of the two branches 201 and 202 are assembled as a mirror image of the same transistor T5, i.e., the drain and gate of the transistor T5 are connected together and connected to the gate of the transistor T4.

[0073] More precisely, in the Figure 2 example, the resistors R1 of the branches 201, 202 respectively include being coupled, preferably connected, to the ends 208, 209 of the branches. The resistors R1 of the branches 201, 202 respectively include a second terminal, preferably connected to the source of the transistor T4 of the said branch. In each of the branches 201, 202, the drain of the transistor T4 of the said branch is coupled, preferably connected, to the drain of the transistor T3 of the said branch.

[0074] Furthermore, in the Figure 2 example, similar to the transistor T4, the source of the transistor T5 is coupled to the node 216 through a resistor R2. The transistor T5 is, for example, the same as the transistor T4, and the resistor R2 is, for example, the same as the resistor R1. The drain of the transistor T5 is, for example, coupled by a current source 218 to the node 212, providing a constant current I0", e.g., equal to the current I0'. As an example, the current source 218 is a P-channel MOS transistor, whose source is coupled, preferably connected, to the rail 212; whose drain is coupled, preferably connected, to the drain of the transistor T5, and whose gate receives a DC bias potential Vb'. Preferably, the transistors 218 and 214 are the same, and the potentials Vb and Vb' are the same.

[0075] According to an embodiment, the circuit 204 includes a P-channel MOS transistor T6, whose source is coupled, preferably connected to the node 212, whose drain is connected to the body region of each transistor T1, and whose gate receives a DC bias potential Vb”. The circuit 204 further includes a resistor R3, coupling the drain of the transistor T6 to the source of each transistor T1. For example, the first terminal of the resistor R3 is connected to the drain of the transistor T6, and the second terminal of the resistor R3 is connected to the body region of the transistor T1. The transistor T6 forms a current source, configured to provide a current flowing through the resistor R3, and the voltage drop between both ends of the resistor R3 determines the source-body voltage of the transistor T1. Preferably, the current provided by the transistor T6 is negligible compared to the current I0' provided by the current source 214, for example, at least 10 times smaller, preferably at least 20 times smaller, more preferably at least 30 times smaller.

[0076] Preferably, the gates of the transistors T6 and 214 are connected together, and then the potential Vb” is the same as the potential Vb. In this case, the size of the transistor T6 is at least 10 times smaller than the size of the transistor 214, preferably at least 20 times smaller, more preferably at least 30 times smaller.

[0077] As an example, when the differential pair is implemented in a rail-to-rail operational amplifier and is provided to operate in a common-mode input value range from -200 mV to Vdd - 1.5 V, the source-body voltage of the transistor T1 can be selected such that the drain-source voltage of the transistor T1 is equal to 150 mV.

[0078] For the example in the above paragraph, the inventors observed that, within the entire common-mode input value range, the input offset value changes by at most 2 μV, while for the differential pair 100 having the same transistor T1 as the differential pair 200 ( Figure 1 ), the input offset value changes by at least 200 μV within this same common-mode input value range.

[0079] The differential pair 200 can be used for the input stage of a rail-to-rail operational amplifier, but can also be used for non-rail-to-rail types of operational amplifiers.

[0080] According to an embodiment, the differential pair 200 is implemented in the input stage of a rail-to-rail operational amplifier, and the input stage further includes another differential pair with N-channel MOS transistors, connected in parallel between the nodes 212 and 216 with the differential pair 200. Those skilled in the art know how to form such a differential pair with N-channel transistors.

[0081] Figure 3 Examples of the input offset Vio (microvolts) as a function of the input common-mode Vicm value (volts) are shown by curves 301, 302, and 303, for the differential pair 200 (curve 301) and Figure 1Variation of an example of a differential pair of the type concerned (curves 302 and 303).

[0082] A differential pair implemented in a rail-to-rail operational amplifier and attempting to operate in the range of an input common-mode Vicm value from -200 mV to Vdd - 1.5 V (Vdd being equal to 5 V) is considered here as an example. For differential pair 200, for example, the source-body voltage of transistor T1 is selected such that the drain-source voltage of transistor T1 is equal to 150 mV.

[0083] As shown by curve 301 of differential pair 200, over the entire range of the considered input common-mode Vicm values, the input offset Vio is constant, being either +2 μV or -2 μV.

[0084] On the other hand, as shown by curves 302 and 303, in Figure 1 a differential pair of the type described, the input offset Vio varies over a range of several hundred microvolts over the entire range of the considered input common-mode Vicm values.

[0085] So far, a differential pair 200 with a P-channel MOS transistor T1 has been described. The solution provided by the present inventors to reduce the variation of the input offset in the differential pair over the common-mode input value range, where the differential pair is provided for operation, can also be implemented in a differential pair with an N-channel MOS transistor T1 and will now be described.

[0086] Figure 4 Another embodiment of a differential pair 300 suitable for use in the input stage of an operational amplifier, for example, a rail-to-rail operational amplifier, is schematically shown.

[0087] More specifically, Figure 4 the differential pair 300 of Figure 2 is similar to the differential pair of

[0088] except that:

[0089] the P-channel transistor, specifically transistor T1 that amplifies the differential mode, is replaced with an N-channel transistor;

[0090] the N-channel transistor is replaced with a P-channel transistor;

[0091] the rails 216 and 212 receiving the respective potentials GND and Vdd are exchanged; and

[0092] When represented in Figure 4 the rails 216 and 212 receiving the respective potentials GND and Vdd are exchanged with respect to those already described in Figure 2 this means that when an element or terminal is coupled or connected to Figure 2When it is one of the two tracks 216 and 212, the element or the terminal is respectively connected or coupled to Figure 4 the other of the two tracks 216 and 212. For example, the second ends 208 and 209 of the branches 201 and 202 are coupled to Figure 2 the track 216 receiving the potential GND, preferably connected, while they are coupled to Figure 4 the track 212 receiving the potential Vdd, preferably connected.

[0093] For the rest, the description of the differential pair 200 related to Figure 2 is applicable to Figure 4 the differential pair 300, except that the tracks 212 and 216 are exchanged, which particularly means that, in Figure 4 the ends 206 of the branches 201 and 202 of the differential pair 300 are coupled to the track 216 at the potential GND, while the ends 208 and 209 of the respective branches 201 and 202 of the differential pair 300 are coupled to the track 212 at the potential Vdd.

[0094] In addition, similar to the case of the differential pair 200 related to Figure 2 , the outputs out_n and out_p of the differential pair 300 can be connected to a folded cascode circuit, for example, a folded cascode circuit, which is different from the circuit 111 ( Figure 1 ) in that the value of the potential Vref it receives and its transistor T2 has a P-channel.

[0095] Figure 5 Schematically shows an embodiment of the input stage IN' of the operational amplifier, particularly an embodiment of a rail-to-rail amplifier.

[0096] The input stage IN' includes the differential pair 200 shown in block form. The differential pair 200 is connected between the tracks 212 and 216, as Figure 2 shown. The inputs in_n, in_p of the differential pair 200 are respectively coupled, preferably connected to the inputs IN_n, IN_p of the stage IN', and the inputs IN_n and IN_p respectively correspond to the inverting and non-inverting inputs of the operational amplifier. The outputs out_n and out_p of the differential pair 200 form the corresponding outputs OUT_n1 and OUT_p1 of the stage IN'.

[0097] According to the embodiment, the input stage IN' further includes the differential pair 300 shown in block form. The differential pair 300 is connected between the tracks 212 and 216, as Figure 4 shown. The inputs in_n, in_p of the differential pair 300 are respectively coupled, preferably connected to the inputs IN_n, IN_p of the stage IN'. The outputs out_n and out_p of the differential pair 300 form the corresponding outputs OUT_n2 and OUT_p2 of the stage IN'.

[0098] Thus, stage IN' includes two inputs IN_n and IN_p and four outputs OUT_n1, OUT_n2, OUT_p1 and OUT_p2. By combining the output OUT_n1 or OUT_p1 of differential pair 200 with the outputs OUT_n2 and OUT_p2 of differential pair 300 at one stage of the intermediate stage (not shown) of the amplifier, the amplifier achieves rail-to-rail operation.

[0099] In another unillustrated embodiment, differential pair 300 composed of N-channel transistor T1 is replaced by a common differential pair composed of N-channel MOS transistors. Then a step of calibrating the differential pair composed of N-channel MOS transistors can be provided to ensure the continuity of the input offset between the common-mode input value range using the output of differential pair 200 and the common-mode input value range using the output of the differential pair composed of N-channel MOS transistors.

[0100] The combination of the output of the differential pair composed of P-channel MOS transistors and the output of the differential pair composed of N-channel MOS transistors in parallel on the differential pair composed of P-channel MOS transistors is known to those skilled in the art, and this combination can be achieved in the case where differential pair 200 is in parallel with differential pair 300 or in parallel with a common differential pair composed of N-channel MOS transistors.

[0101] Furthermore, although this is not shown in Figure 5 , preferably, before being combined at the level of the intermediate stage, it is within the capabilities of those skilled in the art to implement that the outputs OUT_n1, OUT_n2, OUT_p1 and OUT_p2 are each sent to a gain stage, for example, to their respective circuits of the gain stage, each circuit being, for example, a folded cascode circuit, preferably a folded cascode circuit, such as the description related to Figure 1 . In the case where the outputs OUT_n2 and OUT_p2 of differential pair 300 are each provided to a folded cascode circuit of the type related to Figure 1 , the potential Vref is adapted to be, for example, equal to Vdd - 0.3V, and the transistor T2 of these circuits has an N-channel instead of a P-channel.

[0102] Various embodiments and variants have been described. Those skilled in the art should understand that certain features of these different embodiments and variants can be combined, and other variants will also occur.

[0103] Finally, the actual implementation of the described embodiments and variations is within the capabilities of a person skilled in the art, based on the functional indications given above. Specifically, within the capabilities of a person skilled in the art, differential pair 200 and / or differential pair 300 can be associated with a gain circuit that is different from the folded cascode circuit described herein, or even with a non-folded cascode circuit.

Claims

1. A differential pair for an input stage, comprising: Two identical branches connected in parallel, each branch including a first transistor and a second transistor arranged in series, wherein the first transistor and the second transistor have channels of the same type, and wherein each of the first transistor and the second transistor has a gate coupled to the same corresponding input of the differential pair; And A circuit configured to apply a potential difference between the source and the channel formation region of each of the first transistors, Wherein the size ratio of each first transistor is X times the size ratio of each second transistor.

2. The differential pair according to claim 1, wherein X is in the range of 4 to 10.

3. The differential pair according to claim 2, wherein X is in the range of 5 to 6.

4. The differential pair according to claim 1, wherein the potential difference is configured to increase the conduction threshold of the first transistor in absolute value.

5. The differential pair according to claim 4, wherein the potential difference is configured to bring the first transistor into a saturation state.

6. The differential pair according to claim 4, wherein the potential difference is configured to make the absolute value of the drain-source voltage of each first transistor greater than the absolute value of the gate-source voltage of the first transistor minus the absolute value of the conduction threshold of the first transistor.

7. The differential pair according to claim 1, Wherein the first transistor in each branch has a source coupled to the first end of the branch, Wherein the second transistor in each branch has a drain coupled to the second end of the branch through the active load of the branch, Wherein the first end of the branch is coupled to a first node through a current source, the first node being configured to be at a first DC voltage, and Wherein the second end of the branch is coupled to a second node, the second node being configured to be at a second DC voltage.

8. The differential pair according to claim 7, wherein the first DC voltage is Vdd and the second DC voltage is GND.

9. The differential pair according to claim 7, wherein the first DC voltage is GND and the second DC voltage is Vdd.

10. The differential pair according to claim 7, Wherein the active load includes a resistor in series with a third transistor, the third transistor having a channel of a type opposite to the channels of the first transistor and the second transistor, Wherein the resistor is coupled to the second end of the branch, and the drain of the third transistor is coupled to the drain of the second transistor of the branch, the third transistor being a mirror image of a fourth transistor, and the third transistor and the fourth transistor being identical.

11. The differential pair according to claim 10, wherein the current source includes a current source MOS transistor having a channel of the same type as the channels of the first transistor and the second transistor, the current source MOS transistor having a gate, and the gate of the current source MOS transistor being configured to be at a bias potential.

12. The differential pair according to claim 7, wherein the circuit comprises: A circuit MOS transistor having a channel of the same type as the channels of the first and second transistors, wherein the circuit MOS transistor has a source coupled to the first node and a drain connected to the channel formation region of each of the first transistors, and wherein the drain of the circuit MOS transistor is further coupled to the source of each of the first transistors through a resistor.

13. The differential pair according to claim 1, wherein in each branch, the second transistor comprises a conductive terminal connected to the drain of the first transistor and a conductive terminal forming the output of the differential pair.

14. The differential pair according to claim 13, wherein the conductive terminal connected to the drain is a source.

15. An operational amplifier comprising: The input stage including the differential pair according to claim 1, the differential pair being a first differential pair.

16. The operational amplifier according to claim 15, wherein the first and second transistors of the first differential pair have P-channels.

17. The operational amplifier according to claim 16, wherein the input stage further includes a second differential pair connected in parallel with the first differential pair, the second differential pair having the same structure as the first differential pair, wherein the first and second transistors of the second differential pair have N-channels, and wherein the operational amplifier is a rail-to-rail amplifier.

18. The operational amplifier according to claim 15, wherein in each branch of the first differential pair, the second transistor includes a conductive terminal connected to the drain of the first transistor and a conductive terminal forming the output of the differential pair, and wherein the output of the differential pair is coupled to a corresponding folded cascode stage.

19. The operational amplifier according to claim 18, wherein the conductive terminal connected to the drain of the first transistor is a source.

20. A differential pair for an input stage, comprising: Two identical branches connected in parallel, each branch including a first transistor and a second transistor arranged in series, wherein the first and second transistors have channels of the same type, and wherein each of the first and second transistors has a gate coupled to the same corresponding input of the differential pair; And A circuit configured to apply a potential difference between the source and the channel formation region of each of the first transistors, Wherein the first transistor in each branch has a source coupled to the first end of the branch, Wherein the second transistor in each branch has a drain coupled to the second end of the branch through the active load of the branch, Wherein the first end of the branch is coupled to a first node through a current source, the first node being configured to be at a first DC voltage, and Wherein the second end of the branch is coupled to a second node, the second node being configured to be at a second DC voltage, wherein the active load includes a resistor in series with a third transistor, the third transistor having a channel type opposite to that of the channels of the first and second transistors, wherein the resistor is coupled to the second end of the branch, and the drain of the third transistor is coupled to the drain of the second transistor of the branch, the third transistor being a mirror image of a fourth transistor, and the third and fourth transistors being identical.

21. An operational amplifier, comprising: an input stage, comprising: a first differential pair, comprising: two identical branches connected in parallel, each branch including a first transistor and a second transistor arranged in series, wherein the first and second transistors have channels of the same type, and wherein each of the first and second transistors has a gate coupled to the same corresponding input of the differential pair; and a circuit configured to apply a potential difference between the source and the channel forming region of the first transistor to each of the first transistors, wherein the first and second transistors of the first differential pair have P-channels; and a second differential pair connected in parallel with the first differential pair, the second differential pair having the same structure as the first differential pair, wherein the first and second transistors of the second differential pair have N-channels, and wherein the operational amplifier is a rail-to-rail amplifier.

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