Wafer level package structure, method of manufacturing the same and method of activating the getter layer

Abstract

The application discloses a wafer level packaging structure, which comprises a first wafer and a second wafer fixedly connected with the first wafer through a bonding layer to form a cavity for accommodating a MEMS, wherein the bottom surface of the first wafer is provided with a protrusion so that the bottom surface of the first wafer is formed with a deep cavity structure, the protrusion is connected with the deep cavity structure through an inclined side edge, and a metal activation layer is arranged in the protrusion, the inclined side edge and the deep cavity structure, the metal activation layer is discontinuously arranged in the deep cavity structure, an adsorbent layer, a first insulating layer and a second insulating layer which are spaced apart are arranged on the metal activation layer, and the bonding layer is arranged on the first insulating layer so that the adsorbent layer is arranged in the cavity, and an activation electrode can be arranged between the first insulating layer and the second insulating layer, the adsorbent layer is electrically activated through the conduction of the metal activation layer, and the adverse effect of a traditional thermal activation mode on a wafer device is avoided.

Description

Technical Field

[0001] This invention relates to the field of MEMS device technology, and in particular to a wafer-level packaging structure and its fabrication method, as well as a method for activating the getter layer. Background Technology

[0002] With the continuous advancement of science and technology and the continuous development of society in recent years, MEMS (Micro-Electro-Mechanical Systems) has developed greatly, and correspondingly, MEMS sensors have also developed greatly. They have been widely used in automobiles, security, biomedicine, power, smart buildings, forest fire prevention, smartphones and the Internet of Things.

[0003] Currently, MEMS sensor manufacturing typically employs wafer-level packaging (WLP) technology. WLP involves using processes similar to those used in semiconductor front-end development, such as thin-film deposition, photolithography, electroplating, and wet / dry etching, to complete packaging and testing on a silicon wafer, followed by dicing to produce individual packaged products. Compared to traditional metal or ceramic packaging, WLP can significantly reduce the size of the packaged device, meeting the current demand for miniaturized chips in mobile devices. It also eliminates the need for metal or ceramic casings, effectively reducing device costs. Wafer-level vacuum packaging technology primarily involves bonding and packaging the device layer wafer and cap layer wafer in a high-vacuum, sealed chamber after certain semiconductor processes, forming a high-vacuum, highly sealed internal structure. However, after bonding and packaging, the internal vacuum level often decreases due to some vacuum leakage and residual gas on the chamber walls. This is typically addressed by depositing a thin film of getter inside the device to maintain the internal vacuum.

[0004] However, in existing technologies, activating getters through thermal activation can have a significant thermal impact on sensitive device chips: excessively high temperatures may reduce the performance of the device chip; while excessively low temperatures may result in incomplete activation of the getter, thus affecting the vacuum level. Therefore, how to avoid the impact on the sensor structure during getter activation is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] This invention provides a wafer-level packaging structure, its fabrication method, and a getter activation method. The wafer-level packaging structure is a buried wire type. By electrically connecting the getter in the wafer-level packaging structure to the outside, the getter in the wafer-level packaging structure can be activated by electrical activation, avoiding the adverse effects of traditional thermal activation methods on wafer devices.

[0006] This invention provides a wafer-level packaging structure, comprising a first wafer and a second wafer. The bottom surface of the first wafer has a protrusion, forming a deep cavity structure. The protrusion and the deep cavity structure are connected by an inclined side edge, which slopes from top to bottom and from the inner circle to the outer circle. A metal activation layer extending to the inclined side edge and the protrusion is deposited within the deep cavity structure. The metal activation layer is intermittently disposed within the deep cavity structure. A first insulating layer, a second insulating layer, and a getter layer are disposed on the metal activation layer. The first and second insulating layers are located on the protrusion. A bonding layer is disposed on the first insulating layer. The first wafer and the second wafer are fixedly connected by the bonding layer to form a cavity. The getter layer is located within the cavity, and the second insulating layer is located outside the cavity. The first and second insulating layers are spaced apart.

[0007] Furthermore, the acute angle between the inclined side edge and the deep cavity structure is in the range of 30°-60°.

[0008] Furthermore, the thickness of the metal activation layer is set between 200nm and 2000nm.

[0009] Furthermore, the thickness of the first insulating layer and the second insulating layer is between 0.2 μm and 2 μm.

[0010] This invention also provides a method for fabricating a wafer-level packaging structure, comprising the following steps:

[0011] S1: The SOI silicon wafer containing the silicon support layer and the silicon dioxide oxide layer located in the silicon support layer is used as the first wafer. The SOI silicon wafer is cleaned and a thin film protective layer is deposited on the top and bottom surfaces of the SOI silicon wafer.

[0012] S2: An etching process is performed on the central area of ​​the bottom surface of the SOI silicon wafer until the silicon dioxide oxide layer is etched, so as to form protrusions on both sides of the bottom surface of the SOI silicon wafer and a trapezoidal deep cavity structure in the central area of ​​the SOI silicon wafer.

[0013] S3: The silicon dioxide oxide layer inside the deep cavity structure is removed by wet etching process, and the thin film protective layer on the top and bottom surfaces of the SOI silicon wafer is etched away.

[0014] S4: A metal activation layer is deposited on the bottom surface of the SOI silicon wafer, and a patterning process is performed to etch away the metal activation layer in the center of the deep cavity structure.

[0015] S5: An insulating layer is deposited on the metal activation layer and a patterning process is performed to etch away the insulating layer inside the deep cavity structure and partially etch the insulating layer outside the deep cavity structure to form a first insulating layer and a second insulating layer, so that a pad point is formed between the first insulating layer and the second insulating layer.

[0016] S6: A getter layer is vapor-deposited onto the metal activation layer within the deep cavity structure;

[0017] S7: The first insulating layer is bonded to the second wafer by welding.

[0018] Furthermore, the thin-film getter has an alloy structure composed of Zr, Co, Re and Zn metals.

[0019] Furthermore, the thin film protective layer includes a SiNx protective layer with a thickness of 100nm-300nm and a Ti and / or Pt protective layer with a thickness of 50nm-200nm.

[0020] Furthermore, the first insulating layer and the second insulating layer are either SiNx insulating layers or SiO2 insulating layers.

[0021] Furthermore, the metal activation layer is any one of Al activation layer, Ti activation layer and Au activation layer.

[0022] The present invention also provides a method for activating a getter layer in a wafer-level packaging structure, wherein an activation electrode is placed between a first insulating layer and a second insulating layer, and the getter layer is electrically activated by the current of the activation electrode; or, the wafer-level packaging structure is placed in a high-temperature environment, and the getter layer is activated by thermal activation.

[0023] The first aspect of this invention provides a wafer-level packaging structure. A protrusion is provided on the bottom surface of a first wafer to form a deep cavity structure. A metal activation layer is laid on the deep cavity structure, the inclined side edge, and the protrusion. The metal activation layer is intermittently disposed within the deep cavity structure. A first insulating layer and a second insulating layer are disposed at intervals on the metal activation layer. A bonding layer is disposed on the first insulating layer to achieve a fixed connection with a second wafer. A vacuum cavity is formed between the first wafer and the second wafer. The second insulating layer is located outside the cavity, and a getter layer is disposed on the metal activation layer and located inside the cavity. When it is necessary to activate the getter layer to adsorb air in the cavity, positive and negative activation electrodes are placed between the first and second insulating layers. Current is transferred to the getter layer through the metal activation layer. When the current flows through the getter layer, it converts electrical energy into heat energy to activate the getter. That is, by using activation electrodes, only the getter can be heated for activation, thereby avoiding the adverse effects of traditional thermal activation methods on the structure of wafer devices. Moreover, by setting activation electrodes, the getter can be activated multiple times to ensure the vacuum level in the MEMS sensor.

[0024] The second aspect of this invention provides a method for fabricating the aforementioned wafer-level packaging structure. A metal activation layer is embedded within a cavity on the surface of a first wafer (i.e., the cap wafer) using techniques such as metal thin film deposition, insulating layer deposition, and photolithography. This simplifies the structural design and process flow of the electro-activation process, improves process stability and reliability, and reduces process sequence, cost, and cycle time. Furthermore, this process exhibits good compatibility, eliminating issues such as getter contamination and large parasitic capacitance, ensuring the device simultaneously possesses the effects of both electro-activation and thermal activation. Additionally, by patterning the insulating layer structure, a complete electro-activation pathway is formed, while the metal activation layer also facilitates getter deposition and adsorption, increasing its adhesion to the first wafer. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of a wafer-level packaging structure provided in an embodiment of the present invention;

[0027] Figure 2 For preparation Figure 1 A flowchart of a method for fabricating a wafer-level packaging structure.

[0028] 1-First wafer, 2-Second wafer, 3-Metal activation layer, 4-First insulating layer, 5-Second insulating layer, 6-Getter layer, 7-Bonding layer, 8-Cavity, 9-Protrusion, 10-Sloping side edge. Detailed Implementation

[0029] This invention provides a wafer-level packaging structure and its preparation method, as well as a getter activation method, enabling the wafer-level packaging structure to simultaneously possess both electro-activation and thermal activation capabilities. Furthermore, this invention offers advantages such as good process compatibility, simple getter activation method, low cost, and stable performance.

[0030] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0031] This invention addresses the limitations of traditional getter thermal activation, which can reduce device performance and is time-consuming and labor-intensive. It also addresses the high complexity and poor process compatibility of thin-film getter deposition on IC circuit substrates, and the potential for electro-activation to affect pixel arrays. To address these issues, a wafer-cap buried-wire packaging structure is designed that can utilize both electro-activation and thermal activation methods. This packaging structure features a simple and practical electro-activation mechanism, resolving the problems of the impact of device-level electro-activation on the overall wafer wiring and process incompatibility. By utilizing custom silicon wafer dry and wet etching processes to form a trapezoidal ramp structure, using a metal thin film as the getter deposition substrate and electro-activation leads, and employing an insulating layer for protection, a highly efficient and stable wafer-level vacuum packaging structure and getter activation method are formed, ensuring the long-term stable operation of high-vacuum electronic devices.

[0032] Please see Figure 1 , Figure 1A wafer-level packaging structure provided in this embodiment of the invention includes a first wafer 1 and a second wafer 2 fixed together with the first wafer 1. The bottom surface of the first wafer 1 has a protrusion 9, which forms a deep cavity structure on the bottom surface of the first wafer 1. The protrusion 9 and the deep cavity structure are connected by an inclined transition edge 10, which is inclined from top to bottom and from the inner circle to the outer circle. In this embodiment, a metal activation layer 3 is provided on the bottom surface of the protrusion 9, the inclined transition edge 10, and part of the surface of the deep cavity structure. The metal activation layer 3 is intermittently provided within the deep cavity structure. A first insulating layer 4 and a second insulating layer 5 are spaced apart on the metal activation layer 3 on the bottom surface of the protrusion 9. A bonding layer 7 is provided on the first insulating layer 4, and the first wafer 1 and the second wafer 2 are bonded and fixed together by the bonding layer 7. Furthermore, the first wafer 1 and the second wafer 2 are bonded together by welding, that is, the bonding layer 7 is a tin-containing solder layer. This bonding method is simple and easy to operate.

[0033] When it is necessary to activate the getter layer 6, an electrode is placed in the gap between the first insulating layer 4 and the second insulating layer 5. Current is guided to the getter layer 6 through the circuit formed by the metal activation layer 3, achieving electrical heating of the getter layer 6 and thus activating the getter to ensure the vacuum within the cavity 8. This structure can increase the number of activation cycles and maintain a stable high vacuum level inside the device, thereby extending the device's stable and excellent performance and lifespan under high vacuum conditions. Of course, the wafer-level packaging structure of this invention can also be activated by high-temperature heating, allowing the wafer-level packaging structure to simultaneously possess the effects of both electrical and thermal activation.

[0034] The angle between the inclined edge 10 and the acute angle of the top surface of the deep cavity structure is within the range of 30°-60°. If the angle is less than 30°, the cavity 8 formed after the first wafer 1 and the second wafer 2 are bonded together will be low, which is not conducive to the placement of the MEMS sensor. If the angle is greater than 60°, the inclined edge 10 will be too steep, which is not conducive to the integrity of the circuit formed by the metal activation layer 3. Moreover, in order to ensure that the metal activation layer 3 can form a complete electrical activation path, the thickness of the metal activation layer 3 is between 200nm and 2000nm. In order to protect the metal activation layer 3 exposed to the external environment, the thickness of the first insulating layer 4 and the second insulating layer 5 is between 0.2μm and 2μm. In this embodiment, the acute angle between the inclined edge 10 and the bottom surface of the first wafer 1 is 54.7°.

[0035] like Figure 2 This invention provides a flowchart of a method for fabricating a wafer-level packaging structure. An embodiment of the method for fabricating the aforementioned wafer-level packaging structure is also provided, comprising the following steps:

[0036] S1: Clean the customized SOI silicon wafer (which is the first wafer) (the SOI silicon wafer includes a silicon support layer and a silicon dioxide oxide layer, wherein the silicon dioxide oxide layer is located inside the silicon support layer, and the thickness of the silicon support layer is 500 μm and the thickness of the silicon dioxide oxide layer is 1 μm), and deposit thin film protective layers on the top and bottom surfaces of the SOI silicon wafer. The thin film protective layers include a SiNx protective layer with a thickness of 100 nm-300 nm and a Ti and / or Pt protective layer with a thickness of 50 nm-200 nm.

[0037] S2: Photolithographically pattern the central area of ​​the bottom surface of the SOI silicon wafer to expose the thin film protective layer that needs to be dry-etched. Remove the thin film protective layer completely and use any one of the solutions with a concentration of 1wt%-80wt% of KOH, TMAH, or NaOH to perform a wet etching process on the SOI silicon wafer until the silicon dioxide oxide layer automatically stops, so as to form a trapezoidal deep cavity structure.

[0038] S3: Clean the SOI silicon wafer and immerse it in an HF solution with a concentration of 1%-49% for 10-120 seconds to remove the silicon dioxide oxide layer in the deep cavity structure. Then, use a spray coating process to coat the trapezoidal deep cavity structure with photoresist as a protective layer. After that, first etch away the thin film protective layer on the SOI silicon wafer, and then remove the photoresist protective layer in the deep cavity structure.

[0039] S4: Using a spray adhesive process, sputter or vapor deposit any one of the Al, Ti, and Au activation layers with a thickness between 200nm and 2000nm as the metal activation layer on the bottom surface of the SOI silicon wafer. Then, use a lift-off peeling process to remove the metal activation layer at the central position in the deep cavity structure. After the peeling process is completed, clean the SOI silicon wafer.

[0040] S5: An insulating layer with a thickness of 0.2μm-2μm is deposited and grown on the metal activation layer. This insulating layer can be either a SiNx insulating layer or a SiO2 insulating layer. Then, the insulating layer is patterned to etch away the insulating layer inside the deep cavity structure and etch away the insulating layer outside the deep cavity structure to form a first insulating layer and a second insulating layer with space between them. An electrically activated pad point is formed between the first insulating layer and the second insulating layer.

[0041] S6: A getter layer is deposited on the bottom surface of the SOI silicon wafer using a thin film evaporation process involving spraying adhesive, exposure, development, and coating. Part of the getter layer is then removed using a photolithography lift-off process, leaving only the getter layer on the metal activation layer located within the deep cavity structure.

[0042] S7: The first insulating layer and the second wafer are welded together through a tin-containing bonding layer to form a high-vacuum stable wafer-level packaging structure.

[0043] Specifically, the getter layer is generally an alloy structure composed of several metals such as Zr, Co, Re, and Zn. By placing the getter layer on the metal activation layer, it facilitates the subsequent electro-activation process. Moreover, in the above preparation method, a trapezoidal deep cavity structure is set on the lower surface of the SOI silicon wafer, so that protrusions 9 and inclined side edges 10 are formed on both outer edges of the bottom surface of the first wafer 1. The inclined side edges 10 have a certain angle design, which allows the metal activation layer in step S4 to completely cover the inclined side edges 10 to form a complete electrical path.

[0044] The present invention also includes a method for activating a getter in a wafer-level packaging structure: using the wafer-level packaging structure obtained by the above preparation method, an activation electrode is installed at the pad point, the activation electrode is energized, the current flows along the metal activation layer to the getter layer, and the getter layer is heated by current to activate the getter layer.

[0045] Another embodiment of the present invention provides a method for activating the getter in a wafer-level packaging structure: the wafer-level packaging structure obtained by the above preparation method is placed in a high-temperature environment, and the getter layer is activated by thermal activation.

[0046] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wafer-level packaging structure, characterized in that, The device includes a first wafer and a second wafer. The bottom surface of the first wafer has a protrusion, forming a deep cavity structure. The protrusion and the deep cavity structure are connected by an inclined side edge, which slopes from top to bottom and from the inner circle to the outer circle. A metal activation layer extending to the inclined side edge and the protrusion is deposited within the deep cavity structure. The metal activation layer is intermittently disposed within the deep cavity structure. A first insulating layer, a second insulating layer, and a getter layer are disposed on the metal activation layer. The first and second insulating layers are located on the protrusion. A bonding layer is disposed on the first insulating layer. The first wafer and the second wafer are fixedly connected by the bonding layer to form a cavity. The getter layer is located inside the cavity, and the second insulating layer is located outside the cavity. The first and second insulating layers are spaced apart. An activation electrode is placed between the first and second insulating layers.

2. The wafer-level packaging structure according to claim 1, characterized in that, The angle between the inclined side edge and the acute angle of the deep cavity structure is in the range of 30°-60°.

3. The wafer-level packaging structure according to claim 1, characterized in that, The thickness of the metal activation layer is set between 200nm and 2000nm.

4. The wafer-level packaging structure according to claim 1, characterized in that, The thickness of the first insulating layer and the second insulating layer is between 0.2 μm and 2 μm.

5. A method for preparing a wafer-level packaging structure as described in claims 1 to 4, characterized in that, Includes the following steps: S1: The SOI silicon wafer containing the silicon support layer and the silicon dioxide oxide layer located in the silicon support layer is used as the first wafer. The SOI silicon wafer is cleaned and a thin film protective layer is deposited on the top and bottom surfaces of the SOI silicon wafer. S2: An etching process is performed on the central area of ​​the bottom surface of the SOI silicon wafer until the silicon dioxide oxide layer is etched, so as to form a protrusion on the bottom surface of the SOI silicon wafer and a trapezoidal deep cavity structure in the central area of ​​the SOI silicon wafer. S3: The silicon dioxide oxide layer inside the deep cavity structure is removed by wet etching process, and the thin film protective layer on the top and bottom surfaces of the SOI silicon wafer is etched away. S4: A metal activation layer is deposited on the bottom surface of the SOI silicon wafer, and a patterning process is performed to etch away the metal activation layer in the center of the deep cavity structure. S5: An insulating layer is deposited on the metal activation layer and a patterning process is performed to etch away the insulating layer inside the deep cavity structure and partially etch the insulating layer outside the deep cavity structure to form a first insulating layer and a second insulating layer, so that a pad point is formed between the first insulating layer and the second insulating layer. S6: A getter layer is vapor-deposited onto the metal activation layer within the deep cavity structure; S7: The first insulating layer is bonded to the second wafer by welding.

6. The method for fabricating a wafer-level packaging structure according to claim 5, characterized in that, The getter is an alloy structure composed of Zr, Co, Re and Zn metals.

7. The method for fabricating a wafer-level packaging structure according to claim 5, characterized in that, The thin film protective layer includes a SiNx protective layer with a thickness of 100nm-300nm and a Ti and / or Pt protective layer with a thickness of 50nm-200nm.

8. The method for fabricating a wafer-level packaging structure according to claim 5, characterized in that, The first insulating layer and the second insulating layer are either SiNx insulating layer or SiO2 insulating layer.

9. The method for fabricating a wafer-level packaging structure according to claim 5, characterized in that, The metal activation layer is any one of Al activation layer, Ti activation layer and Au activation layer.

10. A method for activating the getter layer of a wafer-level packaging structure as described in claims 1 to 4, characterized in that, An activation electrode is placed between the first insulating layer and the second insulating layer, and the getter layer is electrically activated by the current of the activation electrode; or, the wafer-level packaging structure is placed in a high-temperature environment, and the getter layer is activated by thermal activation.

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