Wafer defect traceability method, device, electronic equipment and computer readable medium

Abstract

The present disclosure relates to a wafer defect tracing method, device, electronic equipment and computer readable medium. The method comprises: obtaining defect data of a wafer; obtaining position data of failed bits of the wafer; determining a defect area of a memory block in the wafer according to the defect data; determining a number of failed bits of the memory block in the wafer according to the position data of the failed bits; processing the defect area and the number of failed bits of each memory block in the wafer to obtain a correlation coefficient; and determining an abnormal reason of the failed bits of the wafer according to the correlation coefficient. The wafer defect tracing method, device, electronic equipment and computer readable medium provided by the present disclosure can realize the source tracing of the abnormal state of the defect, provide an effective method for quickly solving the abnormal problem, and thus improve the yield of the wafer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a wafer defect tracing method and device, an electronic device, and a computer readable medium. BACKGROUND

[0002] In wafer manufacturing, defects often occur on wafers. The causes of the defects can be too many micro-suspended particles in the air or ineffective cleaning of the wafers in some steps. The occurrence of the defects can easily cause the generation of failed bits, and when there are too many failed bits, the limited spare circuits cannot repair all the failed bits, resulting in the chip being determined as a defective product.

[0003] Therefore, the occurrence of too many defects can greatly reduce the yield of the wafers.

[0004] Therefore, a new wafer defect tracing method, device, electronic device, and computer readable medium are needed.

[0005] The above information disclosed in the background section is only intended to strengthen the understanding of the background of the present disclosure, and therefore it can include information that does not constitute the related art known to those of ordinary skill in the art. SUMMARY

[0006] Therefore, the present disclosure provides a wafer defect tracing method, device, electronic device, and computer readable medium, which can realize the source tracing of the abnormal state of the defects and provide an effective method for quickly solving abnormal problems.

[0007] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0008] According to an aspect of the present disclosure, a wafer defect tracing method is provided, which includes: acquiring defect data of a wafer; obtaining position data of failed bits of the wafer; determining a defect area of a storage block in the wafer according to the defect data; determining a number of failed bits of the storage block in the wafer according to the position data of the failed bits; processing the defect area and the number of failed bits of the storage block in the wafer to obtain a correlation coefficient; and determining an abnormal cause of the failed bits of the wafer according to the correlation coefficient.

[0009] In an example embodiment of the present disclosure, processing the defect area and the number of failed bits of the memory block in the wafer to obtain the correlation coefficient includes: obtaining a defect influence area of the wafer according to the defect data; determining a defect area index of the memory block in the wafer according to a ratio of the defect area of the memory block in the wafer to an area of the defect influence area; determining a failed bit index of the memory block in the wafer according to a ratio of the number of failed bits of the memory block in the wafer to the area of the defect influence area; and performing correlation analysis on the defect area index of the memory block in the wafer and the corresponding failed bit index to obtain the correlation coefficient.

[0010] In an example embodiment of the present disclosure, performing correlation analysis on the defect area index of the memory block in the wafer and the corresponding failed bit index to obtain the correlation coefficient includes: removing the memory block containing abnormal data in the wafer to obtain a target memory block set; and performing correlation analysis on the defect area index of the memory block in the target memory block set and the corresponding failed bit index to obtain the correlation coefficient.

[0011] In an example embodiment of the present disclosure, removing the memory block containing abnormal data in the wafer to obtain a target memory block set includes one or more of the following: removing the memory block in the wafer with a failed bit index greater than a failed bit index threshold to obtain the target memory block set; and removing the memory block in the wafer with a number of failed bits greater than a failed bit number threshold to obtain the target memory block set.

[0012] In an example embodiment of the present disclosure, determining the abnormal reason of the failed bit of the wafer according to the correlation coefficient includes: obtaining process data of the wafer, the process data including structure layer information and process information corresponding to the structure layer information; determining the structure layer information where the defect data is located if the correlation coefficient is greater than a correlation coefficient threshold; and determining the abnormal reason according to the process information corresponding to the structure layer information where the defect data is located.

[0013] In an example embodiment of the present disclosure, determining the abnormal reason according to the process information corresponding to the structure layer information where the defect data is located includes: obtaining environmental data of the process information according to the process information corresponding to the structure layer information where the defect data is located; and performing analysis on the environmental data of the process information to obtain the abnormal reason.

[0014] In an example embodiment of the present disclosure, determining the abnormal cause according to the process information corresponding to the structure layer information where the defect data is located comprises: determining the number of defects in the wafer that do not cause failed bits according to the defect data and the position data of the failed bits; determining the defect clearance rate of the wafer according to the ratio of the number of defects in the wafer that do not cause failed bits to the total number of defects in the defect data; evaluating the defect clearance rate of the wafer according to an empirical rule; and if the evaluation result is abnormal, determining that the step including the cleaning abnormal function in the process information is the abnormal cause.

[0015] According to an aspect of the present disclosure, a wafer defect tracing device is provided, which comprises: a defect data module configured to obtain defect data of a wafer; a failed bit data module configured to obtain position data of failed bits of the wafer; a defect area statistical module configured to determine defect areas of memory blocks in the wafer according to the defect data; a failed bit number module configured to determine the number of failed bits of memory blocks in the wafer according to the position data of the failed bits; a correlation coefficient module configured to process the defect areas and the number of failed bits of memory blocks in the wafer to obtain a correlation coefficient; and a defect tracing module configured to determine an abnormal cause of the failed bits of the wafer according to the correlation coefficient.

[0016] According to an aspect of the present disclosure, an electronic device is provided, which comprises: one or more processors; a storage device configured to store one or more programs; and when the one or more programs are executed by the one or more processors, the one or more processors implement the method as described above.

[0017] According to an aspect of the present disclosure, a computer readable medium is provided, which stores a computer program, and the program is executed by a processor to implement the method as described above.

[0018] According to the wafer defect tracing method and device, the electronic device and the computer readable medium provided by some embodiments of the present disclosure, the defect data of the wafer and the position data of the failed bits are used to establish a connection, a correlation coefficient representing the correlation between the defect data and the failed bits is obtained, and whether the defect data is the cause of the formation of the failed bits can be determined based on the correlation coefficient, which helps to determine the abnormal cause of the failed bits of the wafer based on the process data of the wafer, and helps to solve the abnormal problem as soon as possible and improve the yield of the wafer.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0020] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which like reference characters refer to like elements throughout. The following detailed description is presented primarily by way of example in relation to a number of embodiments thereof, as contemplated by the inventor. There is no intention that the application be limited to the embodiments disclosed since modifications can be made by those skilled in the art, with the benefit of the present disclosure, without departing from the scope of the application.

[0021] Figure 1 is a flowchart of a wafer defect traceability method according to an example embodiment.

[0022] Figure 2 is a schematic diagram of a wafer according to an example embodiment.

[0023] Figure 3 is a schematic diagram of a chip according to an example embodiment.

[0024] Figure 4 is a schematic diagram of a correlation analysis process according to an example embodiment.

[0025] Figure 5 is a flowchart of a wafer defect traceability method according to an example embodiment.

[0026] Figure 6 is a block diagram of a wafer defect traceability apparatus according to an example embodiment.

[0027] Figure 7 is a schematic diagram of a computer system suitable for use in implementing an electronic device in accordance with an embodiment of the application. DETAILED DESCRIPTION

[0028] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views.

[0029] Moreover, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

[0030] The block diagrams shown in the drawings are merely functional entities and do not necessarily have to correspond to physically independent entities. That is, the functional entities can be implemented in the form of software, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0031] The flowcharts shown in the drawings are merely exemplary illustrations and do not necessarily include all contents and operations / steps, nor necessarily executed in the described order. For example, some operations / steps can be further decomposed, and some operations / steps can be combined or partially combined, so the actual execution order can be changed according to actual situations.

[0032] It should be understood that although the terms first, second, third, etc. can be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first component discussed below can be called the second component without departing from the teachings of the present disclosure concept. As used herein, the term "and / or" includes all combinations of any one and one or more of the associated listed items.

[0033] Those skilled in the art can understand that the modules or flows in the drawings are not necessarily required for implementing the present disclosure, and therefore cannot be used to limit the protection scope of the present disclosure.

[0034] Figure 1 is a flowchart of a wafer defect tracing method according to an exemplary embodiment. The wafer defect tracing method provided by the embodiments of the present disclosure can be executed by any electronic device with computing processing capability, such as a user terminal and / or a server. In the following embodiments, the method is executed by a server as an example, but the present disclosure is not limited thereto. The wafer defect tracing method provided by the embodiments of the present disclosure can include steps S102 to S112.

[0035] As shown in Figure 1 In step S102, defect data of a wafer is acquired.

[0036] In the embodiments of the present disclosure, the defect data provides detailed data of the defect, which can include the number of defects, defect area data of the area occupied by the defect in the wafer, position information of the defect in the wafer, structure layer (Layer) information of the wafer where the defect data is located, etc.

[0037] Specifically, defect data can include: absolute location, relative location, area, type, and structural layer. Absolute location refers to the coordinate position relative to an entire wafer. Relative location refers to the coordinate position relative to an entire chip. Type is the category analyzed by a pattern recognition system. Structural layer refers to a specific layer within the wafer. Each layer may undergo one or more process steps. ADDR is used to record whether the defect is newly encountered; in other words, it does not exist in an older layer.

[0038] In step S104, the location data of the failure bits of the wafer are obtained.

[0039] In this embodiment of the disclosure, the location data of failure bits can be obtained through circuit probing (also called CP testing). Circuit probing is a process of probing each die on a wafer by attaching a probe made of gold wire, as fine as a hair, to the probe head and contacting the pads on the die to test its electrical characteristics. A failure bit is a defective cell obtained during the circuit probing process.

[0040] In step S106, the defect area of ​​the memory block in the wafer is determined based on the defect data.

[0041] In this embodiment of the disclosure, a wafer may include a plurality of chips. A chip's organizational structure includes a plurality of banks, each bank being divided into two equal-sized half-banks (different products may have different partitioning methods, some being divided into four banks). Each bank has a memory array containing multiple memory cells defined by bit line and word line intersections; one memory cell represents one bit. In this step, the memory bank within the wafer is used as the granularity of study. In other embodiments, a quarter of a bank may be used as the granularity of study; this disclosure does not impose any particular limitation on this.

[0042] Figure 2 This is a schematic diagram of a wafer according to an exemplary embodiment. Figure 2 As shown, one cell in wafer 20 is a chip 21. Figure 3 This is a schematic diagram of a chip according to an exemplary embodiment. (As shown) Figure 3 As shown, chip 21 may include several storage repositories 30, each of which may be divided into two storage blocks 31 of the same size, left and right.

[0043] In this embodiment of the present disclosure, the defect data corresponding to the location of the memory block can be determined based on the defect data, and the total area of ​​all defects in the memory block can be calculated as the defect area of ​​the memory block in the wafer.

[0044] In step S108, the number of failed bits of the memory block in the wafer is determined according to the position data of the failed bits.

[0045] In the embodiments of the present disclosure, the failed bit data corresponding to the position of the memory block can be determined according to the position data of the failed bits, and the number of all failed bits in the memory block is calculated as the number of failed bits of the memory block in the wafer.

[0046] In step S110, the defect area and the number of failed bits of the memory block in the wafer are processed to obtain the correlation coefficient.

[0047] One defect may or may not cause the generation of failed bits. Therefore, by processing the defect area and the number of failed bits of each memory block in the wafer, the correlation coefficient obtained can represent whether the defect has a causal relationship with the formation of failed bits.

[0048] In the embodiments of the present disclosure, the defect area and the number of failed bits of each memory block in the wafer can be counted and obtained, and the defect area and the number of failed bits of each memory block are taken as the horizontal and vertical coordinates respectively for correlation analysis to obtain the correlation coefficient.

[0049] In step S112, the abnormal reason of the failed bits of the wafer is determined according to the correlation coefficient.

[0050] In the embodiments of the present disclosure, the formation reason of the defect having a causal relationship can be determined through the correlation coefficient. The formation reason can be in the process in which the defect is formed.

[0051] According to the wafer defect tracing method provided in the embodiments of the present disclosure, the defect data of the wafer and the position data of the failed bits are used to establish a correlation, and a correlation coefficient representing the correlation between the defect data and the failed bits is obtained. The correlation coefficient can be used to determine whether the defect data is the formation reason of the failed bits, which helps to determine the abnormal reason causing the failed bits of the wafer based on the process data of the wafer, and helps to solve the abnormal problem as soon as possible and improve the yield of the wafer.

[0052] In the exemplary embodiments, in step S110, the defect affected region (DAR) of the wafer can be obtained according to the defect data; the defect area index of the memory block in the wafer is determined according to the ratio of the defect area of the memory block in the wafer to the area of the defect affected region; the failed bit index of the memory block in the wafer is determined according to the ratio of the number of failed bits of the memory block in the wafer to the area of the defect affected region; and the defect area index and the corresponding failed bit index of the memory block in the wafer are correlated to obtain the correlation coefficient.

[0053] In this embodiment, the defect area index and the failed bit index of each memory block in the wafer can be obtained statistically, and the defect area index and the failed bit index of each memory block are correlated as the horizontal and vertical coordinates respectively to obtain the correlation coefficient. In this embodiment, the defect area index and the failed bit index are correlated, which is more accurate than the correlation between the defect area index and the failed bit index in the embodiment shown in FIG. 2. Figure 1 The embodiment shown in FIG. 3 can make different wafers have the same scaling degree, and improve the observability of the correlation analysis.

[0054] In the example embodiment, when the defect area index and the corresponding failed bit index of the memory block in the wafer are correlated to obtain the correlation coefficient, the following steps can be included: removing the memory block containing abnormal data in the wafer to obtain a target memory block set; and correlating the defect area index and the corresponding failed bit index of the memory block in the target memory block set to obtain the correlation coefficient.

[0055] When removing the memory block containing abnormal data in the wafer, one or more of the following cases can be included: 1) removing the memory block in the wafer whose failed bit index is greater than a failed bit index threshold to obtain the target memory block set; and 2) removing the memory block in the wafer whose failed bit number is greater than a failed bit number threshold to obtain the target memory block set.

[0056] Figure 4 FIG. 4 is a schematic diagram of a correlation analysis process according to an example embodiment. As shown in FIG. 4, a failed bit index threshold τ is used to filter out a part of the Chip (such as the grid in FIG. 3) that often has too many failed bits in the process, and the failed bits in such Chip are not caused by the Defect directly. As shown in 211 in FIG. 3, removing such Chip helps to improve the accuracy of the correlation analysis. In general, the failed bit index threshold can satisfy the following condition: Figure 4 Figure 1 Figure 4 In this embodiment, the defect area index and the failed bit index of each memory block in the wafer can be obtained statistically, and the defect area index and the failed bit index of each memory block are correlated as the horizontal and vertical coordinates respectively to obtain the correlation coefficient. In this embodiment, the defect area index and the failed bit index are correlated, which is more accurate than the correlation between the defect area index and the failed bit index in the embodiment shown in FIG. 2.

[0057] ​​​Each chip (Chip) can be divided into multiple regions: A, B, C, D, E, in order from the outermost circle to the innermost circle, E region to A region. In general, in wafer manufacturing, the outer circle of the wafer is more likely to be damaged than the inner circle, and the main cause of such damage is not caused by Defect, so the data of the outer circle (for example, D, E) can be ignored for analysis, thereby increasing the accuracy of the correlation analysis.

[0058] In an example embodiment, in step S112, process data of the wafer can be acquired, the process data including structure layer information and process information corresponding to the structure layer information; when the correlation coefficient is greater than the correlation coefficient threshold, the structure layer information in which the defect data is located is determined; and the abnormal reason is determined according to the process information corresponding to the structure layer information in which the defect data is located.

[0059] When the correlation coefficient is greater than the correlation coefficient threshold, the structure layer information in which the defect data appears can be determined, and it can be traced back to which manufacturing steps the structure layer information has passed through, and one or several manufacturing steps with abnormalities can be locked in turn.

[0060] In an example embodiment, when the abnormal reason is determined according to the process information corresponding to the structure layer information in which the defect data is located, the following steps can be included: obtaining environmental data of the process information according to the process information corresponding to the structure layer information in which the defect data is located; and analyzing the environmental data of the process information to obtain the abnormal reason.

[0061] When an index representing micro-suspended particles in the air in the environmental data is higher than a preset threshold, the abnormal environment can be determined as the abnormal reason.

[0062] In an example embodiment, when the abnormal reason is determined according to the process information corresponding to the structure layer information in which the defect data is located, the following steps can be included: determining the number of defects in the wafer that do not cause the failed bit according to the defect data and the position data of the failed bit; determining the defect cleaned rate (DCR) of the wafer according to the ratio of the number of defects in the wafer that do not cause the failed bit to the total number of defects in the defect data; evaluating the defect cleaned rate of the wafer according to an empirical rule; and if the evaluation result is abnormal, determining that the step including the cleaning abnormal function in the process information is the abnormal reason.

[0063] Wherein, in the process of wafer, some steps have the function of removing defects. When these steps do not normally play the cleaning function (i.e. abnormal), it can cause defects and lead to the generation of fail bits. Defect removal rate DCR = (the number of defects without any fail bits in the defect coverage area / the total number of defects). The DCR in normal and abnormal states will change significantly, and by comparing the calculated DCR with the DCR in the normal state, it can be evaluated whether an abnormality occurs. If there is a significant change, the evaluation result is abnormal; if there is no significant change, the evaluation result is normal. Empirical rules show that 68% of the data will be distributed within the first standard deviation, 95% will fall within the second standard deviation, and 99.7% will fall within the first three standard deviations of the mean. The DCR falling within the first standard deviation can be determined as normal, and the DCR falling within the second and third standard deviations can be determined as abnormal.

[0064] It should be clearly understood that the present disclosure describes how to form and use specific examples, but the principles of the present disclosure are not limited to any details of these examples. On the contrary, based on the teachings of the disclosure disclosed in the present disclosure, these principles can be applied to many other embodiments.

[0065] Figure 5 is a flowchart of a wafer defect tracing method according to an exemplary embodiment.

[0066] As Figure 5 shown, the wafer defect tracing method of the embodiments of the present disclosure can include the following steps.

[0067] In step S502, the defect affected area is obtained from the source data.

[0068] Wherein, in the source data, the range data can be included, which is used to provide all fixed parameters, as follows:

[0069] (1) Defect may cause the range of fail bits (Defect Affected Regions, DAR);

[0070] (2) Start / End monitoring: Provide control parameters for starting and stopping monitoring;

[0071] (3) Threshold value, warning value: Provide parameters for correlation analysis, which can be set based on actual conditions.

[0072] Wafer group data: Provide all wafer batch numbers, serial numbers, various related dates, etc.

[0073] Defect Data: Provide detailed data of defect, including absolute position, relative position, area, type, Layer, ADDR, …, etc. Among them:

[0074] Absolute Position: Coordinate position based on wafer range;

[0075] Relative Position: Coordinate position based on chip range;

[0076] Type: Category analyzed by pattern recognition system;

[0077] Layer: Indicates a layer in the wafer. Each layer may be processed by one or more processes;

[0078] ADDR: Used to record whether the defect is a new defect. In other words, it does not exist in the older layer.

[0079] Failure bit position data: Provide failure bit (FB) position data obtained during CP test.

[0080] chip_region: Provide chip location area. Generally, chips in a wafer can be divided into A, B, C, D, E, etc.

[0081] In step S504, a wafer data (hereinafter referred to as new wafer data) that has been tested and not read by the process is obtained.

[0082] In step S506, a short time is rested, and the next process is continued.

[0083] In step S508, a new memory block position in the same wafer data is obtained.

[0084] In step S510, the defect data corresponding to the memory block position is obtained from the defect data, and the total area of all defects in the memory block (Defect Area, DA) is calculated.

[0085] In step S512, the failure bit data corresponding to the memory block position is obtained from the failure bit position data, and the number of failure bits in the memory block (FB Count, FBc) is calculated.

[0086] In step S514, DA and FBc of the memory block are stored as a data point in the analysis data.

[0087] Wherein each data_point represents a memory block information, including the corresponding memory block DA, FBc, location information, etc.

[0088] In step S516, if it is the last memory block (HB), step S518 is performed. Otherwise, S504 is performed.

[0089] In step S518, correlation analysis is performed.

[0090] In the embodiments of the present disclosure, the correlation analysis can be performed based on the analysis data, and the abnormal reason of the defect can be traced according to the obtained correlation coefficient. Figure 1 In step S110 of the embodiments, correlation analysis is performed, and the abnormal reason of the defect is traced according to the obtained correlation coefficient.

[0091] Those skilled in the art can understand that all or part of the steps of the above embodiments are implemented as computer programs executed by the CPU. When the computer program is executed by the CPU, the above functions defined by the method provided by the present disclosure are executed. The program can be stored in a computer readable storage medium, which can be a read-only memory, a disk or an optical disk, etc.

[0092] In addition, it should be noted that the above figures are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present disclosure, and are not for limiting purposes. It is easy to understand that the processes shown in the above figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be executed synchronously or asynchronously, for example, in multiple modules.

[0093] The following is an apparatus embodiment of the present disclosure, which can be used to execute the method embodiments of the present disclosure. For details not disclosed in the apparatus embodiments of the present disclosure, please refer to the method embodiments of the present disclosure.

[0094] Figure 6 is a block diagram of a wafer defect tracing device according to an exemplary embodiment. The wafer defect tracing device provided by the embodiments of the present disclosure can include a defect data module 602, a failed bit data module 604, a defect area statistics module 606, a failed bit number module 608, a correlation coefficient module 610 and a defect tracing module 612.

[0095] In the wafer defect tracing device, the defect data module 602 can be configured to obtain defect data of a wafer.

[0096] The failed bit data module 604 can be configured to obtain position data of failed bits of the wafer.

[0097] The defect area statistics module 606 is configured to determine a defect area of a memory block in the wafer according to the defect data.

[0098] The failed bit quantity module 608 can be configured to determine the failed bit quantity of the memory block in the wafer according to the position data of the failed bits.

[0099] The correlation coefficient module 610 can be configured to process the defective area and the failed bit quantity of the memory block in the wafer to obtain a correlation coefficient.

[0100] The defect tracing module 612 can be configured to determine the abnormal reason of the failed bits of the wafer according to the correlation coefficient.

[0101] The wafer defect tracing device provided by the embodiments of the present disclosure establishes a correlation between the defect data and the position data of the failed bits of the wafer, obtains a correlation coefficient representing the correlation between the defect data and the failed bits, and determines whether the defect data is the forming reason of the failed bits based on the correlation coefficient, which helps to determine the abnormal reason of the failed bits of the wafer based on the process data of the wafer, helps to solve the abnormal problem as soon as possible, and improves the yield of the wafer.

[0102] Reference will be made to the following description Figure 7 which shows a structural schematic diagram of a computer system 700 of an electronic device suitable for implementing embodiments of the present disclosure. Figure 7 The computer system 700 of the electronic device shown is only an example and should not impose any limitation on the functions and use range of the embodiments of the present disclosure.

[0103] As shown in Figure 7 , the computer system 700 includes a central processing unit (CPU) 701 which can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 702 or programs loaded into a random access memory (RAM) 703 from a storage portion 708. Various programs and data required for system operation are also stored in the RAM 703. The CPU 701, the ROM 702, and the RAM 703 are connected to each other through a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0104] The following components are connected to the I / O interface 705: an input portion 706 including a keyboard, a mouse, and the like; an output portion 707 including a cathode ray tube (CRT), a liquid crystal display (LCD), and the like, and a speaker, and the like; a storage portion 708 including a hard disk, and the like; and a communication portion 709 including a network interface card such as a LAN card, a modem, and the like. The communication portion 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the I / O interface 708 as necessary. A removable medium 711 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, and the like is mounted on the drive 710 as necessary, so that a computer program read therefrom is installed in the storage portion 708 as necessary.

[0105] In particular, the processes described above with reference to the flowcharts can be implemented as a computer software program in accordance with embodiments of the present application. For example, embodiments of the present application include a computer program product comprising a computer program carried on a computer readable storage medium, the computer program comprising program code for performing the methods illustrated by the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via the communications section 709 and / or installed from the removable media 711. When the computer program is executed by the central processing unit (CPU) 701, the above-described functions defined in the system of the present application are performed.

[0106] It should be noted that the computer readable storage medium shown in the present application can be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus. In the present application, the computer readable signal medium can include a data signal carried in a baseband or as a carrier wave in a propagated data signal, which carries computer readable program code. Such a propagated data signal can take many forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination of the above. The computer readable signal medium can also be any computer readable storage medium other than the computer readable storage medium that can send, propagate or transfer a program for use by or in connection with an instruction execution system, device or apparatus. The program code contained on the computer readable storage medium can be transmitted by any suitable medium, including but not limited to wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0107] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0108] The units described in the embodiments of the present invention can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0109] In another aspect, this application also provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The computer-readable storage medium carries one or more programs that, when executed by the electronic device, cause the electronic device to implement the wafer fabrication process detection method as described in the above embodiments.

[0110] For example, the electronic device described above can achieve the following: Figure 1 As shown: Step S102, acquire wafer defect data. Step S104, acquire wafer failure bit location data. Step S106, determine the defect area of ​​the memory block in the wafer based on the defect data. Step S108, determine the number of failure bits in the memory block in the wafer based on the failure bit location data. Step S110, process the defect area and number of failure bits in the memory block in the wafer to obtain a correlation coefficient. Step S112, determine the cause of the failure of the wafer based on the correlation coefficient.

[0111] For example, the aforementioned electronic device can also achieve the following: Figure 5 The steps shown.

[0112] It should be noted that, although several modules or units for a device for action execution are mentioned in the above detailed description, such a division is not mandatory. Indeed, according to an embodiment of the application, the features and functionalities of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functionalities of one module or unit described above can be further divided into several modules or units embodied.

[0113] Those skilled in the art can easily understand that the example embodiments described herein can be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solutions according to the embodiments of the present application can be embodied in the form of a software product. The software product can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash disk, a mobile hard disk, etc.) or a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) to perform the methods according to the embodiments of the present application.

[0114] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the present application cover any and all variations of the application that come within the scope of the claims and their equivalents. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0115] It should be understood that the application is not limited to the precise construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application should be limited only by the appended claims.

Claims

1. A method for tracing the origin of wafer defects, characterized in that, The method comprises: obtaining defect data of a wafer; obtaining position data of failed bits of the wafer; determining defect areas of memory blocks in the wafer according to the defect data; determining the number of failed bits of memory blocks in the wafer according to the position data of the failed bits; processing the defect areas and the number of failed bits of memory blocks in the wafer to obtain a correlation coefficient; determining an abnormal reason of the failed bits of the wafer according to the correlation coefficient; wherein the processing of the defect areas and the number of failed bits of memory blocks in the wafer to obtain a correlation coefficient comprises: obtaining a defect influence area of the wafer according to the defect data; determining a defect area index of memory blocks in the wafer according to a ratio of the defect areas of memory blocks to the area of the defect influence area; determining a failed bit index of memory blocks in the wafer according to a ratio of the number of failed bits of memory blocks to the area of the defect influence area; performing correlation analysis on the defect area index and the corresponding failed bit index of memory blocks in the wafer to obtain the correlation coefficient.

2. The method of claim 1, wherein, The correlation analysis on the defect area index and the corresponding failed bit index of memory blocks in the wafer to obtain the correlation coefficient comprises: eliminating memory blocks containing abnormal data in the wafer to obtain a target memory block set; performing correlation analysis on the defect area index and the corresponding failed bit index of memory blocks in the target memory block set to obtain the correlation coefficient.

3. The method of claim 2, wherein, The elimination of memory blocks containing abnormal data in the wafer to obtain a target memory block set comprises one or more of the following cases: eliminating memory blocks in the wafer with a failed bit index greater than a failed bit index threshold to obtain the target memory block set; eliminating memory blocks in the wafer with a number of failed bits greater than a failed bit number threshold to obtain the target memory block set.

4. The method of claim 1, wherein, The determination of an abnormal reason of the failed bits of the wafer according to the correlation coefficient comprises: obtaining process data of the wafer, the process data comprising structure layer information and process information corresponding to the structure layer information; if the correlation coefficient is greater than a correlation coefficient threshold, determining the structure layer information where the defect data is located; determining the abnormal reason according to the process information corresponding to the structure layer information where the defect data is located.

5. The method of claim 4, wherein, The determination of the abnormal reason according to the process information corresponding to the structure layer information where the defect data is located comprises: obtaining environmental data of the process information according to the process information corresponding to the structure layer information where the defect data is located; analyzing the environmental data of the process information to obtain the abnormal reason.

6. The method of claim 4, wherein, The determination of the abnormal reason according to the process information corresponding to the structure layer information where the defect data is located comprises: determining the number of defects in the wafer that do not cause failed bits according to the defect data and the position data of the failed bits; determining a defect clearance rate of the wafer according to a ratio of the number of defects in the wafer that do not cause failed bits to the total number of defects in the defect data; evaluating the defect clearance rate of the wafer according to an empirical rule; If the evaluation result is abnormal, a step including a cleaning abnormal function in the process information is determined as the abnormal cause.

7. A wafer defect tracing device, characterized in that, The method comprises the steps of: acquiring defect data of a wafer; obtaining position data of a failed bit of the wafer; determining a defect area of a memory block in the wafer according to the defect data; determining a failed bit number of the memory block in the wafer according to the position data of the failed bit; processing the defect area and the failed bit number of the memory block in the wafer to obtain a correlation coefficient; determining an abnormal cause of the failed bit of the wafer according to the correlation coefficient; wherein the processing of the defect area and the failed bit number of the memory block in the wafer to obtain the correlation coefficient comprises: obtaining a defect influence area of the wafer according to the defect data; determining a defect area index of the memory block in the wafer according to a ratio of the defect area of the memory block in the wafer to an area of the defect influence area; determining a failed bit index of the memory block in the wafer according to a ratio of the failed bit number of the memory block in the wafer to the area of the defect influence area; performing correlation analysis on the defect area index and the corresponding failed bit index of the memory block in the wafer to obtain the correlation coefficient.

8. An electronic device, comprising: The method comprises the steps of: one or more processors; a storage device for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1-6.

9. A computer readable medium having stored thereon a computer program, characterized in that, The program is executed by the processor to implement the method according to any one of claims 1-6.

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