Configuration method and reading method of 3D memory and 3D memory

Abstract

The present disclosure provides a configuration method, a reading method and a 3D memory. The configuration method comprises writing data in a plurality of selected memory cells corresponding to a selected word line, measuring threshold voltages of the selected memory cells to obtain a relationship table, and writing the relationship table into a configuration block. The reading method comprises obtaining a data reading request to determine a memory block where data to be read is located, reading a selected word line thereof to obtain a number of memory cells corresponding to the selected word line and having threshold voltages less than a first predetermined voltage, searching the relationship table in the configuration block to obtain a turn-on voltage corresponding thereto, applying the turn-on voltage on a non-reading word line, and applying a reading voltage on a reading word line to obtain the data to be read. The 3D memory using the configuration method and the reading method can dynamically reduce the turn-on voltage of the memory cells to reduce read disturbance caused by the read operation.

Description

[0001] This application is a divisional application of the patent filed on January 15, 2021, with application number 202110054084.7, entitled "Configuration Method and Reading Method of 3D Memory and 3D Memory". Technical Field

[0002] This disclosure relates to the field of storage technology, and in particular to a method for configuring a 3D memory, a method for reading a 3D memory, and a 3D memory itself. Background Technology

[0003] The increase in storage density of memory devices is closely related to advancements in semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes shrinks, the storage density of memory devices increases. To further improve storage density, three-dimensional memory devices (i.e., 3D memory devices) have been developed. 3D memory devices consist of multiple memory cells stacked along a vertical direction, which can multiply the integration density on a unit area of ​​wafer and reduce costs.

[0004] 3D memory devices are primarily used as non-volatile flash memory. The two main non-volatile flash memory technologies employ NAND and NOR structures, respectively. Compared to NOR memory devices, NAND memory devices have slightly slower read speeds but faster write speeds, simpler erase operations, and can achieve smaller storage cells, thus enabling higher storage density. Therefore, 3D memory devices using the NAND structure have gained widespread application.

[0005] In one example of a 3D memory device, multiple memory cell strings are arranged in a two-dimensional array. Each memory cell string is connected between a source line and a bit line and includes multiple memory cells stacked vertically. Thus, the multiple memory cell strings together form multiple memory cells arranged in a three-dimensional array. Each memory cell includes a gate conductor, a channel region, and a tunneling dielectric layer, a charge storage layer, and a barrier dielectric layer sandwiched between them. A read method is used to read data in selected memory cells. The memory cell string includes multiple memory cells sharing a common channel pillar. During the read operation, a read voltage is applied not only to the gate conductor of the selected memory cell to read the data in the memory cell, but also a forward voltage is applied to the gate conductor of the unselected memory cells to suppress the read operation. The forward voltage applied to the gate conductor of the memory transistor causes the threshold voltage in the memory transistor to drift towards a higher voltage direction, making it more error-prone when reading data in the memory block and reducing the reliability of data read.

[0006] In 3D memory devices, reducing the on-state voltage can suppress read interference to unselected memory transistors. Due to charge leakage, the highest-state threshold voltage in the memory transistors drifts towards lower voltages, and the on-state voltage can also be reduced accordingly. Therefore, dynamically reducing the on-state voltage of the memory cells is desirable to minimize read interference to unselected memory transistors. Summary of the Invention

[0007] In view of the above problems, this disclosure provides a configuration method, a reading method, and a 3D memory, which dynamically reduces the on-state voltage of the memory cell to reduce read interference caused by read operations and increase the reliability of data storage.

[0008] According to one aspect of this disclosure, a method for configuring a 3D memory is provided, the 3D memory including a plurality of memory blocks, the configuration method including: writing data into a plurality of selected memory cells corresponding to selected word lines in one of the plurality of memory blocks;

[0009] Measure the threshold voltage of the plurality of selected memory cells;

[0010] Obtain a relationship table, which represents the correspondence between the number of memory cells with a threshold voltage less than a first predetermined voltage among the plurality of selected memory cells and the turn-on voltage required to perform a read operation on a certain memory block.

[0011] Optionally, the 3D memory includes a configuration block, and the configuration method further includes writing the relationship table into the configuration block.

[0012] Optionally, the data written in the plurality of selected storage units is known data; the known data means that both the stored data and the threshold voltage distribution corresponding to the stored data are known.

[0013] Optionally, obtaining the relationship table includes: repeatedly writing the data and measuring the threshold voltage of the plurality of selected storage cells to obtain the relationship table.

[0014] Optionally, writing data into a plurality of selected memory cells corresponding to a selected word line in one of the plurality of memory blocks includes: applying a programming voltage to the selected word line; and applying a low voltage VPS1 to an unselected word line in the plurality of memory blocks.

[0015] Optionally, the configuration block stores one or more of the relationship tables of the storage blocks.

[0016] Optionally, in the relation table, the more memory cells among the plurality of selected memory cells whose threshold voltage is less than a first predetermined voltage, the smaller the corresponding turn-on voltage.

[0017] Optionally, the on-state voltage is greater than the highest state threshold of the memory cell, and the difference between the on-state voltage and the highest state threshold of the memory cell is equal to a second predetermined voltage.

[0018] According to another aspect of this disclosure, a method for reading a 3D memory is provided, the 3D memory including a plurality of storage blocks, the method comprising: acquiring a data read request, the data read request including the address of data to be read;

[0019] The storage block containing the data to be read is determined based on the address of the data to be read; the storage block belongs to any one of the plurality of storage blocks.

[0020] Read the selected word line of the memory block to obtain the number of memory cells whose threshold voltage is less than a first predetermined voltage among a plurality of selected memory cells corresponding to the selected word line;

[0021] Look up the relation table to obtain the turn-on voltage required to perform a read operation on the memory block, corresponding to the number of memory cells whose threshold voltage is less than a first predetermined voltage among the plurality of selected memory cells;

[0022] The conduction voltage is applied to the non-read word line, and the read voltage is applied to the read word line to obtain the data to be read;

[0023] The relationship table is used to represent the correspondence between the number of selected memory cells whose threshold voltage is less than a first predetermined voltage and the conduction voltage.

[0024] Optionally, the 3D memory further includes a configuration block, in which the relation table is stored.

[0025] Optionally, the relation table is obtained by the configuration method of the 3D memory according to any one of claims 1 to 8.

[0026] Optionally, the step of reading a selected word line of the memory block to obtain the number of memory cells among a plurality of selected memory cells corresponding to the selected word line whose threshold voltage is less than a first predetermined voltage includes:

[0027] The first predetermined voltage is applied to the selected word line to detect the threshold voltage of each of the plurality of selected memory cells corresponding to the selected word line. If the threshold voltage of a selected memory cell is less than the first predetermined voltage, the selected memory cell is determined to be a memory cell with a threshold voltage less than the first predetermined voltage, so as to obtain the number of memory cells with a threshold voltage less than the first predetermined voltage among the plurality of selected memory cells.

[0028] Optionally, the configuration block stores one or more of the relationship tables of the storage blocks.

[0029] Optionally, the turn-on voltage is less than or equal to the initial turn-on voltage of the memory block.

[0030] Optionally, in the relationship table, the more storage cells with voltages less than the first predetermined voltage, the smaller the corresponding on-state voltage.

[0031] Optionally, the on-state voltage is greater than the highest state threshold of the memory cell, and the difference between the on-state voltage and the highest state threshold of the memory cell is equal to a second predetermined voltage.

[0032] According to a third aspect of this disclosure, a 3D memory is provided, the 3D memory comprising:

[0033] A storage array, the storage array comprising multiple storage blocks;

[0034] and control circuitry connected via a storage interface; among which,

[0035] The control circuit is configured to: write data into a plurality of selected memory cells corresponding to a selected word line in one of the plurality of memory blocks; measure the threshold voltage of the plurality of selected memory cells; and obtain a relationship table, the relationship table representing the correspondence between the number of memory cells in the plurality of selected memory cells whose threshold voltage is less than a first predetermined voltage and the turn-on voltage required to perform a read operation on the plurality of memory blocks.

[0036] Optionally, the storage array further includes a configuration block, and the control circuit is further configured to write the relationship table into the configuration block.

[0037] Optionally, the control circuit is further configured to:

[0038] Obtain a data read request, wherein the data read request includes the address of the data to be read;

[0039] Based on the address of the data to be read, the storage block where the data to be read is located is determined; the storage block belongs to one of the plurality of storage blocks;

[0040] Read the selected word line of the memory block to obtain the number of memory cells whose threshold voltage is less than a first predetermined voltage among a plurality of selected memory cells corresponding to the selected word line;

[0041] The relationship table is searched to obtain the turn-on voltage required to perform a read operation on the memory block, corresponding to the number of memory cells whose threshold voltage is less than a first predetermined voltage among the plurality of selected memory cells;

[0042] The conduction voltage is applied to the non-read word line, and the read voltage is applied to the read word line to obtain the data to be read.

[0043] Optionally, the turn-on voltage is less than or equal to the initial turn-on voltage of the memory block.

[0044] Optionally, the control circuit includes: a processor for implementing access requests to the storage array and managing data in the storage array; and a cache connected to the processor for caching data waiting to be written to the storage array or caching data read from the storage array.

[0045] The 3D memory configuration method, reading method, and 3D memory disclosed herein dynamically adjust the on-state voltage based on the number of reads of the memory block and the threshold distribution of the memory cell. Under the premise of ensuring that the on-state voltage is greater than the highest state threshold voltage, the on-state voltage is dynamically reduced, thereby reducing read interference caused by reading operations on the memory block, increasing the reliability of data storage, and thus improving the overall read performance of the 3D memory.

[0046] Furthermore, the configuration method, reading method, and 3D memory provided in this disclosure store a relationship table in advance in the configuration block of the storage array. The relationship table records the relationship between the number of storage cells with voltages lower than a first predetermined voltage and the corresponding turn-on voltage. In the reading method, the control circuit quickly selects the corresponding turn-on voltage from the relationship table based on the number of storage cells with voltages lower than the first predetermined voltage detected on the selected word line. This eliminates the need for the user to manually adjust the turn-on voltage, making it more convenient. At the same time, it eliminates the need to open the interface for adjusting the turn-on voltage, ensuring the safety and stability of the 3D memory.

[0047] Furthermore, the conduction voltage of each memory block in the 3D memory is adjusted independently. The control circuit adjusts the conduction voltage of the corresponding memory block independently according to the number of memory cells on the selected word line with a voltage lower than the first predetermined voltage in different memory blocks. The conduction voltage of memory blocks with more reads is relatively low, and the conduction voltage of memory blocks with fewer reads is relatively high. It is not necessary to unify the conduction voltage of each memory block to a high potential, which further improves the overall performance of the 3D memory. Attached Figure Description

[0048] The above and other objects, features and advantages of this disclosure will become clearer from the following description of the disclosure with reference to the accompanying drawings, in which:

[0049] Figure 1a and 1b The circuit diagram and structural schematic diagram of the storage cell string of the 3D storage device are shown respectively.

[0050] Figure 2 A perspective view of a 3D storage device is shown.

[0051] Figure 3 The circuit diagram of the storage block of the 3D memory is shown.

[0052] Figure 4 It shows Figure 3 A schematic diagram of the structure when a conduction voltage is applied to the control gate of a memory cell.

[0053] Figure 5 It shows Figure 4 Threshold distribution diagram of the storage cells.

[0054] Figure 6 A schematic diagram showing the relationship between the turn-on voltage and the read interference offset voltage is presented.

[0055] Figure 7 It shows Figure 3 A schematic diagram of the structure of a memory cell when no voltage is applied to the control gate.

[0056] Figure 8 It shows Figure 7 Threshold distribution diagram of the storage cells.

[0057] Figure 9 A method for configuring a 3D memory provided in this disclosure is shown.

[0058] Figure 10 A simplified schematic diagram showing the relationship between the number of memory cells with a voltage lower than the fixed read voltage and the on-state voltage is shown.

[0059] Figure 11 A method for reading 3D memory provided in this disclosure is shown.

[0060] Figure 12 A schematic diagram of the threshold distribution for memory cells corresponding to selected word lines is shown.

[0061] Figure 13 The 3D memory provided in this disclosure is shown. Detailed Implementation

[0062] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0063] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0064] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0065] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0066] Figure 1a and 1b The circuit diagram and structural schematic diagram of the storage cell string of the 3D memory are shown respectively. In this embodiment, the storage cell string shown includes four storage cells. It is understood that this disclosure is not limited thereto, and the number of storage cells in the storage cell string can be any number, for example, 32 or 64.

[0067] like Figure 1aAs shown, the first end of the memory cell string 100 is connected to the bit line BL, and the second end is connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between the first and second ends, including: a first selection transistor Q1, storage transistors M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the string select line SSL, and the gate of the second selection transistor Q2 is connected to the ground select line GSL. The gates of the storage transistors M1 to M4 are respectively connected to the corresponding word lines WL1 to WL4.

[0068] like Figure 1b As shown, the first selection transistor Q1 and the second selection transistor Q2 of the memory cell string 100 each include gate conductors 122 and 123, and the memory transistors M1 to M4 each include a gate conductor 121. The gate conductors 121, 122, and 123 are arranged in the same stacking order as the transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 extends through the gate stack structure. In the middle portion of the channel pillar 110, a tunneling dielectric layer 112, a charge storage layer 113, and a barrier dielectric layer 114 are sandwiched between the gate conductor 121 and the channel region 111, thereby forming memory transistors M1 to M4. At both ends of the channel pillar 110, the gate conductors 122 and 123 are sandwiched between the gate conductors 122 and 123 and the channel region 111, thereby forming the first selection transistor Q1 and the second selection transistor Q2.

[0069] In this embodiment, the channel region 111 is composed, for example, of doped polysilicon; the tunneling dielectric layer 112 and the barrier dielectric layer 114 are each composed of oxides, such as silicon oxide; the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, such as silicon nitride containing metal or semiconductor particles; and the gate conductors 121, 122, and 123 are composed of metals, such as tungsten. The channel region 111 serves as the channel region for the select transistor and the storage transistor, and the doping type of the channel region 111 is the same as the type of the select transistor and the storage transistor. For example, for an N-type select transistor and a storage transistor, the channel region 111 can be N-type doped polysilicon.

[0070] In this embodiment, the core of the channel post 110 is a channel region 111, and the tunneling dielectric layer 112, the charge storage layer 113, and the barrier dielectric layer 114 form a stacked structure surrounding the sidewall of the core. In an alternative embodiment, the core of the channel post 110 is an additional insulating layer, and the channel region 111, the tunneling dielectric layer 112, the charge storage layer 113, and the barrier dielectric layer 114 form a stacked structure surrounding the core.

[0071] In this embodiment, the first selection transistor Q1 and the second selection transistor Q2, and the storage transistors M1 to M4 use a common channel region 111 and a barrier dielectric layer 114. In the channel pillar 110, the channel region 111 provides the source / drain regions and channel regions for the plurality of transistors. In an alternative embodiment, the semiconductor layers and barrier dielectric layers of the first selection transistor Q1 and the second selection transistor Q2, as well as the semiconductor layers and barrier dielectric layers of the storage transistors M1 to M4, can be formed in separate steps.

[0072] Figure 2 A perspective view of the 3D memory is shown. For clarity, in... Figure 2 The individual insulating layers in the 3D memory are not shown.

[0073] The 3D memory 200 shown in this embodiment includes 16 4x4 memory cell strings 100, each containing 4 memory cells, thus forming a 4x4x4 memory array with a total of 64 memory cells. It is understood that this disclosure is not limited thereto; the 3D memory may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

[0074] In the 3D memory 200, each memory cell string includes its own channel pillar 110 and a common gate conductor 121, 122, and 123. The gate conductors 121, 122, and 123 are arranged in the same order as the transistors in the memory cell string 100. Adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the figure.

[0075] The internal structure of the channel column 110 is as follows Figure 1b As shown, no further details will be provided here. The channel pillars 110 penetrate the gate stack structure 120 and are arranged in an array. The first ends of multiple channel pillars 110 in the same column are connected to the same bit line (i.e., one of bit lines BL1 to BL4), and the second ends are connected to the substrate 101. The second ends form a common source connection through the substrate 100.

[0076] The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit 102. The gate lines of multiple channel pillars 110 in the same row are connected to the same series select line (i.e., one of the series select lines SSL1 to SSL4).

[0077] The gate conductors 121 of storage transistors M1 and M4 are respectively connected to the corresponding word lines. If the gate conductors 121 of storage transistors M1 and M4 are divided into different gate lines by gate line gaps 161, the gate lines on the same layer reach the interconnect layer 132 through their respective conductive channels 131, thereby interconnecting with each other, and then connected to the same word line (i.e., one of word lines WL1 to WL4) through conductive channels 133.

[0078] The gate conductors of the second selection transistor Q2 are connected as one. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line gap 161, the gate lines reach the interconnect layer 132 through their respective conductive channels 131, thereby interconnecting with each other, and then connected to the same ground selection line GSL through the conductive channel 133.

[0079] Figure 3 A circuit diagram of a storage block of a 3D memory is shown. In this embodiment, the storage block 300 shown includes three storage cell strings 100. It is understood that this disclosure is not limited thereto, and the number of storage cell strings 100 in the storage block 300 can be any number.

[0080] like Figure 3 As shown, the memory block 300 includes three memory cell strings 100. The first end of each memory cell string 100 is connected to bit lines BL1, BL2, and BL3, respectively, and the second end is connected to the source line SL. The gates of first selection transistors Q1, Q3, and Q5 are connected to the first selection line SSL, and the gates of second selection transistors Q2, Q4, and Q6 are connected to the second selection line GSL. The gates of memory cells M1 to M12 are connected to the corresponding word lines WL1 to WL4, respectively.

[0081] During a write operation, memory block 300 utilizes FN tunneling efficiency to write data to selected memory cells M1 to M12. Taking memory cell M2 as an example, while the source line SL is grounded, the second gate selective line GSL is biased to approximately zero volts, causing the second select transistor Q2 corresponding to the second gate selective line GSL to turn off, and the first source selective line SSL is biased to a high voltage VDD, causing the first select transistor Q1 corresponding to the first selective line SSL to turn on. Further, the bit line BL1 is grounded, the word line WL2 is biased to the programming voltage VPG, for example, around 20V, and the remaining word lines are biased to a low voltage VPS1.

[0082] During a read operation, memory block 300 determines the amount of charge in the floating gate based on the conduction state of selected memory cells M1 to M12, thereby obtaining the data represented by that charge amount. Taking memory cell M2 as an example, word line WL2 is biased at the read voltage Vread, while the other word lines are biased at the conduction voltage Vpass. The conduction state of memory cell M2 is related to its threshold voltage, i.e., related to the amount of charge in the floating gate, thus the data value can be determined based on the conduction state of memory cell M2. Memory cells M1, M3, and M4 are always in the conduction state; therefore, the conduction state of memory block 300 depends on the conduction state of memory cell M2. The control circuit determines the conduction state of memory cell M2 based on the electrical signals detected on bit line BL1 and source line SL, thereby obtaining the data stored in memory cell M2.

[0083] Figure 4 It shows Figure 3 A schematic diagram of the structure of a memory cell when a conduction voltage is applied to the control gate. The memory cell M1 includes a control gate 410, a first insulating layer 420, a floating gate 430, a second insulating layer 440, a substrate 450, and a source 460 and a drain 470 formed on the substrate 450.

[0084] The first insulating layer 420 is selected, for example, from a polycrystalline silicon oxide layer, and the second insulating layer 440 is selected, for example, from a tunnel oxide layer.

[0085] See Figure 3 WL2 is the read word line, and the gates of memory cells M2, M6, and M10 are subjected to a read voltage Vread. WL1, WL3, and WL4 are non-read word lines, and the gate of memory cell M1 is subjected to a pass voltage Vpass.

[0086] The gate voltage of memory cell M1 is the turn-on voltage Vpass. The selection of Vpass depends on the highest state threshold of the data write operation and must be higher than that threshold. Typically, it needs to be higher than the highest state threshold by a second predetermined voltage V1 to ensure the conduction of memory cells not containing read word lines. The turn-on voltage Vpass creates a strong electric field between the floating gate 430 and the substrate 450, causing current to flow from the floating gate 430 to the substrate 450, meaning the floating gate 430 absorbs some electrons. As the number of read operations of the memory block 300 increases, the number of electrons absorbed by the floating gate 430 also increases, resulting in a rightward shift of the threshold voltage of memory cell M1.

[0087] See Figure 5 , Figure 5 It shows Figure 4A schematic diagram of the threshold distribution of the storage cells is shown. This embodiment illustrates the case where the storage cells are MLC (Multi-Level Cell). It is understood that this disclosure is not limited to this; the storage cells can also be selected from SLC (Single-Level Cell), TLC (Triple-Level Cell), and QLC (Quad-Level Cell). In a 3D memory that stores n bits of data in each storage cell, there are a total of 2 storage cells. n There are several different threshold states.

[0088] Each memory cell M1 stores two bits of data, with four states. These four states are distinguished by injecting different amounts of charge into the floating gate 430 of the memory cell. To turn on the memory cell, a control voltage greater than the cell's threshold voltage must be applied to the gate. For memory cell M1, injecting different numbers of electrons into the floating gate 330 will change the threshold voltage of memory cell M1. Since different states have different threshold voltages, the current data in the memory cell can be determined by applying different read voltages Vread to the control gate.

[0089] As the number of reads on word line WL2 of this block increases, more and more electrons enter the floating gate of memory cell M1 in non-read word line WL1, causing a change in its data state. The threshold voltage of memory cell M1 shifts to the right. Taking the threshold voltage representing data 11 as an example: the threshold voltage shifts to the right (the dashed line represents the threshold voltage of data 11 after the shift), and the shift amount is Vshift. Part of this shift value is greater than the reference voltage Vref1. Therefore, when reading data on word line WL1, misjudgment may occur, leading to the reading of incorrect data. This situation is called read interference. The shift amount Vshift is positively correlated with the on-state voltage Vpass and the number of reads of memory block 300.

[0090] Figure 6 The relationship between the turn-on voltage and read interference offset is shown. With a fixed number of reads, a higher turn-on voltage (Vpass) results in a greater offset (Vshift) of the threshold voltage due to read interference.

[0091] Figure 7 It shows Figure 3 A schematic diagram of the structure of a memory cell when no voltage is applied to the control gate. The memory cell M1 includes a control gate 410, a first insulating layer 420, a floating gate 430, a second insulating layer 440, a substrate 450, and a source 460 and a drain 470 formed on the substrate 450.

[0092] When no voltage is applied to the gate, an intrinsic electric field is generated, and current flows from the substrate 450 to the floating gate 430. That is, electrons will leak from the floating gate 430, which causes the threshold voltage to drift to the left.

[0093] See Figure 8 , Figure 8 It shows Figure 7 The threshold distribution diagram of the memory cell. Taking the threshold representing data 00 as an example: due to the existence of the intrinsic electric field, the charge stored in the floating gate will leak, and the threshold voltage representing data 00 will drift to the left (the dashed line represents the threshold voltage representing data 00 after the drift). This allows the use of a lower turn-on voltage Vpass'. While ensuring that the turn-on voltage Vpass' is higher than the highest state threshold voltage by a second predetermined voltage V1, and that data reading is not affected, read interference can be effectively reduced.

[0094] Figure 9 A method for configuring the 3D memory provided in this disclosure is illustrated. The 3D memory includes multiple storage blocks and a configuration block, see also [link to relevant documentation]. Figure 3 .

[0095] In step S10, data is written to the selected memory cell corresponding to the selected word line. Word line WLn in memory block 300 is selected as the selected word line, for example, word line WL2 is selected as the selected word line. When writing data to memory block 300, the data is written to the memory cell on the selected word line WL2. A programming voltage is applied to the gates of the multiple selected memory cells in memory block 300, and an on-state voltage is applied to the gates of the multiple unselected memory cells in memory block 300. The data written to the selected word line WL2 is both stored data and data with a known threshold distribution corresponding to the stored data.

[0096] In step S20, the threshold voltage of the selected memory cell is measured.

[0097] In step S30, a relationship table is obtained. The relationship table represents the correspondence between the number of memory cells among the plurality of selected memory cells whose threshold voltage is less than a first predetermined voltage and the conduction voltage.

[0098] Figure 10 A simplified diagram showing the relationship between the number of memory cells with voltages lower than the fixed read voltage and the turn-on voltage is provided. The more memory cells with voltages lower than the first predetermined voltage Vfix in the memory cells corresponding to the selected word line WL2, the smaller the turn-on voltage Vpass-n required for the read operation of memory block 300.

[0099] In step S40, the relationship table is written to the configuration block. The relationship table obtained in step S30 is written to the configuration block, where the configuration block is a storage block used to store various configuration information, including the relationship table.

[0100] The configuration method of the 3D memory provided in this disclosure obtains a relation table by writing a large amount of data and stores the relation table in the configuration block. In the subsequent reading method, the corresponding turn-on voltage is quickly selected according to the number of memory cells on the selected word line that are less than the first predetermined voltage. This eliminates the need for manual adjustment by the user, making it more convenient. At the same time, it eliminates the need to open the interface for adjusting the turn-on voltage, thus ensuring the safety and stability of the 3D memory.

[0101] Figure 11 A method for reading a 3D memory provided in this disclosure is illustrated. The 3D memory includes multiple storage blocks and a configuration block, see also... Figure 3 .

[0102] In step S10, a data read request is obtained, and the storage block where the data to be read is located is determined. The data read request includes the address of the data to be read, and the storage block where the data to be read is located is determined based on the address of the data to be read.

[0103] In step S20, the selected word line WLn of the memory block is read to obtain the number of memory cells whose threshold voltage is less than a first predetermined voltage among the multiple selected memory cells corresponding to the selected word line. For example, if the selected word line is WL2, the first predetermined voltage Vfix is ​​applied to the selected word line WL2, and the threshold distribution in the memory cells M2, M6, and M10 corresponding to the selected word line WL2 is detected. If the threshold voltage of a certain memory cell is partially or completely less than the first predetermined voltage Vfix, it is determined that the memory cell is less than the first predetermined voltage Vfix, thereby obtaining the number of memory cells in the memory cells corresponding to the selected word line WL2 whose threshold voltage is less than the first predetermined voltage Vfix.

[0104] like Figure 12 As shown, Figure 12 A schematic diagram of the threshold distribution of memory cells corresponding to a selected word line is shown. If the threshold voltage portions of memory cells M2 and M6 are less than a first predetermined voltage Vfix, then the number of memory cells corresponding to the selected word line WL2 with threshold voltages less than the first predetermined voltage Vfix is ​​2.

[0105] In step S30, the relationship table in the configuration block is searched.

[0106] In step S40, the turn-on voltage required for the current memory block read operation is quickly selected. Based on the number of memory cells with threshold voltages less than the first predetermined voltage among the multiple selected memory cells corresponding to the selected word line WL2 obtained in step S20, and the relationship table read in step S30, the corresponding turn-on voltage Vpass-n is quickly selected. This turn-on voltage Vpass-n is the turn-on voltage required for the memory block 300 read operation.

[0107] In step S50, a read voltage Vread is applied to the read word lines and an on-state voltage Vpass-n is applied to the non-read word lines to read data. The read voltage Vread is applied to the read word lines of the memory block 300, and the on-state voltage Vpass-n is applied to the non-read word lines to read data from the memory block 300.

[0108] Wherein, the turn-on voltage Vpass-n is less than or equal to the initial turn-on voltage Vpass.

[0109] The 3D memory reading method disclosed herein dynamically adjusts the on-state voltage based on the number of reads of the memory block and the threshold distribution of the memory cell. Under the premise of ensuring that the on-state voltage is greater than the highest state threshold voltage, the on-state voltage is dynamically reduced, thereby reducing read interference caused by reading operations on the memory block, increasing the reliability of data storage, and thus improving the overall read performance of the 3D memory.

[0110] Furthermore, the turn-on voltage of each memory block in the 3D memory is adjusted independently. Different turn-on voltages are set according to the number of reads of different memory blocks. The turn-on voltage of memory blocks with more reads is relatively low, and the turn-on voltage of memory blocks with fewer reads is relatively high. It is not necessary to unify the turn-on voltage of each memory block to a high potential, which further improves the overall read performance of the 3D memory.

[0111] Figure 13 The 3D memory provided in this disclosure is shown. The 3D memory provided in this disclosure includes a control circuit 410, a storage interface 420, and a storage array 430.

[0112] The control circuit 410 is connected to the storage interface 420 and is used to perform operations such as reading and writing data in the storage array 430.

[0113] The control circuit 410 includes a processor 411 and a cache 412. The processor 411 can handle access requests to the memory array 430 and manage the data in the memory array 430. The processor 411 is selected, for example, from a CPU (Center Processing Unit), an ASIC (application-specific integrated circuit), or one or more integrated circuits configured to have the above-described functions.

[0114] Cache 412 is connected to processor 411 and is used to cache data that processor 411 is waiting to write to storage array 430, or to cache data read from storage array 430. Cache 412 is a temporary storage located between processor 411 and memory, with a smaller capacity than memory but a faster read / write speed than memory.

[0115] The storage interface 420 is connected to the storage array 430 and is used for communication with the storage array 430 and for data transmission between the control circuit 410 and the storage array 430. For example, it can be used to manage access commands to the storage array 430 issued by the processor 411 and to perform data transmission.

[0116] The storage array 430 includes multiple storage blocks and configuration blocks. The storage blocks are used to store data, and the configuration blocks are used to store various configuration information, including relational tables.

[0117] The storage array 430 is selected, for example, from a 3D flash memory device, and the storage cells are selected from MLC.

[0118] As mentioned earlier, read interference in 3D memory is positively correlated with the magnitude of the turn-on voltage Vpass. In order to reduce read interference, the turn-on voltage Vpass needs to be dynamically adjusted according to the drift of the highest state threshold in the memory cell.

[0119] In the reconfiguration method, the control circuit 410 selects a word line as the selected word line from one or more memory blocks in the memory array 430, writes data into the one or more memory blocks, and simultaneously writes known data into the selected word line in the memory block. Here, the known data refers to the stored data and the corresponding threshold distribution of the stored data, both of which are known.

[0120] Under the control of the control circuit 410, the process of writing data into the memory block is repeated, thereby writing a large amount of data to obtain a table showing the relationship between the number of memory cells on each selected word line that are less than the first predetermined voltage and the on-state voltage, such as... Figure 10 As shown.

[0121] Figure 10 A simplified diagram showing the relationship between the number of memory cells with voltages lower than a fixed read voltage and the turn-on voltage is provided. The more memory cells with voltages lower than the first predetermined voltage Vfix in the memory cells corresponding to the selected word line, the smaller the turn-on voltage Vpass-n required for the read operation of memory block 300.

[0122] The control circuit 410 writes the obtained relation table of each word line into the configuration block in the storage array 430, wherein the configuration block is a storage block used to store various configuration information including the relation table.

[0123] In the reading method, to read data from a specific memory block of the memory array 430, the selected word line of the memory block is first read under the control of the control circuit 410, such as... Figure 11 As shown, a first predetermined voltage Vfix is ​​applied to a selected word line to obtain the number of memory cells in the memory cell corresponding to the selected word line that are less than the first predetermined voltage Vfix, for example, m.

[0124] At the same time, the control circuit 410 reads the relationship table of the selected word line of the memory block in the configuration block, finds the corresponding on-state voltage Vpass-n in the relationship table, and sets the on-state voltage Vpass-n as the on-state voltage when the memory block performs a read operation.

[0125] Under the control of the control circuit 410, a read voltage Vread is applied to the read word line and a conduction voltage Vpass-n is applied to the non-read word line to read the data in the word line to be read.

[0126] The 3D memory provided in this disclosure dynamically adjusts the on-state voltage based on the number of reads of the storage block and the threshold distribution of the storage cell. Under the premise of ensuring that the on-state voltage is greater than the highest state threshold voltage, the on-state voltage is dynamically reduced, thereby reducing read interference caused by read operations on the storage block, increasing the reliability of data storage, and thus improving the overall read performance of the 3D memory.

[0127] Furthermore, the 3D memory provided in this disclosure stores a relationship table in advance in the configuration block of the storage array. The relationship table records the relationship between the number of storage cells with voltages lower than a first predetermined voltage and the corresponding turn-on voltage. During use, the control circuit quickly selects the corresponding turn-on voltage from the relationship table based on the number of storage cells with voltages lower than the first predetermined voltage detected on the selected word line. This eliminates the need for the user to manually adjust the turn-on voltage, making it more convenient. At the same time, it eliminates the need to open an interface for adjusting the turn-on voltage, ensuring the safety and stability of the 3D memory.

[0128] Furthermore, the conduction voltage of each memory block in the 3D memory is adjusted independently. The control circuit adjusts the conduction voltage of the corresponding memory block independently according to the number of memory cells on the selected word line with a voltage lower than the first predetermined voltage in different memory blocks. The conduction voltage of memory blocks with more reads is relatively low, and the conduction voltage of memory blocks with fewer reads is relatively high. It is not necessary to unify the conduction voltage of each memory block to a high potential, which further improves the overall performance of the 3D memory.

[0129] In summary, the configuration method, reading method, and 3D memory provided in this disclosure dynamically adjust the on-state voltage based on the number of reads of the storage block and the threshold distribution of the storage cell. Under the premise of ensuring that the on-state voltage is greater than the highest state threshold voltage, the on-state voltage is dynamically reduced, thereby reducing read interference caused by reading operations on the storage block, increasing the reliability of data storage, and thus improving the overall read performance of the 3D memory.

[0130] Furthermore, the configuration method, reading method, and 3D memory provided in this disclosure store a relationship table in advance in the configuration block of the storage array. The relationship table records the relationship between the number of storage cells with voltages lower than a first predetermined voltage and the corresponding turn-on voltage. In the reading method, the control circuit quickly selects the corresponding turn-on voltage from the relationship table based on the number of storage cells with voltages lower than the first predetermined voltage detected on the selected word line. This eliminates the need for the user to manually adjust the turn-on voltage, making it more convenient. At the same time, it eliminates the need to open the interface for adjusting the turn-on voltage, ensuring the safety and stability of the 3D memory.

[0131] Furthermore, the conduction voltage of each memory block in the 3D memory is adjusted independently. The control circuit adjusts the conduction voltage of the corresponding memory block independently according to the number of memory cells on the selected word line with a voltage lower than the first predetermined voltage in different memory blocks. The conduction voltage of memory blocks with more reads is relatively low, and the conduction voltage of memory blocks with fewer reads is relatively high. It is not necessary to unify the conduction voltage of each memory block to a high potential, which further improves the overall performance of the 3D memory.

[0132] It should be noted that those skilled in the art will understand that the terms “during,” “when,” and “when…” used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the commencement of a startup action, but rather that there may be some small but reasonable delays, such as various propagation delays, between the startup action and the reaction action initiated by it. The terms “approximately” or “substantially” used herein mean that an element value is expected to be close to the declared value or position. However, as is well known in the art, there are always small deviations that make it difficult for the value or position to be strictly the declared value. It has been properly determined in the art that a deviation of at least ten percent (10%) (or at least twenty percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state of the signal (e.g., “1” or “0”) depends on whether positive or negative logic is used.

[0133] As described above, these embodiments of the present disclosure do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present disclosure, thereby enabling those skilled in the art to make good use of the present disclosure and modifications based on it. The scope of protection of this disclosure should be determined by the scope defined by the claims and their equivalents.

Claims

1. A method for configuring a 3D memory, characterized in that, The 3D memory includes multiple storage blocks, and the configuration method includes: Known data is written into a plurality of selected memory cells corresponding to a selected word line in one of the plurality of memory blocks, wherein the known data indicates that the stored data and the threshold voltage distribution corresponding to the stored data are both known. Read the threshold voltage of the plurality of selected memory cells; Obtain a relationship table, which represents the correspondence between the number of memory cells with a threshold voltage less than a first predetermined voltage among the plurality of selected memory cells and the turn-on voltage required to perform a read operation on a certain memory block; During a read operation on a certain memory block, the required turn-on voltage for the read operation is obtained according to the relation table, and the turn-on voltage is applied to the non-read word line.

2. The method for configuring a 3D memory according to claim 1, characterized in that, The 3D memory includes a configuration block, and the configuration method further includes writing the relationship table into the configuration block.

3. The method for configuring a 3D memory according to claim 1, characterized in that, The process of obtaining the relationship table includes repeatedly writing the data and reading the threshold voltage of the plurality of selected storage units to obtain the relationship table.

4. The method for configuring a 3D memory according to claim 1, characterized in that, The step of writing data into a plurality of selected memory cells corresponding to a selected word line in a certain memory block of the plurality of memory blocks includes: applying a programming voltage to the selected word line; and applying a low voltage VPS1 to an unselected word line in the certain memory block.

5. The method for configuring a 3D memory according to claim 2, characterized in that, The configuration block stores one or more of the relationship tables of the storage blocks.

6. The method for configuring a 3D memory according to claim 1, characterized in that, In the relationship table, the more memory cells among the selected memory cells whose threshold voltage is less than the first predetermined voltage, the smaller the corresponding turn-on voltage.

7. The method for configuring a 3D memory according to claim 1, characterized in that, The on-state voltage is greater than the highest state threshold of the memory cell, and the difference between the on-state voltage and the highest state threshold of the memory cell is equal to a second predetermined voltage.

8. A method for reading a 3D memory, characterized in that, The 3D memory includes multiple storage blocks, and the reading method includes: Obtain a data read request, wherein the data read request includes the address of the data to be read; The storage block containing the data to be read is determined based on the address of the data to be read; the storage block belongs to any one of the plurality of storage blocks. Read the selected word line of the memory block to obtain the number of memory cells whose threshold voltage is less than a first predetermined voltage among a plurality of selected memory cells corresponding to the selected word line; Look up the relation table to obtain the turn-on voltage required to perform a read operation on the memory block, corresponding to the number of memory cells whose threshold voltage is less than a first predetermined voltage among the plurality of selected memory cells; The conduction voltage is applied to the non-read word line, and the read voltage is applied to the read word line to obtain the data to be read; The relationship table is used to represent the correspondence between the number of selected memory cells whose threshold voltage is less than a first predetermined voltage and the conduction voltage.

9. The method for reading a 3D memory according to claim 8, characterized in that, The 3D memory also includes a configuration block, in which the relation table is stored.

10. The method for reading a 3D memory according to claim 8, characterized in that, The relation table is obtained by the configuration method of the 3D memory according to any one of claims 1 to 7.

11. The method for reading a 3D memory according to claim 8, characterized in that, The step of reading a selected word line of the memory block to obtain the number of memory cells whose threshold voltage is less than a first predetermined voltage among a plurality of selected memory cells corresponding to the selected word line includes: The first predetermined voltage is applied to the selected word line to detect the threshold voltage of each of the plurality of selected memory cells corresponding to the selected word line. If the threshold voltage of a selected memory cell is less than the first predetermined voltage, the selected memory cell is determined to be a memory cell with a threshold voltage less than the first predetermined voltage, so as to obtain the number of memory cells with a threshold voltage less than the first predetermined voltage among the plurality of selected memory cells.

12. The method for reading a 3D memory according to claim 9, characterized in that, The configuration block stores one or more of the relationship tables of the storage blocks.

13. The method for reading a 3D memory according to claim 8, characterized in that, The on-state voltage is less than or equal to the initial on-state voltage of the memory block.

14. The method for reading a 3D memory according to claim 8, characterized in that, In the relationship table, the more storage cells with voltages less than the first predetermined voltage, the smaller the corresponding turn-on voltage.

15. The method for reading a 3D memory according to claim 8, characterized in that, The on-state voltage is greater than the highest state threshold of the memory cell, and the difference between the on-state voltage and the highest state threshold of the memory cell is equal to a second predetermined voltage.

16. A 3D memory, characterized in that, The 3D memory includes: A storage array, the storage array comprising multiple storage blocks; and control circuitry connected via a storage interface; among which, The control circuit is configured to: write known data into a plurality of selected memory cells corresponding to a selected word line in one of the plurality of memory blocks, wherein the known data indicates that the stored data and the threshold voltage distribution corresponding to the stored data are known; read the threshold voltage of the plurality of selected memory cells; obtain a relational table, wherein the relational table indicates the correspondence between the number of memory cells in the plurality of selected memory cells whose threshold voltage is less than a first predetermined voltage and the turn-on voltage required to perform a read operation on the plurality of memory blocks; and during the read operation on the plurality of memory blocks, obtain the turn-on voltage required for the read operation according to the relational table and apply the turn-on voltage on the non-read word line.

17. The 3D memory according to claim 16, characterized in that, The storage array further includes a configuration block, and the control circuit is further configured to write the relation table into the configuration block.

18. The 3D memory according to claim 16, characterized in that, The control circuit is also configured to: Obtain a data read request, wherein the data read request includes the address of the data to be read; The storage block where the data to be read is located is determined based on the address of the data to be read; The storage block belongs to one of the plurality of storage blocks; Read the selected word line of the memory block to obtain the number of memory cells whose threshold voltage is less than a first predetermined voltage among a plurality of selected memory cells corresponding to the selected word line; The relationship table is searched to obtain the turn-on voltage required to perform a read operation on the memory block, corresponding to the number of memory cells whose threshold voltage is less than a first predetermined voltage among the plurality of selected memory cells; The conduction voltage is applied to the non-read word line, and the read voltage is applied to the read word line to obtain the data to be read.

19. The 3D memory according to claim 16, characterized in that, The on-state voltage is less than or equal to the initial on-state voltage of the memory block.

20. The 3D memory according to claim 16, characterized in that, The control circuit includes: A processor, the processor being configured to implement access requests to the storage array and manage the data in the storage array; A cache, connected to the processor, is used to cache data waiting to be written to the storage array, or to cache data read from the storage array.

Images