Method for preparing wafer sample for chip-on-board and chip-on-board manufacturing method

Abstract

The application provides a preparation method of a wafer sample for making a chip on board and a method for making a chip on board, wherein the preparation method of the wafer sample for making a chip on board comprises the following steps: determining a target wafer in a multi-wafer stack sample, the target wafer being a non-lowermost wafer and being directly connected to the substrate through a gold wire, the gold wire having a first gold ball at a contact part with the substrate; removing the substrate to expose a solder resist layer at the bottom of the lowermost wafer in the plurality of wafers; measuring a first distance in a horizontal direction between the first gold ball on the gold wire connecting the target wafer to the substrate and the edge of the target wafer; determining a grinding area for removing one or more wafers below the target wafer according to the first distance; and removing the one or more wafers below the target wafer based on the determined grinding area to obtain the wafer sample for making a chip on board. The wafer sample for making a chip on board prepared by the application is beneficial to wire bonding operation.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor testing, and in particular to a preparation method of a wafer sample for making a chip on board and a method for making a chip on board. BACKGROUND

[0002] In the failure analysis of a multi-wafer encapsulated sample, if a certain die is found to be defective, the back of the target die needs to be exposed by back processing, and then a chip on board (COB) is made for testing or detecting the failure position. The wire bonding operation of the target die is a critical step, which affects whether the detection or testing operation can be successfully and effectively performed. SUMMARY

[0003] The present application provides a preparation method of a wafer sample for making a chip on board and a method for making a chip on board, which retains the gold ball to make the wire bonding operation simple and easy, so that the detection operation of the target die can be conveniently performed.

[0004] To solve the above technical problems, the present application provides a preparation method of a wafer sample for making a chip on board, comprising the following steps: determining a target die in a multi-wafer encapsulated sample, the multi-wafer encapsulated sample comprising a substrate and a plurality of dies, the target die being a non-lowermost die and being directly connected to the substrate by a gold wire, the gold wire having a first gold ball at the contact portion with the substrate; removing the substrate to expose the solder mask layer at the bottom of the lowermost die in the plurality of dies; measuring the first distance in the horizontal direction between the first gold ball on the gold wire connecting the target die to the substrate and the edge of the target die; determining the grinding area when removing one or more dies below the target die according to the first distance in the horizontal direction; and grinding and removing the one or more dies below the target die based on the determined grinding area to obtain the wafer sample for making a chip on board.

[0005] In an embodiment of the present application, the grinding and removing of the one or more dies below the target die based on the determined grinding area to obtain the wafer sample for making a chip on board comprises: grinding and removing the one or more dies below the target die to expose the die connection film at the bottom of the target die.

[0006] In an embodiment of the present application, the removing of the substrate to expose the solder mask layer at the bottom of the lowermost die in the plurality of dies comprises: removing the substrate by chemical etching.

[0007] In an embodiment of the present application, the first distance between the first gold ball on the gold wire connecting the target wafer to the substrate and the edge of the target wafer in the horizontal direction is determined by a distance scanning device.

[0008] In an embodiment of the present application, the polishing area for polishing one or more wafers under the target wafer according to the horizontal distance is determined as follows: the distance between the edge of the first gold ball and the edge of the target wafer is less than the first distance.

[0009] In an embodiment of the present application, after the one or more wafers under the target wafer are polished according to the determined polishing area, the bottom of the target wafer is polished again for failure position detection.

[0010] In an embodiment of the present application, the target wafer is determined in a multi-wafer stack sample as follows: the multi-wafer stack sample is subjected to electrical failure analysis to determine a failure wafer; and the failure wafer is determined as the target wafer.

[0011] In an embodiment of the present application, the multi-wafer stack sample comprises a three-dimensional memory.

[0012] In an embodiment of the present application, the chemical etching method comprises etching with dilute nitric acid.

[0013] The present application also provides a method for manufacturing a chip-on-board, comprising the following steps: in a multi-wafer stack sample, a wafer sample for manufacturing a chip-on-board is obtained by any of the above methods, wherein the wafer sample comprises a target wafer connected with a gold wire comprising a first gold ball; and a wire bonding operation is performed on the first gold ball of the gold wire to connect or extend the gold wire to manufacture a chip-on-board.

[0014] Compared with the prior art, the present application has the following advantages: compared with directly polishing one or more wafers under the target wafer, the present application can completely retain the gold ball at the end of the gold wire connecting the target wafer to the substrate in the multi-wafer stack sample, thereby facilitating the connection or extension of the gold wire when the wafer sample is manufactured to form a chip-on-board, and improving the efficiency of wafer testing. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this application, illustrate embodiments of the present application, and together with the description serve to explain the principles of the present application. In the drawings:

[0016] Figure 1 is a flow chart of a preparation method of a wafer sample for making a chip on board according to an embodiment of the present application.

[0017] Figures 2 to 9 is a process diagram of a preparation method of a wafer sample for making a chip on board according to the present application, wherein Figures 6 to 8 corresponds to different embodiments. DETAILED DESCRIPTION

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some examples or embodiments of the present application, and for those skilled in the art, the present application can also be applied to other similar scenarios without creative labor. Unless the context clearly indicates otherwise or otherwise stated, the same reference numbers in the drawings represent the same structure or operation.

[0019] As shown in the present application and claims, unless the context clearly indicates otherwise or otherwise stated, "one", "a", "an", and / or "the" do not specifically refer to the singular, but can also include the plural. Generally speaking, the terms "comprise" and "include" only indicate the inclusion of the steps and elements explicitly identified, and these steps and elements do not constitute an exclusive list, and the method or device can also include other steps or elements.

[0020] Unless specifically stated otherwise, the relative arrangement of the components and steps illustrated in these embodiments, numerical expressions, and numerical values do not limit the scope of the present application. At the same time, it should be understood that the sizes of the various parts shown in the drawings are not drawn in accordance with the actual proportional relationship. The technology, methods and devices known to those skilled in the relevant art can not be discussed in detail, but in appropriate cases, the technology, methods and devices should be considered as part of the authorized description. In all examples shown and discussed here, any specific value should be interpreted as merely exemplary, and not as a limitation. Therefore, other examples of exemplary embodiments can have different values. It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0021] In the description of the present application, it needs to be understood that the orientation words such as "front, back, up, down, left, right", "transverse, vertical, perpendicular, horizontal" and "top, bottom" and the like indicated orientation or position relationship are generally based on the orientation or position relationship shown in the drawings, and only for the convenience of describing the present application and simplifying the description, without the opposite description, these orientation words do not indicate and imply that the indicated device or element must have a specific orientation or be constructed and operated in a specific orientation, therefore it cannot be understood as a limitation on the protection scope of the present application; the orientation words "inner, outer" refer to the inner and outer of the contour of each component itself.

[0022] For the convenience of description, spatial relative terms such as "over", "above", "upper surface", "upper" and the like can be used herein to describe the spatial position relationship of one device or feature with other devices or features as shown in the drawings. It should be understood that the spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the drawings. For example, if the device in the drawing is inverted, the device described as "above" or "over" other devices or structures will be positioned "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below" orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein are interpreted accordingly.

[0023] In addition, it needs to be explained that the use of "first", "second" and the like to define parts is only for the convenience of distinguishing the corresponding parts, and the above words have no special meaning unless otherwise stated, therefore it cannot be understood as a limitation on the protection scope of the present application. In addition, although the terms used in the present application are selected from the commonly known and used terms, some terms mentioned in the specification of the present application can be selected by the applicant according to his or her judgment, and the detailed meanings of which are described in the relevant part of the description. In addition, the present application is required to be understood not only by the actual terms used, but also by the meaning implied by each term.

[0024] Flowcharts are used in the present application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in sequence. On the contrary, various steps can be processed in reverse order or simultaneously. Meanwhile, or other operations are added to these processes, or one or more steps of operation are removed from these processes.

[0025] Embodiments of the present application describe a preparation method for preparing a wafer sample for making a chip on board and a method for making a chip on board.

[0026] Figure 1 is a flow chart of a preparation method of a wafer sample for making a chip-on-board according to an embodiment of the present disclosure.

[0027] As shown in Figure 1 , the preparation method of a wafer sample for making a chip-on-board includes, step 101, determining a target wafer in a multi-wafer stack sample, the multi-wafer stack sample including a substrate and a plurality of wafers, the target wafer being a non-lowermost wafer and being directly connected to the substrate by a gold wire, the gold wire having a first gold ball at a contact portion with the substrate; step 102, removing the substrate to expose a solder mask layer at a bottom of a lowermost wafer in the plurality of wafers; step 103, measuring a first distance in a horizontal direction between the first gold ball on the gold wire connecting the target wafer to the substrate and an edge of the target wafer; step 104, determining a grinding area for removing one or more wafers below the target wafer according to the first distance in the horizontal direction; step 105, grinding and removing the one or more wafers below the target wafer based on the determined grinding area, to obtain the wafer sample for making a chip-on-board.

[0028] Specifically, in step 101, a target wafer is determined in a multi-wafer stack sample, the multi-wafer stack sample including a substrate and a plurality of wafers, the target wafer being a non-lowermost wafer and being directly connected to the substrate by a gold wire, the gold wire having a first gold ball at a contact portion with the substrate.

[0029] As shown in Figure 2 , the multi-wafer stack sample 200 includes a substrate 201 and a plurality of wafers, Figure 2 , wafers 202, 203, 204 and 205 are shown. In some embodiments, the substrate further includes a tin ball structure 208 below.

[0030] Figure 2 In some embodiments, the wafers 202, 203, 204 and 205 are directly or indirectly connected to the substrate 201 by gold wires 210, 211, 212 and 213.

[0031] In some embodiments, determining a target wafer in a multi-wafer stack sample includes, step 201, performing electrical failure analysis on the multi-wafer stack sample to determine a failed wafer; and step 202, determining the failed wafer as the target wafer. In some embodiments, the multi-wafer stack sample includes a three-dimensional memory.

[0032] As shown in Figure 3 , for example, by electrical failure analysis, a failed wafer 204 is determined, and the failed wafer 204 is the target wafer, as shown in Figure 3The target wafer 204 is a non-bottommost wafer and is directly connected to the substrate 201 by a gold wire 212. The contact portion of the gold wire 212 with the substrate 201 (also referred to as the gold wire end) has a first gold ball 220.

[0033] In some embodiments, the multi-wafer stack sample 200 is provided with an electromagnetic shield (EMC shield) (not shown in the figures).

[0034] In step 101, a target wafer is determined, and the target wafer is a non-bottommost wafer and is directly connected to the substrate by a gold wire. In step 102, the substrate is removed to expose a solder mask at the bottom of the bottommost wafer in the plurality of wafers, and the solder mask is also referred to as a green oil layer, so as to insulate the bottommost wafer from the substrate.

[0035] In some embodiments, removing the substrate to expose the solder mask at the bottom of the bottommost wafer in the plurality of wafers includes removing the substrate by a chemical etching method. The chemical etching method includes, for example, etching with dilute nitric acid. In some embodiments, it further includes removing the tin ball structure under the substrate by a grinding method.

[0036] The multi-wafer stack sample 200 after the substrate is removed is shown as Figure 4 illustrated.

[0037] Next, in step 103, a first distance in a horizontal direction between a first gold ball on a gold wire connecting the target wafer to the substrate and an edge of the target wafer is measured.

[0038] As shown in Figure 5 , a first distance L between the first gold ball 220 on the gold wire 212 connecting the target wafer 204 to the substrate (the substrate has been removed at this time) and an edge of the target wafer 204 in a horizontal direction is measured, for example Figure 5 indicated. The first distance can be specifically a distance between the edge of the target wafer on a side close to the first gold ball and the edge of the target wafer.

[0039] In some embodiments, measuring the first distance in the horizontal direction between the first gold ball on the gold wire connecting the target wafer to the substrate and the edge of the target wafer includes determining the horizontal distance between the first gold ball on the gold wire connecting the target wafer to the substrate and the edge of the target wafer by a distance scanning device. The distance scanning device is, for example, a device that emits an X-ray signal and receives a return signal to determine the distance.

[0040] In step 104, a grinding area for removing one or more wafers under the target wafer is determined according to the first distance in the horizontal direction.

[0041] As Figure 6 illustrated, the grinding area, for example, area 230, when removing one or more wafers under the target wafer.

[0042] In some embodiments, the grinding area when removing one or more wafers under the target wafer according to the horizontal direction interval includes that the distance of the grinding area near the edge of the first gold ball beyond the edge of the target wafer is less than the first interval.

[0043] Referring to Figure 6 , the distance S of the grinding area near the edge of the first gold ball beyond the edge of the target wafer is less than the first interval L.

[0044] Figure 7 is a diagram of another embodiment of a grinding area. In Figure 7 , the distance S of the grinding area 231 near the edge of the first gold ball beyond the edge of the target wafer 204 is, for example, 0 (or close to 0), at which time the distance S of the grinding area near the edge of the first gold ball beyond the edge of the target wafer is also less than the first interval L.

[0045] Figure 8 is a diagram of another embodiment of a grinding area. In Figure 8 , the grinding area 232 near the edge of the first gold ball does not exceed the edge of the target wafer 204, at which time the distance S' of the grinding area near the edge of the first gold ball to the edge of the target wafer, if converted to the aforementioned distance S, can also be understood as the distance S of the grinding area near the edge of the first gold ball beyond the edge of the target wafer being a negative value, so at this time the distance S of the grinding area near the edge of the first gold ball beyond the edge of the target wafer is still less than the first interval L.

[0046] In step 105, one or more wafers under the target wafer are ground and removed based on the determined grinding area, to obtain the wafer sample for making a chip on board.

[0047] Grinding and removing one or more wafers under the target wafer based on the determined grinding area to obtain the wafer sample for making a chip on board includes grinding and removing one or more wafers under the target wafer to expose a wafer connection film at the bottom of the target wafer.

[0048] Figure 9 is a diagram of the wafer sample 260 for making a chip on board obtained after grinding and removing one or more wafers under the target wafer based on the determined grinding area.

[0049] Figure 9 In some embodiments, the wafer attached film (DAF) at the bottom of the target wafer is indicated by reference numeral 240. The grinding operation is performed by a grinding machine, for example.

[0050] In some embodiments, the preparation method for the wafer sample for making a chip on board further comprises, after the one or more wafers under the target wafer are removed by grinding based on the determined grinding area, performing a secondary grinding (also referred to as a fine grinding operation) on the bottom of the target wafer to perform a failure location detection operation (also referred to as a grab point operation).

[0051] The present application also provides a method for making a chip on board, comprising: step 301, in a multi-wafer stack sample, obtaining a wafer sample for making a chip on board by the method described above, wherein the wafer sample comprises a target wafer connected to a gold wire comprising a first gold ball; and step 302, performing a wire bonding operation on the first gold ball of the gold wire to connect or extend the gold wire to make a chip on board (COB).

[0052] Compared with directly removing the one or more wafers under the target wafer, the technical solution of the present application can completely retain the gold ball at the end of the gold wire connecting the target wafer to the substrate in the multi-wafer stack sample, thereby facilitating the connection or extension of the gold wire when the wafer sample is subsequently made into a chip on board. Since the gold ball at the end of the gold wire is completely retained, the wire bonding operation can be performed on the gold ball.

[0053] If the one or more wafers under the target wafer are directly removed, the gold ball is also easily removed by grinding, so that the wire bonding operation can only be continued on the wire head segment of the gold wire to achieve the connection or extension of the gold wire. The diameter of the gold wire is much smaller than the diameter of the gold ball, which will significantly increase the difficulty of the wire bonding operation. If the wire bonding operation is not successful at one time, the gold wire that has been bonded needs to be pulled out and re-bonded. However, the gold wire that has been bonded before the wire bonding operation is easily pulled out during the pulling process, resulting in the failure of the subsequent wire bonding operation and the failure of the wafer sample processing, thereby reducing the efficiency of wafer testing.

[0054] Therefore, the preparation method for the wafer sample for making a chip on board and the method for making a chip on board of the present application can facilitate the subsequent wire bonding operation by retaining the gold ball at the end of the gold wire connecting the target wafer to the substrate in the multi-wafer stack sample when preparing the wafer sample for making a chip on board, thereby reducing the difficulty of the wire bonding operation and improving the efficiency of wafer testing.

[0055] Having described the basic concepts, it is obvious that the above-described application is merely an example for the person skilled in the art and does not limit the application. Although not explicitly stated, the person skilled in the art can make various modifications, improvements and adaptations to the application. Such modifications, improvements and adaptations are suggested in the application and still fall within the spirit and scope of the exemplary embodiments of the application.

[0056] Also, the application uses specific terminology with respect to the embodiments of the application. As used herein, the terms "one embodiment," "an embodiment," "some embodiments," and / or "one alternative" are intended to mean that a certain feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Therefore, use of the terms "in one embodiment" or "in an embodiment" or "in one alternative" or "in some alternatives" or "one alternative" in various places in the specification are not necessarily referring to the same embodiment of the application, nor are separate or alternative embodiments mutually exclusive of one another. Moreover, certain features, structures, or characteristics of one or more embodiments of the application can be combined in any manner.

[0057] Similarly, it is to be noted that, in this disclosure, where a generic chemical structure is described in the one or more embodiments of the application, it is intended that the generic chemical structure can be used in one or more embodiments of the application. Conversely, where specific chemical structures are described in the one or more embodiments of the application, it is intended that the specific chemical structures can not be used in one or more embodiments of the application. Also, it is to be noted that the foregoing description of the embodiments of the application is sometimes in terms of functional aspects of the application, and thus the description can set forth one or more means or method steps corresponding to each of the functional blocks based on their functionality. These functional blocks (for example, a "means for determining" or "a determining means") can be implemented as described herein or as would be understood by one of ordinary skill in the art. This can be implemented as hardware, software, firmware, or any combination thereof.

[0058] Some embodiments use numerical ranges to describe quantities of components, attributes, etc. It should be understood that such numerical ranges described in the embodiments are, in some examples, modified by the word "about." Unless otherwise indicated, the word "about" means ±20% of the indicated value. Accordingly, any numerical parameters set forth in the specification and attached claims are approximations. While these numerical ranges and parameters are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, can contain certain errors associated with testing measurements.

[0059] While the application has been described with reference to the currently preferred embodiments, those skilled in the art will recognize that various changes can be made in form and detail without departing from the spirit and scope of the application. Therefore, although the application has been described with reference to particular embodiments, it is to be understood that variations and modifications can be affected without departing from the scope of the application.

Claims

1. A method for preparing a wafer sample for fabricating chips on a board, comprising the following steps: In a multi-wafer stacked sample, a target wafer is identified. The multi-wafer stacked sample includes a substrate and multiple wafers. The target wafer is not the bottommost wafer and is directly connected to the substrate via gold wires. The gold wires have a first gold ball at the contact portion with the substrate. Remove the substrate until the solder mask layer at the bottom of the lowest of the plurality of wafers is exposed; Measure the first horizontal distance between the first gold ball on the gold wire connecting the target wafer to the substrate and the edge of the target wafer; The grinding area for removing one or more wafers below the target wafer is determined based on the first spacing in the horizontal direction. Based on the determined grinding area, one or more wafers below the target wafer are ground and removed to obtain the wafer sample used to fabricate the chip on the board.

2. The method for preparing a wafer sample for fabricating chips on a board according to claim 1, characterized in that, Based on the determined grinding area, one or more wafers below the target wafer are ground and removed to obtain the wafer sample for fabricating chips on the board, including: One or more wafers below the target wafer are ground away to expose the wafer bonding film at the bottom of the target wafer.

3. The method for preparing a wafer sample for fabricating chips on a board according to claim 1, characterized in that, Removing the substrate to expose the solder mask layer at the bottom of the lowest wafer among the plurality of wafers includes: removing the substrate by chemical etching.

4. The method for preparing a wafer sample for fabricating chips on a board according to claim 1, characterized in that, Measuring the first horizontal distance between the first gold ball on the gold wire connecting the target wafer to the substrate and the edge of the target wafer includes: The horizontal distance between the first gold ball on the gold wire connecting the target wafer to the substrate and the edge of the target wafer is determined by a distance scanning device.

5. The method for preparing a wafer sample for fabricating chips on a board according to claim 1, characterized in that, Determining the grinding area for removing one or more wafers below the target wafer based on the horizontal spacing includes: The distance from the edge of the grinding area near the first gold ball to the edge of the target wafer is less than the first spacing.

6. The method for preparing a wafer sample for fabricating chips on a board according to claim 1, characterized in that, It also includes performing a second grinding operation on the bottom of the target wafer after grinding and removing one or more wafers below the target wafer based on the determined grinding area, in order to perform a failure location detection operation.

7. The method for preparing a wafer sample for fabricating chips on a board according to claim 1, characterized in that, Identifying the target wafer in a multi-wafer stacked sample includes: Electrical failure analysis was performed on the multi-wafer stacked samples to identify the failed wafers; The failed wafer is identified as the target wafer.

8. The method for preparing a wafer sample for fabricating chips on a board according to claim 1, characterized in that, The multi-wafer stacked sample includes a three-dimensional memory.

9. The method for preparing a wafer sample for fabricating chips on a board according to claim 3, characterized in that, The chemical corrosion method includes corrosion with dilute nitric acid.

10. A method for fabricating a chip on a board, comprising the following steps: In the multi-wafer stacked sample, a wafer sample for fabricating chips on a board is obtained by the method of any one of claims 1-9, including a target wafer connected to a gold wire including a first gold ball; A wire bonding operation is performed on the first gold ball of the gold wire to connect or extend the gold wire in order to create a chip on the board.

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