Semiconductor device manufacturing method and semiconductor device

Abstract

The present invention discloses a method for preparing a semiconductor device and a semiconductor device, comprising: providing a first substrate, and forming a first non-metallic bonding material layer on the surface of the first substrate; providing a second substrate, and forming a device material layer on the surface of the second substrate; forming a second non-metallic bonding material layer on the surface of the device material layer; bonding the second non-metallic bonding material layer and the first non-metallic bonding material layer to form a non-metallic bonding layer; removing the second substrate; and patterning and etching the device material layer to obtain a device layer containing at least one semiconductor device. The present invention avoids the leakage problem caused by metal overflow during patterning etching after metal bonding and residual metal particles after cleaning by non-metallic bonding. The present invention forms an effective etching high selectivity by non-metallic bonding, increases the process window and improves feasibility.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor device and a semiconductor device. Background Art

[0002] At present, there are two main solutions for achieving monolithic integration: patterned metal alignment bonding and full-surface metal bonding. Both the patterned metal alignment bonding and full-surface metal bonding solutions have the following disadvantages.

[0003] The equipment and manufacturing costs of patterned metal alignment bonding solutions are high, and there are high requirements for the density of integrated devices.

[0004] The whole-surface metal bonding scheme will form a complex variety of different crystal phases during the bonding process. General dry etching equipment cannot meet the etching requirements, so it adopts the electron beam etching scheme. During the metal etching process, it is easy for metal particles to scatter and device leakage problems caused by incomplete removal, and it is easy to cause damage to driver-related devices.

[0005] In addition, because both patterned metal bonding and full-surface metal bonding face the problem of etching the bonding metal, a relatively wide etching channel space needs to be reserved to ensure that metal etching can be performed, which has an adverse effect on the density of highly integrated devices.

[0006] In addition, the metal bonding process of both graphic metal bonding and full-surface metal bonding needs to be carried out in a high-temperature environment. Coupled with the objective factor of the difference in thermal expansion coefficients of different material systems, the wafer after bonding will warp, which can easily lead to cracking and faulting of the effective structure, as well as manufacturing difficulties caused by excessive warping.

[0007] Therefore, how to avoid the above-mentioned disadvantages of patterned metal bonding and full-surface metal bonding has become an urgent problem to be solved.

[0008] Patent document TW201724442A provides a metal bonding integration solution. One example is Figure 1 As shown, it includes a driving wafer 8120, a driving circuit 8140, a functional device or apparatus 8150, and a metal bonding layer 8170. Figure 1In the structure shown, during the preparation process, after metal bonding, there is a one-to-one correspondence between the bonding metal pad 8180 at the driving end and the device 8160, and the bonding metal pads 8180 are isolated from each other. During the preparation process of this solution, when the entire surface is metal bonded, a large metal etching space needs to be reserved to complete the one-to-one isolation etching between the bonding metal and the device. During the patterned metal bonding, extremely high alignment accuracy is required, and the alignment accuracy further limits the device size and integration density. After the bonding metal is etched into the bonding metal pad 8180, the device 8160 corresponding to it needs to complete the electrical and physical connection of one of the electrodes, which requires a certain bonding metal thickness (on the one hand, it is necessary to ensure the resistivity requirement of the cross section of the bonding metal; on the other hand, metal bonding often involves eutectic bonding. In order to form a stable crystal phase and offset the impact of wafer warping, surface roughness and eutectic penetration on the reliability of the device, a certain thickness of bonding metal is also required). The thickness of the bonding metal pad 8180 will limit the size of the integrated device. When the device size is reduced to a certain extent, the bonding metal pad 8180 will have a metal column morphology with a large aspect ratio, which poses a great challenge to the reliability of the device 8160 (including adhesion and the firmness of the bonding metal pad 8180 itself). In addition, Figure 1 In the structure shown, the driving circuit 8140, the bonding metal pad 8180, and the device 8160 correspond one to one. If a device 8160 at a certain position is damaged, there will be no spare device 8160 to replace it. Therefore, the structure also has a low acceptance of dead points and requires ultra-high yield control, resulting in low overall reliability.

[0009] Patent TW202006968A proposes a monolithic LED array precursor. Figure 2A and Figure 2B The cross-sectional structure of the LED array precursor and the LED array structure of the prior art are shown respectively. The main structure includes a growth substrate 9100, a first semiconductor layer 9110, a masking layer 9120 including N through holes, a second semiconductor layer 9130 (N-type semiconductor) selectively grown based on the through holes of the masking layer 9120, a third semiconductor layer 9140 including a plurality of quantum well layers 9141 and a fourth semiconductor layer 9150 (P-type semiconductor), and a main electrical contact 9160 (main contact electrode) for ohmic contact current injection.

[0010] After the above-mentioned basic device (precursor) is completed, it is transferred to the driving backplane, and the driving backplane includes a backplane substrate 9200 and a backplane contact pad 9220, on which a secondary processed basic device is included. The device removes the growth substrate 9100, and the first semiconductor layer 9121 is covered again on the outside of the third semiconductor layer 9140 for polarity insulation passivation, and the first semiconductor layer 9110 is roughened to increase the light extraction rate, and the roughened layer 9112 is completed. At the same time, an auxiliary electrical contact 9180 (auxiliary contact electrode) is completed on the first semiconductor layer 9110 for forming electrical contact with the first semiconductor layer 9110.

[0011] Patent TW202006968A mainly has the following problems:

[0012] 1) If Figure 2A As shown, the device is prepared by a selective growth scheme. When the actual material is grown, defects may exist in the material around the masking layer 9120, resulting in defects in the active area of ​​the quantum well layer, resulting in performance impairment and other problems;

[0013] 2) The devices share the first semiconductor layer 9110 (i.e., they share a common electrode through the first semiconductor layer 9110), and there will be photoelectric and signal crosstalk problems between the devices due to the shared first semiconductor layer 9110;

[0014] 3) The auxiliary electrical contact 9180 (auxiliary contact electrode) has poor electrical contact ability on the side close to the substrate (growth substrate 9100) than on the side far from the substrate (growth substrate 9100). Taking GaN polar material as an example, the side close to the substrate (growth substrate 9100) is the N polarity side, and the side far from the substrate (growth substrate 9100) is the Ga polarity side. The difficulty and stability of forming ohmic contact on the N polarity side are worse than those on the Ga polarity side, and the voltage of the device finally manufactured is slightly higher;

[0015] 4) The auxiliary electrical contact 9180 (auxiliary contact electrode) is located on a side close to the substrate (growth substrate 9100). If an electrical connection is to be formed, the substrate (growth substrate 9100) must be removed.

[0016] The US patent with publication number US10297585B1 discloses a multi-resolution composite micro-device, which mentions the structure and preparation method of the device. In this scheme, the silicon nitride film itself as a mechanical support structure has the problem of insufficient mechanical strength, so it is still easy to be damaged when the device size is large, and silicon nitride has poor electrical capacity (electrical transmission, heat transfer) performance, which will affect the performance release of the device. This scheme needs to transfer the target device to the process structure by means of mass transfer, which requires very high transfer alignment accuracy, and when multiple devices are integrated, the transfer process requires a large device spacing, which affects the integration density and final size of the device. When performing mass transfer, an organic material bonding layer (such as polymer resin) is required to fix the micro-device, and the organic material will limit the use environment of the device. In addition, this scheme is not friendly to the device when making electrical connections. For optoelectronic devices, the electrical connection metal blocks the light-emitting surface in large quantities, resulting in low light-emitting efficiency. For electrical and power devices, the electrical connection of this scheme is very likely to generate parasitic capacitance, affecting device performance.

[0017] In the scheme of US10297585B1, the micro device is fixed on the substrate and the device is electrically interconnected in a fan-out manner. In this process, the electrical connection metal for electrical interconnection is located above the micro device and the substrate. This method is not good for the device, especially for optoelectronic devices. The electrical connection metal located above the micro device and the substrate blocks the light-emitting surface in large quantities, resulting in low light-emitting efficiency of the optoelectronic device. For electrical and power devices, the electrical connection of this scheme is very likely to produce parasitic capacitance, affecting device performance. At the same time, in this scheme, the silicon nitride film itself, which serves as a mechanical support structure, has the problem of insufficient mechanical strength, and is easily damaged when the device size is large, and silicon nitride has poor electrical capacity (electrical transmission, heat transmission) performance, which will affect the performance release of the device. In addition, this scheme needs to use a mass transfer method to transfer the target device to the process structure, which requires very high transfer alignment accuracy, and when multiple devices are integrated, the transfer process requires a large device spacing, affecting the integration density and final size of the device. When performing mass transfer, an organic material bonding layer (such as polymer resin) is required to fix the micro-device, and the organic material will also limit the use environment of the device. Summary of the invention

[0018] In view of this, the present invention provides a method for preparing an integrated semiconductor device and an integrated semiconductor device, which adopts non-metallic bonding means to solve the problems of high cost and limited integration density of graphic metal alignment bonding scheme, leakage and device damage of full-surface metal bonding scheme, and wafer warping, structural cracking and faulting caused by metal bonding.

[0019] The technical solution is implemented as follows:

[0020] A method for preparing an integrated semiconductor device, comprising:

[0021] Providing a first substrate, and forming a first non-metallic bonding material layer on a surface of the first substrate;

[0022] Providing a second substrate, and forming a device material layer on a surface of the second substrate;

[0023] forming a second non-metal bonding material layer on the surface of the device material layer;

[0024] Bonding the second non-metallic bonding material layer and the first non-metallic bonding material layer to form a non-metallic bonding layer;

[0025] removing the second substrate;

[0026] The device material layer is patterned and etched to obtain a device layer containing at least one semiconductor device.

[0027] An integrated semiconductor device comprising:

[0028] a first substrate;

[0029] a non-metal bonding layer, wherein the non-metal bonding layer is located on the surface of the first substrate;

[0030] A device layer, the device layer is located on the non-metal bonding layer, and the device layer contains at least one semiconductor device;

[0031] in:

[0032] The non-metal bonding layer is formed by bonding a first non-metal bonding material layer formed on the surface of the first substrate and a second non-metal bonding material layer formed on a device material layer, and the device layer is formed by patterning and etching the device material layer.

[0033] It can be seen from the above scheme that in the preparation method of the integrated semiconductor device and the integrated semiconductor device of the present invention, the leakage problem caused by metal overflow during graphic etching and residual metal particles after cleaning after metal bonding is avoided through the non-metallic bonding method. Through the non-metallic bonding method, an effective high etching selectivity is formed, the process window is increased and the feasibility is improved.

[0034] In addition, in the present invention, the device spacing is reduced by through-holes, and the through-hole size is small. At the same time, because the non-metallic bonding layer does not need to be completely isolated, a larger active area or a higher integration level can be achieved at the same size.

[0035] In the present invention, through non-metallic bonding, the integrated optoelectronic performance (such as light transmittance) of multiple target wafers is no longer affected by the bonding metal, and multiple vertically integrated and distributed devices can be prepared, which can achieve a larger single device size within the same area or a higher device integration density and finished product output of the same size.

[0036] In the present invention, the contact point contact mode can be freely defined, common-pole or non-common-pole bridging can be freely adopted, and the series-parallel scheme between devices is more convenient.

[0037] In addition, compared with metal bonding which requires high temperature, the non-metal bonding in the present invention can achieve low-temperature bonding to optimize thermal mismatch and avoid yield and reliability damage caused by thermal mismatch.

[0038] The present invention also provides a method for preparing a common-pole semiconductor device and a common-pole semiconductor device to solve the reliability problem of the above-mentioned one-to-one corresponding bonding metal pads and devices under ultra-high integration or ultra-small device size.

[0039] The technical solution is implemented as follows:

[0040] A method for preparing a common-electrode semiconductor device, comprising:

[0041] Providing a first substrate, and preparing a first bonding conductive material layer on a surface of the first substrate;

[0042] Providing a second substrate, and preparing a device material layer on a surface of the second substrate, wherein the device material layer at least comprises a first electrode layer away from the second substrate;

[0043] Preparing a second bonding conductive material layer on the surface of the first electrode layer;

[0044] Bonding the second bonding conductive material layer and the first bonding conductive material layer to form a bonding conductive layer;

[0045] The device material layer is patterned and etched from the second substrate side to obtain a device layer containing at least two semiconductor devices, wherein the semiconductor device includes a first electrode formed by patterning and etching the first electrode layer, and the first electrodes of the at least two semiconductor devices are electrically connected to each other through the bonding conductive layer.

[0046] A common-electrode semiconductor device, comprising:

[0047] a first substrate;

[0048] A bonding conductive layer, the bonding conductive layer is located on the surface of the first substrate, and the bonding conductive layer is formed by bonding a first bonding conductive material layer and a second bonding conductive material layer formed on the surface of the first substrate;

[0049] A device layer, the device layer is located on the bonding conductive layer, the device layer contains at least two semiconductor devices, and the first electrodes of the at least two semiconductor devices are electrically connected through the bonding conductive layer; wherein,

[0050] The device layer is formed by graphically etching a device material layer from one side of a second substrate, the device material layer is formed on the surface of the second substrate, the device material layer at least includes a first electrode layer away from the second substrate, the second bonding conductive material layer is formed on the surface of the first electrode layer, and the semiconductor device includes the first electrode formed by graphically etching the first electrode layer.

[0051] It can be seen from the above scheme that in the preparation method of the common-pole semiconductor device and the common-pole semiconductor device of the present invention, the first electrode is common, and there is no need for a one-to-one correspondence between the bonding conductive layer and the first electrode (semiconductor device), which avoids the problem of adhesion firmness of the bonding conductive layer (bonding metal) after patterning due to the small size of the semiconductor device, and the problem of electrical connection performance caused by the thickness of the bonding metal, such as the uniformity of current diffusion and heat dissipation, thereby improving integration and reliability. In the present invention, the first electrode of the semiconductor device is common, and the second electrode can be bridged at the same driving contact at the same time, so that multiple semiconductor devices are connected in parallel and have the same function, which maximizes the failure of the entire device caused by the failure of a single semiconductor device, and improves the reliability of the entire device. In addition, in the present invention, the spacing between semiconductor devices can be reduced by through-holes, and small-sized through-holes are used, and there is no need to completely isolate the bonding conductive layer, thereby achieving a larger active area or higher integration under the condition of the same size device. By adopting the method of the present invention, the contact contact method can be freely defined, and common or non-common bridges can be freely used, and the series-parallel scheme between semiconductor devices is more convenient.

[0052] The present invention also provides a method for preparing a compound semiconductor device and a compound semiconductor device, so as to avoid problems such as functional layer defects and signal crosstalk, and improve the performance of the compound semiconductor device.

[0053] The technical solution is implemented as follows:

[0054] A method for preparing a compound semiconductor device, comprising:

[0055] Providing a first substrate, and preparing a semiconductor stacking structure on the entire surface of the first substrate, wherein the semiconductor stacking structure comprises a transition semiconductor layer, a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer stacked outward from a surface of the first substrate;

[0056] Performing pattern etching on the semiconductor stack structure from a side of the second conductive type semiconductor layer to form a first pattern etching structure exposed to the first conductive type semiconductor layer;

[0057] Forming a second contact electrode and a first contact electrode on the surface of the second conductive type semiconductor layer and the surface of the first conductive type semiconductor layer exposed at the bottom of the first patterned etching structure, respectively;

[0058] preparing an insulating passivation layer in the first patterned etching structure;

[0059] Providing a driving backplane including driving contacts, and electrically connecting the second contact electrodes to the driving contacts one-to-one;

[0060] The semiconductor stack structure is pattern-etched to form a second pattern-etched structure that exposes a portion of the first contact electrode from a side away from the second conductive type semiconductor layer and close to the first conductive type semiconductor layer.

[0061] A compound semiconductor device, comprising:

[0062] A drive backplane, wherein the drive backplane includes drive contacts;

[0063] a second conductivity type semiconductor layer;

[0064] A first conductive type semiconductor layer, wherein the first conductive type semiconductor layer is stacked on the second conductive type semiconductor layer;

[0065] a second contact electrode, the second contact electrode being located on a surface of the second conductive type semiconductor layer, and the second contact electrode being electrically connected to the driving contact in a one-to-one manner;

[0066] A first patterned etching structure, wherein the first patterned etching structure is located in the second conductive type semiconductor layer and a portion of the first conductive type semiconductor layer;

[0067] A first contact electrode, wherein the first contact electrode is located on the first conductive type semiconductor layer at the bottom of the first patterned etched structure;

[0068] an insulating passivation layer, wherein the insulating passivation layer is located in the first patterned etching structure;

[0069] A second patterned etching structure, wherein the second patterned etching structure is located in the first conductive type semiconductor layer, and the second patterned etching structure is located on a side away from the second conductive type semiconductor layer and close to the first conductive type semiconductor layer, and a portion of the first contact electrode is exposed from the second patterned etching structure.

[0070] It can be seen from the above scheme that in the preparation method of the compound semiconductor device and the compound semiconductor device of the present invention, after the entire surface of the semiconductor stacking structure is prepared on the first substrate, the device area including the second contact electrode and the first contact electrode is defined by means of graphic etching. The present invention does not adopt graphic growth means. Therefore, there are no defects in the material layer or functional layer caused by selective growth or graphic growth.

[0071] At the same time, in the present invention, the second contact electrode is electrically connected to the driving contact one-to-one, so there is no common pole connection between the second contact electrodes. The first contact electrode can be prepared with a corresponding functional structure as needed to realize a non-common pole connection structure of the first contact electrode, thereby avoiding the signal crosstalk problem caused by the common pole between devices.

[0072] In addition, in the present invention, the first contact electrode and the second contact electrode are not on the first substrate, so the electrical connection structure does not involve connection on the substrate, thereby solving the problem that the first substrate must be removed to make an electrical connection and the high requirements for making an electrical connection on the first substrate.

[0073] Overall, the method for preparing a compound semiconductor device and the compound semiconductor device of the present invention can improve the performance of the compound semiconductor device as a whole.

[0074] The present invention also provides a method for preparing a thin semiconductor device and a thin semiconductor device, which utilizes a non-aligned bonding method to replace mass transfer to reduce the difficulty of alignment, and uses the bonding layer of the inorganic material as a mechanical support structure to improve the support strength of the device and remove the restrictions of organic materials on the use environment of the semiconductor device.

[0075] The technical solution is implemented as follows:

[0076] A method for preparing a thin semiconductor device, comprising:

[0077] Providing a temporary substrate, preparing a contact electrode on the surface of the temporary substrate, and preparing a first inorganic material bonding layer on the surface of the temporary substrate including the contact electrode;

[0078] Providing a target wafer, the target wafer comprising a wafer substrate and a device material layer prepared on the wafer substrate;

[0079] Preparing a second inorganic material bonding layer on the surface of the device material layer;

[0080] Non-aligned bonding of the first inorganic material bonding layer and the second inorganic material bonding layer to form an inorganic bonding layer;

[0081] Removing the wafer substrate, and performing a first patterning etching on the device material layer and the inorganic bonding layer to form a semiconductor device;

[0082] electrically connecting the semiconductor device to the contact electrode;

[0083] At least a portion of the temporary substrate is removed.

[0084] A thin semiconductor device comprising:

[0085] A semiconductor device, wherein the semiconductor device is formed by first patterning and etching a device material layer prepared on a wafer substrate after the wafer substrate is removed;

[0086] An inorganic bonding layer, wherein the inorganic bonding layer is formed by non-aligned bonding of a first inorganic material bonding layer and a second inorganic material bonding layer, and the inorganic bonding layer and the device material layer are subjected to the first patterning etching together;

[0087] A contact electrode, wherein the contact electrode is prepared on a surface of a temporary substrate, and the semiconductor device is electrically connected to the contact electrode;

[0088] Wherein, the first inorganic material bonding layer is prepared on the surface of the temporary substrate including the contact electrode;

[0089] The second inorganic material bonding layer is prepared on the surface of the device material layer.

[0090] It can be seen from the above scheme that in the preparation method of the thin semiconductor device and the thin semiconductor device of the present invention, the semiconductor device is prepared after the entire surface is bonded, and there is no need to perform alignment transfer for each semiconductor device separately. Compared with the prior art, the cost is low, and the integration density and firmness and reliability are high; the inorganic bonding layer serves as a mechanical support structure during the release process of the semiconductor device, and its mechanical strength is high, which increases the mechanical strength of the thin semiconductor device and helps to reduce the risk of easy damage to the thin semiconductor device. If the inorganic bonding layer is a metal material, the electrical function (electrical and thermal conduction) of the thin semiconductor device is stronger; the material of the inorganic bonding layer adopts metal and inorganic structure, and no organic material is introduced, so that the compatible use environment of the thin semiconductor device is no longer affected by organic materials.

[0091] In addition, in the present invention, the contact electrode and the semiconductor device are prepared on one side of the temporary substrate and one side of the target wafer, respectively, and the contact electrode and the semiconductor device are located on both sides of the inorganic bonding layer, respectively. Therefore, the contact electrode will not occupy the effective area of ​​the area where the semiconductor device is located. Under the same electrode and device size conditions, the effective area lost in the active area where the semiconductor device is located is smaller. For example, if a 100-micron semiconductor device is required to be matched with a 30-micron contact electrode, if the contact electrode is set on the same side of the semiconductor device in a manner other than the present invention, then the active area on the side where the semiconductor device is located needs to lose at least 30 microns of area to accommodate the contact electrode; in the present invention, the size of the contact electrode does not occupy the active area on the side where the semiconductor device is located. It can be seen that under the same active area, the present invention can integrate more semiconductor devices in the active area. In addition, because there is no structural influence of the contact electrode on the side where the semiconductor device is located, the contact electrode will not affect the preparation for the continued miniaturization and miniaturization of semiconductor devices.

[0092] The present invention also provides a method for preparing an integrated semiconductor device and an integrated semiconductor device, so as to place the electrical connection structure of the semiconductor device in the integrated semiconductor device under the integrated semiconductor device, so as to improve the light extraction efficiency of the semiconductor device as a photoelectric device, and reduce the parasitic capacitance of the electrical connection structure as an electrical and power device, thereby improving the device performance of the integrated semiconductor device.

[0093] The technical solution is implemented as follows:

[0094] A method for preparing an integrated semiconductor device, comprising:

[0095] Providing a substrate, and preparing a device material layer including a first material layer and a second material layer on the substrate, wherein the second material layer is located on a side of the device material layer close to the substrate, and the first material layer is located on a side of the device material layer away from the substrate;

[0096] Performing a first patterned etching on a portion of the device material layer from one side of the first material layer to form a step structure exposing a portion of the second material layer;

[0097] preparing a first electrode and a second electrode on the first material layer and on the second material layer exposed from the step structure, respectively, and preparing a protective layer covering the first material layer, the second material layer and the second electrode;

[0098] Preparing a bonding layer on the entire surface of the protective layer, wherein the bonding layer is in electrical contact with the first electrode;

[0099] Providing a carrier, and bonding the bonding layer to the carrier;

[0100] The device material layer is subjected to a second patterning etching from the substrate side to form at least one semiconductor device on the carrier.

[0101] An integrated semiconductor device comprising:

[0102] At least one semiconductor device, the semiconductor device comprising a first material layer and a second material layer, wherein one side of the first material layer has a step structure exposing a portion of the second material layer;

[0103] a first electrode, the first electrode being located on the first material layer;

[0104] a second electrode, the second electrode being located on the second material layer exposed by the step structure;

[0105] a protective layer, the protective layer covering the first material layer, the second material layer and the second electrode;

[0106] A bonding layer is located on the protection layer and is in electrical contact with the first electrode.

[0107] It can be seen from the above scheme that the preparation method and integrated semiconductor device of the present invention can realize a single micro-semiconductor device or a collection of multiple semiconductor devices, and its integrated size and density can be freely defined according to the graphic accuracy and requirements. The integrated semiconductor device implemented by the present invention can include the crystal, active area and electrical contact structure required before the first generation semiconductor, the second generation semiconductor, the third generation semiconductor structure, and the three. The integration mode of the integrated semiconductor device implemented by the present invention can be a single-layer horizontal arrangement or a multi-layer vertical arrangement. According to the requirements, its electrical interconnection can be designed as a series, parallel or series-parallel combination of electrical interconnection structure. And the electrical interconnection structure of series, parallel or series-parallel combination can be realized by using the graphic etching of the bonding layer and combining the bridging technology. In the present invention, the bonding of the carrier to the target wafer can replace the structure and method of alignment bonding or device placement difficulties, and at the same time, the bonding layer has good electrical (electrical and thermal conduction) and mechanical capabilities. The bonding layer is used as an interconnection structure and can also be used as a cantilever beam support structure, which makes full use of the multiple functions of the bonding layer, thereby simplifying the preparation process. In addition, in the present invention, the device surface (ie, the surface of the second material layer) of the integrated semiconductor device has no blocking structure for electrical connection, which can maximize the device capabilities, especially the capabilities of optoelectronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0108] Figure 1 It is a structural schematic diagram of a metal bonding integration solution in the prior art;

[0109] Figure 2A A schematic diagram of the cross-sectional structure of an LED array precursor in the prior art;

[0110] Figure 2B It is a schematic diagram of the LED array structure of the prior art;

[0111] Figure 3 A flowchart of a method for preparing an integrated semiconductor device according to an embodiment of the present invention;

[0112] Figure 4A to Figure 4N A schematic diagram of the device structure evolution process of the method for preparing an integrated semiconductor device implemented by the present invention;

[0113] Figure 5A to Figure 5D It is a schematic diagram of the structures of several bridging modes in the embodiments of the present invention;

[0114] Figure 6 A schematic diagram of a method for preparing a common-electrode semiconductor device according to an embodiment of the present invention;

[0115] Figure 7A to Figure 7H A schematic diagram of the device cross-sectional structure evolution process of the method for preparing a common-polarity semiconductor device implemented by the present invention;

[0116] Figure 8 is a schematic diagram of the distribution of semiconductor devices and driving contacts in a direction perpendicular to the surface of the first substrate in an embodiment of the present invention;

[0117] Fig. 9 A bridge connection structure in an embodiment of the present invention;

[0118] Fig.10 is a schematic diagram of a bridge structure between a driving contact and a semiconductor device in a direction perpendicular to a surface of a first substrate in an embodiment of the present invention;

[0119] Fig.11 is a schematic diagram of the structure in a direction perpendicular to the surface of the bonding conductive layer in an embodiment of the present invention;

[0120] Fig.12 It is a schematic diagram of the structure of the isolation fence in an embodiment of the present invention;

[0121] Fig.13 A schematic diagram of a method for preparing a compound semiconductor device according to an embodiment of the present invention;

[0122] FIG. 14A to FIG. 14F A schematic diagram of the device cross-sectional structure evolution process of the method for preparing a compound semiconductor device implemented by the present invention;

[0123] Fig.15 is a schematic diagram of the morphology structure of another insulating passivation layer in an embodiment of the present invention;

[0124] Fig.16A Schematic diagram of hemispherical and conical structures etched on the first substrate in an embodiment of the present invention;

[0125] Fig. 16B This is a schematic diagram of a cone structure formed by removing the first substrate and etching the transition semiconductor layer in an embodiment of the present invention;

[0126] Fig.17 is a schematic diagram of the shape of the second patterned etching structure in an embodiment of the present invention in a direction perpendicular to the surface of the transition semiconductor layer;

[0127] Fig.18 is a schematic diagram of an optical color conversion structure in an embodiment of the present invention;

[0128] Fig.19 A schematic diagram of a structure in which a device and a first contact electrode are connected one to one in an embodiment of the present invention;

[0129] Fig. 20 A flow chart of a method for preparing a thin semiconductor device according to an embodiment of the present invention;

[0130] FIG. 21A to FIG. 21J A schematic diagram of a device cross-sectional structure change process during the process of manufacturing a thin semiconductor device using the method of an embodiment of the present invention;

[0131] Fig. 22 is a schematic cross-sectional structure diagram of stacking and electrical connection of a three-layer semiconductor device in an embodiment of the present invention;

[0132] Fig.23A is a schematic cross-sectional structure diagram of another connection method of the electrical connection layer in an embodiment of the present invention;

[0133] Fig. 23B is a schematic cross-sectional structure diagram of another connection method of the electrical connection layer in an embodiment of the present invention;

[0134] Fig.24 is a schematic cross-sectional structure diagram of a plurality of semiconductor devices distributed on the surface of a temporary substrate in an embodiment of the present invention;

[0135] Fig.25A A schematic diagram of the cross-sectional structure of a single semiconductor device formed by using a removal method on a temporary substrate;

[0136] Fig.25B A schematic diagram of the cross-sectional structure of a single semiconductor device formed by thinning a temporary substrate;

[0137] Fig.25C A schematic diagram of the cross-sectional structure of a single semiconductor device formed by etching a temporary substrate;

[0138] FIG. 26A to FIG. 26C A schematic diagram of the cross-sectional structure change process when the protective layer is prepared on the surface of the temporary substrate and between the temporary substrate and the contact electrode in an embodiment of the present invention;

[0139] Fig. 27 A flow chart of a method for preparing an integrated semiconductor device according to an embodiment of the present invention;

[0140] FIG. 28A to FIG. 28L A schematic diagram of a device cross-sectional structure change process during the process of manufacturing an integrated semiconductor device using the method of an embodiment of the present invention;

[0141] FIG. 29A to FIG. 29E It is a schematic diagram of the device cross-sectional structure change process during the preparation process of an integrated semiconductor device without dividing grooves in an embodiment of the present invention;

[0142] Fig.30 is a schematic diagram of the distribution structure of the semiconductor device in an embodiment of the present invention in a direction perpendicular to the device surface;

[0143] Fig.31 is a schematic diagram of the distribution structure of the semiconductor device in a direction perpendicular to the device surface after the second electrode is bridged in an embodiment of the present invention;

[0144] Fig.32 This is a schematic diagram of the cross-sectional structure of the device after the carrier is thinned and the conductive layer is prepared in an embodiment of the present invention;

[0145] Fig.33A It is a schematic cross-sectional structure diagram of a hollowed-out carrier below a device having a dividing groove in an embodiment of the present invention;

[0146] Fig.33B It is a schematic cross-sectional structure diagram of a hollowed-out carrier below a device without a dividing groove in an embodiment of the present invention;

[0147] Fig.34A It is a schematic cross-sectional structure diagram of a hollowed-out carrier below a device having a dividing groove and an independent cantilever beam in an embodiment of the present invention;

[0148] Fig.34B It is a schematic cross-sectional structure diagram of a hollowed-out carrier below a device that does not contain a dividing groove and contains an independent cantilever beam in an embodiment of the present invention. DETAILED DESCRIPTION

[0149] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0150] Example 1

[0151] like Figure 3As shown, an embodiment of the present invention provides a method for preparing an integrated semiconductor device, which mainly includes the following steps:

[0152] Step 101: providing a first substrate, and forming a first non-metallic bonding material layer on a surface of the first substrate;

[0153] Step 102, providing a second substrate, and forming a device material layer on the surface of the second substrate;

[0154] Step 103, forming a second non-metallic bonding material layer on the surface of the device material layer;

[0155] Step 104: bonding the second non-metallic bonding material layer and the first non-metallic bonding material layer to form a non-metallic bonding layer;

[0156] Step 105, removing the second substrate;

[0157] Step 106: Perform patterning etching on the device material layer to obtain a device layer containing at least one semiconductor device.

[0158] In optional embodiments, the material of the first substrate can be first-generation semiconductor materials (such as silicon, germanium, etc.), second-generation semiconductor materials (such as gallium arsenide, indium phosphide, etc.), third-generation semiconductor materials (such as gallium nitride, silicon carbide, zinc oxide, diamond, etc.) or semi-finished products and finished devices.

[0159] In an optional embodiment, the material of the first non-metallic bonding material layer may be a single-layer or stacked-layer semiconductor material composed of at least one of silicon oxide, silicon nitride, oxidized titanium, magnesium oxide, aluminum oxide, gallium nitride, gallium arsenide and the like.

[0160] In an optional embodiment, forming the first non-metallic bonding material layer on the surface of the first substrate may be achieved by chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, evaporation, or the like.

[0161] In an optional embodiment, the first non-metallic bonding material layer may have functions such as reflection and heat dissipation in addition to the bonding function.

[0162] In an optional embodiment, the first non-metal bonding material layer is formed on the entire surface of the first substrate.

[0163] In an alternative embodiment, the first non-metallic bonding material layer is patterned.

[0164] In an optional embodiment, the material of the second substrate may be a first-generation semiconductor material, a second-generation semiconductor material, a third-generation semiconductor material, or a semi-finished product or a finished product device.

[0165] In an alternative embodiment, the material of the device material layer includes a material system with wavelengths from deep ultraviolet to far infrared.

[0166] In an optional embodiment, the material of the second non-metal bonding material layer may be a thin film material such as silicon oxide, aluminum oxide, silicon nitride, etc.

[0167] In an optional embodiment, the second non-metal bonding material layer is formed on the entire surface of the device material layer.

[0168] In an alternative embodiment, the second non-metallic bonding material layer is patterned.

[0169] In an optional embodiment, bonding the second non-metallic bonding material layer and the first non-metallic bonding material layer to form a non-metallic bonding layer includes:

[0170] The first non-metal bonding material layer formed on the entire surface and the second non-metal bonding material layer formed on the entire surface are directly bonded.

[0171] In an optional embodiment, bonding the second non-metallic bonding material layer and the first non-metallic bonding material layer to form a non-metallic bonding layer includes:

[0172] The patterned first non-metal bonding material layer and the patterned second non-metal bonding material layer are aligned and bonded.

[0173] In an optional embodiment, the second substrate may be removed by laser lift-off, chemical liquid removal, or mechanical grinding.

[0174] In an optional embodiment, the device material layer is patterned and etched to obtain a device layer containing at least one semiconductor device, which can be achieved by photolithography plus etching, wherein the etching can be done by dry etching or wet etching.

[0175] In an optional embodiment, the shape of the semiconductor devices in the device layer may be a cylindrical, trapezoidal, triangular or other structural shape, and the distribution of the semiconductor devices in the device layer may be arranged neatly or in a cross arrangement.

[0176] In an optional embodiment, the semiconductor device is a micron light emitting diode Micro-LED, and the device material layer is Micro-LED material; the first substrate contains a driver integrated circuit, and the surface of the first substrate is formed on the surface of the first substrate containing the metal contacts of the driver integrated circuit.

[0177] In an optional embodiment, the patterned first non-metallic bonding material layer may cover the metal contacts of the driver integrated circuit, or may not cover the metal contacts of the driver integrated circuit and expose the metal contacts of the driver integrated circuit.

[0178] In an optional embodiment, the device material layer (Micro-LED material) includes a buffer layer, an N-type layer, a quantum well layer, a P-type layer, and an ohmic contact layer stacked in sequence on the second substrate.

[0179] In an optional embodiment, the material of the N-type layer is N-type gallium nitride, and the material of the P-type layer is P-type gallium nitride.

[0180] In an optional embodiment, the buffer layer material may be gallium nitride, aluminum gallium nitride, indium gallium nitride and other materials and alloys thereof.

[0181] In an optional embodiment, the material of the ohmic contact layer may be metal or metal oxide. Specifically, the material of the ohmic contact layer includes metal materials such as silver, nickel, gold, and aluminum, and may also include metal oxide materials such as indium tin oxide and zinc oxide. The ohmic contact layer may be a single layer or a multilayer structure.

[0182] In an optional embodiment, a reflective material or structure, such as a Bragg reflection layer, may be provided between the ohmic contact layer and the second non-metallic bonding material layer.

[0183] In an optional embodiment, the ohmic contact layer may be the entire surface or may be patterned.

[0184] The preparation of the device material layer can be achieved by using existing technologies, which will not be described in detail here.

[0185] In an optional embodiment, the driving integrated circuit includes a TFT thin film transistor and / or an LTPS low temperature polysilicon and / or a CMOS integrated circuit.

[0186] In an optional embodiment, the method for preparing an integrated semiconductor device according to the embodiment of the present invention may further include: step 107 , bridging the device layer and the first substrate.

[0187] Specifically, in an optional embodiment, step 107 includes:

[0188] Step 1071: bridge the first electrodes of all Micro-LEDs in the device layer with the metal contacts in the first substrate.

[0189] In an alternative embodiment, the first electrode of the Micro-LED is a P-electrode. In an alternative embodiment, the P-electrode is a P-type gallium nitride layer in the Micro-LED.

[0190] In addition, in other optional embodiments, step 107 may also include:

[0191] Step 1071 ′: bridge the second electrodes of all Micro-LEDs in the device layer with the metal contacts in the first substrate.

[0192] The second electrode of the Micro-LED is an N-electrode. In an optional embodiment, the N-electrode is an N-type gallium nitride layer in the Micro-LED.

[0193] In an optional embodiment, one of step 1071 and step 1071' may be selectively performed, or both may be performed. The following embodiments are performed on the basis of performing step 1071 but not performing step 1071'.

[0194] In an optional embodiment, after completing step 107 of bridging the device layer and the first substrate, the method for preparing an integrated semiconductor device according to the embodiment of the present invention further includes:

[0195] Step 108: Prepare a common electrode layer on the device layer, and the common electrode layer is simultaneously connected to the second electrodes of all Micro-LEDs in the device layer.

[0196] The second electrode of the Micro-LED is an N-electrode. In an optional embodiment, the N-electrode is an N-type gallium nitride layer in the Micro-LED.

[0197] After completing step 108, a common N-pole Micro-LED light-emitting matrix is ​​formed.

[0198] In an optional embodiment, after completing step 108, the method for preparing an integrated semiconductor device according to the embodiment of the present invention further includes:

[0199] Step 109: prepare an optical structure layer on the surface of the substrate including the device layer.

[0200] In an optional embodiment, the optical structure layer includes micro lenses and / or micro reflective cups.

[0201] In an optional embodiment, the materials of the micro lens and the micro reflector cup may be transparent insulating inorganic materials or organic materials, such as silicon oxide, aluminum oxide, SU8 (a photosensitive organic silicon type material), polyimide, etc. Among them, the inorganic material can be prepared by using a patterned etching process after being plated by a method such as CVD or Sputter, and the inorganic material can be prepared by exposure and high-temperature baking.

[0202] In an optional embodiment, if the micro reflector cup is prepared in step 109, then after completing step 109, the method for preparing an integrated semiconductor device according to the embodiment of the present invention further includes:

[0203] Step 1010: Fill the micro reflective cup with a color conversion material and seal it.

[0204] In an optional embodiment, the color conversion material is phosphor, quantum dots and other materials.

[0205] In an optional embodiment, after completing step 1010, the method for preparing an integrated semiconductor device according to the embodiment of the present invention further includes:

[0206] Step 1011 , cutting the base body including the first substrate and the device layer to obtain an integrated semiconductor device including a set number of semiconductor devices.

[0207] The following is a further description of the method for preparing an integrated semiconductor device according to an embodiment of the present invention in conjunction with a specific example of a Micro-LED preparation process.

[0208] Step 1a1: Figure 4A As shown, a driving backplane (first substrate) 1101 is provided, and a first non-metallic bonding material layer 1102 is formed on the surface of the driving backplane 1101 .

[0209] The driving backplane 1101 includes a TFT thin film transistor driving circuit, an LTPS low temperature polysilicon driving circuit or a CMOS integrated circuit driving circuit. The first non-metal bonding material layer 1102 is formed on one side of the metal contact 1103 of the driving backplane 1101 .

[0210] The material of the first non-metal bonding material layer 1102 may be a single layer or stacked layer semiconductor material such as silicon oxide, silicon nitride, titanium oxide, magnesium oxide, aluminum oxide, gallium nitride, gallium arsenide, etc. The first non-metal bonding material layer 1102 may be prepared by chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, evaporation, etc. In addition to the bonding function, the first non-metal bonding material layer 1102 may also have the capabilities of reflection and heat dissipation.

[0211] The first non-metal bonding material layer 1102 may be Figure 4A The entire surface shown may also be patterned. If the first non-metal bonding material layer 1102 is patterned, the patterned first non-metal bonding material layer 1102 may cover the metal contacts 1103 or expose the metal contacts 1103 .

[0212] Step 1a2: Figure 4B As shown, a wafer substrate (second substrate) 1201 is provided, and a Micro-LED material layer 1202 is formed on the surface of the wafer substrate 1201 .

[0213] The material of the wafer substrate 1201 is, for example, sapphire or silicon carbide.

[0214] The Micro-LED material layer 1202 includes a buffer layer 12021 , an N-type gallium nitride layer 12022 , a quantum well layer 12023 , a P-type gallium nitride layer 12024 and an ohmic contact layer 12025 which are sequentially stacked on the wafer substrate 1201 .

[0215] Step 1a3: Figure 4C As shown, a second non-metal bonding material layer 1203 is formed on the surface of the Micro-LED material layer 1202 .

[0216] The second non-metal bonding material layer 1203 may be a thin film material such as silicon oxide, aluminum oxide, silicon nitride, etc. The material of the second non-metal bonding material layer 1203 corresponds to the material of the first non-metal bonding material layer 1102 .

[0217] There may be a reflective material or structure, such as a Bragg reflection layer, between the ohmic contact layer 12025 and the second non-metallic bonding material layer 1203 .

[0218] The second non-metal bonding material layer 1203 may be Figure 4C The entire surface is shown, but it can also be graphical.

[0219] Step 1a4: Bond the second non-metallic bonding material layer 1203 and the first non-metallic bonding material layer 1102 to form a non-metallic bonding layer 1301, as shown in FIG. Figure 4D shown.

[0220] Among them, the first non-metallic bonding material layer 1102 and / or the second non-metallic bonding material layer 1203 are formed on the entire surface, and the second non-metallic bonding material layer 1203 and the first non-metallic bonding material layer 1102 are directly bonded; the first non-metallic bonding material layer 1102 and the second non-metallic bonding material layer 1203 are both patterned, and alignment bonding is required to ensure that the metal contact 1103 falls within the required range.

[0221] Step 1a5: removing the wafer substrate 1201, such as Figure 4E shown.

[0222] This step uses corresponding processes depending on the material of the wafer substrate 1201. For example, sapphire material can be removed by laser stripping, while silicon substrate, silicon carbide, gallium nitride, gallium arsenide substrate can be removed by chemical solution or grinding.

[0223] The method of the embodiment of the present invention can also realize the stacking and bonding of multiple Micro-LED material layers 1202. For example, after removing the wafer substrate 1201, a first non-metal bonding material layer is prepared on the Micro-LED material layer 1202, and another Micro-LED material layer and a second non-metal bonding material layer are prepared on the surface of another wafer substrate 1201, and the second non-metal bonding material layer is bonded to the first non-metal bonding material layer, thereby realizing the stacking of two Micro-LED material layers. Repeating this method can realize the stacking and bonding of multiple Micro-LED material layers.

[0224] Step 1a6: Prepare the device structure, such as Figure 4F shown.

[0225] In this step, the Micro-LED material layer 1202 is patterned and etched to obtain a device layer containing at least one Micro-LED structure 1204 .

[0226] In this step, the buffer layer 12021 and other sacrificial layer structures are removed by dry or wet etching to expose the ohmic contact layer 12025 and the N-type gallium nitride layer 12022. The shape of the Micro-LED structure 1204 can be common structures such as cylinder, trapezoid, triangle, etc., and its distribution can be neatly arranged or cross-arranged.

[0227] Step 1a7: bridge the P-type gallium nitride layer 12024 of all Micro-LED structures 1204 in the device layer with the metal contacts 1103 in the first substrate 1101, as shown in FIG. Figure 4G shown.

[0228] In this step, the bridging method between the Micro-LED structure 1204 and the metal contact 1103 is determined according to the requirements. Figure 4G A bridging method is shown in FIG. Figure 5A , Figure 5B , Figure 5C Several other bridging methods are shown, among which: Figure 5A In order to bridge the N-type gallium nitride layer 12022 and the metal contact 1103, Figure 5B In order to bridge one side of the G-type gallium nitride layer 12024 with the metal contact 1103, Figure 5C The G-type gallium nitride layer 12024 and the N-type gallium nitride layer 12022 are bridged to different metal contacts 1103. Figure 5D As shown, the metal contact 1103 may also be located on one side of the semiconductor device (eg, Micro-LED structure 1204).

[0229] Insulation protection can be performed before bridging, and the insulation protection can fill the space of Micro-LED structure 1204 or only wrap the surface of Micro-LED structure 1204. Optionally, during the bridging process, the non-metal bonding layer 1301 is etched in the shape of Micro-LED structure 1204 itself, or a hole can be dug in the non-metal bonding layer 1301 to the metal contact 1103 below. The position, size, number and shape of the hole are determined by the space of Micro-LED structure 1204. The bridging solution can be a single electrode (such as Figure 4G , Figure 5A , Figure 5B As shown), it can also be a multi-electrode (as Figure 5C As shown), the bridging position can be selected from any through-hole area, and the material of the bridging layer 1401 can be a metal, such as one or a stack of aluminum, titanium, titanium nitrogen, chromium, platinum, gold, etc., or a metal oxide, such as indium tin oxide, zinc oxide and other conductive materials.

[0230] Step 1a8: prepare a common electrode layer 1402, such as Figure 4H , Fig. 4I , Figure 4J shown.

[0231] For the structure where both the P pole and the N pole are bridged ( Figure 5C In this step, a passivation layer 1501 can be used to cover the planarization ( Figure 4H ) or the passivation layer 1501 covers ( Fig. 4I , Figure 4J ) method, the passivation layer 1501 can be an inorganic material such as silicon oxide, silicon nitride, aluminum oxide, or an organic material such as polyimide, SU8, etc. After the insulation of the passivation layer 1501 is completed, the common electrode layer 1402 is prepared. The common electrode layer 1402 can be made of metal or metal oxide, such as nickel, gold, zinc, chromium, aluminum, titanium, etc., a single or multiple metal single-layer structure or stacked structure that can form an ohmic contact, or a transparent conductive film such as indium tin oxide, zinc oxide, etc., or a mixture of metals and metal oxides.

[0232] Step 1a9: preparing an optical structure layer, such as Figure 4K , Figure 4L , Figure 4M shown.

[0233] The optical structure layer includes a micro lens, the micro lens includes a large light emitting angle structure 1601 , a small light emitting angle structure 1602 , and a butterfly-shaped light emitting angle structure 1603 , and the optical structure layer also includes a micro reflective cup 1604 .

[0234] Among them, the materials of the microlens and microreflector cup can be made of inorganic materials, such as transparent insulating materials such as silicon oxide and aluminum oxide, which can be prepared by graphic etching after coating by CVD or Sputter, or organic materials, such as transparent insulating materials such as SU8 and polyimide, which can be prepared by exposure and high-temperature baking.

[0235] Step 1a10: Colorization and device separation preparation.

[0236] Among them, Figure 4N As shown, the colorization process is to fill the color conversion material 1701 in the micro reflector cup 1604. In an optional embodiment, after the positions of three adjacent Micro-LED structures 1204 are filled with red, green and blue color conversion materials 1701 respectively, the three adjacent Micro-LED structures 1204 can together form a pixel. The color conversion material 1701 is, for example, phosphor, quantum dots and other materials. After the color conversion material 1701 is filled, a thin film deposition seal or a micro lens seal is performed. For different applications, cutting can be performed to select and prepare discrete devices with single or multiple pixels or display screens with a certain resolution.

[0237] The above-mentioned colorization scheme can also be constructed by bonding Micro-LED material wafers of different colors multiple times. After step 1a5 is completed, the relevant processes in steps 1a1 to 1a5 are repeated to integrate the multi-layer material wafers constituting Micro-LED (for example, red light gallium arsenide system Micro-LED wafers of red, green and blue colors, green light gallium nitride system Micro-LED wafers, and blue light gallium nitride system Micro-LED wafers). The bonding film selected for each bonding can select the best combination according to the wafer material system to be bonded. For example, the material of the sapphire substrate can use aluminum oxide-aluminum oxide, or silicon oxide-silicon oxide bonding, and the material of the gallium arsenide substrate can use gallium arsenide-gallium arsenide bonding. The bonding material and the wafer may include an ohmic contact layer and a required optical reflection or filtering layer. The bonding order is based on actual needs. For example, for optoelectronic devices, the bandgap width of the semiconductor material decreases from top to bottom to achieve optimal light extraction. After integration, start from step 1a6, graph one by one, and after completion, perform bridging according to the plan of step 1a7. You can freely choose whether to share the common pole and the common polarity to complete the final integration plan. The integrated bridging can occur between the driver and the wafer device and between the wafer device and the device. You can choose the appropriate series-parallel and through-hole solutions.

[0238] Various embodiments of the method for preparing an integrated semiconductor device according to the embodiment of the present invention may also be used for the integration of other types of semiconductor devices.

[0239] The embodiment of the present invention also provides an integrated semiconductor device, including a first substrate, a non-metallic bonding layer and a device layer. The non-metallic bonding layer is located on the surface of the first substrate. The device layer is located on the non-metallic bonding layer, and the device layer contains at least one semiconductor device. The non-metallic bonding layer is formed by bonding a first non-metallic bonding material layer formed on the surface of the first substrate and a second non-metallic bonding material layer formed on a device material layer, and the device layer is formed by patterning and etching the device material layer.

[0240] In the method for preparing an integrated semiconductor device and the integrated semiconductor device of the embodiment of the present invention, the leakage problem caused by metal overflow during patterned etching and residual cleaning of metal particles after metal bonding is avoided by non-metal bonding, and an effective high etching selectivity is formed by non-metal bonding, which increases the process window and improves feasibility. In addition, in the embodiment of the present invention, the device spacing is reduced by the through-hole method, and the through-hole size is small. At the same time, because the non-metal bonding layer does not need to be completely isolated, a larger active area or a higher integration degree can be achieved at the same size.

[0241] In the embodiment of the present invention, through non-metallic bonding, the integrated optoelectronic performance (such as light transmittance) of multiple target wafers is no longer affected by the bonding metal, multiple vertically integrated and distributed devices can be prepared, and a larger single device size or a higher device integration density and finished product output of the same size can be achieved within the same area.

[0242] In the embodiment of the present invention, the contact mode of the contact point can be freely defined, common-pole or non-common-pole bridging can be freely adopted, and the series-parallel scheme between the devices is more convenient.

[0243] In addition, compared with metal bonding which requires high temperature, the non-metal bonding in the embodiment of the present invention can achieve low-temperature bonding to optimize thermal mismatch and avoid yield and reliability damage caused by thermal mismatch.

[0244] Example 2

[0245] like Figure 6 As shown, the method for preparing a common-electrode semiconductor device according to an embodiment of the present invention mainly comprises the following steps:

[0246] Step 201, providing a first substrate, and preparing a first bonding conductive material layer on the surface of the first substrate;

[0247] Step 202: providing a second substrate, and preparing a device material layer on the surface of the second substrate, wherein the device material layer at least includes a first electrode layer away from the second substrate;

[0248] Step 203, preparing a second bonding conductive material layer on the surface of the first electrode layer;

[0249] Step 204: Bonding the second bonding conductive material layer and the first bonding conductive material layer to form a bonding conductive layer;

[0250] Step 205, pattern-etching the device material layer from the second substrate side to obtain a device layer containing at least two semiconductor devices, wherein the semiconductor device includes a first electrode formed by pattern-etching the first electrode layer, and the first electrodes of at least two semiconductor devices are electrically connected to each other through a bonding conductive layer.

[0251] In the preparation method of the common-pole semiconductor device in the embodiment of the present invention, the first electrodes of each semiconductor device are connected in common through the bonding conductive layer. This structure does not require a one-to-one correspondence between the first electrodes and the bonding conductive layer. Therefore, there is no need to perform corresponding graphic etching on the bonding conductive layer for this one-to-one correspondence, thereby avoiding the adhesion firmness problem of the bonding conductive layer after graphic processing caused by the small size of the semiconductor device, and the electrical connection performance problems such as current diffusion and heat dissipation uniformity caused by the thickness of the bonding conductive layer, thereby improving the integration and reliability of the semiconductor device.

[0252] In an optional embodiment, the surface of the first substrate includes a driving contact electrically connected to the driving circuit; the first bonding conductive material layer is formed on the surface including the driving contact; in a direction perpendicular to the surface of the first substrate, the semiconductor device and the driving contact avoid each other, that is, the semiconductor device is not arranged directly above the driving contact, and the semiconductor device is arranged at a position other than directly above the driving contact, for example, the semiconductor device is arranged on the side obliquely above the driving contact, or it can be arranged around the driving contact. In this optional embodiment, the method for preparing a common-pole semiconductor device may further include:

[0253] Step 206: Remove the bonding conductive layer from the surface of the driving contact or form an isolation fence on the surface of the driving contact by patterned etching to disconnect the electrical contact between the bonding conductive layer and the driving contact.

[0254] Among them, in actual scenarios, the size of the driving contact is very small, and the driving contact can be exposed only through the through hole, so the process of step 206 is to prepare a through hole in the bonding conductive layer above the driving contact to expose the driving contact from the bonding conductive layer through the through hole. In the embodiment of the present invention, the graphic etching using the through hole method can reduce the spacing between semiconductor devices. Since the through hole size is small and the bonding conductive layer after the through hole is formed is not completely isolated in a one-to-one correspondence with the first electrode as in the prior art, a larger active area or a higher integration of semiconductor devices under the condition of the same size semiconductor device can be achieved.

[0255] In an optional embodiment, the device material layer further includes a second electrode layer close to the second substrate; the semiconductor device further includes a second electrode formed by patterning and etching the second electrode layer. In this optional embodiment, the method for preparing a common-polarity semiconductor device may further include:

[0256] Step 207 : bridge the second electrode of at least one semiconductor device in the device layer with the driving contact.

[0257] In an optional embodiment, the number of driving contacts is at least one, and the second electrodes of each semiconductor device can be bridged to different driving contacts one by one. In addition, the same driving contact bridges the second electrodes of more than one semiconductor device at the same time. When the same driving contact bridges the second electrodes of more than one semiconductor device at the same time, more than one semiconductor devices are connected in parallel. In the parallel state, more than one semiconductor device can achieve the same function. After a single semiconductor device fails, other semiconductor devices that have not failed can still perform the same function, thereby avoiding the problem of failure of the entire common-pole semiconductor device due to the failure of a single semiconductor device, thereby improving the reliability of the common-pole semiconductor device.

[0258] In an optional embodiment, step 206 includes:

[0259] Step 2061: after executing step 20201, that is, after forming the first bonding conductive material layer on the surface of the first substrate, removing the first bonding conductive material layer from the surface of the driving contact or forming an isolation fence on the surface of the driving contact by patterned etching to disconnect the electrical contact between the first bonding conductive material layer and the driving contact;

[0260] Step 2062: after performing step 203, that is, after forming the second bonding conductive material layer, removing the second bonding conductive material layer corresponding to the driving contact position by pattern etching;

[0261] And, in step 204, the second bonding conductive material layer is bonded to the first bonding conductive material layer by using alignment bonding to form a bonding conductive layer that is electrically disconnected from the driving contact.

[0262] In this embodiment, the bonding conductive layer on the surface of the driving contact is removed by performing three steps of respectively performing patterning etching of the first bonding conductive material layer, patterning etching of the second bonding conductive material layer, and alignment bonding. This process has high requirements on the photolithography and alignment processes.

[0263] Alternatively, in an optional embodiment, step 206 may include the following process:

[0264] After the device material layer is pattern-etched to obtain the device layer, the bonding conductive layer on the driving contact is removed by pattern-etching to disconnect the electrical contact between the bonding conductive layer and the driving contact.

[0265] This process can be performed after step 205, and only requires one photolithography, without the need for alignment and bonding. Compared with the three steps of alignment and bonding in the above-mentioned steps 2061, 2062 and 204 to achieve the removal of the bonding conductive layer on the surface of the driving contact, it is simpler and easier to implement.

[0266] In an optional embodiment, step 207 includes the following sub-steps:

[0267] Step 2071: after disconnecting the electrical contact between the bonding conductive layer and the driving contact, preparing an insulating protective layer on the side wall of the bonding conductive layer close to the driving contact and the side wall of the first electrode of at least one semiconductor device;

[0268] Step 2072: prepare a bridging layer electrically connected to the second point electrode and the driving contact on the insulating protective layer, wherein the bridging layer and the first electrode and the bridging layer and the bonding conductive layer are isolated by the insulating protective layer, and then the bridging layer and the first electrode and the bonding conductive layer are insulated, thereby avoiding a short circuit between the first electrode and the second electrode.

[0269] In an optional embodiment, if the second substrate does not need to be retained, after completing step 204 of bonding the second bonding conductive material layer and the first bonding conductive material layer, and before performing step 205 of patterning and etching the device material layer from the second substrate side, the method for preparing a common-polarity semiconductor device according to the embodiment of the present invention may further include:

[0270] The second substrate is removed.

[0271] In an optional embodiment, if the second substrate needs to be retained to realize related functions or structures, while performing step 205 of patterning and etching the device material layer from one side of the second substrate to obtain a device layer containing at least two semiconductor devices, the method for preparing a common-polarity semiconductor device according to the embodiment of the present invention may further include:

[0272] The second substrate and the device material layer are pattern-etched together, and a microstructure bearing layer is formed by pattern-etching the second substrate while the device layer is formed.

[0273] Since the second substrate is patterned and etched together with the device material layer, in this optional embodiment, the microstructure bearing layer is located on each semiconductor device of the device layer, and the microstructure bearing layer corresponds to the semiconductor device one by one.

[0274] Furthermore, after the microstructure bearing layer is prepared, in an optional embodiment, the method for preparing the common-electrode semiconductor device of the embodiment of the present invention further includes:

[0275] The microstructure bearing layer is patterned and etched to form a microstructure in the microstructure bearing layer.

[0276] The microstructure includes micro-through holes, micro-cavities, etc. The micro-through holes can limit light emission, and the micro-cavities can carry other materials or device structures formed in the micro-cavities in subsequent processes.

[0277] In an optional embodiment where the second substrate does not need to be retained, further, a process similar to the above steps 202 to 205 may be used on the device material layer to continue bonding other device material layers on the device material layer, thereby obtaining a stacked structure consisting of at least two layers of device material layers. Specifically, after removing the second substrate and before performing patterned etching on the device material layer in step 205, the method for preparing a common-polarity semiconductor device of the embodiment of the present invention may further include:

[0278] Bonding is continued on the device material layer to form a stacked structure consisting of at least two device material layers.

[0279] On the basis of this step, while performing the patterned etching of the device material layer to obtain the device layer in step 205, the method for preparing the common-electrode semiconductor device according to the embodiment of the present invention further includes:

[0280] The stacked structure is patterned and etched to form a device stacking layer, wherein the device stacking layer includes a device layer and other device layers stacked on the device layer.

[0281] The method for preparing the common-polarity semiconductor device according to the embodiment of the present invention is further described below in conjunction with a specific example of a semiconductor device preparation process.

[0282] Step 2a1: Fig. 7A As shown, a first substrate 2101 (driving backplane) is provided, and a first bonding conductive material layer 2102 is formed on the surface of the first substrate 2101 .

[0283] Among them, the first substrate 2101 includes one or more hybrid driving circuits (not shown in the figure) of TFT (Thin Film Transistor) driving circuit, LTPS (Low Temperature Poly-Silicon) driving circuit, CMOS (Complementary Metal Oxide Semiconductor) integrated circuit driving circuit, and HEMT (High Electron Mobility Transistor) driving circuit.

[0284] The surface of the first substrate 2101 includes a driving contact 2103 electrically connected to the driving circuit. The first bonding conductive material layer 2102 is formed on the surface including the driving contact 2103 .

[0285] The material of the first bonding conductive material layer 2102 can be a metal, such as an alloy of one or more of gold, nickel, tin, and indium. The material of the first bonding conductive material layer 2102 also includes non-metallic inorganic substances, such as single-layer or stacked semiconductor materials such as silicon oxide, silicon nitride, magnesium oxide, aluminum oxide, gallium nitride, and gallium arsenide. The material of the first bonding conductive material layer 2102 can also include organic materials, such as polyimide, etc. The material of the first bonding conductive material layer 2102 can also be a combination of one or more of metal, non-metallic inorganic substances, and organic substances. In addition to the bonding function, the first bonding conductive material layer 2102 can have the capabilities of conducting, reflecting, and dissipating heat, and the first bonding conductive material layer 2102 can be a whole surface and can be patterned. If the first bonding conductive material layer 2102 is patterned, the position, shape, and size of the opening (through hole) in the patterned first bonding conductive material layer 2102 must be determined according to the position, shape, and size of the drive contact 2103. When non-conductive materials such as silicon oxide and silicon nitride are used, a metal film layer can be added above or below the non-conductive material film layer to achieve conductivity of the first bonding conductive material layer 2102. At this time, the first bonding conductive material layer 2102 is a composite film layer composed of a non-conductive film layer and a conductive film layer.

[0286] Among them, the preparation of the first bonding conductive material layer 2102 can be achieved by electroplating, chemical plating, PVD (Physical Vapor Deposition), sputtering, evaporation, ALD (Atomic layer deposition), thin film coating, CVD (Chemical Vapor Deposition) plating and other methods.

[0287] Step 2a2: Figure 7BAs shown, a second substrate 2201 (wafer substrate) is selected, and a device material layer 2202 is prepared on the surface of the second substrate 2201 .

[0288] The material of the second substrate 2201 may be a first generation semiconductor material, a second generation semiconductor material, or a third generation semiconductor material. The device material layer 2202 includes a functional material layer (thin film) that can form optoelectronic material devices, laser type devices, micromechanical devices, power electronic devices, and power radio frequency devices, etc. Figure 7B As shown, in the embodiment of the present invention, the device material layer 2202 at least includes a first electrode layer 22021 and a second electrode layer 22022. In the device material layer 2202, other functional material layers except the first electrode layer 22021 and the second electrode layer 22022 are not shown. In the embodiment shown in the figure, the second electrode layer 22022 is located on the side of the device material layer 2202 close to the second substrate 2201, and the first electrode layer 22021 is located on the side of the device material layer 2202 away from the second substrate 2201. For example, if the device material layer 2202 is a material layer structure for preparing a Micro-LED device, the first electrode layer 22021 may be an N-type gallium nitride layer forming the N-level of the Micro-LED device, and the second electrode layer 22022 may be a P-type gallium nitride layer forming the P-level of the Micro-LED device.

[0289] The preparation process of the device material layer 2202 depends on the semiconductor device to be prepared and the materials used.

[0290] Step 2a3: Figure 7C As shown, a second bonding conductive material layer 2203 is prepared on the surface of the first electrode layer 22021.

[0291] Among them, the second bonding conductive material layer 2203 structure may include a structure that forms relevant electrical interconnections with the first electrode layer 22021, such as an ohmic contact, a Schottky contact, etc. At the same time, the material of the second bonding conductive material layer 2203 can be a metal, such as an alloy of one or more of gold, nickel, tin, and indium. The material of the second bonding conductive material layer 2203 can also be a non-metallic inorganic substance, such as single-layer or stacked semiconductor materials such as silicon oxide, silicon nitride, titanium oxide, magnesium oxide, and aluminum oxide. The material of the second bonding conductive material layer 2203 can also be an organic material, such as polyimide, etc. The material of the second bonding conductive material layer 2203 can also be a combination of one or more of metals, non-metallic inorganic substances, and organic substances. In addition to the bonding function, the second bonding conductive material layer 2203 may have the capabilities of conducting, reflecting, and dissipating heat, and the second bonding conductive material layer 2203 may be a whole surface or may be patterned with openings. If the second bonding conductive material layer 2203 is patterned, the position, shape, and size of the openings (through holes) in the patterned second bonding conductive material layer 2203 shall be determined according to the position, shape, and size of the driving contacts 2103 in the first substrate 2101. When non-conductive materials such as silicon oxide and silicon nitride are used, a metal film layer may be added above or below the non-conductive material film layer to realize the conductivity of the second bonding conductive material layer 2203. In this case, the second bonding conductive material layer 2203 is a composite film layer composed of a non-conductive film layer and a conductive film layer.

[0292] Among them, the preparation of the second bonding conductive material layer 2203 can be achieved by electroplating, chemical plating, PVD (Physical Vapor Deposition), sputtering, evaporation, ALD (Atomic layer deposition), thin film coating, CVD (Chemical Vapor Deposition) plating and other methods.

[0293] Step 2a4: Fig.7D As shown, the second bonding conductive material layer 2203 and the first bonding conductive material layer 2102 are bonded to form a bonding conductive layer 2301 .

[0294] In this step, the first bonding conductive material layer 2102 and / or the second bonding conductive material layer 2203 are formed on the entire surface, and the second bonding conductive material layer 2203 and the first bonding conductive material layer 2102 are directly bonded, such as Fig.7D In other embodiments, the first bonding conductive material layer 2102 and the second bonding conductive material layer 2203 are both patterned, and alignment bonding is required to ensure that the driving contact 2103 falls within a range that meets the requirements.

[0295] Step 2a5: removing the second substrate 2201, as Fig. 7E shown.

[0296] The method for removing the second substrate 2201 depends on the material of the second substrate 2201. For example, laser stripping can be used for a sapphire substrate, and chemical liquid removal or grinding can be used for a silicon substrate, silicon carbide, gallium nitride, or gallium arsenide substrate. The second electrode layer 22022 is exposed by dry or wet etching to facilitate subsequent electrical interconnection of the second electrode (formed by the second electrode layer 22022).

[0297] In an optional embodiment, in combination with steps 2a2 to 2a5, it is also possible to Fig. 7E On the basis of the structure shown, more than one device material layer stacking structure is stacked and bonded.

[0298] Step 2a6: Figure 7F As shown, the device structure is prepared.

[0299] The device structure preparation process may include patterning and etching the device material layer 2202 from one side of the second substrate 2201 (which has been removed at this time) (i.e., from the second electrode layer 22022), thereby obtaining a device layer containing at least two semiconductor devices 2204. The semiconductor device 2204 includes at least a first electrode 22041 and a second electrode 22042, wherein, during the device structure preparation process, the first electrode 22041 is formed by etching the first electrode layer 22021, and the second electrode 22042 is formed by etching the second electrode layer 22022.

[0300] Step 2a6 is an embodiment performed after removing the second substrate 2201. In other optional embodiments, the removal of the second substrate 2201 in step 2a5 may not be performed, but the second substrate 2201 is patterned and etched together with the device material layer 2202, and while obtaining a device layer containing at least two semiconductor devices 2204, the second substrate 2201 is also etched on each semiconductor device 2204 to form a microstructure bearing layer. Among them, whether the second substrate 2201 is retained depends on the manufacturing purpose of the integrated circuit and the material selected for the second substrate 2201. If it is required to have an electrical connection function, the microstructure bearing layer can be used for subsequent electrical connection. If it is not required to have an electrical connection function, the microstructure bearing layer can be used for special structure preparation, such as micro-through holes for limiting light emission, micro-cavities for carrying subsequent other materials or device structures, etc.

[0301] Figure 8The distribution relationship between the semiconductor device 2204 and the driving contact 2103 in the direction perpendicular to the surface of the first substrate 2101 is shown. In the direction perpendicular to the surface of the first substrate 2101, the position of the semiconductor device 2204 needs to avoid the driving contact 2103, that is, the semiconductor device 2204 cannot be arranged directly above the driving contact 2103, but is arranged obliquely above the driving contact 2103 to ensure that after the bonding conductive layer 2301 is subsequently etched through the hole, the driving contact 2103 can be exposed in the through hole without being blocked by the semiconductor device 2204. Figure 8 As shown, in a direction perpendicular to the surface of the first substrate 2101 , the semiconductor device 2204 may be arranged on one side of the driving contact 2103 , or may be arranged around the driving contact 2103 .

[0302] Step 2a7: Figure 7G As shown, by pattern etching, the bonding conductive layer 2301 is removed from the surface of the driving contact 2103 or an isolation fence 2501 is formed on the surface of the driving contact 2103 (see the subsequent description and Fig.12 In the structure shown in the figure, a through hole 2302 is formed above the driving contact 2103 in the bonding conductive layer 2301, and the through hole 2302 disconnects the electrical contact between the bonding conductive layer 2301 and the driving contact 2103.

[0303] Among them, the bonding conductive layer 2301 only exposes the driving contact 2103 through the through hole 2302, and does not destroy the integrity of the bonding conductive layer 2301 in other areas outside the driving contact 2103, thereby ensuring the electrical performance of good electrical contact between the bonding conductive layer 2301 and the first electrode 22041 and the reliability of adhesion between the bonding conductive layer 2301 and the semiconductor device 2204.

[0304] See also Fig.11 As shown, in the embodiment of the present invention, the continuity of the bonding conductive layer 2301 is not destroyed, and the corresponding electrical connection of the driving contact 2103 is achieved by opening a slot or a through hole 2302 at a specific position and using a bridge. The number of the slot or through hole 2302 can be one or more, and the shape and size are set according to requirements. In the embodiment of the present invention, the electrical function of the entire surface of the bonding conductive layer 2301 is not destroyed, and there is no need for a one-to-one correspondence between the bonding layer and the device.

[0305] The through hole 2302 may be in any shape, such as circular, square, triangular, or ring-shaped.

[0306] Among them, one to multiple semiconductor devices 2204 or an array composed of semiconductor devices 2204 can be prepared between adjacent driving contacts 2103. The shape of the semiconductor device 2204 can be cylindrical, trapezoidal, triangular or other conventional structures. The distribution of the semiconductor devices 2204 can be neatly arranged or cross-arranged.

[0307] Step 2a8: Figure 7H As shown, the second electrode 22042 is electrically connected to the driving contact 2103 (bridge connection).

[0308] The steps include: firstly preparing an insulating protective layer 2401 on the side wall of the bonding conductive layer 2301 close to the driving contact 2103 and the side wall of the first electrode 22041 of the semiconductor device 2204; then, preparing a bridging layer 2402 electrically connected to the second electrode 22042 and the driving contact 2103 on the insulating protective layer 2401.

[0309] Fig. 9 Another bridge connection structure is shown, wherein an insulating protection layer 2401 is deposited on the entire structure surface including the surface of the bonding conductive layer 2301 and the side wall surface of the semiconductor device 2204, and then the insulating protection layer 2401 is etched at the corresponding position of the driving contact 2103, and a bridge layer 2402 connected between the second electrode 22042 and the driving contact 2103 is deposited in the through hole formed by etching.

[0310] like Fig.12 As shown, it is the structure of the isolation fence 2501. Fig.12 In the bridge structure on the middle right side, the bonding conductive layer 2301 is formed by etching the bonding conductive layer 2301 on the driving contact 2103 during patterning to form an isolation fence 2501 structure, in which a portion of the bonding conductive layer 2301 above the driving contact 2103 is retained to protect the driving contact 2103, and the bridge layer 2402 is directly connected to the bonding conductive layer 2301 retained on the driving contact 2103. The method of retaining a portion of the bonding conductive layer 2301 on the driving contact 2103 can protect the driving contact 2103 from being damaged or peeled off during the preparation process. The isolation fence 2501 isolates the bonding conductive layer 2301 above the driving contact 2103 from the surrounding bonding conductive layers 2301, thereby preventing a short circuit between the driving contact 2103 and the surrounding bonding conductive layers 2301.

[0311] The material of the bridging layer 2402 may be metal, metal oxide or the like, such as single-layer metals such as chromium, aluminum, titanium, platinum, gold, titanium nitrogen, titanium tungsten, indium tin oxide, zinc oxide, or the like, or may be a transparent conductive layer or a mixture thereof.

[0312] The bridge connection in step 2a8 is determined according to the arrangement and design requirements of the semiconductor device 2204, and can realize the electrical connection of one driving contact 2103 to one or more second electrodes 22041 of the semiconductor devices 2204 at the same time, such as Fig.10 As shown, multiple drive contacts 2103 can also be electrically connected to one semiconductor device 2204.

[0313] The material of the insulating protection layer 2401 may be inorganic materials such as silicon oxide, silicon nitride, aluminum oxide, etc., or may be organic materials such as SU8 (a photosensitive organic silicon type material), polyimide, RDL, etc.

[0314] The embodiment of the present invention also provides a common-electrode semiconductor device, see 7A to 7H as well as Fig. 9 As shown, it mainly includes a first substrate 2101, a bonding conductive layer 2301 and a device layer. Among them, the bonding conductive layer 2301 is located on the surface of the first substrate 2101, and the bonding conductive layer 2301 is formed by bonding a first bonding conductive material layer 2102 and a second bonding conductive material layer 2203 formed on the surface of the first substrate 2101. The device layer is located on the bonding conductive layer 2301, and the device layer contains at least two semiconductor devices 2204, and the first electrodes 22041 of the at least two semiconductor devices 2204 are electrically connected to each other through the bonding conductive layer 2301. Among them, the device layer is formed by graphically etching a device material layer 2202 from one side of a second substrate 2201, the device material layer 2202 is formed on the surface of the second substrate 2201, the device material layer 2202 at least includes a first electrode layer 22021 away from the second substrate 2201, the second bonding conductive material layer 2203 is formed on the surface of the first electrode layer 22021, and the semiconductor device 2204 includes a first electrode 22041 formed by graphically etching the first electrode layer 22021.

[0315] In an embodiment of the present invention, the second electrode 22042 is connected to the driving contact 2103 through the bridging layer 2402, and the driving contact 2103 is connected to a driving electrode (for example, a source or a drain) in the driving circuit. Correspondingly, because the first electrodes 22041 of the semiconductor devices 2204 are electrically connected to a common electrode through the bonding conductive layer 2301, it is only necessary to connect the bonding conductive layer 2301 to another driving electrode in the driving circuit or to the ground to realize the driving circuit driving multiple semiconductor devices 2204.

[0316] In the embodiment of the present invention, the types of driving circuits include P-type or N-type CMOS driving devices, thin film transistor driving sections, second generation semiconductor switching devices, third generation semiconductor switching devices, etc. Using the solution of the embodiment of the present invention, the driving circuit is connected to the semiconductor device 2204 through a high-density integrated bridge interconnection solution of a through-hole type, and the driving contact connection corresponding to the source and drain of the driving circuit can be arbitrarily selected according to the needs, and the semiconductor devices 2204 can be connected in series and parallel.

[0317] In an embodiment of the present invention, the integration of one or more layers of target wafers and semiconductor devices may be further included. The target wafers and devices include, but are not limited to, first, second, and third generation semiconductor materials and devices, as well as materials and devices in the fields of OLED (Organic Light-Emitting Diode) and MEMS (Micro-Electro-Mechanical System), and may be semiconductor or optoelectronic material systems and devices made of silicon, germanium, arsenic, gallium, and other materials. When multiple layers of target wafers and semiconductor devices are integrated, the stacking scheme of the final device may be vertically distributed or vertically distributed at different horizontal positions.

[0318] In the embodiment of the present invention, the first electrodes 22041 are electrically interconnected in common, and in the electrical interconnection structure of the second electrodes 22042, the second electrodes 22042 can be connected to a single semiconductor device or multiple semiconductor devices (that is, on the basis of the common electrical interconnection of the first electrodes 22041, connections can also be established between the second electrodes 22042 of multiple semiconductor devices), so that a parallel relationship is formed between the multiple semiconductor devices. This ensures that when a single semiconductor device fails, the other semiconductor devices can still work normally, thereby reducing the impact of dead spots on the use and yield of the overall integrated circuit.

[0319] In the preparation method of the common-pole semiconductor device and the common-pole semiconductor device of the embodiment of the present invention, the first electrode is common, and there is no need for a one-to-one correspondence between the bonding conductive layer and the first electrode (semiconductor device), which avoids the problem of adhesion firmness of the bonding conductive layer (bonding metal) after patterning due to the small size of the semiconductor device, and the problem of electrical connection performance caused by the thickness of the bonding metal, such as the uniformity of current diffusion and heat dissipation, thereby improving the integration and reliability. In the embodiment of the present invention, the first electrode of the semiconductor device is common, and the second electrode can be bridged at the same driving contact at the same time, so that multiple semiconductor devices are connected in parallel and have the same function, which maximizes the failure of the entire device caused by the failure of a single semiconductor device, and improves the reliability of the entire device. In addition, in the embodiment of the present invention, the spacing between semiconductor devices can be reduced by through-holes, and small-sized through-holes are used, and the bonding conductive layer does not need to be completely isolated, thereby achieving a larger active area or higher integration under the condition of the same size device. By adopting the method of the present invention, the contact mode can be freely defined, and common or non-common bridges can be freely used, and the series-parallel scheme between semiconductor devices is more convenient.

[0320] Example 3

[0321] like Fig.13 As shown, the method for preparing a compound semiconductor device provided by an embodiment of the present invention mainly comprises the following steps:

[0322] Step 301, providing a first substrate, and preparing a semiconductor stacking structure on the entire surface of the first substrate, wherein the semiconductor stacking structure includes a transition semiconductor layer, a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer stacked outward from the surface of the first substrate;

[0323] Step 302: pattern-etching the semiconductor stack structure from one side of the second conductive type semiconductor layer to form a first pattern-etched structure exposed to the first conductive type semiconductor layer, wherein the first pattern-etched structure penetrates the second conductive type semiconductor layer but does not penetrate the first conductive type semiconductor layer;

[0324] Step 303, preparing a second contact electrode and a first contact electrode on the surface of the second conductive type semiconductor layer and the surface of the first conductive type semiconductor layer exposed at the bottom of the first patterned etched structure, respectively;

[0325] Step 304, preparing an insulating passivation layer in the first patterned etching structure;

[0326] Step 305, providing a driving backplane including driving contacts, and electrically connecting the second contact electrodes to the driving contacts one-to-one;

[0327] Step 306 : performing patterned etching on the semiconductor stack structure to form a second patterned etching structure exposing a portion of the first contact electrode from a side away from the second conductive type semiconductor layer and close to the first conductive type semiconductor layer.

[0328] In the process of preparing the compound semiconductor device of the embodiment of the present invention, the device area (including the second contact electrode and the first contact electrode) is defined by a graphic etching method after the semiconductor stacking structure is prepared on the first substrate. The method of preparing the compound semiconductor device of the embodiment of the present invention does not use a graphic growth method. Therefore, the compound semiconductor device prepared by the method of the embodiment of the present invention does not have defects in some material layers (functional layers) such as those caused by the selective growth method (graphic growth) in patent TW202006968A. At the same time, in the compound semiconductor device prepared by the method of the embodiment of the present invention, the second contact electrode is electrically connected to the driving contact one-to-one, so there is no common electrode connection between the second contact electrodes. The first contact electrode can also realize a non-common electrode connection structure by preparing the corresponding functional structure as needed, instead of the inevitable situation of the device being common through the first semiconductor layer as in patent TW202006968A, so the signal crosstalk problem caused by the common electrode between devices can be avoided. On the whole, the compound semiconductor device prepared by the method of preparing the compound semiconductor device of the embodiment of the present invention can improve the performance of the compound semiconductor device as a whole.

[0329] In an optional embodiment, the material of the first substrate includes sapphire, silicon carbide, silicon, gallium nitride, gallium arsenide, gallium oxide, diamond, etc. In an optional embodiment, the first substrate can be planar or micro-patterned (180 nanometers to 5 micrometers).

[0330] In an optional embodiment, the surface of the first substrate is cleaned before preparing the semiconductor stacking structure on the entire surface of the first substrate, which may specifically include: hydrogenating the surface of the first substrate at a high temperature of 600° C. to 1300° C. (placing it in a hydrogen atmosphere for 1 to 20 minutes).

[0331] In an optional embodiment, a transition semiconductor layer is grown on the surface of a cleaned first substrate at a growth temperature ranging from room temperature to 1200°C. The material of the transition semiconductor layer may be gallium nitride, gallium oxide, gallium arsenide, silicon carbide, aluminum nitride, aluminum gallium indium phosphide (AlGaInP), aluminum gallium indium nitride (AlGaInN) and other III-V compounds and their multi-element alloys. The transition semiconductor layer may include a stacked structure of different combinations of these materials. The transition semiconductor layer may also be special thin film materials such as graphene, silicon oxide, aluminum oxide, diamond, etc. The transition semiconductor layer may be a whole surface or a patterned surface. The transition semiconductor layer may also be a combination of the above-mentioned III-V compounds and the above-mentioned special thin film materials.

[0332] In an optional embodiment, the preparation method of the transition semiconductor layer includes methods such as MOCVD (Metal-organic Chemical Vapor Deposition), Sputter (sputtering) process, and can also include ALD (Atomic Layer Deposition), HVPE (Hydride Vapor Phase Epitaxy), MBE (Molecular Beam Epitaxy) and other thin film preparation methods and other methods of transferring the film layer to the substrate, including bonding, assembly, etc.

[0333] In the embodiment of the present invention, the main function of the transition semiconductor layer is to improve the lattice, dislocation, thermal expansion and stress mismatch problems between the first substrate and the subsequent compound semiconductor (first conductivity type semiconductor layer, second conductivity type semiconductor layer, etc.).

[0334] In an alternative embodiment, the transition semiconductor layer has a thickness of 1 nanometer to 5 micrometers.

[0335] In an optional embodiment, the first conductive type semiconductor layer is an N-type semiconductor layer, and the second conductive type semiconductor layer is a P-type semiconductor layer; or, the first conductive type semiconductor layer is a P-type semiconductor layer, and the second conductive type semiconductor layer is an N-type semiconductor layer.

[0336] In an optional embodiment, the material of the first conductive type semiconductor layer can be III-V compounds such as gallium nitride, gallium oxide, gallium arsenide, silicon carbide, aluminum nitride, aluminum gallium indium phosphide, aluminum gallium indium nitride and their multi-element alloys. The material of the first conductive type semiconductor layer can include a stacked structure in different combinations of these materials, and form N-type (such as silicon doping) or P-type (such as magnesium doping) by appropriate element doping. The material of the first conductive type semiconductor layer can also include special thin film crystals such as graphene, silicon nitride, silicon oxide, and aluminum oxide. The special thin film crystals can be randomly distributed or arranged in an orderly manner.

[0337] In an optional embodiment, the preparation method of the first conductive type semiconductor layer and the special thin film crystal structure therein includes thin film preparation methods such as MOCVD, Sputter process, ALD, PECVD (Plasma Enhanced Chemical Vapor Deposition), HVPE, MBE, and other methods of transferring other film layers to the substrate, including growth, bonding, assembly, thin film coating and patterning.

[0338] In the embodiment of the present invention, the first conductive type semiconductor layer is mainly used to form an N-type or P-type semiconductor structure.

[0339] In an alternative embodiment, the thickness of the first conductive type semiconductor layer is 200 nanometers to 5 micrometers.

[0340] In an optional embodiment, the material of the second conductive type semiconductor layer can be gallium nitride, gallium oxide, gallium arsenide, silicon carbide, aluminum nitride, aluminum gallium indium phosphide, aluminum gallium indium phosphide and other III-V compounds and their multi-element alloys. The material of the second conductive type semiconductor layer can include a stacked structure in the form of different combinations of these materials, and form a P-type (such as magnesium doping) or N-type (such as silicon doping) by appropriate element doping.

[0341] In an optional embodiment, when the semiconductor stacking structure is entirely prepared on the first substrate in step 301, the method for preparing a compound semiconductor device in the embodiment of the present invention may further include:

[0342] An active region or a high electron mobility film layer is formed between the first conductive type semiconductor layer and the second conductive type semiconductor layer.

[0343] In an optional embodiment, the active region or the high electron mobility film layer may be arranged inside the second conductive type semiconductor layer or between the second conductive type semiconductor layer and the first conductive type semiconductor layer, and the active region or the high electron mobility film layer includes quantum wells, two-dimensional electrical channels, optical DBR (Distributed Bragg Reflection), current blocking layers and other structures.

[0344] In an optional embodiment, the preparation method of the second conductive type semiconductor layer includes thin film preparation methods such as MOCVD, Sputter process, ALD, PECVD, HVPE, MBE and other methods of transferring other film layers to the substrate, including growth, bonding, assembly, thin film coating and patterning.

[0345] In the embodiment of the present invention, the second conductive type semiconductor layer is mainly used to form a P-type or N-type semiconductor structure.

[0346] In an alternative embodiment, the thickness of the second conductive type semiconductor layer is 80 nanometers to 3 micrometers.

[0347] In an optional embodiment, the cross section of the first graphic etching structure in step 302 can be a vertical, regular trapezoidal or inverted trapezoidal structure, and cross-sectional structures of different shapes can be selected according to the target device to be prepared. For example, if the target device to be prepared is an electronic device, the first graphic etching structure with a vertical cross-sectional structure is preferred, and if the target device to be prepared is a photoelectric device, the first graphic etching structure with a regular trapezoidal or inverted trapezoidal cross-sectional structure is preferred. In a preferred embodiment, the angle between the side wall and the bottom of the regular trapezoid or inverted trapezoid is optimally 55°.

[0348] In an optional embodiment, the first contact electrode corresponds to the first conductive type semiconductor layer, and the second contact electrode corresponds to the second conductive type semiconductor layer. If the first conductive type semiconductor layer is an N-type semiconductor layer and the second conductive type semiconductor layer is a P-type semiconductor layer, the first contact electrode is an N-type contact electrode and the second contact electrode is a P-type contact electrode; if the first conductive type semiconductor layer is a P-type semiconductor layer and the second conductive type semiconductor layer is an N-type semiconductor layer, the first contact electrode is a P-type contact electrode and the second contact electrode is an N-type contact electrode.

[0349] In an optional embodiment, only the first contact electrode or only the second contact electrode may be prepared.

[0350] In optional embodiments, the materials of the first contact electrode and the second contact electrode may include one or more stacked-layer structures of metals such as chromium, titanium, aluminum, nickel, silver, gold, platinum, germanium, and zinc, or one or more stacked-layer structures of metal oxides such as indium tin oxide and zinc oxide, or may include mixed film layers of these metals and metal oxides.

[0351] In an optional embodiment, the first contact electrode and the second contact electrode may be prepared by patterned metal evaporation, sputtering coating method, or the contact electrodes may be prepared first and then patterned. In an optional embodiment, the first contact electrode and the second contact electrode may be prepared at the same time, or the first contact electrode and the second contact electrode may be prepared separately. In an optional embodiment, after the electrode film layer of the first contact electrode and the second contact electrode is prepared, high temperature alloy and other related treatments may be performed to obtain the required contact, such as ohmic contact or Schottky contact.

[0352] In the embodiment of the present invention, the insulating passivation layer is used to prevent the sidewalls of the exposed first conductive type semiconductor layer in the first patterned etched structure from having problems such as leakage, dangling bonds adhering to foreign particles, and insulation.

[0353] In an optional embodiment, the insulating passivation layer may be filled only in the first patterned etched structure, or may be filled entirely (including the first patterned etched structure and the surface of the second conductive type semiconductor layer) and then the second contact electrode may be exposed.

[0354] In an optional embodiment, the material of the insulating passivation layer can be dielectric materials such as silicon nitride, silicon oxide, aluminum oxide and their stacked structures. The material of the insulating passivation layer can also be a non-conductive compound semiconductor material that is the same as the material of the transition semiconductor layer. The material of the insulating passivation layer can also be an organic material such as SU8 (a photosensitive silicone type material), polyimide, and polymer.

[0355] In an optional embodiment, the insulating passivation layer can be prepared by CVD, ALD, leveling, etc.

[0356] In alternative embodiments, the driver backplane may contain a driver circuit, or the driver backplane may contain a circuit arrangement electrically connected to the driver contacts by the driver circuit.

[0357] In an optional embodiment, in step 306, a second patterned etching structure is prepared by deep trench etching to expose a portion of the first contact electrode from one side of the first conductive type semiconductor layer, and another portion of the first contact electrode is still in electrical contact with the first conductive type semiconductor layer material at the bottom of the first patterned etching structure. The first conductive type semiconductor layer of a single area or the first conductive type semiconductor layer of the surrounding area of ​​the prepared device can be exposed by designing the second patterned etching structure.

[0358] In an optional embodiment, the shape of the second patterned etched structure can be a common shape such as a single through hole, an annular groove, a rectangular groove, etc. In an optional embodiment, the sidewall morphology of the deep groove etching of the second patterned etched structure can be vertical, a regular trapezoid, etc., preferably a vertical type. The width of the second patterned etched structure (such as the through hole width, the groove width) is 1 micron to 200 microns.

[0359] The first contact electrode exposed in the second patterned etched structure can be integrated with other semiconductor devices in a series-parallel manner.

[0360] The compound semiconductor device after completing the above steps 301 to 306 is equivalent to the precursor (i.e., the basic device) in patent TW202006968A, on which the corresponding functional structure can be prepared as needed, and finally the preparation of the required semiconductor device (device) is completed. Therefore, in an optional embodiment, the method of the compound semiconductor device of the embodiment of the present invention can further include the following after completing step 306:

[0361] Step 307: Prepare a functional structure on one side of the first substrate.

[0362] In an optional embodiment, the semiconductor device structure does not include the first substrate portion. With this optional embodiment, the possibility of the first contact electrode being connected via the first substrate common electrode can be eliminated, thereby eliminating signal crosstalk between devices caused by the common electrode.

[0363] Therefore, in an optional embodiment, after completing the one-to-one electrical connection between the second contact electrodes and the driving contacts in step 305, the method for preparing a compound semiconductor device according to the embodiment of the present invention further includes: removing the first substrate.

[0364] The step of removing the first substrate may be performed before step 306 or after step 306 .

[0365] In addition, in other embodiments that require a first substrate for preparing a functional device, the step of removing the first substrate may not be performed, and the first substrate may be subjected to corresponding patterning etching as required to form a component of the functional device.

[0366] In addition, in an optional embodiment, the transition semiconductor layer may be retained or removed as required.

[0367] In an optional embodiment, if the first substrate and the transition semiconductor layer are retained, the first substrate (or the first substrate and the transition semiconductor layer together) can be patterned and etched as needed in subsequent processes to obtain a desired structure, such as a hemispherical, conical, or other structure.

[0368] In an optional embodiment, the functional structure prepared on the first substrate side may include a metal bridging structure, an interconnection structure, an optical color conversion structure, and the like.

[0369] On this basis, in an optional embodiment, preparing a functional structure on one side of the first substrate in step 307 may include:

[0370] A metal bridge structure or an interconnection structure connecting the first contact electrode with other semiconductor devices is prepared in the second patterned etching structure.

[0371] Alternatively, preparing the functional structure on the first substrate side in step 307 may include:

[0372] Step 3071, preparing an insulating layer filled in the second patterned etching structure and having a height higher than the opening position of the second patterned etching structure, and forming a pit structure surrounded by the insulating layer;

[0373] Step 3072: Fill the pit structure with a color difference conversion material and seal the pit structure to form an optical color conversion structure.

[0374] Wherein, step 3071 and step 3072 are steps for preparing an optical color conversion structure.

[0375] It should be noted that, according to the requirements of semiconductor integrated circuit design, different functional structures such as metal bridging structure, interconnection structure, optical color conversion structure, etc. may exist on the same semiconductor stacking structure at the same time, or only one or several of the functional structures may exist. Different functional structures can be prepared in different areas of the same semiconductor stacking structure according to different functional area divisions.

[0376] In an optional embodiment, the material of the insulating layer used in step 3071 is, for example, an insulating dielectric material, a photoresist, SU8 (a photosensitive silicone type material), etc.

[0377] In an optional embodiment, the color difference conversion material is, for example, quantum dots, phosphors, and the like.

[0378] In an optional embodiment, the material used to seal the pit structure in step 3072 is, for example, silicon oxide, aluminum oxide, etc.

[0379] In an optional embodiment, step 305 of electrically connecting the second contact electrode to the drive contact one-to-one includes:

[0380] The second contact electrodes are electrically connected to the driving contacts one-to-one by means of alignment bonding, welding or electrode bridging.

[0381] In order to meet the requirements of miniaturization and high-density integration, preferably, the second contact electrode is electrically connected to the drive contact one-to-one by using an alignment bonding method. In this preferred embodiment, the second contact electrode is electrically connected to the drive contact one-to-one by using an alignment bonding method, including:

[0382] The driving contact is aligned with the second contact electrode, and the driving back plate is bonded to the second conductive type semiconductor layer.

[0383] The distribution of the driving contacts on the surface of the driving back plate matches the distribution of the second contact electrodes on the surface of the second conductive type semiconductor layer.

[0384] In an optional embodiment, the material used for the electrical connection between the second contact electrode and the drive contact may be the material of the second contact electrode and the drive contact itself, or may be at least one of welding metal materials such as gold, tin, copper, nickel, indium, or an alloy composed of at least two of these metal materials, or may be a non-metallic material such as silicon oxide, polymer, etc. filled in the non-electrode area. If the material used for the electrical connection between the second contact electrode and the drive contact is a non-metallic material such as silicon oxide, polymer, etc. filled in the non-electrode area, it is necessary to prepare a conductive bridge on the non-metallic material such as silicon oxide, polymer, etc. filled in the non-electrode area to electrically connect the second contact electrode and the drive contact.

[0385] The method for preparing a compound semiconductor device according to an embodiment of the present invention is further described below in conjunction with a specific example of a process for preparing a compound semiconductor device.

[0386] Step 3a1: Fig.14A As shown, compound semiconductor wafer preparation.

[0387] First, a suitable first substrate 3101 is selected, including sapphire, silicon carbide, silicon, gallium nitride, gallium arsenide, gallium oxide, diamond and other materials that can be used as the first substrate 3101. The first substrate 3101 can be planar or micro (180 nanometers to 5 micrometers) patterned.

[0388] After the first substrate 3101 is treated with high-temperature hydrogenation at 600°C to 1300°C (placed in a hydrogen atmosphere for 1 to 20 minutes) to complete surface cleaning, a transition semiconductor layer 3102 is grown, and the growth temperature is in the range of room temperature to 1200°C. The transition semiconductor layer 3102 can be GaN (gallium nitride), Ga2O3 (gallium oxide), GaAs (gallium arsenide), SiC (silicon carbide), AlN (aluminum nitride), AlGaInP, AlGaInN and other III-V group three-five compounds and multi-element alloys thereof. The transition semiconductor layer 3102 includes different combination stacks of these materials. The transition semiconductor layer 3102 can also be special thin film materials such as graphene, SiO2 (silicon oxide), Al2O3 (aluminum oxide), diamond, etc. The transition semiconductor layer 3102 can be a whole-surface film layer or a patterned film layer, and the transition semiconductor layer 3102 can also be a combination of III-V compounds and special thin film materials. In addition to conventional MOCVD, Sputter sputtering and other methods, the first semiconductor can also be prepared by thin film preparation methods such as ALD, HVPE, MBE, or other methods of transferring other film layers to the substrate, including bonding, assembly, etc. The transition semiconductor layer 3102 is mainly used to improve the lattice, dislocation, thermal expansion and stress mismatch problems between the first substrate 3101 and the subsequent compound semiconductor. The thickness of the transition semiconductor layer 3102 is in the range of 1 nanometer to 5 micrometers.

[0389] After the transition semiconductor layer 3102 is completed, the first conductive type semiconductor layer 3103 is prepared. The first conductive type semiconductor layer 3103 can be N-type or P-type. The first conductive type semiconductor layer 3103 can be GaN, Ga2O3, GaAs, SiC, AlN, AlGaInP, AlGaInN and other III-V compounds and multi-element alloys thereof. The first conductive type semiconductor layer 3103 includes different combinations of these materials. The first conductive type semiconductor layer 3103 is formed into N-type (such as Si doping) or P-type (such as Mg doping) by appropriate element doping. The first conductive type semiconductor layer 3103 can include special thin film crystals such as graphene, silicon nitride, SiO2, Al2O3, etc., and the special thin film crystals can be randomly distributed or arranged in an orderly manner. The first conductive type semiconductor layer 3103 and the special thin film crystal preparation method therein include thin film preparation methods such as MOCVD, Sputter sputtering, ALD, PECVD, HVPE, MBE, or other methods of transferring the film layer to the substrate, including growth, bonding, assembly, thin film coating and patterning. The first conductive type semiconductor layer 3103 is mainly used to form an N-type or P-type semiconductor structure. The thickness of the first conductive type semiconductor layer 3103 is 200 nanometers to 5 micrometers.

[0390] After the first conductive type semiconductor layer 3103 is completed, the second conductive type semiconductor layer 3104 is prepared. According to the requirements, the second conductive type semiconductor layer 3104 can be P-type or N-type. The second conductive type semiconductor layer 3104 can be GaN, Ga2O3, GaAs, SiC, AlN, AlGaInP, AlGaInN and other III-V compounds and multi-element alloys thereof, and the second conductive type semiconductor layer 3104 includes different combinations of these materials. The second conductive type semiconductor layer 3104 is formed into a P-type (such as Mg doping) or an N-type (such as Si doping) by appropriate element doping. At the same time, an active area or a high electron mobility film layer (not shown in the figure) can be arranged inside the second conductive type semiconductor layer 3104 or between the second conductive type semiconductor layer 3104 and the first conductive type semiconductor layer 3103, and the active area or high electron mobility film layer includes quantum wells, two-dimensional electrical channels, optical DBRs, current blocking layers and other structures. The preparation method of the second conductive type semiconductor layer 3104 includes thin film preparation methods such as MOCVD, Sputter sputtering, ALD, PECVD, HVPE, MBE, or other methods of transferring other film layers to a substrate, including growth, bonding, assembly, thin film coating, and patterning. The second conductive type semiconductor layer 3104 is mainly used to form a P-type or N-type semiconductor structure. The thickness of the second conductive type semiconductor layer 3104 is 80 nanometers to 3 micrometers.

[0391] Step 3a2: Fig. 14B As shown, a first patterned etching structure 3105 is prepared.

[0392] The second conductive type semiconductor layer 3104 is patterned and etched by etching or cutting to form a first patterned etched structure 3105. The first patterned etched structure 3105 is exposed to the first conductive type semiconductor layer 3103, that is, the first patterned etched structure 3105 penetrates the second conductive type semiconductor layer 3104 but does not penetrate the first conductive type semiconductor layer 3103. Fig. 14B As shown, the side wall angle of the first graphic etching structure 3105 can be a vertical structure, a regular trapezoidal structure or an inverted trapezoidal structure. The specific structure is selected depending on the target device to be prepared. For example, a vertical structure is preferred for electronic devices, and a trapezoidal structure is preferred for optoelectronic devices. Regardless of the regular trapezoidal or inverted trapezoidal structure, the angle between the side wall and the bottom surface of the first graphic etching structure 3105 (side wall inclination angle) is optimally 55°.

[0393] Step 3a3: Fig. 14C As shown, prepare the contact electrodes.

[0394] Common devices require the preparation of two types of contact electrodes, namely, a P-type contact electrode and an N-type contact electrode, and the number of actual contact electrodes may range from one to more.

[0395] The preparation of the contact electrode may include a first contact electrode 3106 on the first conductive type semiconductor layer 3103 and a second contact electrode 3107 on the second conductive type semiconductor layer 3104, or only a single contact electrode of the first contact electrode 3106 on the first conductive type semiconductor layer 3103 or the second contact electrode 3107 on the second conductive type semiconductor layer 3104. The materials of the first contact electrode 3106 and the second contact electrode 3107 may include one or more stacked structures of metals such as Cr (chromium), Ti (titanium), Al (aluminum), Ni (nickel), Ag (silver), Au (gold), Pt (platinum), Ge (germanium), Zn (zinc), or one or more stacked layers of metal oxides such as indium tin oxide and zinc oxide, as well as a mixed film layer of metals and metal oxides.

[0396] The contact electrode is prepared by patterned metal evaporation or sputtering coating, or the contact electrode is prepared first and then patterned. The first contact electrode 3106 and the second contact electrode 3107 can be prepared together, or the first contact electrode 3106 and the second contact electrode 3107 can be prepared separately. After the preparation of the electrode film layer of the contact electrode is completed, the electrode film layer can be subjected to relevant treatments such as high-temperature alloy to obtain the required contact, such as ohmic contact or Schottky contact.

[0397] Step 3a4: Fig.14D As shown, passivation treatment.

[0398] An insulating passivation layer 3108 is prepared in the first patterned etched structure 3105. Fig.14D As shown, the insulating passivation layer 3108 can be filled only in the first patterned etched structure 3105. In addition, Fig.15 Another morphology structure of the insulating passivation layer 3108 is shown. The insulating passivation layer 3108 can be fully filled on the surface of the first patterned etching structure 3105 and the second conductive type semiconductor layer 3104, and then the second contact electrode 3107 is exposed.

[0399] The material of the insulating passivation layer 3108 can be dielectric materials such as silicon nitride, SiO2, Al2O3 and their stacks, or it can be a non-conductive compound semiconductor material that is the same as the material of the transition semiconductor layer 3102, or it can be an organic material such as SU8, polyimide, polymer, etc.

[0400] The insulating passivation layer 3108 can be prepared by CVD, ALD, uniform coating, etc.

[0401] The passivation treatment (the prepared insulating passivation layer 3108 ) can prevent the sidewalls of the first conductive type semiconductor layer 3103 exposed in the first patterned etching structure 3105 from having problems such as leakage, dangling bonds adhering to impurity particles, and insulation.

[0402] Step 3a5: Fig.14E As shown, the drive is connected.

[0403] A driving backplane 3201 is provided that includes driving contacts 3202. The driving backplane 3201 may include a driving circuit, or a circuit arrangement that connects the driving circuit and the driving contacts 3202.

[0404] The second contact electrode 3107 is connected to the driving contact 3202 in a one-to-one manner, and the connection method includes alignment bonding, welding, electrode bridge connection, etc. Fig.14E Shown is a structure connected by alignment bonding.

[0405] The material connecting the second contact electrode 3107 and the driving contact 3202 can be the original material of the second contact electrode 3107 and the driving contact 3202, or it can be at least one of the welding metal materials such as Au, Sn (tin), Cu (copper), Ni, In (indium), etc., or an alloy composed of at least two of these metal materials, or it can be a non-metallic material such as SiO2, polymer, etc. filled in the non-electrode area.

[0406] Step 3a6: Fig.14F As shown, the first contact electrode 3106 is exposed.

[0407] In this step, the semiconductor stack structure is patterned and etched from a side away from the second conductive type semiconductor layer 3104 and close to the first conductive type semiconductor layer 3103 to form a second patterned etched structure 3203 that exposes a portion of the first contact electrode 3106 from a side away from the second conductive type semiconductor layer 3104 and close to the first conductive type semiconductor layer 3103.

[0408] In this step, the first substrate 3101 and the transition semiconductor layer 3102 can be retained or removed according to the requirements, for example Fig.14F As shown in the figure, the first substrate 3101 is removed and the transition semiconductor layer 3102 is retained. If the first substrate 3101 and the transition semiconductor layer 3102 are retained, corresponding pattern etching can be performed according to requirements, including hemispherical, pointed cone and other structures, for example Fig.16A The hemispherical and conical structures etched on the first substrate 3101 are shown, and Fig. 16B As shown, the first substrate 3101 is removed and a conical structure is etched out in the transition semiconductor layer 3102 .

[0409] In this step, the device preparation area and shape can be confirmed according to the position of the driving contact 3202 on the driving backplane 3201 and the first contact electrode 3106 connected to the first conductive type semiconductor layer 3103 (for example, alignment can be performed by using infrared or far infrared to penetrate relevant materials, which can include front alignment technology and back alignment technology, or edge alignment can be performed using the wafer contour), and the transition semiconductor layer 3102 (if not removed) and the first conductive type semiconductor layer 3103 are etched by a deep groove etching method to form a second patterned etching structure 3203, and part of the material of the first contact electrode 3106 that forms electrical contact with the first conductive type semiconductor layer 3103 is exposed from the bottom of the second patterned etching structure 3203, and another part of the material of the first contact electrode 3106 continues to maintain electrical contact with the first conductive type semiconductor layer 3103. Fig.17 As shown, the second graphic etching structure 3203 can expose the first conductive type semiconductor layer 3103 in a single area or expose the first conductive type semiconductor layer 3103 in the surrounding area of ​​the prepared device. The shape of the second graphic etching structure 3203 can be a single through hole, a rectangle, a ring, etc.

[0410] The width of the second graphic etching structure 3203 (such as the through hole width, the groove width) is 1 micron to 3200 microns, and the exposed first contact electrode 3106 can be integrated with other devices in series and parallel. The sidewall morphology of the second graphic etching structure 3203 can be vertical or inclined, preferably vertical.

[0411] Fig.16A , Fig. 16B 1 shows a structure in which adjacent devices are connected in common at the same first contact electrode 3106. This structure can realize parallel connection between devices. In other optional embodiments, adjacent devices can be connected as follows: Fig.19 In the structure shown, each device is electrically connected to only one first contact electrode 3106. In this way, individual circuit control for each device can be achieved.

[0412] Step 3a7, prepare other structures.

[0413] In this step, subsequent structures can be prepared based on the structure prepared in step 3a6 according to needs. For example, the deep groove exposed by the second contact electrode 3107 is filled or a concave or convex step is prepared, and after filling, the electrical connection is enhanced or subsequent structures are prepared, such as metal bridges for current expansion enhancement, signal enhancement, interconnection of other devices for signal reception, optical color conversion and other structures.

[0414] like Fig.18As shown, an optical color conversion structure is shown. The process of the optical color conversion structure is as follows:

[0415] An insulating layer 3301 is prepared to be filled in the second patterned etched structure 3203 and to be higher than the opening position of the second patterned etched structure 3203 (i.e., the surface of the transition semiconductor layer 3102), and a pit structure 3302 is formed surrounded by the insulating layer 3301. The color difference conversion material 3303 is filled in the pit structure 3302, and the pit structure 3302 is sealed to form an optical color conversion structure. The material of the insulating layer 3301 is, for example, an insulating dielectric material, a photoresist, an organic substance such as SU8, and the color difference conversion material 3303 is, for example, a material such as a quantum dot, a phosphor, etc. The sealing of the pit structure 3302 can be wrapped with SiO2 or Al2O3.

[0416] The present invention also provides a compound semiconductor device. Fig.14F As shown, it includes a driving backplane 3201, a second conductive type semiconductor layer 3104, a first conductive type semiconductor layer 3103, a second contact electrode 3107, a first patterned etching structure 3105, a first contact electrode 3106, an insulating passivation layer 3108 and a second patterned etching structure 3203. Among them, the driving backplane 3201 contains a driving contact 3202. The first conductive type semiconductor layer 3103 is stacked on the second conductive type semiconductor layer 3104. The second contact electrode 3107 is located on the surface of the second conductive type semiconductor layer 3104 facing the driving backplane 3201, and the second contact electrode 3107 is electrically connected to the driving contact 3202 one by one. The first patterned etching structure 3105 is located in the second conductive type semiconductor layer 3104 and a part of the first conductive type semiconductor layer 3103, that is, the first patterned etching structure 3105 penetrates the second conductive type semiconductor layer 3104 but does not penetrate the first conductive type semiconductor layer 3103.

[0417] The first contact electrode 3106 is located on the first conductive type semiconductor layer 3103 at the bottom of the first patterned etching structure 3105. The insulating passivation layer 3108 is located in the first patterned etching structure 3105. The second patterned etching structure 3203 is located in the first conductive type semiconductor layer 3103, and the second patterned etching structure 3203 is located on a side away from the second conductive type semiconductor layer 3104 and close to the first conductive type semiconductor layer 3103, and a portion of the first contact electrode 3106 is exposed from the second patterned etching structure 3203.

[0418] In the preparation method of the compound semiconductor device and the compound semiconductor device of the embodiment of the present invention, after the entire surface of the semiconductor stacking structure is prepared on the first substrate, a device area including the second contact electrode and the first contact electrode is defined by a graphical etching method. The embodiment of the present invention does not adopt a graphical growth method. Therefore, there are no defects in the material layer or functional layer caused by selective growth or graphical growth.

[0419] At the same time, in the embodiment of the present invention, the second contact electrode is electrically connected to the driving contact one-to-one. Therefore, there is no common pole connection between the second contact electrodes. The first contact electrode can be prepared with a corresponding functional structure as needed to realize a non-common pole connection structure of the first contact electrode, thereby avoiding signal crosstalk problems caused by common poles between devices.

[0420] In addition, in the embodiment of the present invention, the first contact electrode and the second contact electrode are not on the first substrate. Therefore, the electrical connection structure does not involve connection on the substrate, thereby solving the problem that the first substrate must be removed to make an electrical connection and the problem that the requirements for making an electrical connection on the first substrate are high.

[0421] On the whole, the method for preparing a compound semiconductor device and the compound semiconductor device according to the embodiments of the present invention can improve the performance of the compound semiconductor device as a whole.

[0422] Example 4

[0423] like Fig. 20 As shown, the method for preparing a thin semiconductor device provided by an embodiment of the present invention mainly includes the following steps 40:

[0424] Step 401, providing a temporary substrate, preparing a contact electrode on the surface of the temporary substrate, and preparing a first inorganic material bonding layer on the surface of the temporary substrate including the contact electrode;

[0425] Step 402: providing a target wafer, wherein the target wafer includes a wafer substrate and a device material layer prepared on the wafer substrate, wherein the device material layer is used to form various functional layers in the semiconductor device;

[0426] Step 403, preparing a second inorganic material bonding layer on the surface of the device material layer;

[0427] Step 404: non-aligned bonding is performed on the first inorganic material bonding layer and the second inorganic material bonding layer to form an inorganic bonding layer;

[0428] Step 405: remove the wafer substrate, and perform a first patterning etching on the device material layer and the inorganic bonding layer to form a semiconductor device;

[0429] Step 406, electrically connecting the semiconductor device to the contact electrode;

[0430] Step 407: removing at least a portion of the temporary substrate, that is, removing a portion of the temporary substrate or removing the entire temporary substrate.

[0431] In an optional embodiment, the step 401 of preparing a contact electrode on the surface of the temporary substrate includes:

[0432] Step 4011, using a second patterned etching to prepare an electrode bearing structure on the surface of the temporary substrate;

[0433] Step 4012: Prepare contact electrodes on the electrode supporting structure.

[0434] In an optional embodiment, the material of the temporary substrate may be sapphire, silicon carbide, silicon, gallium nitride, gallium arsenide, glass, or a mixture or compound of these materials. Taking the temporary substrate as a silicon wafer as an example, the crystal orientation of the silicon wafer may be 100, 110, 111, or the like.

[0435] In an optional embodiment, the second patterning etching may include wet etching, dry etching, laser through-hole etching and other etching methods.

[0436] The electrode bearing structure may be a pit or a protrusion between pits prepared on the surface of the temporary substrate, and the contact electrode may be prepared in the pit or on the protrusion between the pits as required. In an optional embodiment, the graphic size defined by the electrode bearing structure may cover a size of 0.5 microns or more.

[0437] In an optional embodiment, the shape of the contact electrode can be a trapezoid, an inverted trapezoid, a sphere, an inverted triangle, a cube, a cuboid, a cylinder or a combination of these shapes.

[0438] In an optional embodiment, in step 4012, the material of the contact electrode can be prepared on the surface of the temporary substrate after completing step 4011 by chemical plating, electroplating, evaporation, sputtering, brushing, etc., and the patterned area etched by the second pattern can be completely filled as needed, or only a portion of the film layer can be covered. The process of preparing the contact electrode can also include the process of forming a contact electrode at a specified position by etching the material of the contact electrode.

[0439] In an optional embodiment, the material of the contact electrode is preferably a metal material, such as gold, platinum, titanium, tungsten, chromium, tin, nickel, aluminum, copper, indium, solder paste and other metal materials, as well as mixtures or compounds of these metal materials, or a metal oxide such as indium tin oxide, zinc oxide and other conductive materials. The thickness of the contact electrode is determined according to the size of the patterned electrode supporting structure.

[0440] In an optional embodiment, when the contact electrode is prepared on the surface of the temporary substrate, the method further includes:

[0441] A protective layer is prepared between the temporary substrate and the contact electrode.

[0442] On this basis, removing at least a portion of the temporary substrate in step 407 may include:

[0443] The protective layer between the temporary substrate and the contact electrode is removed together with the temporary substrate.

[0444] In an optional embodiment, when the contact electrode is prepared on the surface of the temporary substrate, the method further includes:

[0445] preparing a protective layer between the temporary substrate and the contact electrode and on the surface of the temporary substrate;

[0446] On this basis, removing at least a portion of the temporary substrate in step 407 may include:

[0447] The protection layer is removed by selective etching to remove the temporary substrate.

[0448] The material of the protective layer is, for example, a dielectric material such as silicon oxide, aluminum oxide, silicon nitride, or a polymer organic material such as polyimide, SU8, resin, etc. The function of the protective layer is to protect the contact electrode from damage or to prevent the contact electrode from merging with the temporary substrate.

[0449] After the contact electrode is prepared, the first inorganic material bonding layer is prepared on the surface of the temporary substrate including the contact electrode. In an optional embodiment, the first inorganic material bonding layer is prepared on the entire surface. In an optional embodiment, the material of the first inorganic material bonding layer can be part of the material selected for the contact electrode, or it can be one or more or at least two alloy materials of welding metal materials such as gold, tin, copper, nickel, indium, etc., or it can be non-metallic materials such as silicon oxide and silicon nitride. In an optional embodiment, the thickness of the first inorganic material bonding layer is 0.1 micron to 5 microns.

[0450] In an optional embodiment, after the contact electrode is prepared, and before the first inorganic material bonding layer is prepared on the surface of the temporary substrate including the contact electrode, step 401 further includes:

[0451] A first insulating layer is formed on the surface of the temporary substrate including the contact electrode.

[0452] On this basis, the first inorganic material bonding layer is prepared on the first insulating layer. The first insulating layer is located between the surface of the temporary substrate including the contact electrode and the first inorganic material bonding layer, ensuring the insulation between the subsequently prepared inorganic bonding layer and the contact electrode and between the inorganic bonding layer and the temporary substrate, avoiding the occurrence of short circuit.

[0453] In an optional embodiment, in step 403, the following steps may be further included before preparing the second inorganic material bonding layer on the surface of the device material layer:

[0454] A second insulating layer is prepared on the surface of the device material layer.

[0455] On this basis, the second inorganic material bonding layer is prepared on the second insulating layer. The second insulating layer is located between the surface of the device material layer and the second inorganic material bonding layer, ensuring the insulation between the subsequently prepared inorganic bonding layer and the device material layer to avoid the occurrence of short circuit.

[0456] In the embodiment of the present invention, the materials of the first inorganic material bonding layer, the second inorganic material bonding layer and the inorganic bonding layer are inorganic materials. In the embodiment of the present invention, the inorganic bonding layer adopts inorganic materials, and in the subsequent process of removing the temporary substrate, the mechanical strength of the support formed by the semiconductor device thereon is high. If the material of the inorganic bonding layer is a metal material, the electrical function (electrical and thermal conduction) of the thin semiconductor device can be enhanced. At the same time, the inorganic bonding layer material no longer introduces (does not have) organic materials, and thus the compatible use environment of the device is no longer affected by organic materials.

[0457] In an optional embodiment, the material of the wafer substrate in the target wafer may be a first-generation semiconductor material, a second-generation semiconductor material, or a third-generation semiconductor material, such as a sapphire substrate, a gallium arsenide substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, etc. The structure and material of the device material layer in the target wafer are determined according to design requirements. For example, if a light-emitting diode is to be prepared, the device material layer may include a buffer layer, an N-type layer, a quantum well layer, a P-type layer, etc. stacked on the wafer substrate.

[0458] In an optional embodiment, the second inorganic material bonding layer may include materials required for bonding with the first inorganic material bonding layer, such as one or more or alloy materials of at least two of welding metal materials such as gold, tin, copper, nickel, indium, etc., and may also be non-metallic materials such as silicon oxide and silicon nitride, and also include materials or film layers that can form electrical contact with the target wafer, such as metal nickel, gold, silver, indium tin oxide, etc. In addition, in an optional embodiment, between the second inorganic material bonding layer and the device material layer, structures such as a Bragg reflection layer, a surface plasma enhancement layer, a selective filter, etc. that can enhance or weaken the device performance may also be included.

[0459] In an alternative embodiment, the thickness of the second inorganic material bonding layer is 0.1 micrometers to 10 micrometers.

[0460] In an optional embodiment, in step 404, the first inorganic material bonding layer and the second inorganic material bonding layer are bonded using a bonding technology, thereby achieving the purpose of bonding the temporary substrate and the target wafer together.

[0461] In an optional embodiment, in step 405, the method of removing the wafer substrate includes laser stripping, grinding and thinning, dry etching or chemical cleaning and removal.

[0462] In an optional embodiment, in step 405, after removing the wafer substrate and before performing the first patterning etching on the device material layer and the inorganic bonding layer, the following may be further included:

[0463] The surface of the device material layer is etched to obtain an enhancement and / or a reduction structure on the surface of the device material layer.

[0464] The enhancing and / or weakening structures are, for example, cones, spheres, and other structures located on the surface of the device material layer.

[0465] In an optional embodiment, if multiple device integration is required, the above-mentioned method of bonding the temporary substrate and the target wafer can be referred to for bonding multiple layers of the target wafer. The specific method is as follows.

[0466] In an optional embodiment, in step 405, after removing the wafer substrate and before performing the first patterning etching on the device material layer and the inorganic bonding layer, bonding of the multi-layer target wafer may be further performed by the following method:

[0467] Providing at least one other target wafer, wherein the other target wafer comprises another wafer substrate and another device material layer prepared on the other wafer substrate and used for forming each functional layer in another semiconductor device;

[0468] bonding at least one other target wafer sequentially to the device material layer by non-aligned stack bonding;

[0469] Wherein, each bonding process is to stack and bond another device material layer in each other target wafer onto the device material layer through another inorganic bonding layer formed by non-aligned bonding between a third inorganic material bonding layer and a fourth inorganic material bonding layer;

[0470] Wherein, the third inorganic material bonding layer is prepared on the outermost device material layer that has been bonded to the temporary substrate, and the fourth inorganic material bonding layer is prepared on another device material layer on another target wafer that has not been bonded;

[0471] After each bonding of another target wafer is completed, the other wafer substrate of the other target wafer is removed.

[0472] In the above description, the names of another target wafer, another wafer substrate, another semiconductor device, and another device material layer are used to distinguish them from the aforementioned target wafer, wafer substrate, semiconductor device, and device material layer.

[0473] For example, if a double-layer device stacking structure is to be realized, then in step 405, after removing the wafer substrate and before performing the first patterning etching on the device material layer and the inorganic bonding layer, the following method may be further included:

[0474] Providing another target wafer, which may be named as a second target wafer, the second target wafer comprising a second wafer substrate and a second device material layer prepared on the second wafer substrate for forming each functional layer in a second semiconductor device;

[0475] bonding the second target wafer to the device material layer using non-aligned stack bonding;

[0476] Wherein, the bonding process is to stack and bond the second device material layer in the second target wafer onto the device material layer through another inorganic bonding layer formed by non-aligned bonding between the third inorganic material bonding layer and the fourth inorganic material bonding layer;

[0477] Wherein, the third inorganic material bonding layer is prepared on the device material layer, and the fourth inorganic material bonding layer is prepared on the second device material layer on the second target wafer;

[0478] After the bonding of the second target wafer is completed, the second wafer substrate of the second target wafer is removed.

[0479] For example, if a three-layer device stacking structure is to be implemented, the following steps are performed based on the above-mentioned two-layer device stacking structure:

[0480] Providing another target wafer, which may be named as a third target wafer, the third target wafer comprising a third wafer substrate and a third device material layer prepared on the third wafer substrate and used for forming each functional layer in a third semiconductor device;

[0481] bonding the third target wafer to the second device material layer using non-aligned stack bonding;

[0482] The bonding process is to stack and bond the third device material layer in the third target wafer onto the second device material layer through another inorganic bonding layer formed by non-aligned bonding between another third inorganic material bonding layer and another fourth inorganic material bonding layer;

[0483] Wherein, another third inorganic material bonding layer is prepared on the second device material layer, and another fourth inorganic material bonding layer is prepared on the third device material layer on the third target wafer;

[0484] After the bonding of the third target wafer is completed, the third wafer substrate of the third target wafer is removed.

[0485] If a device stacking structure with four or more layers is to be realized, the stacking bonding method of the second device material layer and the third device material layer described above may be referred to.

[0486] In an optional embodiment, if the above stacked structure is adopted, the first patterning etching of the device material layer and the inorganic bonding layer in step 405 to form a semiconductor device includes the following steps:

[0487] The at least one other device material layer and at least one other bonding layer stacked on the device material layer are simultaneously subjected to a first patterning etching to form a device stacking structure including a semiconductor device and at least one other semiconductor device stacked on the semiconductor device.

[0488] For example, if it is the above-mentioned double-layer device stacking structure, then:

[0489] The second device material layer and another inorganic bonding layer stacked on the device material layer are simultaneously subjected to a first patterning etching to form a device stacking structure including a semiconductor device and a second semiconductor device stacked on the semiconductor device.

[0490] For example, if it is the above three-layer device stacking structure, then:

[0491] The first graphic etching is performed simultaneously on the second device material layer, the third device material layer and two other inorganic bonding layers (one inorganic bonding layer is located between the device material layer and the second device material layer, and the other inorganic bonding layer is located between the second device material layer and the third device material layer) stacked on the device material layer to form a device stacking structure including a semiconductor device and a second semiconductor device and a third semiconductor device stacked on the semiconductor device.

[0492] Based on the above device stacking structure, while electrically connecting the semiconductor device to the contact electrode in step 406, the following steps are also included:

[0493] electrically connecting at least one other semiconductor device in the device stack structure to the contact electrode;

[0494] and / or,

[0495] At least one other semiconductor device in the device stack structure is electrically connected to the semiconductor device.

[0496] For example, for a double-layer device stacking structure, step 406 may further include:

[0497] The second semiconductor device is electrically connected to the contact electrode; and / or the second semiconductor device is electrically connected to the semiconductor device.

[0498] For example, for a three-layer device stacking structure, step 406 may further include at least one of the following steps:

[0499] The second semiconductor device is electrically connected to the contact electrode; the third semiconductor device is electrically connected to the contact electrode; the second semiconductor device is electrically connected to the third semiconductor device; the second semiconductor device is electrically connected to the semiconductor device; and the third semiconductor device is electrically connected to the semiconductor device.

[0500] The specific electrical connection depends on the design requirements.

[0501] In an optional embodiment, insulation protection can be performed between the metal or metal oxide used for electrical connection and the semiconductor device as needed. For example, the metal or metal oxide and the semiconductor device are isolated by an insulating layer, and the insulating layer material can be a low-K dielectric such as silicon oxide and silicon nitride, or a high-K dielectric such as hafnium oxide.

[0502] In an optional embodiment, the prepared semiconductor device may be a single device or an integration of multiple devices, and its integration method includes multiple semiconductor devices laid flat on the surface of the wafer substrate, and also includes multiple semiconductor devices of the stacked structure mentioned in the above description. In the electrical connection method of the multiple semiconductor devices in the laying direction, a suitable series, parallel or common pole scheme can be selected according to the design requirements, wherein the prepared contact electrodes can be defined in advance on the temporary substrate according to the series and parallel scheme of the multiple semiconductor devices. The number of contact electrodes corresponding to a single semiconductor device is at least 1 (for example, if the semiconductor device is a vertical device, it has one electrode at the top, and if the semiconductor device is a horizontal device, it has two electrodes, such as positive and negative electrodes. At the same time, in order to ensure reliability, the electrodes described above can also have multiple connecting wires or welding electrodes led out after multiple devices are connected in series and parallel). The contact electrodes can be distributed at any position. Considering the subsequent electrical connection of the semiconductor device, the contact electrodes are preferably distributed at positions close to the corners of the entire device, so that the electrode spacing can be maximized.

[0503] In the embodiment of the present invention, the purpose of performing step 407 is to release the semiconductor device. In an optional embodiment, step 407 includes: removing at least a portion of the temporary substrate by thinning, stripping or etching.

[0504] If there is a protective layer between the temporary substrate and the contact electrode, the protective layer is removed during the release process to expose the contact electrode.

[0505] In addition, depending on the material of the contact electrode, it can be selected whether to further perform high-temperature treatment to further optimize the shape of the contact electrode, such as converting a columnar solder paste material into a spherical shape after high-temperature reflow.

[0506] Wherein, when the temporary substrate is removed by etching, the method specifically includes:

[0507] The contact electrodes and a portion of the temporary substrate below the semiconductor device are hollowed out by etching.

[0508] In the process of etching and hollowing out, at least the inorganic bonding layer serves as a mechanical support structure between the temporary substrate and the contact electrodes and the semiconductor device.

[0509] When a protective layer exists between the temporary substrate and the contact electrode, the protective layer 4104 can be removed together when the temporary substrate is hollowed out.

[0510] The method for preparing a thin semiconductor device according to an embodiment of the present invention is further described below in conjunction with a specific example of a process for preparing a thin semiconductor device.

[0511] Step 4a1: Fig.21A As shown, patterning preparation on a temporary substrate 4101.

[0512] In this step, a temporary substrate 4101 of suitable material is selected. The material of the temporary substrate 4101 may include sapphire, silicon carbide, silicon, gallium nitride, gallium arsenide, glass, etc., and a mixture or compound of these materials may also be used as the material of the temporary substrate 4101. An electrode supporting structure 4102 is prepared on the surface of the temporary substrate 4101 by patterning etching. The electrode supporting structure 4102 may be as follows: Fig.21A The various groove structures or blind hole structures shown in the figure, the shape of the electrode supporting structure 4102 can be determined according to the shape of the contact electrode to be prepared, including trapezoidal, inverted trapezoidal, spherical, inverted triangle, cube, rectangular parallelepiped and cylindrical structures and their combined shapes, and the shapes of the contact electrodes subsequently prepared in the electrode supporting structure 4102 include trapezoidal, inverted trapezoidal, spherical, inverted triangle, cube, rectangular parallelepiped and cylindrical structures and their combined shapes.

[0513] Taking a silicon wafer as a temporary substrate 4101 as an example, the crystal orientation of the silicon wafer can be 100, 110, 111, etc., and the required shape (electrode supporting structure 4102) is prepared by etching schemes such as graphic wet etching or dry etching and laser through-hole etching. The shape can be Fig.21A Various pit shapes of the electrode supporting structure 4102 are shown in FIG.

[0514] The position distribution and size of the electrode supporting structure 4102 on the surface of the temporary substrate 4101, that is, the position distribution and size of the contact electrode subsequently manufactured, can limit the graphic size to cover a size of more than 0.5 microns.

[0515] Step 4a2: Fig.21B As shown, contact electrode 4103 is prepared.

[0516] in, Fig.21B And in the subsequent figures, only the preparation of the contact electrode 4103 on the trapezoidal electrode supporting structure 4102 is taken as an example. Fig.21B The shapes of three contact electrodes 4103 are shown in FIG. The contact electrodes 4103 can be prepared on the electrode supporting structure 4102 by chemical plating, electroplating, evaporation, sputtering, brushing, etc. Among them, the contact electrodes 4103 can be completely filled in the pits of the electrode supporting structure 4102 (for example, Fig.21B The contact electrode 4103 on the left side may also be covered with a partial film layer (e.g. Fig.21B The contact electrode 4103 in the middle and right side is shaped), and a protective layer 4104 (eg, Fig.21B The contact electrode 4103 and protective layer 4104 structure on the right).

[0517] In an optional embodiment, the contact electrode 4103 preferably uses a metal material, including metal materials such as gold, platinum, titanium, tungsten, chromium, tin, nickel, aluminum, copper, indium, solder paste, and a mixture or compound of at least two of these metal materials. Metal oxides such as indium tin oxide, zinc oxide, and other conductive materials can also be selected as the material of the contact electrode 4103. The thickness of the contact electrode 4103 depends on the size of the graphic after visualization.

[0518] In an optional embodiment, the material of the protective layer 4104 includes dielectric materials such as silicon oxide, aluminum oxide, silicon nitride, and polymer organic materials such as polyimide, SU8, and resin. The function of the protective layer 4104 is to protect the contact electrode 4103 from damage and to prevent the contact electrode 4103 from merging with the temporary substrate 4101. The protective layer 4104 can be removed together with the temporary substrate 4101 in the subsequent step 40.

[0519] Step 4a3: Fig. 21C As shown, a first inorganic material bonding layer 4301 is prepared.

[0520] In an optional implementation, after the contact electrode 4103 is prepared, a first inorganic material bonding layer 4301 is prepared on the entire surface. The material of the first inorganic material bonding layer 4301 can be part of the material in the contact electrode 4103, or it can be an alloy of one or at least two welding metal materials such as gold, tin, copper, nickel, indium, etc., or it can be a non-metallic material such as silicon oxide, silicon nitride, etc.

[0521] In an optional embodiment, the thickness of the first inorganic material bonding layer 4301 is 0.1 micrometer to 5 micrometers.

[0522] In an optional embodiment, before preparing the first inorganic material bonding layer 4301, the method further includes:

[0523] A first insulating layer (not shown) is prepared on the surface of the temporary substrate 4101 including the contact electrode 4103 .

[0524] On this basis, the first inorganic material bonding layer 4301 is prepared on the first insulating layer (not shown in the figure). The first insulating layer is located between the surface of the temporary substrate 4101 including the contact electrode 4103 and the first inorganic material bonding layer 4301, ensuring the insulation between the subsequently prepared inorganic bonding layer 4303 and the contact electrode 4103 and between the inorganic bonding layer 4303 and the temporary substrate 4101, avoiding the occurrence of short circuit.

[0525] Step 4a4: Prepare a target wafer.

[0526] like Fig.21D As shown, the preparation of the target wafer includes preparing a device material layer 4202 on a wafer substrate 4201 , and the wafer substrate 4201 and the device material layer 4202 constitute the target wafer.

[0527] The device material layer 4202 includes various functional layers in the semiconductor device to be manufactured. For example, if the semiconductor device to be manufactured is a light-emitting diode device, the device material layer 4202 may at least include a buffer layer, an N-type layer, a quantum well layer, a P-type layer, etc. stacked on the wafer substrate 4201.

[0528] Step 4a5: Fig.21E As shown, a second inorganic material bonding layer 4302 is prepared on the device material layer 4202 .

[0529] Among them, the material of the second inorganic material bonding layer 4302 may include materials required for bonding with the first inorganic material bonding layer 4301 on the temporary substrate 4101, such as one or an alloy of at least two welding metal materials such as gold, tin, copper, nickel, indium, etc., or it may be a non-metallic material such as silicon oxide and silicon nitride. At the same time, the second inorganic material bonding layer 4302 also includes materials or film layers that can form electrical contact with the device material layer 4202, such as metal nickel, gold, silver, indium tin oxide and other materials, and there may be structures such as a Bragg reflection layer, a surface plasma enhancement layer, a selective filter, etc. between the second inorganic material bonding layer 4302 and the device material layer 4202 to enhance or weaken the device performance.

[0530] In an alternative embodiment, the thickness of the second inorganic material bonding layer 4302 is 0.1 micrometers to 10 micrometers.

[0531] The material of the wafer substrate 4201 in the target wafer can be a first-generation semiconductor material, a second-generation semiconductor material, or a third-generation semiconductor material, such as a sapphire substrate, a gallium arsenide substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, etc.

[0532] In an optional embodiment, before preparing the second inorganic material bonding layer 4302, the method further includes:

[0533] A second insulating layer (not shown) is prepared on the device material layer 4202 .

[0534] On this basis, the second inorganic material bonding layer 4302 is prepared on the second insulating layer (not shown in the figure). The second insulating layer is located between the device material layer 4202 and the second inorganic material bonding layer 4302, ensuring the insulation between the subsequently prepared inorganic bonding layer 4303 and the device material layer 4202, avoiding the occurrence of short circuit.

[0535] Step 4a6: Non-aligned bonding.

[0536] In this step, the first inorganic material bonding layer 4301 and the second inorganic material bonding layer 4302 are non-alignedly bonded to form an inorganic bonding layer 4303, so that the temporary substrate 4101 and the structure thereon and the wafer substrate 4201 and the structure thereon are bonded together. Fig.21F In an optional embodiment, the inorganic bonding layer 4303 is insulated and isolated from the temporary substrate 4101 and the contact electrode 4103 by a first insulating layer (not shown in the figure), and the inorganic bonding layer 4303 is insulated and isolated from the device material layer 4202 by a second insulating layer (not shown in the figure).

[0537] Fig.21F The subsequent cross-sectional structure drawings only show Fig.21BThe shape of the contact electrode 4103 on the left side, i.e. the shape in which the contact electrode 4103 completely fills the recess of the electrode supporting structure 4102, is shown. Contact electrodes of other shapes can also use the same method to perform step 4a6 and subsequent steps.

[0538] Step 4a7: Remove the wafer substrate 4201 as needed.

[0539] The structure after removing the wafer substrate 4201 is as follows Figure 21G The removal method of the wafer substrate 4201 includes laser stripping, grinding and thinning, dry etching or chemical cleaning.

[0540] In addition, multi-layer target wafer bonding can be performed if multiple device integration is required.

[0541] The bonding of the multi-layer target wafer can utilize the means of bonding the temporary substrate 4101 and the structure thereon and the wafer substrate 4201 and the structure thereon in the above description. Specifically, the stacking structure of the bonded multi-layer semiconductor device is realized by mutual bonding between two inorganic material bonding layers.

[0542] For example Fig. 22 The stacked structure of the three-layer semiconductor device is shown in FIG. 4 , wherein the temporary substrate 4101 together with the contact electrode 4103 and the bottom semiconductor device 4401 are bonded together through the inorganic bonding layer 4303 formed after the bonding in the above step 4a6 .

[0543] The bottom semiconductor device 4401 and the middle semiconductor device 4401 are bonded together via another inorganic bonding layer 4303. The specific bonding process includes: preparing a third inorganic material bonding layer on the surface of the device material layer of the bottom semiconductor device 4401; providing a second target wafer, the second target wafer including a second wafer substrate and a second semiconductor device (i.e., Fig. 22 The semiconductor device 4401 of the intermediate layer in the second device material layer of each functional layer, and the fourth inorganic material bonding layer is prepared on the second device material layer; the third inorganic material bonding layer and the fourth inorganic material bonding layer are non-alignedly bonded to form Fig. 22 An inorganic bonding layer 4303 is shown between the bottom semiconductor device 4401 and the middle semiconductor device 4401; then the second wafer substrate is removed.

[0544] Fig. 22The top semiconductor device 4401 and the middle semiconductor device 4401 are bonded together by another inorganic bonding layer 4303. The specific bonding process includes: preparing a fifth inorganic material bonding layer on the surface of the device material layer 4202 corresponding to the bottom semiconductor device 4401; providing a third target wafer, the third target wafer including a third wafer substrate and a third semiconductor device (i.e., Fig. 22 The third device material layer of each functional layer in the topmost semiconductor device 4401) is prepared, and a sixth inorganic material bonding layer is prepared on the third device material layer; the fifth inorganic material bonding layer and the sixth inorganic material bonding layer are non-alignedly bonded to form Fig. 22 The inorganic bonding layer 4303 between the semiconductor device 4401 in the middle layer and the semiconductor device 4401 on the top layer is shown; then the third wafer substrate is removed.

[0545] Step 4a8: Perform a first patterning etching on the device material layer 4202 and the inorganic bonding layer 4303 to form a semiconductor device 4401, such as Fig.21H shown.

[0546] In this step, the pattern alignment during the first pattern etching can be performed by backside alignment exposure and other techniques, and the semiconductor device 4401 can be prepared according to the location of the contact electrode 4103 on the temporary substrate 4101.

[0547] Among them, the first graphic etching of the inorganic bonding layer 4303 is mainly to remove the inorganic bonding layer 4303 on the surface of the temporary substrate 4101 outside the semiconductor device 4401, and retain the inorganic bonding layer 4303 between the semiconductor device 4401 and the temporary substrate 4101 and between the semiconductor device 4401 and the contact electrode 4103.

[0548] In an optional embodiment, the surface of the device material layer 4202 may be etched before the first patterning etching to obtain an enhancement and / or reduction structure 4402 on the surface of the device material layer 4202, and the enhancement and / or reduction structure 4402 remains on the semiconductor device 4401 after the first patterning etching, such as Fig.21I This step is an optional step, and the strengthening and / or weakening structure 4402 can be prepared or not prepared according to the needs.

[0549] Step 4a9: As required, the semiconductor device 4401 is electrically connected to the contact electrode 4103, such as Fig.21J shown.

[0550] In this step, an electrical connection layer 4501 is prepared according to design requirements. The electrical connection layer 4501 connects the electrode layer in the semiconductor device 4401 to the contact electrode 4103. Depending on the position of the electrode layer in the semiconductor device 4401, the electrical connection layer 4501 can be connected to different positions on the semiconductor device 4401. Fig.21J In addition to the connection method of the electrical connection layer 4501 shown, Fig.23A and Fig. 23B Two other connection modes of the electrical connection layer 4501 are shown respectively. Fig.23A In the embodiment, both electrical connection layers 4501 are connected to the top of the semiconductor device 4401. Fig. 23B In the embodiment, both electrical connection layers 4501 are connected to the bottom of the semiconductor device 4401, and Fig.21J In the figure, two electrical connection layers 4501 are connected to the top and bottom positions of the semiconductor device 4401 respectively.

[0551] In an optional embodiment, an insulating protective layer may be prepared between the electrical connection layer 4501 and the semiconductor device 4401 as required, and the material of the insulating protective layer may be a low-K dielectric such as silicon oxide, silicon nitride, or a high-K dielectric such as hafnium oxide, or an organic material such as a polymer or resin. If it is necessary to consider that the compatible use environment of the device is not affected by organic materials, the material of the insulating protective layer is only selected from inorganic materials.

[0552] Fig.21J , Fig.23A , Fig. 23B Only a single semiconductor device 4401 is shown in FIG. In other optional embodiments, multiple semiconductor devices 4401 may be integrated on the temporary substrate 4101. The integration method may include: Fig.24 As shown, multiple semiconductor devices 4401 distributed on the surface of the temporary substrate 4101, and Fig. 22 The stacked structure of the semiconductor device shown.

[0553] According to the design requirements, the series connection, parallel connection or common pole scheme between the semiconductor devices 4401 is realized through the electrical connection between the semiconductor devices 4401 and between the semiconductor devices 4401 and the contact electrodes 4103. The positions of the contact electrodes 4103 can be defined in advance on the temporary substrate 4101 according to the designed series and parallel connection scheme. The number of contact electrodes 4103 electrically connected to a single semiconductor device 4401 is at least one, and the contact electrodes 4103 can be distributed at any position. Considering the subsequent electrical connection of the semiconductor device 4401, the contact electrodes 4103 are preferably distributed at positions close to the corners of the overall device, so that the spacing between the contact electrodes 4103 can be maximized.

[0554] in, Fig. 22 The box area in the figure indicates that the electrical connection layer 4501 in the box area is connected to the corresponding position (such as the contact electrode 4103 at other semiconductor devices 4401 or other positions, etc.) according to the designed series-parallel scheme.

[0555] Step 4a10: device release (removal of temporary substrate).

[0556] The device release method used in this step includes thinning, peeling, etching, etc. of the temporary substrate 4101. Fig.25A , Fig.25B , Fig.25C The structure examples of a single semiconductor device 4401 formed by thinning and etching the temporary substrate 4101 are shown respectively. If a protective layer 4104 exists between the temporary substrate 4101 and the contact electrode 4103, the protective layer 4104 is removed during the device release process to expose the required contact electrode 4103.

[0557] in, Fig.25C As shown, a portion of the temporary substrate 4101 below the semiconductor device 4401 is hollowed out by an etching method to achieve a structure in which the temporary substrate 4101 is removed. Fig.25C The structure of the embodiment shown includes a cantilever beam 4601, which is formed by pre-patterning and etching the inorganic bonding layer 4303, ensuring that the semiconductor device 4401 will not collapse during the process of hollowing out a portion of the temporary substrate 4101. The cantilever beam 4601 and the temporary substrate 4101 below, as well as the cantilever beam 4601 and the contact electrode 4103 below are insulated and isolated by a first insulating layer (not shown in the figure).

[0558] remove Fig.25C In addition to the inorganic bonding layer 4303 being used as the support structure of the cantilever beam 4601 as shown, in other embodiments, the functional layer used to prepare the semiconductor device 4401 can also be used as a support structure through a graphical treatment during the preparation process of the semiconductor device 4401.

[0559] In addition, in an optional embodiment, depending on the material of the contact electrode 4103, it can be selected whether to further perform high-temperature treatment to optimize the shape of the contact electrode 4103 again, such as the contact electrode 4103 of columnar solder paste is transformed into a spherical shape after high-temperature reflow.

[0560] In an optional embodiment, the structures of the temporary substrate 4101, the contact electrode 4103 and the protective layer 4104 prepared in step 4a2 are as follows: Fig.26AThe protective layer 4104 is prepared between the temporary substrate 4101 and the contact electrode 4103 and is prepared on a portion of the surface of the temporary substrate 4101 .

[0561] exist Fig.26A The structure after the semiconductor device 4401 and the electrical connection with the contact electrode 4103 are completed on the basis of the temporary substrate 4101 shown in the figure is as follows: Fig.26B As shown. Fig.26B In the illustrated embodiment, the semiconductor device 4401 and the electrical connection structure are all located above the contact electrode 4103 and the protection layer 4104 .

[0562] exist Fig.26B Based on the structure shown, the device release in step 4a10 can be performed by the following method:

[0563] The protective layer 4104 is removed by selective etching to remove the temporary substrate 4101, and the device is released. Fig.26C In the process of removing the protective layer 4104 , the cantilever beam 4601 formed by the inorganic bonding layer 4303 through prior patterning and etching can be used as a supporting structure to ensure that the semiconductor device 4401 will not collapse in the process of removing the protective layer 4104 .

[0564] Regarding the selective etching method, for example, organic matter or silicon oxide is used as the material of the protective layer 4104. After the bonding and device preparation are completed, the protective layer 4104 can be removed by wet selective etching using graphic exposure and related chemicals.

[0565] Using the above FIG. 26A to FIG. 26C The main advantage of the structure of the protective layer 4104 is that after removing the protective layer 4104, the structure of the temporary substrate 4104 remains intact, and the temporary substrate 4104 can be recycled, thereby greatly reducing production costs and raw material consumption.

[0566] The present invention also provides a thin semiconductor device. Fig.25A , Fig.25B or Fig.25CAs shown in the figure and in combination with other figures, it includes a semiconductor device 4401, an inorganic bonding layer 4303 and a contact electrode 4103. Among them, the semiconductor device 4401 is formed by a device material layer 4202 prepared on a wafer substrate 4201 through a first patterning etching after the wafer substrate 4201 is removed. The inorganic bonding layer 4303 is formed by non-aligned bonding of a first inorganic material bonding layer 4301 and a second inorganic material bonding layer 4302, and the inorganic bonding layer 4303 and the device material layer 4202 are subjected to the first patterning etching together. The contact electrode 4103 is prepared on the surface of a temporary substrate 4101, and the semiconductor device 4401 and the contact electrode 4103 are electrically connected. Among them, the first inorganic material bonding layer 4301 is prepared on the surface of the temporary substrate 4101 including the contact electrode 4103; the second inorganic material bonding layer 4302 is prepared on the surface of the device material layer 4202.

[0567] The main advantages of the preparation method of the thin semiconductor device and the thin semiconductor device of the embodiment of the present invention are: the semiconductor device is prepared after the entire surface is bonded, and there is no need to perform alignment transfer for each semiconductor device separately. Compared with the prior art, the cost is low, and the integration density and firmness and reliability are high; the inorganic bonding layer serves as a mechanical support structure during the release process of the semiconductor device, and its mechanical strength is high, which increases the mechanical strength of the thin semiconductor device and helps to reduce the risk of easy damage to the thin semiconductor device. If the inorganic bonding layer is a metal material, the electrical function (electrical and thermal conduction) of the thin semiconductor device is stronger; the material of the inorganic bonding layer adopts metal and inorganic structure, and no organic material is introduced, so that the compatible use environment of the thin semiconductor device is no longer affected by organic materials.

[0568] In addition, in the embodiment of the present invention, the contact electrode and the semiconductor device are prepared on one side of the temporary substrate and one side of the target wafer, respectively, and the contact electrode and the semiconductor device are located on both sides of the inorganic bonding layer, respectively. Therefore, the contact electrode will not occupy the effective area of ​​the area where the semiconductor device is located. Under the same electrode and device size conditions, the effective area lost in the active area where the semiconductor device is located is smaller. For example, if a 100-micron semiconductor device is required to be matched with a 30-micron contact electrode, if the contact electrode is set on the same side of the semiconductor device in a manner other than the embodiment of the present invention, then the active area on the side where the semiconductor device is located needs to lose at least 30 microns of area to accommodate the contact electrode; in the embodiment of the present invention, the size of the contact electrode does not occupy the active area on the side where the semiconductor device is located. It can be seen that under the same active area, the embodiment of the present invention can integrate more semiconductor devices in the active area. In addition, because there is no structural influence of the contact electrode on the side where the semiconductor device is located, the contact electrode will not affect the preparation for the continued miniaturization and miniaturization of semiconductor devices.

[0569] Example 5

[0570] like Fig. 27 As shown, the method for preparing an integrated semiconductor device according to an embodiment of the present invention mainly comprises the following steps:

[0571] Step 501: providing a substrate, and preparing a device material layer including a first material layer and a second material layer on the substrate, wherein the second material layer is located on a side of the device material layer close to the substrate, and the first material layer is located on a side of the device material layer away from the substrate;

[0572] Step 502, performing a first patterning etching on a portion of the device material layer from one side of the first material layer to form a step structure exposing a portion of the second material layer;

[0573] Step 503, preparing a first electrode and a second electrode on the first material layer and the second material layer exposed from the step structure, respectively, and preparing a protective layer covering the first material layer, the second material layer and the second electrode;

[0574] Step 504: preparing a bonding layer on the entire surface of the protective layer, wherein the bonding layer is in electrical contact with the first electrode;

[0575] Step 505: providing a carrier, and bonding the bonding layer to the carrier;

[0576] Step 506: Perform a second patterning etching on the device material layer from the substrate side to form at least one semiconductor device on the carrier.

[0577] By adopting the method for preparing an integrated semiconductor device of the embodiment of the present invention, when the number of semiconductor devices formed on the carrier is more than one, the first electrodes in each semiconductor device can be connected to each other through the bonding layer located on one side of the carrier, and the step structure together with the second electrode thereon and the first electrode are all facing the same side of the integrated semiconductor device (outside the first material layer). On this basis, when designing the electrical connection structure, it is only necessary to design the electrical connection structure on the outside of the first material layer of the integrated semiconductor device. The designed electrical connection structure is on the same side of the integrated semiconductor device as the first electrode and the second electrode, and can be conveniently connected to the first electrode and the second electrode. When the method for preparing an integrated semiconductor device of the embodiment of the present invention is applied to an optoelectronic device, the light-emitting surface is designed on the side of the second material layer, and the electrical connection structure is located on the side of the first material layer, which will not affect the light-emitting efficiency on the side of the second material layer; when the method for preparing an integrated semiconductor device of the embodiment of the present invention is applied to electric power and power devices, the electrical connection structure can be easily arranged on the same side of the integrated semiconductor device, thereby reducing the parasitic capacitance of the electrical connection structure, thereby helping to improve the device performance of the integrated semiconductor device as a whole.

[0578] In an optional embodiment, the protective layer prepared in step 503 is prepared on the entire surface of the wafer including the first material layer, the step structure, the first electrode and the second electrode. In order to achieve electrical contact between the bonding layer prepared in step 504 and the first electrode, the protective layer can be flattened by laser stripping, grinding, etc. after the protective layer is prepared, so as to expose the first electrode from the protective layer.

[0579] Further, in an optional embodiment, when the number of semiconductor devices is more than one (at least two semiconductor devices), the first electrodes in each semiconductor device are connected in common through a bonding layer. In this optional embodiment, the first electrodes in each semiconductor device are directly connected in common using the prepared bonding layer. In this optional embodiment, the bonding layer also acts as an electrical connection structure between the first electrodes, thereby combining the bonding with the preparation of the electrical connection structure, simplifying the preparation steps of the integrated semiconductor device. The common connection between the first electrodes through the bonding layer also eliminates the high-precision alignment lithography step required when preparing the electrical connection structure of the first electrode, which helps to reduce the difficulty of preparing the integrated semiconductor device. At the same time, the common connection between the first electrodes through the bonding layer does not require a one-to-one correspondence between the bonding layer and the first electrode, and also avoids the problem of weakened adhesion of the bonding layer after patterning due to the continued miniaturization of the size of the semiconductor device, as well as the electrical connection performance problems caused by the thickness of the bonding layer, such as the uniformity of current diffusion and heat dissipation, thereby improving the integration and reliability of the integrated semiconductor device.

[0580] In an optional embodiment, the material of the substrate includes sapphire, silicon carbide, silicon, gallium nitride, gallium arsenide, etc. The material of the first material layer can be GaN (gallium nitride), Ga2O3 (gallium oxide), GaAs (gallium arsenide), SiC (silicon carbide), AlN (aluminum nitride), AlGaInP (aluminum gallium indium phosphide), AlGaInN (aluminum gallium indium nitride) and other III-V compounds and their multi-element alloys, including different combinations and stacks thereof, and are formed into N-type (such as Si (silicon) doping) or P-type (such as Mg (magnesium) doping) by appropriate element doping; the material of the second material layer can be GaN, Ga2O3, GaAs, SiC, AlN, AlGaInP, AlGaInN and other III-V compounds and their multi-element alloys, including different combinations and stacks thereof, and are formed into P-type (such as Mg doping) or N-type (such as Si doping) by appropriate element doping. In an optional embodiment, the first material layer or the second material layer may also include a required active area or device structure, such as MQW (Multiple Quantum Well), internal reflection cavity, DBR (Distributed Bragg Reflection), etc. In this optional implementation, the device material layer can be used to prepare optoelectronic devices, such as LED (Light-Emitting Diode). In addition, in other optional embodiments, the structure and material of the device material layer are selected according to different designs, wherein the first material layer and the second material layer are necessary as functional layers connecting the first electrode and the second electrode in the device material layer.

[0581] The target wafer composed of the substrate and the device material layer prepared thereon is made of compound semiconductor material.

[0582] In an optional embodiment, in step 502, a first graphic etching is performed so that the target wafer can simultaneously expose both the first material laminated portion and the second material layer on one side of the first material layer, and optionally, the second material layer can be etched or not according to demand, and the etching angle (the inclination angle of the side wall) depends on the device type, such as the optimal etching angle of GaN optoelectronic devices is 55°, and the optimal etching angle of GaN or SiC power devices is 89°, etc.

[0583] In an optional embodiment, in step 503, the preparation order of the first electrode and the second electrode can be to prepare the first electrode first and then prepare the second electrode, or to prepare the second electrode first and then prepare the first electrode. The first electrode can be prepared on the first material layer on the entire surface, or can be prepared on the first material layer in a patterned manner. The material of the first electrode includes metals such as silver, nickel, rhodium, and gold, and can also include metal oxides such as indium tin oxide and zinc oxide, and can also include metal stacks of these metals and stacks of metals and metal oxides. The material of the second electrode includes metals such as nickel, chromium, titanium, gold, and platinum, and can also include metal oxides such as indium tin oxide and zinc oxide, and can also include metal stacks of these metals and stacks of metals and metal oxides.

[0584] In an optional embodiment, in step 503, the material of the protective layer includes low-K (dielectric constant) dielectrics such as silicon oxide and silicon nitride, and may also include high-K dielectrics such as hafnium oxide, and may also include organic substances such as polymers and resins. The protective layer may also be a stack of these dielectrics, and may integrate functions such as DBR. The main function of the protective layer is insulation protection.

[0585] In an optional embodiment, the material of the bonding layer includes metals such as titanium, platinum, gold, tin, indium, nickel, copper, or mixtures or compounds thereof, and may also include a laminate of these metals and non-metals, wherein the non-metals include dielectrics such as silicon oxide, silicon nitride, titanium oxide, magnesium oxide, aluminum oxide, or organic polymers such as SU8 and polyimide, etc. The bonding layer may be the entire surface (such as the entire surface bonding layer prepared in step 504), or may be patterned (such as the second patterned etching in the following embodiments).

[0586] In an optional embodiment, the preparation of the patterned bonding layer mainly includes the following steps, which are performed after completing the step 504 of preparing the bonding layer on the protective layer and before bonding the bonding layer to the carrier in step 505:

[0587] The bonding layer is subjected to a second patterning etching to form a dividing groove which divides the bonding layer into at least two parts which are insulated from each other, wherein a part of the bonding layer is in electrical contact with the first electrode.

[0588] In an optional embodiment, in step 505, non-aligned bonding is adopted. The material of the carrier includes sapphire, silicon carbide, silicon, gallium nitride, gallium arsenide, glass and other materials and their mixtures or compounds. The bonding material can be part of the material in the contact electrode, or one or more welding metal materials such as gold, tin, copper, nickel, indium and alloys of these materials, or non-metallic materials such as silicon oxide, silicon nitride, polymers, etc. The thickness of the bonding material is 0.1 micron to 5 microns. Among them, the bonding material can be a layer of material for bonding formed on the carrier, and the bonding material can also be the carrier itself. For example, if gold-tin eutectic bonding is adopted, a layer of bonding material needs to be prepared on the carrier. If gold-silicon bonding is adopted, the bonding material can be the carrier itself of silicon material.

[0589] In an optional embodiment, after completing the bonding with the carrier in step 505, the substrate can be removed as needed. For example, if an optoelectronic device is to be manufactured, the substrate needs to be removed, and if an electrical and power device is to be manufactured, the substrate can be retained as needed for subsequent integrated circuit manufacturing. Methods for removing the substrate include laser stripping, grinding and thinning, dry etching, or chemical cleaning.

[0590] In other optional embodiments, if stacking integration of multiple devices is required, multiple bonding of device material layers of the multiple devices may be performed.

[0591] On the basis of the patterned bonding layer, a subsequent step may establish an electrical connection between the patterned bonding layer that is not in electrical contact with the first electrode and the second electrode. Specifically, after completing step 506 of forming the at least one semiconductor device on the carrier, the following steps are performed:

[0592] Performing a third patterned etching on a portion of the second material layer on the second electrode (from one side of the second material layer) to expose a portion of the second electrode, and the unexposed portion of the second electrode is still electrically connected to the second material layer;

[0593] The exposed portion of the second electrode is bridged with another portion of the bonding layer (ie, the bonding layer that is not in electrical contact with the first electrode).

[0594] The bridging material may include metals such as nickel, chromium, titanium, gold, platinum, tungsten, aluminum, etc., and may also include metal oxides such as indium tin oxide and zinc oxide, and may also include metal stacks of these metals and stacks of metals and metal oxides.

[0595] Among them, the bridging method, for example, uses photolithography to etch the protective layer next to the second electrode that is exposed together with part of the second electrode through the third graphic etching to form a through hole in the protective layer to expose another part of the bonding layer, and prepares a bridging layer in the through hole, which is electrically connected to the other part of the bonding layer and the second electrode.

[0596] For exposure of the second electrode, if the substrate has been removed previously, only part of the second material layer needs to be directly etched during the third graphic etching process; if the substrate has been retained for subsequent manufacturing, the third graphic etching process includes etching part of the substrate and etching part of the second material layer.

[0597] In an optional embodiment, the surface of the second material layer may be processed accordingly as required. For example, a suitable device enhancement or reduction structure, such as a surface cone, a sphere, etc., may be customized on the surface of the second material layer as required.

[0598] In an optional embodiment, a suitable passivation treatment may be performed on the surface of the second material layer at the same time. The passivation layer generated by the passivation treatment may be a low-K dielectric such as silicon oxide, silicon nitride, or a high-K dielectric such as hafnium oxide, or an organic material such as a polymer or resin. The main function of the passivation layer is insulation protection.

[0599] In an optional embodiment, after executing step 506, at least one semiconductor device distributed and integrated in the plane direction is formed on the carrier. In addition, in other embodiments, only one semiconductor device can be formed on the carrier according to needs. In addition, in combination with the stacking integration of multiple devices mentioned above, it is also possible to form an integration method of multiple semiconductor devices stacked perpendicular to the plane direction through step 506 after multiple bonding, and it is also possible to realize an integration method of multiple semiconductor devices that are distributed in the plane direction and stacked perpendicular to the plane direction. In an optional embodiment, the side length of a single semiconductor device is 10 microns to 500 microns, and the distance between adjacent semiconductor devices in the plane direction is not less than 3 microns.

[0600] In an optional embodiment, after completing step 506, the method for preparing an integrated semiconductor device according to the embodiment of the present invention may further include:

[0601] A functional structure is produced on at least one semiconductor device.

[0602] Among them, preparing a functional structure on at least one semiconductor device includes removing the substrate as mentioned above or modifying the substrate according to needs, such as doping and etching the substrate.

[0603] In an optional embodiment, preparing a functional structure on at least one semiconductor device also includes: adding quantum dots to at least one semiconductor device for color conversion when preparing an optoelectronic device without removing the substrate, and performing passivation treatment after adding the quantum dots.

[0604] In an optional embodiment, the method for preparing an integrated semiconductor device of the embodiment of the present invention may further include a step of removing the carrier. After removing the carrier, a thin semiconductor device (without a substrate) can be obtained, which is beneficial to further integration of the semiconductor device.

[0605] In the embodiment where the bonding layer is not patterned, after the second patterning etching is completed to form at least one semiconductor device, a step of removing the carrier is performed.

[0606] In the embodiment in which the bonding layer is subjected to a second patterning etching to form the dividing grooves, after the exposed portion of the second electrode is bridged with another portion of the bonding layer, a step of removing the carrier is performed.

[0607] In an alternative embodiment, the carrier is not removed.

[0608] In the embodiment where the carrier is not removed, the carrier may be modified according to design requirements. For example, if the carrier is required to be conductive and electrically connected to the second electrode, the following steps may also be included in an optional embodiment:

[0609] Prepare a conductive layer on the surface of the carrier facing away from the bonding layer;

[0610] The second electrode is bridged to the conductive layer.

[0611] In this embodiment, the material of the conductive layer can be metal such as chromium, titanium, gold, or a stack of metals.

[0612] At this time, the step of bridging the second electrode to the bonding layer is no longer performed, and the second electrode is no longer bridged to the bonding layer.

[0613] In alternative embodiments, the carrier may be removed using substrate removal, thinning or etching methods.

[0614] Wherein, the etching method for removing the carrier includes:

[0615] Corrosion and hollowing out a portion of the carrier below the bonding layer by etching;

[0616] In the process of etching and hollowing out, the bonding layer serves as a mechanical support structure between the carrier and the semiconductor device.

[0617] The method for preparing an integrated semiconductor device according to an embodiment of the present invention is further described below with reference to a specific example of a preparation process of an integrated semiconductor device.

[0618] Step 5a1: Fig.28A As shown, a substrate 501 is provided, and a device material layer 502 is prepared on the substrate 501 .

[0619] The device material layer 502 includes a first material layer 5021 and a second material layer 5022 , wherein the second material layer 5022 is located on a side of the device material layer 502 close to the substrate 501 , and the first material layer 5021 is located on a side of the device material layer 502 away from the substrate 501 .

[0620] In an optional embodiment, the wafer composed of the substrate 501 and the device material layer 502 is a compound semiconductor material. The material of the substrate 501 includes sapphire, silicon carbide, silicon, gallium nitride, gallium arsenide, etc. The material of the first material layer 5021 can be GaN, Ga2O3, GaAs, SiC, AlN, AlGaInP, AlGaInN, etc. III-V compounds and their multi-element alloys, including different combinations and stacks thereof, and are formed into N-type (such as Si doping) or P-type (such as Mg doping) by appropriate element doping. The material of the second material layer 5022 can be GaN, Ga2O3, GaAs, SiC, AlN, AlGaInP, AlGaInN, etc. III-V compounds and their multi-element alloys, including different combinations and stacks thereof, and are formed into P-type (such as Mg doping) or N-type (such as Si doping) by appropriate element doping. The first material layer 5021 or the second material layer 5022 may include the required active area or device structure, such as MQW, internal reflection cavity, DBR, etc.

[0621] Step 5a2: Fig.28B As shown, a first patterning etching is performed on a portion of the device material layer 502 to form a step structure exposing a portion of the second material layer 5022 .

[0622] In this step, part of the device material layer 502 is etched from one side of the first material layer 5021. After the first patterned etching, the first material layer 5021 and the second material layer 5022 on the wafer can be exposed at the same time on the side away from the substrate 501. Among them, the second material layer 5022 can be partially etched or not etched as needed. The etching angle (i.e., the inclination angle of the side wall of the first material layer 5021 after etching) depends on the type of semiconductor device to be prepared. For example, the optimal angle of GaN optoelectronic devices is 55°, and the optimal angle of GaN or SiC power devices is 89°.

[0623] Step 5a3: Fig.28C As shown, prepare the contact electrodes.

[0624] In this step, the first electrode 5031 and the second electrode 5032 are prepared on the first material layer 5021 and the second material layer 5022 exposed from the step structure, respectively. In this step, the first electrode 5031 can be prepared first, and then the second electrode 5032 can be prepared, or vice versa. Among them, the number of the first electrode 5031 is at least one, that is, it can be prepared on the first material layer 5021 on the whole surface (as a first electrode as a whole), or it can be patterned on the first material layer 5021 (patterned into multiple first electrodes), and the material of the first electrode 5031 can include metals such as silver, nickel, rhodium, and gold, and can also include metal oxides such as indium tin oxide and zinc oxide, and can also include metal stacks of these metals and stacks of metals and metal oxides. The material of the second electrode 5032 can include metals such as nickel, chromium, titanium, gold, and platinum, and can also include metal oxides such as indium tin oxide and zinc oxide, and can also include metal stacks of these metals and stacks of metals and metal oxides. The second electrode 5032 does not contact the first material layer 5021.

[0625] Step 5a4: Fig.28D As shown, a protective layer 504 is prepared.

[0626] In this step, if Fig.28D As shown, the protective layer 504 is prepared on the entire surface of the wafer including the first material layer 5021, the step structure, the first electrode 5031 and the second electrode 5032. After the protective layer 504 is prepared, the protective layer 504 can be flattened by laser stripping, grinding, etc. to expose the first electrode 5031 from the protective layer 504.

[0627] The material of the protective layer 504 includes low-K dielectrics, such as silicon oxide, silicon nitride, etc., and may also include high-K dielectrics, such as hafnium oxide, etc., and may also include organic substances such as polymers and resins. The protective layer 504 may also be a stack of these dielectrics, and may integrate functions such as DBR. The main function of the protective layer 504 is insulation protection.

[0628] Step 5a5: Fig.28E As shown, a bonding layer 505 is prepared.

[0629] In this step, the bonding layer 505 is prepared on the entire surface of the protective layer 504. Since the first electrode 5031 is exposed from the protective layer 504 when step 5a4 is completed, the bonding layer 505 is in electrical contact with the first electrode 5031 after step 5a5 is completed.

[0630] The material of the bonding layer 505 includes metals such as titanium, platinum, gold, tin, indium, nickel, copper, or mixtures or compounds thereof, and may also include stacks of these metals and non-metals, wherein the non-metals include dielectrics such as silicon oxide, silicon nitride, titanium oxide, magnesium oxide, aluminum oxide, or organic polymers such as SU8 and polyimide.

[0631] The protection layer 504 forms an insulating protection between the bonding layer 505 and the second electrode 5032 and between the second electrode 5032 and the first material layer 5021 .

[0632] Step 5a6: Fig.28F As shown, a second patterning etching is performed on the bonding layer 505 to form the dividing grooves 506 .

[0633] Among them, the dividing groove 506 divides the bonding layer 505 into at least two parts that are insulated from each other, wherein one part of the bonding layer 505 is in electrical contact with the first electrode 5031, and the other part of the bonding layer 505 is not in electrical contact with the first electrode 5031, and the protective layer 504 under the bonding layer 505 forms insulating protection for the two parts of the bonding layer 505.

[0634] Step 5a6 is an optional step and is performed according to design requirements.

[0635] Step 5a7: Figure 28G or Fig.29A As shown, a carrier 507 is provided, and a bonding layer 505 is bonded to the carrier 507 .

[0636] In the embodiment of the present invention, step 5a7 uses non-aligned bonding to perform bonding. The material of the carrier 507 includes sapphire, silicon carbide, silicon, gallium nitride, gallium arsenide, glass and other materials and mixtures or compounds thereof. The bonding material can be part of the material in the contact electrode, or one or more welding metal materials such as gold, tin, copper, nickel, indium and the like, or alloys of these materials, or non-metallic materials such as silicon oxide, silicon nitride, polymers, etc. The thickness of the bonding material is 0.1 micron to 5 microns. The bonding material can be a layer of material for bonding formed on the carrier 507, or the bonding material can be the carrier 507 itself. For example, if gold-tin eutectic bonding is used, a layer of bonding material needs to be prepared on the carrier 507. If gold-silicon bonding is used, the bonding material can be the carrier 507 itself made of silicon material.

[0637] in, Figure 28G The structure after bonding is shown when the dividing groove 506 is included. Fig.29A The structure after bonding is shown without the dividing groove 506 .

[0638] Step 5a8: Fig.28H or Fig.29BAs shown, substrate 501 is removed.

[0639] The means of removing the substrate 501 may include laser lift-off, grinding and thinning, dry etching or chemical cleaning, etc. If multiple device integration is required, other device material layers may be bonded on the device material layer 502 after removing the substrate 501 .

[0640] in, Fig.28H is Figure 28G Based on the structure after removing the substrate 501, Fig.29B is Fig.29A The structure after removing the substrate 501 on the basis of.

[0641] Step 5a9: Fig.28I or Fig.29C As shown, a third patterning etching is performed on a portion of the second material layer 5022 on the second electrode 5032 to expose a portion of the second electrode 5032 .

[0642] After step 5 a 9 is completed, the unexposed portion of the second electrode 5032 is still electrically connected to the second material layer 5022 .

[0643] in, Fig.28I is Fig.28H The structure after the third graphic etching is based on Fig.29C is Fig.29B The structure after the third graphic etching on the basis.

[0644] Step 5a10: Fig.28J or Fig.29D As shown, the device surface is etched to obtain an enhancement and / or reduction structure 508 on the device surface.

[0645] In this step 5a10, the device surface refers to the surface of the second material layer 5022 after removing the substrate 501. In this step, the enhancement and / or reduction structure 508 is mainly provided for the preparation of the optoelectronic semiconductor device, wherein the surface of the second material layer 5022 is the light emitting surface of the optoelectronic semiconductor device.

[0646] The shape of the enhancing and / or weakening structure 508 is, for example, a cone, a sphere, etc.

[0647] In addition, in an optional embodiment, a suitable passivation treatment may be performed on the device surface (the surface of the second material layer 5022). The material of the passivation layer formed by the passivation treatment may be a low-K dielectric such as silicon oxide, silicon nitride, or a high-K dielectric such as hafnium oxide, or an organic substance such as a polymer or resin.

[0648] This step 5a10 is an optional step, and the strengthening and / or weakening structure 508 can be prepared or not prepared according to needs.

[0649] in, Fig.28J is Fig.28I The structure after etching the device surface is based on Fig.29D is Fig.29C The structure is obtained by etching the device surface.

[0650] Step 5a11 , performing a second patterning etching on the device material layer 502 to form a semiconductor device 509 on the carrier 507 .

[0651] Fig.30 An embodiment of a distributed structure of semiconductor devices 509 perpendicular to the surface direction of the device is shown. In an optional embodiment, only one semiconductor device 509 may be formed according to design requirements. In a preferred embodiment, the number of semiconductor devices 509 formed is at least one, for example Fig.30 Three semiconductor devices 509 are formed in the illustrated embodiment. Fig.30 As shown, the plurality of semiconductor devices 509 are distributed in the planar direction. In other embodiments, if a plurality of other device material layers are pre-bonded on the device material layer 502, the plurality of semiconductor devices 509 formed after step 5a11 may be a structure stacked and distributed in a direction perpendicular to the surface of the carrier 507, or may be a structure that is stacked and distributed and distributed in the planar direction at the same time.

[0652] In an optional embodiment, the side length of a single semiconductor device 509 may be 10 micrometers to 500 micrometers, and the spacing between semiconductor devices 509 is not less than 3 micrometers.

[0653] Depend on Fig.30 Combination Fig.28J or Fig.29D As shown, in an optional embodiment, a plurality of semiconductor devices 509 (or Fig.28J , Fig.29DThe first material layers 5021 of the reference numeral 2) are all connected to the bonding layer 505 through their respective first electrodes 5031. If the bonding layer 505 at the bottom of each semiconductor device 509 is not subjected to patterning etching related to the preparation of the semiconductor device 509, the first material layers 5021 of each semiconductor device 509 can be connected to a common electrode through the bonding layer 505. At the same time, the second material layers 5022 of each semiconductor device 509 are not connected to a common electrode. After the integrated semiconductor device manufactured in step 5a11 is completed, in the subsequent further manufacturing, the second material layers 5022 in each semiconductor device 509 can be electrically connected to a specified position through the exposed second electrode 5032 according to design requirements. For example, the process of step 5a12 is shown below.

[0654] Step 5a12: Figure 28K and Fig.31 As shown, in Fig.28J On the basis of the illustrated embodiment, the second electrode 5032 is bridged to another part of the bonding layer 505 .

[0655] in, Fig.31 An embodiment of a semiconductor device 509 distribution structure after bridging in a direction perpendicular to the surface of the device material layer 502 is shown.

[0656] exist Figure 28K and Fig.31 In the illustrated embodiment, the bridging method includes, for example, etching the protective layer 504 on the side of the exposed second electrode 5032 to form a bridging hole, preparing a bridging layer 5010 in the bridging hole, and the bridging layer 5010 bridges another portion of the bonding layer 505 at the bottom of the bridging hole and the exposed second electrode 5032 together.

[0657] After completing the above-mentioned electrically connected single semiconductor device 509 or integrated multiple semiconductor devices 509, subsequent device processing procedures can be carried out according to design requirements, such as adding quantum dots to optoelectronic devices for color conversion, etc., and passivation can continue after completing subsequent processing.

[0658] Step 5a13: device release (removing the carrier 507).

[0659] The device release method used in this step includes removing, thinning, etching, cutting, etc. the carrier 507.

[0660] like Figure 28L , Fig.29EAs shown, in the structure after removing the carrier 507, the bonding layer 505 is exposed on the side opposite to the second material layer 5022. When the optoelectronic device is prepared by the preparation method of the integrated semiconductor device of the embodiment of the present invention, the light emitting surface is located at the second material layer 5022, and the bonding layer 505 serving as the electrical connection structure is on the other side opposite to the second material layer 5022, so that the electrical connection structure will not affect the luminous efficiency of the optoelectronic device.

[0661] In an optional embodiment, if the carrier 507 needs to be provided with a conductive function, after the carrier 507 is thinned, a conductive layer 5011 is prepared on the surface of the carrier 507 facing away from the bonding layer 505, such as Fig.32 If it is necessary to electrically connect the second electrode 5032 to the conductive layer 5011 , the second electrode 5032 can be bridged to the conductive layer 5011 using a bridging technique.

[0662] The conductive layer 5011 can be prepared by metal evaporation. The material of the conductive layer 5011 can be metal or laminate such as chromium, titanium, gold, etc.

[0663] Fig.33A , Fig.33B The structures of hollowing out the carrier 507 under the device by etching are respectively shown for the device with the dividing groove 506 and the device without the dividing groove 506. In the process of hollowing out the carrier 507 under the device by etching, using part of the bonding layer 505 as a supporting structure such as the cantilever beam 5012 can prevent the device from collapsing during the hollowing process.

[0664] Fig.33A and Fig.33B Only one implementation form of the cantilever beam 5012 is illustrated. In addition, in other optional embodiments, the structure of the cantilever beam can also be other various, and the material of the cantilever beam can include organic materials and inorganic materials, organic materials such as photoresists, polymers, etc., and inorganic materials such as bonding layers, which can be used to prepare the functional layer used in the semiconductor device 509 through the graphic processing in the preparation process of the semiconductor device 509 to become the cantilever beam structure. In addition, a thin film structure can be introduced as a cantilever beam structure in the subsequent preparation, for example Fig.34A , Fig.34B As shown, after completing the above device preparation process, the cantilever beam 5012 can be prepared separately, wherein a part of the thin film structure of the cantilever beam 5012 is prepared on the surface of the carrier 507, and another part of the thin film structure of the cantilever beam 5012 is prepared on the completed device structure, for example Fig.34A , Fig.34B As shown, another portion of the thin film structure of the cantilever beam 5012 is prepared on the bridging layer 5010 ( Fig.34A as shown) or the second electrode 5032 ( Fig.34BAs shown), in other embodiments, another part of the thin film structure of the cantilever beam 5012 can also be prepared on the second material layer 5022 in the semiconductor device 509 or prepared at other positions of the semiconductor device 509, as long as the prepared thin film structure of the cantilever beam 5012 can be sufficient to support the semiconductor device 509 and the first electrode 5031, the bonding layer 505, the second electrode 5032 and the bridging layer 5010 and other structures to avoid collapse during the hollowing process.

[0665] The present invention also provides an integrated semiconductor device, which can be seen in Figure 28K , Figure 28L , Fig.29D , Fig.29E , Fig.30 , Fig.31 As shown in the accompanying drawings, it includes a semiconductor device 509, a first electrode 5031, a second electrode 5032, a protective layer 504 and a bonding layer 505. Among them, there is at least one semiconductor device 509, and the semiconductor device 509 includes a first material layer 5021 and a second material layer 5022, and has a step structure on one side of the first material layer 5021 that exposes a portion of the second material layer 5022. The first electrode 5031 is located on the first material layer 5021. The second electrode 5032 is located on the second material layer 5022 exposed by the step structure. The protective layer 504 covers the first material layer 5021, the second material layer 5022 and the second electrode 5032. The bonding layer 505 is located on the protective layer 504, and the bonding layer 505 is in electrical contact with the first electrode 5031.

[0666] In an optional embodiment, when the number of the semiconductor device 509 is more than one, the first electrodes 5031 in the semiconductor devices 509 are connected in common through the bonding layer 505 .

[0667] The preparation method of the integrated semiconductor device and the integrated semiconductor device of the embodiment of the present invention can realize a single micro semiconductor device or a collection of multiple semiconductor devices, and its integrated size and density can be freely defined according to the graphic accuracy and requirements. The integrated semiconductor device implemented by the present invention can include the crystals, active areas and electrical contact structures required in the first generation semiconductor, the second generation semiconductor, and the third generation semiconductor structure, and the integrated mode of the integrated semiconductor device implemented by the present invention can be a single-layer horizontal arrangement or a multi-layer vertical arrangement. According to the requirements, its electrical interconnection can be designed as a series, parallel or series-parallel combination of electrical interconnection structure. And the series, parallel or series-parallel combination of electrical interconnection structure can be realized by using the graphic etching of the bonding layer and combining the bridging technology. In the embodiment of the present invention, the bonding of the carrier to the target wafer can replace the structure and method of alignment bonding or device placement difficulties, and at the same time, the bonding layer has good electrical (electrical and thermal conduction) and mechanical capabilities. The bonding layer is used as an interconnection structure and can also be used as a cantilever beam support structure, which fully utilizes the multiple functions of the bonding layer, thereby simplifying the preparation process. In addition, in the embodiment of the present invention, the device surface (ie, the surface of the second material layer) of the integrated semiconductor device has no blocking structure for electrical connection, which can maximize the device capability, especially the capability of the optoelectronic device.

[0668] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a compound semiconductor device, comprising: Providing a first substrate, and preparing a semiconductor stacking structure on the entire surface of the first substrate, wherein the semiconductor stacking structure comprises a transition semiconductor layer, a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer stacked outward from a surface of the first substrate; Performing pattern etching on the semiconductor stack structure from a side of the second conductive type semiconductor layer to form a first pattern etching structure exposed to the first conductive type semiconductor layer; Forming a second contact electrode and a first contact electrode on the surface of the second conductive type semiconductor layer and the surface of the first conductive type semiconductor layer exposed at the bottom of the first patterned etching structure, respectively; preparing an insulating passivation layer in the first patterned etching structure; Providing a driving backplane including driving contacts, and electrically connecting the second contact electrodes to the driving contacts one-to-one; Performing patterned etching on the semiconductor stack structure to form a second patterned etching structure exposing a portion of the first contact electrode from a side away from the second conductive type semiconductor layer and close to the first conductive type semiconductor layer; Wherein, no graphical growth means is used during the preparation method.

2. The method for preparing a compound semiconductor device according to claim 1, characterized in that: Also includes: A functional structure is prepared on one side of the first substrate.

3. The method for preparing a compound semiconductor device according to claim 2, wherein: The structure of the semiconductor device does not include the first substrate portion.

4. The method for preparing a compound semiconductor device according to claim 3, characterized in that: After the second contact electrodes are electrically connected to the drive contacts one-to-one, the method further comprises: The first substrate is removed.

5. The method for preparing a compound semiconductor device according to claim 4, characterized in that: The step of preparing a functional structure on one side of the first substrate includes: Preparing a metal bridge structure in the second patterned etching structure or preparing an interconnection structure connecting the first contact electrode with other semiconductor devices; or, Prepare an insulating layer filled in the second patterned etching structure and having a height higher than the opening position of the second patterned etching structure, and form a pit structure surrounded by the insulating layer; The chromatic aberration conversion material is filled in the pit structure, and the pit structure is sealed to form an optical color conversion structure.

6. The method for preparing a compound semiconductor device according to claim 1, characterized in that: The step of electrically connecting the second contact electrode to the driving contact point one-to-one includes: The second contact electrodes are electrically connected to the driving contacts one-to-one by means of alignment bonding, welding or electrode bridging.

7. The method for preparing a compound semiconductor device according to claim 6, characterized in that: The second contact electrode is electrically connected to the driving contact point one-to-one by using an alignment bonding method, comprising: Aligning the driving contact with the second contact electrode, and bonding the driving back plate to the second conductive type semiconductor layer; The distribution of the driving contacts on the surface of the driving backplane matches the distribution of the second contact electrodes on the surface of the second conductive type semiconductor layer.

8. The method for preparing a compound semiconductor device according to claim 1, wherein: The first conductive type semiconductor layer is an N-type semiconductor layer, and the second conductive type semiconductor layer is a P-type semiconductor layer; or, The first conductive type semiconductor layer is a P-type semiconductor layer, and the second conductive type semiconductor layer is an N-type semiconductor layer.

9. The method for preparing a compound semiconductor device according to claim 1, characterized in that: When the semiconductor stacked structure is entirely prepared on the first substrate, the method further includes: An active region or a high electron mobility film layer is formed between the first conductive type semiconductor layer and the second conductive type semiconductor layer.

10. A compound semiconductor device, characterized in that: include: A drive backplane, wherein the drive backplane includes drive contacts; a second conductivity type semiconductor layer; A first conductive type semiconductor layer, wherein the first conductive type semiconductor layer is stacked on the second conductive type semiconductor layer; a second contact electrode, the second contact electrode being located on a surface of the second conductive type semiconductor layer, and the second contact electrode being electrically connected to the driving contact in a one-to-one manner; A first patterned etching structure, wherein the first patterned etching structure is located in the second conductive type semiconductor layer and a portion of the first conductive type semiconductor layer; A first contact electrode, wherein the first contact electrode is located on the first conductive type semiconductor layer at the bottom of the first patterned etched structure; An insulating passivation layer, wherein the insulating passivation layer is located in the first patterned etching structure; a second patterned etching structure, wherein the second patterned etching structure is located in the first conductive type semiconductor layer, and the second patterned etching structure is located at a side away from the second conductive type semiconductor layer and close to the first conductive type semiconductor layer, and a portion of the first contact electrode is exposed from the second patterned etching structure; Wherein, in the process of preparing the compound semiconductor device, no graphical growth method is used.

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