Fan-out packaging method and packaging structure

Abstract

The present invention provides a fan-out packaging method and a packaging structure. The method includes: fixing the back surfaces of multiple groups of functional chips on a wafer carrier in the form of a first array, forming a first encapsulation layer on the front surfaces of the multiple groups of functional chips, wherein conductive bumps are provided on the front surfaces of the multiple groups of functional chips; removing the wafer carrier and forming a high-density interconnect wiring layer on the front surfaces of the multiple groups of functional chips; cutting the multiple groups of functional chips and fixing the side with the high-density interconnect wiring layer on a panel carrier in the form of a second array; fixing the first surfaces of multiple first chips and multiple passive devices on the panel carrier; forming a second encapsulation layer on the side of the multiple groups of functional chips facing away from the high-density interconnect wiring layer and on the second surfaces of the first chips and the passive devices; removing the panel carrier and forming a low-density interconnect wiring layer on the high-density interconnect wiring layer. The packaging method of the present invention can well meet the requirements of high-density interconnection, and has low cost and high yield.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and particularly relates to a fan-out packaging method and a packaging structure. Background Art

[0002] With the development of semiconductor technology, packaging technology has been developing towards high density / high integration. Currently, the fan-out technology has become an important development direction for high-density interconnection. By using a redistribution layer to connect single-chip and multi-chip, the flexibility of packaging integration has been greatly improved. The fan-out technology has been applied to fields such as high-performance computing (HPC) and mobile phone processors.

[0003] Currently, there are two main development directions for the fan-out technology. One is the fan-out wafer-level packaging (FOWLP) based on wafer technology, and the other is the fan-out panel-level packaging (FOPLP) based on panel technology. The wiring density of the fan-out wafer-level packaging can be higher. Currently, mass production with a line width of 2 microns has been achieved, but the yield is low and the cost is high. For the fan-out panel-level packaging, due to the high yield and low cost, but due to the large panel size and the difficulty in achieving a fine line width, the currently mass-producible line width is all above 5um.

[0004] For multi-chip system-level packaging, it contains multiple types of chips in the middle, and the wiring density requirements for each type of chip are different. However, currently, the same process is used, and it needs to be manufactured according to the strictest technical standards, resulting in a high manufacturing cost.

[0005] In view of the above problems, it is necessary to propose a fan-out packaging method and a packaging structure with reasonable design and can effectively solve the above problems. Summary of the Invention

[0006] The present invention aims to at least solve one of the technical problems existing in the prior art, and provides a fan-out packaging method and a packaging structure.

[0007] In one aspect of the present invention, a fan-out packaging method is provided, and the method includes:

[0008] Providing a wafer carrier and a panel carrier;

[0009] Fixing the back surfaces of multiple groups of functional chips on the surface of the wafer carrier in the form of a first array, and forming a first encapsulation layer on the front surfaces of the multiple groups of functional chips, wherein a plurality of conductive bumps are provided on the front surfaces of the multiple groups of functional chips;

[0010] Separating the multiple groups of functional chips from the wafer carrier, and forming a high-density interconnect wiring layer on the front surfaces of the multiple groups of functional chips;

[0011] Cut the multiple groups of functional chips and fix the side with the high-density interconnect wiring layer formed thereon to the surface of the panel carrier in the form of a second array;

[0012] Fix the first surfaces of multiple first chips and multiple passive devices to the surface of the panel carrier;

[0013] Form a second encapsulation layer on the side of the multiple groups of functional chips facing away from the high-density interconnect wiring layer, and on the second surfaces of the multiple first chips and the multiple passive devices;

[0014] Separate the multiple groups of functional chips, the multiple first chips, and the multiple passive devices from the panel carrier, and form a low-density interconnect wiring layer on the high-density interconnect wiring layer.

[0015] Optionally, before forming the high-density interconnect wiring layer on the front surface of the multiple groups of functional chips, the method further includes:

[0016] Separate the multiple groups of functional chips from the wafer carrier, and grind the front surfaces of the multiple groups of functional chips to expose the conductive bumps.

[0017] Optionally, forming the high-density interconnect wiring layer on the front surface of the multiple groups of functional chips includes:

[0018] Form a first dielectric layer on the first encapsulation layer and the multiple conductive bumps;

[0019] Pattern the first dielectric layer to form multiple first openings;

[0020] Form a first metal interconnect layer on the surface of the patterned first dielectric layer, wherein the first metal interconnect layer is electrically connected to the conductive bumps;

[0021] Pattern the first metal interconnect layer to form the high-density interconnect wiring layer.

[0022] Optionally, forming the low-density interconnect wiring layer on the surface of the high-density interconnect wiring layer includes:

[0023] Form a second dielectric layer on the surface of the high-density interconnect wiring layer, the first surfaces of the multiple first chips, and the multiple passive devices;

[0024] Pattern the second dielectric layer to form multiple second openings;

[0025] Form a second metal interconnect layer on the surface of the patterned second dielectric layer;

[0026] Pattern the second metal interconnect layer to form the low-density interconnect wiring layer.

[0027] Optionally, after forming the low-density interconnect wiring layer, the method further includes:

[0028] Forming a third dielectric layer on the surface of the patterned second metal interconnect layer;

[0029] Pattern the third dielectric layer to form a plurality of third openings;

[0030] Ball planting is performed at the plurality of third openings to form a plurality of solder balls.

[0031] Optionally, each group of functional chips includes at least two different types of chips.

[0032] Another aspect of the present invention provides a fan-out package structure, the package structure includes a functional chip group, a first chip, passive devices, a high-density interconnect wiring layer, a low-density interconnect wiring layer, a first encapsulation layer, and a second encapsulation layer, wherein, conductive bumps are provided on the front surface of the functional chips in the functional chip group;

[0033] The high-density interconnect wiring layer is disposed on the front surface of the first encapsulation layer and the functional chips in the functional chip group;

[0034] The low-density interconnect wiring layer is disposed above the high-density interconnect wiring layer and on the first surface of the first chip and the passive devices;

[0035] The first encapsulation layer encapsulates the functional chip group;

[0036] The second encapsulation layer encapsulates the functional chip group, the first chip, and the passive devices.

[0037] Optionally, the high-density interconnect wiring layer includes a first dielectric layer disposed on the conductive bumps and a first metal interconnect layer disposed above the first dielectric layer, wherein the first metal interconnect layer is electrically connected to the conductive bumps.

[0038] Optionally, the low-density interconnect wiring layer includes a second dielectric layer disposed above the first metal interconnect layer, on the first surface of the first chip and the passive devices, and a second metal interconnect layer disposed above the second dielectric layer.

[0039] Optionally, the package structure further includes a third dielectric layer and a plurality of solder balls, the third dielectric layer is disposed above the second metal interconnect layer, and the plurality of solder balls are disposed above the third dielectric layer.

[0040] Optionally, the first chip and the passive devices are respectively disposed on both sides of the functional chip group.

[0041] Optionally, the functional chipset includes at least two different types of chips.

[0042] The fan-out packaging method and packaging structure of the present invention. In this packaging method, multiple groups of functional chips use high-density interconnection, which can well meet the requirements of high-density interconnection; the first chip and passive devices use low-density interconnection, which can improve the yield and reduce the manufacturing cost. By integrating the wafer-level fan-out technology and the panel-level fan-out technology, different levels of interconnection are integrated in one package. Compared with the current traditional fan-out wafer-level packaging, the fan-out packaging method of the present invention can provide lower cost and higher yield under the condition of the same interconnection density. Compared with the current traditional fan-out panel-level packaging, the fan-out packaging method of the present invention can provide higher interconnection density to meet the requirements of high-performance devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic flowchart of a fan-out packaging method according to an embodiment of the present invention;

[0044] Figure 2 It is a schematic diagram of the chip layout area on the wafer carrier of another embodiment of the present invention;

[0045] Figure 3 It is a schematic diagram of the second array B on the panel carrier of another embodiment of the present invention;

[0046] Figure 4 It is a schematic diagram of the first array A on the wafer carrier of another embodiment of the present invention;

[0047] Figures 5 to 19 It is a schematic diagram of the packaging process of a fan-out packaging structure according to another embodiment of the present invention;

[0048] Figure 20 It is a schematic diagram of a fan-out packaging structure according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0050] As Figure 1 shown, one aspect of the present invention provides a packaging method S100 for a fan-out packaging structure. The packaging method S100 includes:

[0051] S110. Provide a wafer carrier and a panel carrier.

[0052] Specifically, as Figure 2 , Figure 3 and Figure 4As shown, a wafer carrier 110 and a panel carrier 120 are provided. The main materials of the wafer carrier 110 are glass, silicon wafers or metals. The main materials of the panel carrier 120 are glass, metals or fiberglass resin sheets. The materials of the wafer carrier 110 and the panel carrier 120 are not specifically limited in this embodiment and can be selected according to needs.

[0053] S120. Fix the back sides of multiple groups of functional chips on the surface of the wafer carrier in the form of a first array, and form a first encapsulation layer on the front sides of the multiple groups of functional chips, wherein multiple conductive bumps are provided on the front sides of the multiple groups of functional chips.

[0054] It should be noted that each group of functional chips includes at least two different types of chips. As Figure 5 shown, in this embodiment, each group of functional chips includes a second chip 150 and a third chip 160, wherein the second chip 150 and the third chip 160 are different types of chips, and the second chip 150 and the third chip 160 are high-performance chips, such as processors, etc. Of course, each group of functional chips can also include other functional chips, which are not specifically limited in this embodiment. Multiple conductive bumps 161 are provided on the front sides of the multiple groups of functional chips, that is to say, multiple conductive bumps 161 are provided on the front sides of the second chip 150 and the third chip 160. In this embodiment, the conductive bumps 161 are respectively provided at both ends of the second chip 150 and the third chip 160, and the conductive bumps 161 are metal copper conductive bumps, and other metal materials can also be used, which are not specifically limited in this embodiment.

[0055] Specifically, as Figure 5 shown, in this embodiment, the back sides of the second chip 150 and the third chip 160 in the multiple groups of functional chips are fixed on the surface of the wafer carrier 110 through a first adhesive 111, and the wafer-level packaging technology can well meet the requirements of high-density interconnection. As Figure 3 shown, after pasting, the multiple groups of functional chips form a first array A, and the first array A is a square array. As Figure 6 shown, use encapsulant to encapsulate on the front sides of the multiple groups of functional chips, that is, form a first encapsulation layer 170 on the front sides of the second chip 150 and the third chip 160 in the multiple groups of functional chips. The encapsulation method can be film layer vacuum lamination or traditional encapsulation process, which is not specifically limited in this embodiment.

[0056] S130. Separate the multiple groups of functional chips from the wafer carrier, and form a high-density interconnection wiring layer on the front sides of the multiple groups of functional chips.

[0057] Specifically, as Figure 7As shown, multiple groups of functional chips are separated from the wafer carrier 110, that is, the wafer carrier 110 is removed. The separation method can be thermal separation, laser separation, ultraviolet light separation, mechanical separation, etc. These methods are all commonly used temporary bonding separation methods at present. The separation method is not specifically limited in this embodiment and can be selected according to actual needs.

[0058] As Figure 8 shown, after separating the back sides of multiple groups of functional chips from the wafer carrier 110, the front sides of the multiple groups of functional chips are polished. That is to say, the front sides of the second chip 150 and the third chip 160 are polished to expose the conductive bumps 161 on the front sides of the second chip 150 and the third chip 160. Other processes can also be used to expose the conductive bumps 161, which are not specifically limited in this embodiment.

[0059] A high-density interconnect wiring layer is formed on the front sides of the multiple groups of functional chips, including:

[0060] First, a first dielectric layer is formed on the first encapsulation layer and the multiple conductive bumps.

[0061] Specifically, as Figure 9 shown, the first dielectric layer 151 is coated on the surfaces of the first encapsulation layer 170 and the multiple conductive bumps 161. The material of the first dielectric layer 151 is polyimide (PI), polybenzoxazole (PBO), etc. The coating method is usually wafer spin coating, which is not specifically limited in this embodiment. The first dielectric layer 151 plays a protective role for the multiple groups of functional chips.

[0062] Second, the first dielectric layer is patterned to form multiple first openings.

[0063] As Figure 9 shown, the first dielectric layer 151 is patterned through a photolithography process to form multiple first openings 152.

[0064] Third, a first metal interconnect layer is formed on the surface of the patterned first dielectric layer, wherein the first metal interconnect layer is electrically connected to the conductive bumps.

[0065] Specifically, as Figure 10 shown, the first metal interconnect layer 153 is deposited on the surface of the patterned first dielectric layer 151. The deposition method can adopt processes such as electroplating, sputtering, thermal evaporation, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition. The metal material of the first metal interconnect layer 153 is usually metal titanium and metal copper, which are not specifically limited in this embodiment. The first metal interconnect layer 153 is electrically connected to the conductive bumps 161.

[0066] Finally, pattern the first metal interconnect layer to form the high-density interconnect wiring layer.

[0067] Specifically, as Figure 10 shown, pattern the first metal interconnect layer 153 through photolithography and etching processes to form the high-density interconnect wiring layer. The etching process can be wet etching or dry etching, and this embodiment does not make specific limitations.

[0068] In this embodiment, multiple groups of functional chips are different types of high-performance chips, such as processor chips. In system-in-package design, usually, high-performance chips have high wiring requirements. Therefore, using fan-out wafer-level packaging for multiple groups of functional chips to form the above high-density interconnect wiring layer can provide a higher interconnect density and meet the requirements of high-performance devices.

[0069] S140. Cut the multiple groups of functional chips and fix the side with the formed high-density interconnect wiring layer on the surface of the panel carrier in the form of a second array.

[0070] Specifically, cut the multiple groups of functional chips according to the area size of the panel carrier 120 and fix them on the surface of the panel carrier 120 in the form of the second array B as Figure 4 shown. Using panel-level packaging technology can improve the yield and reduce the manufacturing cost. In this embodiment, as Figure 11 shown, fix the side with the formed high-density interconnect wiring layer on the panel carrier 120 through the second adhesive 121. That is to say, the first metal interconnect layer 153 is bonded to the second adhesive 121.

[0071] S150. Fix the first surfaces of multiple first chips and multiple passive devices on the surface of the panel carrier.

[0072] It should be noted that in this embodiment, the first chip 130 is a low-performance chip, or it can be other types of chips, and this embodiment does not make specific limitations. The passive device 140 can be at least one of a resistor, a capacitor, an inductor, a converter, a taper, a matching network, a resonator, a filter, a mixer, and a switch, etc., and this embodiment does not make specific limitations.

[0073] Specifically, as Figure 12 shown, fix multiple first chips 130 and multiple passive devices 140 on the panel carrier 120 through the second adhesive 121 as well. Further, in this embodiment, the first chips 130 and the passive devices 140 are respectively arranged on both sides of each group of functional chips. The first chips 130 and the passive devices 140 can also be in other distribution manners, and this embodiment does not make specific limitations.

[0074] S160. On the side of the multiple groups of functional chips facing away from the high-density interconnect wiring layer, and on the second surfaces of the multiple third chips and the multiple passive devices, form a second encapsulation layer.

[0075] Specifically, as Figure 13 shown, fix the multiple groups of functional chips on the panel carrier 120 in the form of a second array B, and then form a second encapsulation layer on the side of the multiple groups of functional chips facing away from the high-density interconnect wiring layer and on the second surfaces of the multiple first chips 130 and the multiple passive devices 140. That is to say, the second encapsulation layer 180 wraps the multiple first chips 130, the multiple passive devices 140, the multiple second chips 150, and the multiple third chips 160. The encapsulation method can be film layer vacuum lamination or traditional encapsulation process, and this embodiment does not make specific limitations.

[0076] S170. Separate the multiple groups of functional chips, the multiple first chips, and the multiple passive devices from the panel carrier, and form a low-density interconnect wiring layer on the high-density interconnect wiring layer.

[0077] Specifically, as Figure 14 shown, separate the multiple groups of functional chips, the multiple first chips 130, and the multiple passive devices 140 from the panel carrier 120, that is, remove the panel carrier 120. The separation method can adopt thermal separation, laser separation, ultraviolet light separation, mechanical separation and other methods. These methods are all currently commonly used temporary bonding separation methods, and this embodiment does not make specific limitations on the separation method, and can be selected according to actual needs.

[0078] Forming a low-density interconnect wiring layer on the high-density interconnect wiring layer includes:

[0079] First, form a second dielectric layer on the surface of the high-density interconnect wiring layer, the first surfaces of the multiple first chips, and the multiple passive devices.

[0080] Specifically, as Figure 15 shown, form a second dielectric layer 131 on the first metal interconnect layer 153, the first surfaces of the multiple first chips 130, and the first surfaces of the multiple passive devices 140. The second dielectric layer 131 plays a protective role for the first metal interconnect layer 153. The material of the second dielectric layer 131 is a photosensitive dielectric layer (PID) or an Ajinomoto build-up film (ABF), etc., and this embodiment does not make specific limitations. The process of covering the second dielectric layer 131 on the first metal interconnect layer 153, the first surfaces of the multiple first chips 130, and the first surfaces of the multiple passive devices 140 can be vacuum laminating or printing process, and this embodiment does not make specific limitations.

[0081] Secondly, pattern the second dielectric layer to form a plurality of second openings.

[0082] Specifically, as Figure 15 shown, the second dielectric layer 131 is patterned by a photolithography process, and a plurality of second openings 132 are formed on the second dielectric layer 131.

[0083] Next, a second metal interconnect layer is formed on the surface of the patterned second dielectric layer.

[0084] Specifically, as Figure 16 shown, a second metal interconnect layer 133 is deposited on the surface of the patterned second dielectric layer 131. The deposition method can adopt processes such as electroplating, sputtering, thermal evaporation, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition. The metal material of the second metal interconnect layer 133 is usually metal titanium and metal copper. The deposition method and metal material are not specifically limited in this embodiment.

[0085] Finally, the second metal interconnect layer is patterned to form the low-density interconnect wiring layer.

[0086] Specifically, as Figure 16 shown, the second metal interconnect layer 133 is patterned through a photolithography and etching process to form a low-density interconnect wiring layer. The etching process can be wet etching or dry etching, which is not specifically limited in this embodiment.

[0087] In this embodiment, the first chip is a low-performance chip, such as a power device. In system-level packaging design, generally, the wiring requirements of low-performance chips are low. Therefore, a plurality of first chips and a plurality of passive devices are packaged in a fan-out panel-level manner to form the above-mentioned low-density interconnect wiring layer, which can improve the yield and reduce the manufacturing cost.

[0088] Exemplarily, the dielectric materials of the first dielectric layer 151 and the second dielectric layer 131 are different. The material of the first dielectric layer 151 is polyimide (PI), polybenzoxazole (PBO), etc., and the material of the second dielectric layer 131 is a photosensitive dielectric layer (PID) or an Ajinomoto build-up film (ABF), etc. This is because the first dielectric layer 151 is fabricated in a wafer-level process, and the second dielectric layer 131 is fabricated in a panel-level process. The preferred dielectric layer is selected according to different processes, and the materials of the two dielectric layers being close to each other will not cause problems such as contact difference or process infeasibility.

[0089] Exemplarily, after forming the low-density interconnect wiring layer, the method further includes:

[0090] First, a third dielectric layer is formed on the surface of the patterned second metal interconnect layer.

[0091] Specifically, as Figure 17As shown, a third dielectric layer 134 is covered on the surface of the patterned second metal interconnect layer 133. The material of the third dielectric layer 134 can be photosensitive solder resist (PSR) or the like, and this embodiment does not make specific limitations. The process of covering the third dielectric layer 134 on the second metal interconnect layer 133 can be vacuum lamination or printing process, and this embodiment does not make specific limitations on the process of covering the third dielectric layer 134 on the second metal interconnect layer 133.

[0092] Secondly, pattern the third dielectric layer to form a plurality of third openings.

[0093] Specifically, as Figure 17 shown, the third dielectric layer 134 is patterned through a photolithography process to form a plurality of third openings 135 on the third dielectric layer 134.

[0094] Finally, ball implantation is performed at the plurality of third openings to form a plurality of solder balls.

[0095] Specifically, as Figure 18 shown, ball implantation is performed at the plurality of third openings 135 to form a plurality of solder balls 136, and the plurality of solder balls 136 are electrically connected to the outside.

[0096] Exemplarily, as Figure 19 shown, after forming the plurality of solder balls 136, the plurality of functional chips and the first chips 130 and passive devices 140 located on both sides of each group of functional chips are cut to form a single group of chip package structures. Among them, each group of chip package structures includes a second chip 150 and a third chip 160 located in the middle region, and a first chip 130 and a passive device 140 located in the edge region.

[0097] It should be noted that if the thickness of the formed second encapsulation layer 180 is very thick, then after forming the solder balls 136, the side of the second encapsulation layer facing away from the plurality of functional chips can be polished to reduce the encapsulation thickness. It is also possible to polish the side of the second encapsulation layer facing away from the plurality of functional chips after forming the second encapsulation layer 180 to reduce the encapsulation thickness. Finally, an optimal package structure is formed.

[0098] The fan-out package method and package structure of the present invention. In this package method, a plurality of groups of functional chips adopt high-density interconnection, which can well meet the high-density interconnection requirements; the first chips and passive devices adopt low-density interconnection, which can improve the yield and reduce the manufacturing cost. By integrating the wafer-level fan-out technology and the panel-level fan-out technology, different levels of interconnection are integrated in one package. Compared with the current traditional fan-out wafer-level package, the fan-out package method of the present invention can provide lower cost and higher yield under the condition of the same interconnection density. Compared with the current traditional fan-out panel-level package, the fan-out package method of the present invention can provide higher interconnection density to meet the requirements of high-performance devices.

[0099] It should be noted that in the given embodiments, the dielectric layer structure is a three-layer or four-layer structure. In fact, the present invention can be applied to various numbers of layers and can be adjusted according to actual design requirements. The number of interconnect layers used in wafer-level and panel-level processes can also be adjusted according to actual design needs. For example, when high-density interconnects are also required for the second interconnect layer (which cannot be achieved in panel-level processes), two interconnect layers can be fabricated using wafer-level processes and then transferred to panel-level processes for subsequent processing.

[0100] It should be further noted that in the present invention, as Figure 2 shown, the middle area of the wafer carrier 110 is the chip layout area 112, and the chip layout area 112 is distributed in the first array A as shown in Figure 3 shown. The chip layout area 112 has a square structure, and the length of its diagonal is equivalent to the diameter of the wafer carrier 110. Through temporary bonding and wafer-level redistribution, a high-density interconnect wiring layer is formed in the middle area. The chip layout area 112 with completed high-density interconnects is diced and then integrally built onto the panel carrier 120 in the form of the second array B as shown in Figure 4 shown.

[0101] As Figure 4 shown, the current common size of the panel carrier 120 is 510×515 mm. In this case, 4 chip layout areas 112 can be placed simultaneously, and subsequent processes can be completed using panel-level packaging interconnect technology. The production efficiency can reach 4 times that of wafer-level packaging technology. In the future, if LCD panel technology is used, the production efficiency can be increased to 6 - 8 times, and the cost will be greatly reduced.

[0102] As Figure 2 shown, since the area of the chip layout area 112 is smaller than the area of the wafer carrier 110, there will be a certain area loss. Considering that the chips are all rectangular or square in size, the main loss area is the blank area 113 in the figure, and the short side dimension of it is 28 mm. For samples with a package size close to or larger than 28 mm, this area is an invalid area. However, for samples with a package size close to or smaller than 28 mm, the blank area 113 can still be used. Therefore, the design of the chip layout area 112 will not increase the cost of wafer-level packaging. Since high-density interconnects are mainly applied in fields such as high-performance computing, and the packaging in this field is moving towards larger sizes, the present invention has a significant effect of reducing costs.

[0103] In the package design, usually, the interconnect layer density is high near the chip and low far from the chip, and the connection line width shows a trend of gradually expanding. Taking advantage of this feature, in the packaging method of the fan-out package structure provided by the present invention, the fan-out wafer-level packaging technology and the fan-out panel-level packaging technology are integrally used to complete the production of the fan-out package. For the interconnect layer near the chip, the wafer-level packaging technology can well meet the high-density interconnect requirements, while for the interconnect layer far from the chip, the panel-level packaging technology can improve the yield and reduce the manufacturing cost.

[0104] As Figure 19 shown, on the other hand, the present invention provides a fan-out package structure 100, which includes a functional chip group (not marked in the figure), a first chip 130, a passive device 140, a high-density interconnect wiring layer (not marked in the figure), a low-density interconnect wiring layer (not marked in the figure), a first encapsulation layer 170, and a second encapsulation layer 180. Among them, conductive bumps 161 are arranged on the front surface of the functional chips in the functional chip group.

[0105] It should be noted that each functional chip group includes at least two different types of chips. As Figure 19 shown, in this embodiment, each functional chip group includes a second chip 150 and a third chip 160. The second chip 150 and the third chip 160 are different types of chips, and the second chip 150 and the third chip 160 are high-performance chips, such as processors, etc. Of course, each group of functional chips can also include other functional chips, and this embodiment does not make specific limitations. Conductive bumps 161 are arranged on the front surface of the functional chips in the functional chip group, that is to say, a plurality of conductive bumps 161 are arranged on the front surfaces of the second chip 150 and the third chip 160.

[0106] In this embodiment, the first chip 130 is a low-performance chip, or it can be other types of chips, and this embodiment does not make specific limitations. The passive device 140 can be at least one of a resistor, a capacitor, an inductor, a converter, a taper, a matching network, a resonator, a filter, a mixer, and a switch, etc., and this embodiment does not make specific limitations.

[0107] As Figure 19 and Figure 20 shown, the high-density interconnect wiring layer is arranged on the front surface of the first encapsulation layer 170 and the functional chips in the functional chip group. That is to say, the high-density interconnect wiring layer is arranged on the surface of the first encapsulation layer 170, and the front surfaces of the second chip 150 and the third chip 160. Further, as Figure 19 shown, the high-density interconnect wiring layer is arranged on the surface of the first encapsulation layer 170 and on the conductive bumps 161.

[0108] As Figure 19 andFigure 20 As shown, the low-density interconnect wiring layer is disposed above the high-density interconnect wiring layer and on the first surfaces of the first chip 130 and the passive device 140. In this embodiment, the first chip 130 and the passive device 140 are respectively disposed on two sides of the functional chip group.

[0109] As Figure 19 and Figure 20 shown, the first encapsulation layer 170 encapsulates the functional chip group. That is to say, the first encapsulation layer 170 encapsulates a plurality of second chips 150 and a plurality of third chips 160.

[0110] As Figure 19 and Figure 20 shown, the second encapsulation layer 180 encapsulates the functional chip group, the first chip 130, and the passive device 140. That is to say, the second encapsulation layer 180 encapsulates a plurality of first chips 130, a plurality of passive devices 140, a plurality of second chips 150, and a plurality of third chips 160.

[0111] Exemplarily, as Figure 18 shown, the high-density interconnect wiring layer includes a first dielectric layer 151 disposed on the conductive bump 161 and a first metal interconnect layer 153 disposed above the first dielectric layer 151. That is to say, the first dielectric layer 151 is disposed on the conductive bump 161 in each group of functional chips.

[0112] Exemplarily, the low-density interconnect wiring layer includes a second dielectric layer 131 disposed above the first metal interconnect layer 153 and on the first surfaces of the first chip 130 and the passive device 140, and a second metal interconnect layer 133 disposed above the second dielectric layer 131.

[0113] Exemplarily, the packaging structure further includes a third dielectric layer 134 and a plurality of solder balls 136. The third dielectric layer 134 is disposed above the second metal interconnect layer 133, and the plurality of solder balls 136 are disposed above the third dielectric layer 134.

[0114] The fan-out packaging structure provided by the present invention not only has low cost and high yield, but also can well meet the requirements of high-density interconnect.

[0115] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present invention. However, the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A fan-out packaging method, characterized in that The method includes: providing a wafer carrier and a panel carrier; fixing the back sides of multiple groups of functional chips on the surface of the wafer carrier in a first array form, and forming a first encapsulation layer on the front sides of the multiple groups of functional chips, wherein a plurality of conductive bumps are disposed on the front sides of the multiple groups of functional chips; separating the multiple groups of functional chips from the wafer carrier, and forming a high-density interconnect wiring layer on the front sides of the multiple groups of functional chips; dicing the multiple groups of functional chips, and fixing the side with the high-density interconnect wiring layer formed thereon on the surface of the panel carrier in a second array form; fixing the first surfaces of a plurality of first chips and a plurality of passive devices on the surface of the panel carrier; forming a second encapsulation layer on the side of the multiple groups of functional chips facing away from the high-density interconnect wiring layer, and on the second surfaces of the plurality of first chips and the plurality of passive devices; separating the multiple groups of functional chips, the plurality of first chips, and the plurality of passive devices from the panel carrier, and forming a low-density interconnect wiring layer on the high-density interconnect wiring layer.

2. The method according to claim 1, wherein Before forming the high-density interconnect wiring layer on the front sides of the multiple groups of functional chips, the method further includes: separating the multiple groups of functional chips from the wafer carrier, and grinding the front sides of the multiple groups of functional chips to expose the conductive bumps.

3. The method according to claim 2, characterized in that, Forming the high-density interconnect wiring layer on the front sides of the multiple groups of functional chips includes: forming a first dielectric layer on the first encapsulation layer and the plurality of conductive bumps; patterning the first dielectric layer to form a plurality of first openings; forming a first metal interconnect layer on the surface of the patterned first dielectric layer, wherein the first metal interconnect layer is electrically connected to the conductive bumps; patterning the first metal interconnect layer to form the high-density interconnect wiring layer.

4. The method according to claim 3, wherein Forming the low-density interconnect wiring layer on the surface of the high-density interconnect wiring layer includes: forming a second dielectric layer on the surface of the high-density interconnect wiring layer, the first surfaces of the plurality of first chips, and the plurality of passive devices; patterning the second dielectric layer to form a plurality of second openings; forming a second metal interconnect layer on the surface of the patterned second dielectric layer; patterning the second metal interconnect layer to form the low-density interconnect wiring layer.

5. The method according to claim 4, wherein After forming the low-density interconnect wiring layer, the method further includes: forming a third dielectric layer on the surface of the patterned second metal interconnect layer; patterning the third dielectric layer to form a plurality of third openings; performing ball planting at the plurality of third openings to form a plurality of solder balls.

6. The method according to any one of claims 1 to 5, characterized in that, Each group of functional chips includes at least two different types of chips.

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