Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: forming a groove on a substrate. The groove has a side surface and a bottom surface. Forming a first dielectric layer on the side surface and the bottom surface of the groove, and on the substrate, so that the first dielectric layer has a groove. Filling a first conductive material in the groove. Etching back the first conductive material to form a first conductive layer and exposing a portion of the first dielectric layer located on the side surface of the groove. Etching the first dielectric layer so that the portion of the first dielectric layer located on the side surface of the groove has a width that decreases in a direction away from the bottom surface of the groove. Filling a second conductive material in the groove to form a second conductive layer on the first conductive layer. The semiconductor structure and the method for forming the same provided by the embodiments of the present invention can reduce or avoid defects in the formed conductive structure to obtain a semiconductor structure with better electrical characteristics and reliability.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for forming the same, and more particularly to a semiconductor structure and a method for forming the same capable of reducing defects in a conductive layer. Background Art

[0002] In recent years, shielded gate trench (SGT) MOSFETs have been widely used and researched due to their lower on-resistance (Rds_on), which significantly reduces power consumption. They have become the mainstream of high-frequency, low-voltage power components.

[0003] In SGT-MOSFETs, different conductive materials are often selected for the electrodes based on user needs. Common electrode materials include metals, polysilicon, and conductive metal oxides. However, due to the trench structure of SGT-MOSFETs, the filling of the electrode material can be affected by defects caused by the trench shape, the trench aspect ratio, and / or the type of electrode material, which can affect the electrical characteristics of the resulting electrodes. Furthermore, this can even impact the electrical characteristics and reliability of the entire SGT-MOSFET.

[0004] Therefore, while existing semiconductor structures and their formation methods have gradually met their intended uses, they still do not fully meet the requirements in all aspects. Therefore, there are still some challenges to overcome in order to further process the semiconductor structures and their formation methods that can be used as SGT-MOSFETs. Summary of the Invention

[0005] In view of the above problems, the present invention reduces or avoids defects in the formed conductive structure through at least two steps of etching back the conductive material; etching a portion of the dielectric layer; and refilling the conductive material, thereby obtaining a semiconductor structure with better electrical characteristics and reliability.

[0006] The present invention provides a method for forming a semiconductor structure. A recess is formed on a substrate. The recess has side surfaces and a bottom surface. A first dielectric layer is formed on the side surfaces and bottom surfaces of the recess and on the substrate, so that the first dielectric layer has a groove. A first conductive material is filled in the groove. The first conductive material is etched back to form a first conductive layer and expose a portion of the first dielectric layer located on the side surface of the recess. The first dielectric layer is etched so that the portion of the first dielectric layer located on the side surface of the recess has a width that decreases as it moves away from the bottom surface of the recess. A second conductive material is filled in the groove to form a second conductive layer on the first conductive layer.

[0007] The present invention further provides a semiconductor structure. The semiconductor structure includes a substrate, a first dielectric layer, a shielding electrode, a second dielectric layer, a gate electrode, and a source electrode. The substrate has a groove. The groove includes a first groove and a second groove. The first dielectric layer is disposed on the side surface and bottom surface of the first groove, and the side surface and bottom surface of the second groove, and has a first groove corresponding to the first groove, and a second groove corresponding to the second groove. The shielding electrode is disposed in the first groove. The second dielectric layer is disposed in the first groove and on the shielding electrode. The gate electrode is disposed in the first groove and on the second dielectric layer. The source electrode is disposed in the second groove. Part of the first dielectric layer located on the side surface of the second groove has a width that decreases in a direction away from the bottom surface of the second groove.

[0008] The semiconductor structure provided by the present invention can be applied to various types of semiconductor devices. To make the features and advantages of the present invention more clearly understood, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0010] Figures 1 to 9 is a schematic cross-sectional view illustrating a semiconductor structure formed at various stages according to some embodiments of the present invention; and

[0011] Figures 10 to 19 According to some embodiments of the present invention, Figure 9 The semiconductor structure shown is a schematic cross-sectional view of the SGT-MOSFET in various stages of forming some embodiments of the present invention.

[0012] Description of reference numerals:

[0013] 1: Semiconductor structure

[0014] 100: Substrate

[0015] 101: Patterned Hard Mask

[0016] 110: First doped region

[0017] 120: Second doping region

[0018] 120: Groove

[0019] 121: First groove

[0020] 122: Second groove

[0021] 200: First dielectric layer

[0022] 210, 220: Sub-dielectric layer

[0023] 300: first conductive material

[0024] 310, 320: first conductive layer

[0025] 400: Second conductive material

[0026] 410, 420: second conductive layer

[0027] 430: Photoresist layer

[0028] 500: Second dielectric layer

[0029] 600: The third conductive material

[0030] 610: third conductive layer

[0031] 700: Third dielectric layer

[0032] 701: Through-hole material

[0033] 710, 720, 730: Contact plugs

[0034] 800: Metal layer

[0035] CT: Contact Through Hole

[0036] ILD: Interlayer Dielectric Layer

[0037] L1: First depth

[0038] L2: Second Depth

[0039] L3: Third Depth

[0040] L4: Fourth Depth

[0041] OP: Opening

[0042] T: Groove

[0043] T1: First groove

[0044] T2: Second groove

[0045] W1: first width

[0046] W2: Second width

[0047] W3: third width

[0048] W4: fourth width

[0049] W5: fifth width DETAILED DESCRIPTION

[0050] The present invention below provides many different embodiments or examples for implementing different components of the provided semiconductor structure. Specific examples of each component and its configuration are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, if the description refers to a first component formed on a second component, it may include an embodiment in which the first and second components are in direct contact, and it may also include an embodiment in which an additional component is formed between the first and second components so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numbers and / or letters in different examples. Such repetition is for simplicity and clarity, and is not intended to indicate the relationship between the different embodiments and / or forms discussed.

[0051] In the different drawings and the embodiments of the description, the same or similar component symbols are used to mark the same or similar components. It is understood that additional operations can be provided before, during, and after the method, and some narrated operations can be replaced or deleted for other embodiments of the method.

[0052] Figures 1 to 9 1 is a schematic cross-sectional view illustrating the formation of a semiconductor structure 1 at various stages according to some embodiments of the present invention.

[0053] like Figure 1 As shown, a substrate 100 of a semiconductor structure is provided, and a patterned hard mask 101 is disposed on the substrate 100. The substrate 100 may be a wafer, such as a silicon wafer. The substrate 100 may be a bulk semiconductor or a semiconductor-on-insulation (SOI) substrate. Generally speaking, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer is, for example, a buried oxide (BOX) layer, a silicon oxide layer, or a similar material, which provides an insulating layer on a silicon or glass substrate. Other substrate types include, for example, multi-layer or gradient substrates.

[0054] The substrate 100 may be an elemental semiconductor, including silicon and germanium. The substrate 100 may also be a compound semiconductor, including, for example, but not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. The substrate 100 may also be an alloy semiconductor, including, for example, but not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or any combination thereof.

[0055] The substrate 100 may optionally include an epitaxial layer (not shown) and / or a semiconductor layer (not shown). Alternatively, the semiconductor layer may be formed in a subsequent step by ion implantation. The epitaxial layer may include silicon, germanium, silicon and germanium, a III-V compound, or a combination thereof. The epitaxial layer may be formed by an epitaxial growth process.

[0056] In some embodiments, the substrate 100 and the epitaxial layer have a first conductivity type, and the semiconductor layer has a second conductivity type different from the first conductivity type. For example, if the first conductivity type of the substrate 100 and the epitaxial layer is N-type, the second conductivity type of the semiconductor layer is P-type; conversely, if the first conductivity type of the substrate 100 and the epitaxial layer is P-type, the second conductivity type of the semiconductor layer is N-type. The first and second conductivity types can be adjusted as needed, as can the doping concentration, doping depth, and doping region size.

[0057] According to different needs of users, the patterned hard mask 101 may have a shape corresponding to a groove subsequently formed on the substrate 100. The patterned hard mask 101 may expose a portion of the top surface of the substrate 100. The patterned hard mask 101 may include an oxide, a nitride, or a combination thereof. In some embodiments, the oxide layer may include, for example, an oxide with tetraethyl orthosilicate (TEOS) as a precursor or other suitable oxides. The nitride may include silicon nitride (SiN), silicon oxynitride (SiON), titanium nitride (TiN), tantalum nitride (TaN), or other suitable nitrides. It is understandable that a suitable hard mask material can be matched according to process conditions, so the embodiments of the present invention are not limited thereto.

[0058] In some embodiments, the patterned hard mask layer 101 is an oxide. In some embodiments, the step of forming the patterned hard mask layer 101 on the substrate 100 may further include: depositing an oxide layer as a hard mask layer on the substrate 100; forming a photoresist layer on the oxide layer; exposing the photoresist layer as required to obtain a patterned photoresist layer; using the patterned photoresist layer as an etch mask to etch the oxide layer to form a patterned oxide layer; and removing the patterned photoresist layer to obtain the patterned hard mask layer 101 on the substrate 100. The oxide layer may be deposited by chemical vapor deposition (CVD) or other suitable processes. The photoresist layer may be removed by ashing and / or wet stripping processes.

[0059] like Figure 2 As shown, the substrate 100 is etched using the patterned hard mask layer 101 as an etching mask to form a recess 120 on the substrate 100. In some embodiments, a subsequently formed electrode is disposed in the recess 120; that is, the electrode is disposed at a position corresponding to the position of the recess 120. In some embodiments, a plurality of recesses 120 may be provided, depending on the shape of the opening of the patterned hard mask layer 101. In some embodiments, the recess 120 may include a first recess 121 and a second recess 122. In some embodiments, the shield electrode and gate electrode of a subsequently formed SGT-MOSFET may be disposed corresponding to the first recess 121, and the source electrode of the subsequently formed SGT-MOSFET may be disposed corresponding to the second recess 122.

[0060] To facilitate explanation of the relative placement of the shield electrode, gate electrode, and source electrode in the subsequently formed SGT-MOSFET, the following detailed description assumes that the recess 120 includes a first recess 121 and a second recess 122. However, the present invention is not limited to this embodiment. Specifically, the first recess 121 and the second recess 122 can be formed simultaneously in the same process, thereby forming the shield electrode and the source electrode simultaneously. Alternatively, the first recess 121 and the second recess 122 can be formed sequentially in different processes, thereby forming the shield electrode and the source electrode sequentially in different processes.

[0061] Furthermore, it should be noted that, for ease of understanding, the following detailed description and illustrations assume that the first and second grooves 121 and 122 have the same shape, depth, and width. However, the present invention is not limited thereto. In other words, the shapes, depths, and widths of the first and second grooves 121 and 122 may be substantially different depending on actual needs.

[0062] like Figure 3As shown, the patterned hard mask layer 101 is removed. The patterned hard mask layer 101 can be removed by performing an etching process or other suitable process. The etching process may include dry etching, wet etching, or other suitable etching methods. Dry etching may include but is not limited to plasma etching, plasma-free gas etching, sputtering etching, ion milling, reactive ion etching (RIE). Wet etching may include but is not limited to using an acidic solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed. In addition, the etching process may also be pure chemical etching, pure physical etching, or any combination thereof.

[0063] like Figure 3 As shown, the first groove 121 formed in the substrate 100 has a first depth L1 and a first width W1, and the second groove 122 has substantially the same depth and width as the first groove 121. The first groove 121 has a side surface and a bottom surface, and the second groove 122 also has a side surface and a bottom surface.

[0064] like Figure 4 As shown, a first dielectric layer 200 is conformally, that is, conformally, formed on the side surfaces and bottom surface of the recess 120, and on a portion of the substrate 100, so that the first dielectric layer 200 has a trench T. Since the recess 120 may include a first recess 121 and a second recess 122, the first dielectric layer 200 may include a sub-dielectric layer 210 corresponding to the first recess 121 and a sub-dielectric layer 220 corresponding to the second recess 122. Furthermore, since the first dielectric layer 200 includes the sub-dielectric layer 210 and the sub-dielectric layer 220, the trench T may include a first trench T1 corresponding to the sub-dielectric layer 210 and a second trench T2 corresponding to the sub-dielectric layer 220.

[0065] In some embodiments, the first dielectric layer 200 may be made of silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, or any other suitable dielectric material, or a combination thereof. The high-k dielectric material may be made of a metal oxide, a metal nitride, a metal silicide, a transition metal oxide, a transition metal nitride, a transition metal silicide, a metal oxynitride, a metal aluminate, a zirconium silicate, or a zirconium aluminate. For example, the high-k dielectric material may be LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfO2, HfO3, HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr)TiO3 (BST), Al2O3, other suitable dielectric materials, or combinations thereof, but is not limited thereto. In some embodiments, the first dielectric layer 200 may include an oxide.

[0066] In some embodiments, the first dielectric layer 200 can be formed by CVD or thermal oxidation. CVD can be low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), PECVD, atomic layer deposition (ALD) using atomic layer chemical vapor deposition, or other suitable CVD processes. In some embodiments, the first dielectric layer 200 is formed by thermal oxidation in a furnace.

[0067] Specifically, the first dielectric layer 200 may include a sub-dielectric layer 210 conformally formed on the first recess 121, and a sub-dielectric layer 220 conformally formed on the second recess 122. The sub-dielectric layer 210 is disposed on the side and bottom surfaces of the first recess 121, thereby forming a first trench T1. The sub-dielectric layer 220 is disposed on the side and bottom surfaces of the second recess 122, thereby forming a second trench T2. As shown in FIG. 4 , the first trench T1 has a second depth L2 and a second width W2, and the second trench T2 has substantially the same depth and width as the first trench T1. In some embodiments, because the first dielectric layer 200 has a specific thickness, the second depth L2 of the first trench T1 is less than the first depth L1 of the first recess 121, and the second width W2 of the first trench T1 is less than the first width W1 of the first recess 121.

[0068] That is to say, with Figure 3 Shown and Figure 4 As shown, since a portion of the first dielectric layer 200 is formed in the recess 120, before the first dielectric layer 200 is formed in the recess 120, the aspect ratio of the recess 120 is the ratio of the first depth L1 to the first width W1. However, after the first dielectric layer 200 is formed in the recess 120, the aspect ratio of the trench T of the first dielectric layer 200 is the second depth L2 to the second width W2. Therefore, when the second depth L2 of the first trench T1 is less than the first depth L1 of the first recess 121, and the second width W2 of the first trench T1 is less than the first width W1 of the first recess 121, the aspect ratio increases after the first dielectric layer 200 is formed. However, when the trenches, recesses, holes, concave portions, or similar structures to be filled have a large aspect ratio, it is difficult for a filling material, such as a conductive material, to be uniformly filled in the above-mentioned structures. This may result in undesirable structures such as voids, holes, seam defects in the conductive material body, and / or recesses on the surface of the conductive material. These may degrade the electrical characteristics of the conductive structure in the semiconductor structure and reduce the reliability of the subsequently formed SGT-MOSFET.

[0069] In order to reduce or prevent the generation of defective conductive structures in the filling step, that is, the process of forming the conductive structure, some embodiments of the present invention use a multi-stage formation process, for example, at least a two-stage formation process, to reduce the defective structures in the formed conductive structure, thereby obtaining a semiconductor structure with better electrical characteristics and reliability. Figures 5 to 91 , a two-stage formation process of some embodiments of the present invention is described in detail, which includes etching back a first conductive layer; etching a portion of a first dielectric layer; and forming a second conductive layer on the first conductive layer.

[0070] like Figure 5 As shown, the first conductive material 300 is filled in the trench T. That is, the first trench T1 and the second trench T2 are filled with the first conductive material 300 to obtain a first conductive layer disposed in the first trench T1 and the second trench T2. The first conductive material 300 may include polycrystalline silicon, metal, metal nitride, conductive metal oxide, or other suitable materials. In some embodiments, the first conductive material 300 may be polycrystalline silicon. The method of filling the first conductive material 300 may include: CVD, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process, but is not limited thereto. In some embodiments, the method of filling the first conductive material 300 is in-situ deposition.

[0071] In some embodiments, when the first conductive material 300 is polysilicon, a concave portion may be generated on the surface of the first conductive material 300 at the center axis of the trench T, and the first conductive material 300 in the trench T may have the following characteristics: Figure 5 In some embodiments, when viewed in cross-section, the surface of the first conductive material 300 may have a concave portion having a V-shape, a U-shape, a round shape, or other irregular concave shapes.

[0072] Then, if Figure 6As shown, the first conductive material 300 is etched back until the top surface of the first dielectric layer 200 is exposed, forming a first conductive layer 310 disposed in the first trench T1 and a first conductive layer 320 disposed in the second trench T2. In some embodiments, the top surface of the first conductive layer 310 is lower than the top surface of the sub-dielectric layer 210, and the top surface of the first conductive layer 320 is lower than the top surface of the sub-dielectric layer 220. In some embodiments, the etching back of the first conductive material 300 exposes a portion of the first dielectric layer 200 located on the side surface of the recess 120, forming an opening OP located above the trench T. The depth of the etching back of the first conductive material 300 affects the size of the exposed portion of the first dielectric layer 200. The width of the opening OP can be substantially the same as the second width W2 of the trench T. The deeper the etching back of the first conductive material 300, that is, the shorter the lengths of the first conductive layers 310 and 320, the larger the size of the exposed portion of the first dielectric layer 200. In some embodiments, even if the first conductive material 300 has been etched back, a recessed portion may still be formed on the surface of the etched first conductive material 300 corresponding to the central axis of the trench T, and the first conductive material 300 in the trench T may still have seam defects.

[0073] In some embodiments, since the depth of etching back the first conductive material 300 affects the aspect ratio of the to-be-filled region located above the first conductive layers 310 and 320, the aspect ratio of the to-be-filled region located above the first conductive layers 310 and 320 can be reduced by appropriately etching back the first conductive material 300. In some embodiments, the first conductive material 300 is etched back to a third depth L3, so that the depth of the exposed portion of the first dielectric layer 200 located on the side surface of the recess 120 is substantially the third depth L3. The ratio of the third depth L3 to the second depth L2 can be 1 / 2 to 1 / 7. Preferably, the ratio of the third depth L3 to the second depth L2 can be 2 / 5 to 1 / 7; more preferably, the ratio of the third depth L3 to the second depth L2 can be 1 / 3 to 1 / 7. In some embodiments, the ratio of the third depth L3 to the second depth L2 can be any numerical range between 1 / 2 and 1 / 7. If the ratio of the third depth L3 to the second depth L2 is too large, meaning the etch-back depth is too deep, the aspect ratio of the area to be filled above the first conductive layers 310 and 320, i.e., the ratio of the third depth L3 to the second width W2, will still be too large, causing seam defects and / or recesses to reappear in the area to be filled. If the ratio of the third depth L3 to the second depth L2 is too small, meaning the etch-back depth is too shallow, it will be difficult to effectively eliminate or reduce the seam defects in the first conductive layers 310 and 320 themselves. It should be noted that in some embodiments, even if the seam defects in the first conductive layers 310 and 320 themselves are not completely eliminated, the electrical characteristics and reliability of the overall semiconductor structure can still be improved because the semiconductor structure and formation method thereof of some embodiments of the present invention can keep the seam defects relatively far away from the contact plugs in the subsequently formed SGT-MOSFET.

[0074] Furthermore, if Figure 7As shown, the first dielectric layer 200 is etched to remove a portion of the first dielectric layer 200, so that the portion of the first dielectric layer 200 located on the side surface of the groove 120 has a width that decreases in a direction away from the bottom surface of the groove 120. The process of etching the first dielectric layer 200 may include dry etching, wet etching, or other suitable etching methods. In some embodiments, the first dielectric layer 200 is etched by a wet etching process. In some embodiments, a buffered oxide etchant (BOE) is used as a wet etchant. BOE includes hydrofluoric acid (HF), ammonium fluoride (NH4F), and water, but is not limited thereto. Any etchant capable of etching the first dielectric layer 200 can be used. In addition, the first conductive layers 310 and 320 are used as etching masks to perform wet etching. Without the first conductive layers 310 and 320 serving as etching masks, it may be difficult to perform a wet etching process on the specific portion, and thus the portion of the first dielectric layer 200 cannot be effectively removed.

[0075] Next, after wet etching the first dielectric layer 200, the wet etching process removes a portion of the first dielectric layer 200 located on the side surfaces of the recess 120 and a portion of the first dielectric layer 200 located on the top surface of the substrate 100. This removes the fifth width W5 of the upper portion of the first dielectric layer 200 and the fourth width W4 of the lower portion of the first dielectric layer 200. Furthermore, the third width W3 located above the opening OP is greater than the second width W2 located below the opening OP. In some embodiments, the second width W2 corresponds to the fourth width W4, and the third width W3 corresponds to the fifth width W5. The shape of the opening OP can be modified by adjusting parameters such as the wet etching process's etch rate and etch selectivity. In some embodiments, the ratio of the third width W3 to the second width W2 can be between 1.1 and 1.5. Correspondingly, the ratio of the fifth width W5 to the fourth width W4 can be less than 1; preferably, it can be between 0.5 and 1. When the ratio of the third width W3 to the second width W2 is too large, the insulation properties of the sidewalls of the electrode subsequently formed in the trench T may be poor, resulting in leakage current or short circuit problems; however, when the ratio of the third width W3 to the second width W2 is too small, the shape of the opening OP cannot be significantly transformed into a shape that is wide at the top and narrow at the bottom, so it is difficult to improve the ease of subsequent filling of the second conductive material. In addition, seam defects may still exist in the second conductive material itself that is subsequently filled.

[0076] like Figure 8As shown, a second conductive material 400 is filled in the trench T to form a second conductive layer on the first conductive layers 310 and 320. In some embodiments, the first conductive material 300 and the second conductive material 400 may be the same or different. In some embodiments, the first conductive material 300 and the second conductive material 400 are the same, so the filled first conductive material 300 and the second conductive material 400 can together form a conductive structure. In some embodiments, the first conductive material 300 and the second conductive material 400 are both polysilicon. Therefore, although the first conductive material 300 and the second conductive material 400 are disposed sequentially, the first conductive material 300 and the second conductive material 400 can be integrated into a conductive structure.

[0077] In detail, since the first conductive layers 310 and 320 are already provided in the trench T, the depth-to-width ratio of the area to be filled above the first conductive layers 310 and 320 is small, that is, the ratio of the third depth L3 to the second width W2 is smaller than the ratio of the second depth L2 to the second width W2 (e.g. Figure 7 As shown, the second conductive material 400 further filled in the trench T does not have seam defects and has good electrical characteristics. In addition, the second conductive material 400 can be filled to effectively fill the recessed portions on the surfaces of the first conductive layers 310 and 320, so that the conductive structure including both the first conductive material 300 and the second conductive material 400 has good electrical characteristics.

[0078] like Figure 9 As shown, by planarizing the second conductive material 400, a second conductive layer 410 disposed on the first conductive layer 310 and a second conductive layer 420 disposed on the first conductive layer 320 are formed. In some embodiments, the planarization process may include, but is not limited to, a chemical mechanical polishing (CMP) process, so that the top surfaces of the second conductive layers 410 and 420 are substantially coplanar with the top surface of the first dielectric layer 200. In some embodiments, the planarization process may also include, but is not limited to, an etch back process, so that the top surfaces of the second conductive layers 410 and 420 are substantially coplanar with the top surface of the first dielectric layer 200. In some embodiments, although the surface of the second conductive material 400 processed by the etch back process may still have slight depressions, the slight depressions generated after the etch back process do not significantly affect the electrical properties of the overall semiconductor structure. That is, by planarizing the second conductive material 400 , the problem of depressions on the surface of the second conductive material 400 or the problem of depressions affecting electrical properties can be easily eliminated, thereby forming second conductive layers 410 and 420 with good electrical properties, thereby obtaining the semiconductor structure 1 of some embodiments of the present invention.

[0079] In some embodiments, due to the opening OP (eg Figure 7 2 (shown in FIG. 2 ), the second conductive layers 410 and 420 have a shape that is wider at the top and narrower at the bottom, and thus the second conductive layers 410 and 420 have a shape corresponding to the opening OP. In other words, since the shape of the opening OP corresponds to the shape of the first dielectric layer 200, the second conductive layers 410 and 420 have a shape corresponding to the first dielectric layer 200. In some embodiments, the width of the top surface of the second conductive layers 410 and 420 is greater than the width of the bottom surface.

[0080] In short, in some embodiments of the present invention, the depth of the area to be filled located above the first conductive layers 310 and 320 is adjusted by etching back the first conductive material 300; a portion of the first dielectric layer 200 is removed using a wet etching process so that the opening OP has a shape that is wide at the top and narrow at the bottom; and a two-stage formation process of filling the second conductive material 400 is used to achieve the advantages of (1) reducing seam defects in the filled second conductive material 400, (2) forming the second conductive layers 410 and 420 with good electrical properties, and / or (3) filling the recessed portions on the surfaces of the first conductive layers 310 and 320 with the filled second conductive material 400 to eliminate defects in the first conductive layers 310 and 320, thereby forming a semiconductor structure 1 with good electrical characteristics.

[0081] After obtaining the semiconductor structure 1 according to some embodiments of the present invention, further processes may be performed to obtain an SGT-MOSFET having the semiconductor structure 1. Therefore, the SGT-MOSFET structure based on the semiconductor structure 1 is described in detail below.

[0082] It should be noted that, for ease of description, the following detailed description focuses on the SGT-MOSFET structure including the shield electrode and gate electrode disposed in the first trench T1 and the source electrode disposed in the second trench T2 . However, the present invention is not limited thereto.

[0083] like Figure 10As shown, since the first conductive layer 310 and the second conductive layer 410 in the first trench T1 will later form a shield electrode, a portion of the second conductive layer 410 needs to be removed to facilitate the placement of a gate electrode on the shield electrode. However, since the first conductive layer 320 and the second conductive layer 420 in the second trench T2 will later form a source electrode, a photoresist layer 430 can be provided to protect the first conductive layer 320 and the second conductive layer 420. Therefore, a portion of the second conductive layer 410 disposed in the first trench T1 is removed, so that the top surface of the second conductive layer 410 is lower than the top surface of the substrate 100, leaving a conductive structure serving as a shield electrode in the first trench T1. The conductive structure serving as the shield electrode includes the first conductive layer 310 and the remaining second conductive layer 410. The portion of the second conductive layer 410 can be removed by performing an etching process or other suitable process. The etching process herein can include any of the aforementioned etching processes.

[0084] In some embodiments, a portion of the second conductive layer 410 is removed until the top surface of the second conductive layer 410 is coplanar with the top surface of the first conductive layer 310. However, the present invention is not limited thereto. In some embodiments, the top surface of the second conductive layer 410 may be higher than the top surface of the first conductive layer 310. Therefore, it should be noted that as long as the remaining second conductive layer 410 can completely fill the recessed portion on the surface of the first conductive layer 310 after the portion of the second conductive layer 410 is removed, the defect in the first conductive layer 310 can be eliminated.

[0085] like Figure 11 As shown, a portion of the first dielectric layer 200, that is, a portion of the sub-dielectric layer 210 corresponding to the first trench T1, is removed, so that the top surface of the sub-dielectric layer 210 is parallel to or lower than the top surface of the conductive structure. In some embodiments, the top surface of the sub-dielectric layer 210 is lower than the top surface of the second conductive layer 410. In some embodiments, the photoresist layer 430 is removed to expose the sub-dielectric layer 220 and the second conductive layer 420.

[0086] like Figure 12As shown, a second dielectric layer 500 is conformally formed on the conductive structure, that is, formed on the second conductive layer 420. In some embodiments, the bottom surface of the second dielectric layer 500 has a shape corresponding to the sub-dielectric layer 210 and the conductive structure. In some embodiments, the bottom surface of the second dielectric layer 500 may be a substantially flat surface. In some embodiments, since the top surface of the second conductive layer 420 is higher than the top surface of the substrate 100, the second dielectric layer 500 may be step-shaped. In some embodiments, the second dielectric layer 500 serves as a gate dielectric layer. The second dielectric layer 500 may be silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or any other suitable dielectric material, or a combination thereof, but is not limited thereto. In some embodiments, the second dielectric layer 500 may include an oxide. In some embodiments, the second dielectric layer 500 and the first dielectric layer 200 may be formed using the same or different processes.

[0087] like Figure 13 As shown, a third conductive material 600 is filled to form a third conductive layer 610 on the second dielectric layer 500. In some embodiments, similar to Figure 5 The surfaces of the first conductive material 300 and the third conductive material 600 shown may have recessed portions. However, due to the aspect ratio of the first recess 121, the recessed portions may not appear in the first recess 121. In some embodiments, the third conductive material 600 may be the same as or different from the first conductive material 300 and the second conductive material 400. In some embodiments, the third conductive material 600 may be polysilicon. In some embodiments, the third conductive layer 610 serves as a gate electrode. In some embodiments, because the second dielectric layer 500 is conformally formed on the sub-dielectric layer 210 and the conductive structure, the third conductive layer 610 has an extension extending toward the conductive structure. In other words, a portion of the bottom surface of the third conductive layer 610 is lower than the top surface of the second conductive layer 410.

[0088] like Figure 14As shown, in one embodiment, the process of filling the third conductive material 600 can be the same as or different from the process of filling the first conductive material 300 and the second conductive material 400. Specifically, in some embodiments, the third conductive material 600 can be filled on the second dielectric layer 500, and then a planarization process can be further performed to expose the top surface of the second dielectric layer 500. In some embodiments, during the planarization process, such as a polysilicon etch back process, a portion of the second dielectric layer 500 is etched, thereby reducing the thickness of the portion of the second dielectric layer 500. However, the second dielectric layer 500 is still retained and the second dielectric layer 500 may not be completely etched. In some embodiments, the first conductive layer 320 and the second conductive layer 420 protected by the second dielectric layer 500 can serve as a source electrode.

[0089] like Figure 15 As shown, after the planarization step is performed, the thickness of a portion of the second dielectric layer 500 is reduced. Then, a third dielectric layer 700 is formed on the gate electrode and the source electrode. The third dielectric layer 700 is formed on the third conductive layer 610 serving as the gate electrode, and the third dielectric layer 700 is formed on the second conductive layer 420 serving as a portion of the source electrode. The third dielectric layer 700 forms an interlayer dielectric (ILD) layer with the first dielectric layer 200 and the second dielectric layer 500 on the top surface of the substrate 100. In some embodiments, the first dielectric layer 200 on the top surface of the substrate 100 may be a portion of the sub-dielectric layer 220 on the top surface of the substrate 100. The third dielectric layer 700 may be silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or any other suitable dielectric material, or a combination thereof, but is not limited thereto. In some embodiments, the third dielectric layer 700 and the second dielectric layer 500 or the first dielectric layer 200 may be formed of the same or different materials. In some embodiments, the third dielectric layer 700 and the second dielectric layer 500 or the first dielectric layer 200 may be formed by the same or different processes.

[0090] like Figure 16As shown, for ease of subsequent description and understanding, the first dielectric layer 200, the second dielectric layer 500, and the third dielectric layer 700 are simply referred to as the interlayer dielectric layer ILD. A first doped region 110 and a second doped region 120 are formed in the substrate 100. The second doped region 120 is further away from the top surface of the substrate 100 than the first doped region 110. That is, the second doped region 120 is further away from the interlayer dielectric layer ILD than the first doped region 110. Methods for forming the first doped region 110 and the second doped region 120 include, for example, ion implantation or diffusion processes, but are not limited thereto. In addition, the implanted dopants can also be activated by a rapid thermal annealing (RTA) process. In some embodiments, the first doped region 110 and the second doped region 120 have the same or different conductivity types. In some embodiments, the first doped region 110 and the second doped region 120 have the same conductivity type. In some embodiments, the substrate 100 has a first conductivity type, and the first doped region 110 and the second doped region 120 have a second conductivity type different from the first conductivity type. For example, if the first conductivity type of the substrate 100 is N-type, the second conductivity type of the first doped region 110 and the second doped region 120 is P-type. The first conductivity type and the second conductivity type can be adjusted as needed.

[0091] like Figure 17 As shown, a contact via CT is formed. The contact via CT may penetrate the interlayer dielectric layer ILD. In some embodiments, the bottom surface of the contact via CT is lower than the top surface of the third conductive layer 610 to ensure good electrical contact between the contact plug subsequently formed in the contact via CT and the third conductive layer 610, which serves as the gate electrode, and the first conductive layer 320 and the second conductive layer 420, which collectively serve as the source electrode. In some embodiments, the bottom surface of the contact via CT is lower than the top surface of the second conductive layer 420. In some embodiments, the contact via CT penetrates the first doped region 110 but does not penetrate the second doped region 120. In some embodiments, the first doped region 110 and the second doped region 120 jointly cover the contact plug subsequently formed. The contact via CT exposes a portion of the third conductive layer 610 and the second conductive layer 420. In other embodiments, the bottom surface of the contact via CT is flush with the top surface of the third conductive layer 610 and the top surface of the second conductive layer 420.

[0092] In some embodiments, the steps of forming the first doped region 110 and the second doped region 120 can be adjusted according to needs, and the order of the steps of forming the contact through hole CT can be adjusted according to process requirements, but the present invention is not limited thereto.

[0093] like Figure 18 As shown, a through-hole material 701 is filled into the contact through-hole CT to form contact plugs 710, 720, and 730. In some embodiments, the through-hole material may include a metal material, a conductive material, or other suitable materials. In some embodiments, a portion of the through-hole material 701 on the interlayer dielectric layer ILD and the contact through-hole CT is removed to form the contact plugs 710, 720, and 730. Figure 19 As shown, a metal layer 800 is then formed on the interlayer dielectric layer ILD, so that the metal layer 800 contacts the contact plugs 710, 720, and 730 to obtain an SGT-MOSFET in some embodiments of the present invention. In some embodiments, the contact plug 710 is electrically connected to the third conductive layer 610, which serves as the gate electrode, and the metal layer 800, and the contact plugs 720 and 730 are electrically connected to the first conductive layer 320 and the second conductive layer 420, which serve as the source electrodes, and the metal layer 800.

[0094] In summary, according to some embodiments of the present invention, the present invention further improves the electrical characteristics of a semiconductor structure through a two-stage formation process and a specific semiconductor structure, thereby correspondingly enhancing the electrical characteristics and reliability of an SGT-MOSFET including the semiconductor structure of the present invention. For example, because the recessed portions and seam defects on the surfaces of the first conductive layer 310 and the second conductive layer 410 of the present invention are improved through the two-stage formation process, gate-source leakage and breakdown issues are reduced, thereby improving the electrical characteristics and reliability of the SGT-MOSFET including the semiconductor structure of the present invention. Furthermore, because the present invention provides a method for forming a semiconductor structure that includes a step for excellent conductive material filling, the formation method of the present invention can be widely applied to various conductive material filling processes and is a method for forming electrodes with fewer defects using simple steps. For example, the formation method of the semiconductor structure of the present invention can be widely used in various processes for filling polysilicon to form electrodes.

[0095] It should be understood that although the embodiments of the present invention only disclose specific semiconductor structures and their manufacturing methods, the at least two-stage formation process of the embodiments of the present invention can also be applied to the formation methods of any other semiconductor structures and / or devices that need to be filled with conductive materials such as polysilicon, such as complementary MOS (CMOS) transistors, bi-junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, vertical MOS (VDMOS) transistors, high-power MOS transistors, or any other type of transistors.

[0096] Although the embodiments of the present invention and their advantages have been disclosed as above, it should be understood that any person with ordinary knowledge in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present invention. In addition, the scope of protection of the present invention is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the art can understand from the disclosure of some embodiments of the present invention that the processes, machines, manufacturing, material compositions, devices, methods and steps currently or in the future are developed. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each patent application constitutes a separate embodiment, and the scope of protection of the present invention also includes the combination of each patent application and embodiment.

[0097] The above summarizes several embodiments to facilitate a better understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that they can design or modify other steps and structures based on the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent steps and structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: forming a groove on a substrate, wherein the groove has a side surface and a bottom surface; forming a first dielectric layer on the side surface and the bottom surface of the groove and the substrate, so that the first dielectric layer has a trench; filling a first conductive material in the trench; Etching back the first conductive material to form a first conductive layer and exposing a portion of the first dielectric layer on the side surface of the groove; etching the first dielectric layer so that the portion of the first dielectric layer located on the side surface of the groove has a width that decreases in a direction away from the bottom surface of the groove; Filling a second conductive material in the trench to form a second conductive layer on the first conductive layer; removing a portion of the second conductive layer so that a top surface of the second conductive layer is parallel to or lower than a top surface of the substrate, and leaving a conductive structure; removing a portion of the first dielectric layer so that a top surface of the first dielectric layer is lower than a top surface of the conductive structure; forming a second dielectric layer on the second conductive layer; and A third conductive layer is formed on the second dielectric layer.

2. The forming method according to claim 1, wherein: The step of etching the first dielectric layer comprises: A portion of the first dielectric layer on the side surface of the groove and the first dielectric layer on the top surface of the substrate are etched.

3. The forming method according to claim 1, wherein: The step of etching the first dielectric layer comprises: The first conductive layer is used as an etching mask, and the first dielectric layer is etched by a wet etching process.

4. The forming method according to claim 1, wherein: The step of filling the trench with the second conductive material further includes: The second conductive material is planarized so that a top surface of the second conductive material is coplanar with a top surface of the first dielectric layer.

5. The forming method according to claim 1, wherein: The conductive structure includes the first conductive layer and the remaining second conductive layer.

6. The forming method according to claim 1, wherein: Also includes: forming an interlayer dielectric layer on the third conductive layer; forming a first doped region on the substrate; forming a second doped region on the substrate, wherein the second doped region is further away from the interlayer dielectric layer than the first doped region; forming a contact hole, wherein the contact hole exposes a portion of the third conductive layer; filling a via material into the contact via to form a contact plug; and A metal layer is formed on the interlayer dielectric layer so that the metal layer and the contact plug are in contact with each other.

7. A semiconductor structure, characterized in that include: A substrate having a groove, wherein the groove includes a first groove and a second groove; a first dielectric layer disposed on a side surface and a bottom surface of the first recess, and a side surface and a bottom surface of the second recess, and having a first groove corresponding to the first groove and a second groove corresponding to the second groove; a shielding electrode disposed in the first trench; a second dielectric layer disposed in the first trench and conformally disposed on the shielding electrode; a gate electrode disposed in the first trench and on the second dielectric layer; and a source electrode disposed in the second trench; A portion of the first dielectric layer located on the side surface of the second groove has a width that decreases in a direction away from the bottom surface of the second groove.

8. The semiconductor structure according to claim 7, wherein: A shape of a portion of the source electrode corresponds to a shape of the portion of the first dielectric layer on the side surface of the second groove.

9. The semiconductor structure according to claim 7, wherein: A width of a top surface of the source electrode is greater than a width of a bottom surface.

10. The semiconductor structure according to claim 7, wherein: The gate electrode has an extension portion extending toward the shield electrode.

11. The semiconductor structure according to claim 7, wherein: Also includes: an interlayer dielectric layer disposed on the gate electrode and the source electrode; a first doped region disposed on the substrate; a second doped region disposed on the substrate and further away from the interlayer dielectric layer than the first doped region; a gate plug penetrating the interlayer dielectric layer and contacting the gate electrode; and A source plug penetrates the interlayer dielectric layer and contacts the source electrode.

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