Semiconductor package structure and processing method thereof

Abstract

The application discloses a semiconductor packaging structure and a processing method thereof, and belongs to the technical field of semiconductor processes. The processing method of the semiconductor packaging structure comprises the following steps: providing a wafer, the wafer comprising a first surface and a second surface arranged oppositely, and the first surface of the wafer exposing a solder pad; sequentially forming a patterned first passivation layer and a wiring layer on the first surface, the wiring layer being electrically connected to the solder pad; forming a second passivation layer with a passivation layer pattern on the second surface; taking the second passivation layer as a mask, etching the wafer under preset process conditions to form a tapered hole penetrating through the wafer, the width of the tapered hole gradually decreasing from the second surface to the first surface, and the first passivation layer being exposed; wherein the preset process conditions comprise that the adopted lower electrode power is less than or equal to 50 W. The above technical scheme can solve the problem that the current packaging method is prone to causing adverse effects on subsequent metal filling when forming a through silicon via.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor process, and particularly relates to a semiconductor packaging structure and a processing method thereof. BACKGROUND

[0002] Electronic packaging has become an extremely important component of the semiconductor industry. In recent years, with the trend of multifunctionalization and miniaturization of electronic products and the development of packaging technology, related enterprises take miniaturization and high density of packaging as the main research and development direction, and a large number of advanced packaging methods and packaging structures are applied to mass production. For packaging, if the area of three-dimensional space can be used to increase the integration of chips, it can be regarded as a continuation of Moore's law. The use of three-dimensional space for stacked packaging is called 3D system-level packaging, which has higher capacity, better performance and higher yield. Compared with traditional chip packaging, wafer-level packaging is to process the entire wafer first and then cut it, which can reduce the processing cost.

[0003] In the 3D system-level packaging technology, in order to realize the interconnection between different chips in the 3D space, through silicon via technology is needed. In the specific through silicon via process, the two main steps are through silicon via etching and metal filling. In related technologies, when performing through silicon via etching, Bosch process (high aspect ratio etching process) is adopted, which forms a through hole with a relatively vertical angle. In the through silicon via of 3D system-level packaging, the aspect ratio is relatively large, which is not conducive to subsequent metal filling and is prone to problems such as sealing effect and discontinuous filling in the metal filling process, affecting the yield and production efficiency of the product. SUMMARY

[0004] The purpose of the embodiment of the application is to provide a semiconductor packaging structure and a processing method thereof, which can solve the problem that the existing packaging method is prone to adversely affecting subsequent metal filling when forming a through silicon via.

[0005] In order to solve the above technical problems, the application is implemented as follows:

[0006] The embodiment of the application provides a processing method of a semiconductor packaging structure, which comprises the following steps:

[0007] A wafer is provided, the wafer comprising a first surface and a second surface arranged oppositely, and the first surface of the wafer exposes a solder pad;

[0008] A patterned first passivation layer and a wiring layer are formed on the first surface in sequence, and the wiring layer is electrically connected to the solder pad;

[0009] A second passivation layer is formed on the second surface, and a second passivation layer pattern is formed on the second passivation layer; a taper hole is formed in the wafer by etching under a preset process condition, the taper hole is communicated with the first passivation layer, and the taper hole has a gradually decreasing width from the second surface to the first surface.

[0010] Based on the taper hole, a window is formed on the first passivation layer by etching, and the window is communicated with the taper hole.

[0011] A metal connecting column is formed in the taper hole and the window, one end of the metal connecting column is exposed by the taper hole, and the other end of the metal connecting column is electrically connected with the wiring layer.

[0012] The technical scheme adopted by the present application can achieve the following beneficial effects:

[0013] The processing method of the semiconductor packaging structure disclosed by the embodiment of the present application can form a taper hole in the packaging process. In the processing method disclosed by the embodiment of the present application, a lower electrode power is used when the taper hole is formed by etching, and the lower electrode power can be 50 W or less. With the low-power lower electrode power, it is beneficial to avoid forming a straight hole with a vertical side wall and to form a taper hole with a required inclined side wall. Therefore, compared with the existing Bosch process or the existing method of forming a straight hole, the embodiment of the present application uses a non-Bosch process to obtain a taper hole with an inclined side wall, which can avoid forming a notch at the bottom, which is beneficial to subsequent metal filling, can avoid the top sealing effect, and can avoid the problem of incomplete filling in the hole, can improve the yield of the device, can improve the production efficiency, and is suitable for chip packaging with small size and thin thickness.

[0014] In summary, the processing method of the semiconductor packaging structure disclosed by the embodiment of the present application can solve the problem that the existing packaging method has an adverse effect on subsequent metal filling when forming a through silicon via. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which are included to provide a further understanding of the present application, form a part of the present application and illustrate the illustrative embodiments of the present application and its description, which do not constitute improper limitations on the present application.

[0016] Figure 1 A flowchart of the processing method of the semiconductor packaging structure disclosed by the embodiment of the present application is shown in FIG. 1;

[0017] Figure 2 Another embodiment of the processing method of the semiconductor packaging structure disclosed by the embodiment of the present application is shown in FIG. 2.

[0018] Figure 3 Flow chart of part of the process of the method for processing the semiconductor package structure disclosed in the embodiments of the present application;

[0019] Figure 4 Flow chart of another part of the process of the method for processing the semiconductor package structure disclosed in the embodiments of the present application;

[0020] Figure 5 Flow chart of still another part of the process of the method for processing the semiconductor package structure disclosed in the embodiments of the present application;

[0021] Figure 6 Schematic diagram of the whole process of the method for processing the semiconductor package structure disclosed in the embodiments of the present application;

[0022] Figure 7 Schematic diagram of the structure of the tapered hole obtained in the process of the method for processing the semiconductor package structure disclosed in the embodiments of the present application;

[0023] Figure 8 Schematic diagram of the process of forming a right-angle hole in a semiconductor package using the Bosch process;

[0024] Figure 9 Schematic diagram of the contrast of the enhanced tolerance of the bottom notch of the tapered hole formed in a semiconductor package;

[0025] Figure 10 SEM image of the contrast of the bottom notch defect of the tapered hole formed in a semiconductor package and the bottom notch defect of the right-angle hole formed in a semiconductor package;

[0026] Figure 11 SEM image of a tapered hole formed by the method for processing the semiconductor package structure disclosed in the embodiments of the present application;

[0027] Figure 12 SEM image of another tapered hole formed by the method for processing the semiconductor package structure disclosed in the embodiments of the present application;

[0028] Figure 13 SEM image of still another tapered hole formed by the method for processing the semiconductor package structure disclosed in the embodiments of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0030] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of a kind and are not limited in number, for example, the first object can be one or more. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / ", generally indicates that the objects before and after are in an "or" relationship.

[0031] The embodiments of the present application will be described in detail below with reference to the accompanying drawings, specific embodiments and application scenarios.

[0032] In the related art, the 3D system-level packaging method can improve the capacity, performance and yield of the packaging structure. However, the via angle formed in the packaging process in the related art is perpendicular, that is, a straight-angle via with a vertical side wall is formed, and due to the large aspect ratio of the hole in the 3D system-level packaging, various adverse effects on the subsequent metal filling step are caused, the hole opening is easily blocked during filling, and problems such as sealing effect and discontinuous filling in the subsequent metal filling process are easily caused, which is difficult to meet the actual application requirements. For example, as shown in Figure 8 In the related art, a Bosch process is used to etch a hole, and the process result obtained by using the Bosch process often contains a bottom notch, which is also not conducive to the preparation of a thick insulating layer. Specifically, the reason for the occurrence of the bottom notch is mainly that the angle of the hole obtained by using the Bosch process is a right angle, and if a right-angle hole is formed, lateral etching will occur due to charge scattering when the stop layer is reached, that is, a bottom notch will occur. It is found through research that, compared with Figure 8 As shown in Figure 9 If a tapered hole is formed, the deposition effect of the hole side wall will be stronger, a wider process window can be obtained, and the formation of the bottom notch can be avoided.

[0033] Based on this, the embodiments of the present application provide a processing method of a semiconductor packaging structure and a semiconductor packaging structure obtained by using the processing method. The processing method of the semiconductor packaging structure provided by the embodiments of the present application can be applied to the field of 3D system-level packaging (advanced packaging), and by forming a tapered hole with an inclined side wall in the packaging process instead of the straight-angle hole with a vertical side wall in the related art, the problems such as sealing effect and discontinuous filling in the subsequent metal filling process can be solved.

[0034] On this basis, the processing method of the semiconductor packaging structure provided by the embodiment of the application comprises: providing a wafer, the wafer comprising a first surface and a second surface arranged oppositely, the first surface of the wafer exposing a solder pad; sequentially forming a patterned first passivation layer and a wiring layer on the first surface, the wiring layer being electrically connected to the solder pad; forming a second passivation layer with a passivation layer pattern on the second surface; taking the second passivation layer as a mask, etching the wafer under preset process conditions to form a tapered hole penetrating through the wafer, the width of the tapered hole gradually decreasing from the second surface to the first surface, and the first passivation layer being exposed; wherein the preset process conditions comprise: the lower electrode power used being less than or equal to 50 W; based on the tapered hole, etching is performed on the first passivation layer to form a window, the window being in communication with the tapered hole; and a metal connecting column is formed in the tapered hole and the window, one end of the metal connecting column being exposed by the tapered hole, and the other end of the metal connecting column being electrically connected to the wiring layer.

[0035] Figure 10 A scanning electron microscope image showing that the bottom of the tapered hole has no notch defect is compared with a right-angle hole with a bottom notch defect, as shown in Figure 10 In the case of using the above technical solution, the tapered hole with an inclined sidewall is formed by etching; on the one hand, since the opening of the 3D system-level package is small, if the sidewall of the hole is perpendicular to form a right-angle hole, it is not conducive to the subsequent metal filling step, and due to the existence of the passivation layer (stop layer), due to the accumulation of electric charge, etching will proceed laterally to form a bottom notch; if a tapered hole is formed, the deposition of the sidewall of the hole will be stronger, and it is constantly etching laterally, which can obtain a wider process window and avoid the formation of a bottom notch. On the other hand, the inclination angle of the sidewall of the formed tapered hole needs to be moderate, if the inclination angle is too large, such as the inclination angle approaching 90°, the hole approaches a right-angle hole, which will bring various problems as described above; if the inclination angle is too small, such as the inclination angle being less than 60° or less than 45°, the inclination is too large, which will reduce the wafer utilization rate, and the insulating layer of the sidewall is easily damaged in the etching-back step.

[0036] Therefore, the processing method of the embodiment of the application adopts a lower lower electrode power when etching to form a tapered hole, and the lower electrode power can be 50 W or less. With the low-power lower electrode power, it is beneficial to avoid forming a right-angle hole with a vertical sidewall, and to form a tapered hole with a required inclined sidewall. In addition, in some preferred embodiments of the application, the upper electrode power used is greater than or equal to 500 W, the etching gas used comprises sulfur hexafluoride and oxygen, and the chamber pressure is less than or equal to 500 mTorr. By adjusting the above parameter conditions, a tapered hole with a required shape or size can be obtained, that is, adjusting the above parameter conditions can avoid the sidewall inclination angle of the obtained tapered hole being too large or too small, so that the sidewall inclination angle of the tapered hole is more appropriate.

[0037] In summary, the processing method of the semiconductor packaging structure disclosed in the embodiments of the present application forms a tapered hole with an inclined sidewall, avoids bottom notches, improves device yield, and thus solves the problem that the current packaging method has an adverse effect on subsequent metal filling when forming a through silicon via.

[0038] The technical solutions of the present application will be described clearly and completely in combination with the drawings. The specific technical solutions are described below.

[0039] As shown in Figure 1 , Figure 6 , the present application provides a processing method of a semiconductor packaging structure, which comprises the following steps:

[0040] S1, providing a wafer, the wafer comprising a first surface and a second surface arranged oppositely, and the first surface of the wafer exposing a pad. The wafer can be a KGD (Known good die), i.e. a wafer formed after wafer front-end processing; the wafer comprises a first surface and a second surface, and the first surface and the second surface are arranged oppositely, for example, the first surface can be the upper surface of the wafer, and the second surface can be the lower surface of the wafer, or the first surface can be the lower surface of the wafer, and the second surface can be the upper surface of the wafer. The embodiments of the present application do not limit the specific structure or type of the wafer.

[0041] S2, sequentially forming a patterned first passivation layer and a wiring layer on the first surface, and the wiring layer is electrically connected to the pad on the first surface. This step comprises: forming a first passivation layer on the first surface, etching the first passivation layer to form a plurality of grooves in the first passivation layer. Specifically, as shown in Figure 3 , step S2 comprises:

[0042] S21, surface passivation, that is, passivating the first surface of the wafer to form a first passivation layer on the first surface. Specifically, a PECVD (plasma enhanced chemical vapor deposition) method can be used to grow a passivation layer such as a silicon nitride layer or a silicon oxide layer on the first surface, and the thickness of the first passivation layer can be 0.1 microns to 2 microns, and further, the thickness of the first passivation layer can be 0.5 microns. More specifically, the operating conditions when performing the PECVD can be as follows: the cavity pressure can be 20 to 200 Pa, the plasma power can be 50 to 500 W, the SiH4 flow rate can be 5 to 150 sccm, the N2O flow rate can be 100 to 5000 sccm, the N2 flow rate can be 100 to 5000 sccm, the growth temperature can be 100 to 500°C, and the growth time can be selected according to the thickness and the growth rate, such as 1450s for growing the preferred 0.5 micron thickness under the above-mentioned various preferred conditions. The role of N2O is to provide oxygen ions and adjust the discharge characteristics of the plasma (easier ionization than the rest of the gas), and N2 acts to dilute the reactants.

[0043] It should be understood that the embodiments of the present application do not limit the specific type or specific preparation method of the first passivation layer, and conventional passivation layers such as silicon nitride layers, silicon oxide layers, etc. can be used, and of course other types of passivation layers that can be applied to wafers can also be used.

[0044] S22, spin coating photoresist, that is, using a spin coating method to cover the photoresist on the surface of the first passivation layer, thereby forming a photoresist layer on the first passivation layer. Specifically, the thickness of the photoresist layer can be 0.5 microns to 10 microns, and further, the thickness of the photoresist layer can be 3 microns.

[0045] S23, exposure and development, that is, exposing and developing the photoresist layer to pattern the photoresist layer and form a patterned photoresist layer. Specifically, a mask plate with a preset pattern can be used to block the photoresist layer, and then the photoresist layer can be developed with light to transfer the preset pattern on the mask plate to the photoresist layer, thereby patterning the photoresist layer to have the preset pattern. The pattern on the mask plate can be designed and processed according to actual needs. More specifically, the exposure time can be 3 to 20s, and further, it can be 6s; the development time can be 45 to 120s, and further, it can be 75s; the fixing time can be 60 to 300s, and further, it can be 120s, thereby patterning the photoresist layer.

[0046] S24, etching, that is, based on the patterned photoresist layer, etching the first passivation layer to form a patterned first passivation layer to form a plurality of trenches in the first passivation layer. Based on different first passivation layer types, the etching operation conditions can be adjusted as appropriate. The embodiment of the present application takes the first passivation layer as a silicon oxide layer as an example, and the etching operation conditions can be as follows: the cavity pressure can be in the range of 1-30 mTorr, the upper electrode power can be in the range of 600-3000 W, the lower electrode power can be in the range of 50-500 W, the etching gas used includes argon and fluorocarbon gas, wherein the argon flow rate can be in the range of 10-100 sccm, the fluorocarbon gas flow rate can be in the range of 10-100 sccm, the fluorocarbon gas can be CF4, CHF3 or other types of fluorocarbon gas, etc.; the base cooling liquid temperature range can be -15-10°C.

[0047] S25, de-gluing, that is, removing the photoresist layer. Specifically, a wet de-gluing method can be used to remove the photoresist layer on the first passivation layer. More specifically, an acetone solution can be used to remove the photoresist layer, or sulfuric acid and hydrogen peroxide can also be used to remove the photoresist layer. In the above process, the first passivation layer or the wafer is basically not damaged; it is beneficial to ensure that the subsequent process can proceed normally.

[0048] Based on the above steps S21 to S25, a wafer with a passivated surface and a slotted passivation layer can be obtained, which facilitates the smooth progress of the subsequent steps.

[0049] S3, forming a metal layer in the trench, and electroplating copper on the metal layer to form a wiring layer extending to the outside of the trench. Specifically, as shown in Figure 4 S3 includes:

[0050] S31, glue coating, exposure and development, that is, based on the etched first passivation layer, spin-coating photoresist on the first passivation layer, exposing and developing the photoresist to expose the trenches in the first passivation layer. In this way, by exposing the trenches in the first passivation layer, the solder pads on the first surface can be exposed, and the area that needs to be rewired, that is, the area covered by the subsequent copper electroplating, can be exposed, thereby facilitating the manufacture of the subsequent wiring layer. Specifically, a spin-coating method can be used to cover the photoresist on the surface of the etched first passivation layer, thereby forming a photoresist layer on the first passivation layer; and then, the photoresist layer is exposed and developed to pattern the photoresist layer.

[0051] The specific operation mode and operation conditions of the glue coating, exposure and development in step S31 can refer to the operation conditions of the glue coating, exposure and development in the aforementioned steps S22 and S23, which will not be described here.

[0052] S32, depositing a metal layer, that is, depositing a metal layer in the trench, which can include a titanium metal layer and a copper metal layer. Specifically, the trench in the first passivation layer can be exposed under the shielding of the photoresist layer patterned on the first passivation layer, so that the metal layer can be deposited in the trench in the first passivation layer by PVD (physical vapor deposition). The thickness of the metal layer can be determined according to the type of metal deposited or the thickness of the wafer and other parameters. More specifically, the metal layer can be divided into two layers, that is, a titanium metal layer and a copper metal layer, wherein the thickness of the titanium metal layer can be 0.05 microns to 0.2 microns, and further, the thickness of the titanium metal layer can be 0.1 microns; the thickness of the copper metal layer can be 0.1 microns to 0.5 microns, and further, the thickness of the copper metal layer can be 0.3 microns. When the PVD process is implemented, the operating conditions can be as follows: the cavity pressure can be 10-100 mTorr, the upper electrode power can be 750-3000 W, the lower electrode power can be 5-500 W, and the argon flow rate can be 50-500 sccm.

[0053] S33, electroplating, that is, electroplating copper on the metal layer to form a wiring layer (RDL, redistribution layer), which extends to the outside of the trench. Specifically, the method of forming the wiring layer is electroplating process; the material of the wiring layer includes but is not limited to copper. The wiring layer extends from the surface of the metal layer in the trench to the outside of the trench and is located on the first passivation layer. In this way, the wiring layer, that is, the RDL circuit, is electrically connected to the chip, which can enable the chip to communicate with other devices such as different chips. Specifically, the thickness of the wiring layer can be 0.5 microns to 5 microns, and further, the thickness of the wiring layer can be 2 microns to ensure the reliability of the electrical connection.

[0054] The first surface described above is provided with a solder pad, and the wiring layer is electrically connected to the solder pad.

[0055] S34, de-gluing, that is, removing the photoresist in step S31.

[0056] The specific operation mode and operating conditions of de-gluing in step S34 can refer to the description of de-gluing in the aforementioned step S25, which will not be described here.

[0057] Based on the above steps S31 to S34, a wafer with a first surface passivated and an RDL prepared can be obtained, based on which the second surface of the wafer can be further operated.

[0058] S4, forming a second passivation layer with a passivation layer patterning on the second surface; taking the second passivation layer as a mask, etching the wafer under preset process conditions to form a tapered hole penetrating through the wafer, the width of the tapered hole gradually decreases from the second surface to the first surface, and the first passivation layer is exposed. Specifically, step S4 includes:

[0059] S41, gluing, exposing and developing, that is, the second surface of the wafer is glued, exposed and developed. Specifically, the photoresist can be covered on the second surface in a spin coating manner, so as to form a photoresist layer on the second surface; then, the photoresist layer is exposed and developed to pattern the photoresist layer and form a patterned second passivation layer.

[0060] The specific operation mode and operation condition of gluing, exposing and developing in step S41 can refer to the operation condition of gluing, exposing and developing in the foregoing steps S22 and S23, which will not be described here again.

[0061] S42, etching, that is, based on the patterned second passivation layer obtained in step S41, taking the second passivation layer as a mask, etching the wafer under preset process conditions to form a tapered hole penetrating through the wafer, the tapered hole extends from the surface of the patterned second passivation layer to the inside of the wafer, for example, can extend to the first passivation layer located on the first surface.

[0062] Wherein, the etching can adopt plasma etching. When the tapered hole is formed by etching, the lower electrode power is less than or equal to 50W, the upper electrode power is greater than or equal to 500W, the etching gas used includes sulfur hexafluoride and oxygen, and the chamber pressure is less than or equal to 500mTorr.

[0063] Specifically, regarding the shape of the tapered hole, the width of the tapered hole gradually decreases from the second surface to the first surface; that is, the width of the mounting surface part of the tapered hole tapers inwardly from a first wider width to a second narrower width at the bottom surface part of the hole. In this way, no bottom gap is generated, and problems such as easy clogging at the hole opening when filling metal in the hole, discontinuity of the filled metal material, etc. can be avoided.

[0064] As described before, the inclination angle of the hole wall of the tapered hole needs to be moderate, which is not too large or too small, such as Figure 7 As shown in the figure, the embodiment of the present application can avoid various problems caused by the right-angle hole by limiting the inclination angle α of the hole wall of the tapered hole to 70°-88°, and can also avoid problems such as reducing wafer utilization and easily damaging the insulating layer of the side wall in the etch-back step caused by excessive inclination.

[0065] Specifically, in some embodiments, the inclination angle of the hole wall of the tapered hole is 82°-88°;

[0066] In the etching process for forming the tapered hole, the lower electrode power is 5-50W, the upper electrode power is 500-5000W, the etching gas includes sulfur hexafluoride and oxygen, the flow rate of sulfur hexafluoride is 10-1000sccm, the flow rate of oxygen is 10-1000sccm, and the chamber pressure is 5-500mTorr.

[0067] In a more specific embodiment, as shown in Figure 11 the tapering angle of the hole wall of the tapered hole is 84-86°; in the etching process for forming the tapered hole, the lower electrode power is 30W, the upper electrode power is 700W, the etching gas includes sulfur hexafluoride and oxygen, the flow rate of sulfur hexafluoride is 50sccm, the flow rate of oxygen is 50sccm, and the chamber pressure is 50mTorr; and the process time is 600s.

[0068] In another more specific embodiment, as shown in Figure 12 the tapering angle of the hole wall of the tapered hole is 84-86°; in the etching process for forming the tapered hole, the lower electrode power is 30W, the upper electrode power is 1200W, the etching gas includes sulfur hexafluoride and oxygen, the flow rate of sulfur hexafluoride is 50sccm, the flow rate of oxygen is 50sccm, and the chamber pressure is 55mTorr; and the process time is 600s.

[0069] As can be seen from the above two specific embodiments, the upper electrode power does not mainly affect the etching morphology, and in fact, the lower electrode power has a greater effect on the etching morphology. Therefore, the process recipe of the present application can be selected in the following ranges: the chamber pressure is 5-500mTorr, preferably 50mTorr; the upper electrode power is 500-5000W, preferably 1200W; the lower electrode power is 5-50W, preferably 30W; the flow rate of oxygen is 10-1000sccm, preferably 50sccm; the flow rate of sulfur hexafluoride is 10-1000sccm, preferably 50sccm; and the process time is not limited in range and is determined according to the etching depth. In the etching process, a very low lower electrode power is used, which is beneficial to obtaining the required hole morphology, and in addition, the tapering angle of the hole wall of the tapered hole can be adjusted by the chamber pressure.

[0070] Specifically, in some other embodiments, the tapering angle of the hole wall of the tapered hole is 70-79°;

[0071] When etching to form a tapered hole, the lower electrode power is 5-45W, preferably 15W, and the upper electrode power is 500-5000W, preferably 2000W. The etching gases used include octafluorocyclobutane (C4F8), sulfur hexafluoride (SF6), and oxygen. The flow rate of octafluorocyclobutane is 10-1000 sccm, preferably 165 sccm, the flow rate of sulfur hexafluoride is 10-1000 sccm, preferably 600 sccm, the flow rate of oxygen is 10-1000 sccm, preferably 60 sccm, and the chamber pressure is 5-500 mTorr, preferably 150 mTorr.

[0072] In another, more specific embodiment, such as Figure 13 As shown, the inclination angle of the conical hole wall is 75° to 77°; when etching to form the conical hole, the lower electrode power is 15W, the upper electrode power is 2000W, and the etching gases used include octafluorocyclobutane, sulfur hexafluoride, and oxygen. The flow rate of octafluorocyclobutane is 165 sccm, the flow rate of sulfur hexafluoride is 600 sccm, the flow rate of oxygen is 60 sccm, the chamber pressure is 150 mTorr, and the process time is 180 s.

[0073] Therefore, it can be seen that the embodiments of the present invention employ a lower electrode etching power of 50W or less in the dry etching step, and introduce a slanted via interconnect structure between 70° and 88° in the 3D system-in-package. Figures 11 to 13 As shown, the embodiments of the present invention can avoid bottom notches and improve device yield, thereby realizing a three-dimensional packaging method suitable for chip packaging with small size and thin thickness.

[0074] S5. Based on the tapered hole, an opening is formed by etching on the first passivation layer, and the opening is connected to the tapered hole. Specifically, after forming the tapered hole by etching, the bottom of the tapered hole is etched to form an opening, that is, the first passivation layer is etched to form an opening, which is connected to the tapered hole, and the opening is connected to the wiring layer through the metal layer.

[0075] The specific etching operation conditions in step S5 can refer to the etching operation conditions in step S24. Specifically, the etching operation conditions in step S5 can be as follows: the cavity pressure range can be 1 to 30 mTorr, the upper electrode power range can be 600 to 3000 W, the lower electrode power range can be 50 to 500 W, and the etching gas used includes argon and fluorocarbon gases, wherein the argon flow rate range can be 10 to 100 sccm, and the fluorocarbon gas flow rate range can be 10 to 100 sccm. The fluorocarbon gas can be, for example, CF4, CHF3, or other types of fluorocarbon gases; the coolant temperature range of the base can be -15 to 10℃.

[0076] S6, forming a metal connecting post in the tapered hole and the window, the tapered hole exposing one end of the metal connecting post, and the other end of the metal connecting post being electrically connected with the wiring layer. Specifically, as shown in FIG. 6, step S6 includes: Figure 5

[0077] S61, growing a stop layer, that is, forming a stop layer (also called an internal passivation layer) on the sidewall and the bottom of the tapered hole and the window. Specifically, a passivation layer such as a silicon nitride layer or a silicon oxide layer can be grown on the sidewall and the bottom of the tapered hole and the window by means of PECVD.

[0078] The specific formation manner or type of the stop layer in step S6 can refer to the specific formation manner and type of the first passivation layer in step S21, which will not be repeated here.

[0079] S62, etching back, that is, etching back the stop layer to remove the stop layer on the bottom.

[0080] The specific etching back operation condition in step S62 can refer to the etching operation condition in step S24, which will not be repeated here.

[0081] S63, growing a barrier layer, that is, forming a barrier layer on the stop layer.

[0082] The operation condition of forming the barrier layer in step S63 can refer to the operation condition of forming the metal layer in step S32. Specifically, titanium nitride can be deposited on the stop layer by means of PVD to form the barrier layer, and the thickness of the barrier layer can be determined according to the type of the deposited material and other parameters. More specifically, the specific material of the barrier layer can be titanium nitride, the thickness of the barrier layer can be 0.1 microns to 1 micron, and further, the thickness of the barrier layer can be 0.5 microns. When the PVD process is implemented, the operation condition can be as follows: the cavity pressure can be 10-100 mTorr, the upper electrode power can be 750-3000 W, the lower electrode power can be 5-500 W, and the argon flow rate can be 50-500 sccm.

[0083] S64, growing a seed layer, that is, forming a seed layer on the barrier layer.

[0084] ​The operation condition of forming the seed layer in step S64 can refer to the operation condition of forming the metal layer in step S32. Specifically, titanium and copper can be deposited on the barrier layer by PVD to form the seed layer, and the thickness of the seed layer can be determined according to the type of the deposited material and other parameters. More specifically, the specific material of the seed layer can be titanium and copper, wherein the thickness of titanium can be 0.05 microns to 0.2 microns, and further, the thickness of titanium can be 0.1 microns; the thickness of copper can be 0.1 microns to 0.5 microns, and further, the thickness of copper can be 0.3 microns. When the PVD process is implemented, the operation condition can be as follows: the cavity pressure can be 10 to 100 mTorr, the upper electrode power can be 750 to 3000 W, the lower electrode power can be 5 to 500 W, and the argon flow rate can be 50 to 500 sccm.

[0085] S65, filling, that is, filling metal in the tapered hole and the window based on the stop layer, the barrier layer and the seed layer to form a metal connecting column in the tapered hole and the window, and the metal connecting column is electrically connected with the wiring layer. Specifically, the method of forming the metal connecting column is electroplating process; the material of the metal connecting column includes but is not limited to copper. By electroplating copper, the metal copper can be filled into the tapered hole and the window, and in this process, the electroplated copper can also be inevitably provided on the patterned photoresist layer on the second surface. More specifically, the operation condition of electroplating can be as follows: the voltage can be 1 to 30 V, and further, the voltage can be 5 V; the current can be 1 to 100 mA / cm 2 , and further, the current can be 75 mA / cm 2 .

[0086] S66, removing the patterned photoresist layer on the second surface.

[0087] The specific operation mode and operation condition of removing in step S66 can refer to the description of removing in the foregoing step S25, which will not be repeated here.

[0088] S67, etching, that is, etching the second surface to remove the second passivation layer on the second surface, so that one end of the metal connecting column is exposed from the tapered hole, and the other end of the metal connecting column is electrically connected with the wiring layer. Specifically, the operation conditions of the etching can be as follows: the cavity pressure can be 5-500 mTorr, further can be 25 mTorr, the upper electrode power can be 500-5000 W, further can be 2200 W, the lower electrode power can be 30-500 W, further can be 50 W, the etching gas used includes sulfur hexafluoride, the flow rate of sulfur hexafluoride can be 10-100 sccm, further can be 750 sccm. The process time of etching has no range limit, and can be determined according to the etching depth.

[0089] Further, in order to package chips of the same type or different types together to form a three-dimensional packaging structure and improve the data processing efficiency of the packaging structure, as shown in Figure 2 and Figure 6 The processing method disclosed in the embodiments of the present application can further include the following steps after step S67:

[0090] S7, passivation, that is, forming a third passivation layer on the second surface.

[0091] The specific operation mode of forming the passivation layer in step S7 and the type of the passivation layer can refer to the forming mode and type of the first passivation layer in the aforementioned step S21, and will not be described here.

[0092] S8, etching, that is, etching the third passivation layer to obtain a chip-level wafer. The chip-level wafer is obtained by the above steps S1 to S8.

[0093] S9, stacking, that is, stacking a plurality of chip-level wafers to complete layer-by-layer interconnection. The plurality of chip-level wafers can be of the same type or different types.

[0094] Further, the processing method can further include the steps of bonding, wafer cutting, etc. These steps can refer to the prior art, and will not be described in detail here.

[0095] The embodiments of the present application also provide a semiconductor packaging structure, which can be obtained by the above-mentioned processing method of the semiconductor packaging structure.

[0096] In the provided semiconductor packaging structure, a plurality of chip-level wafers are vertically stacked together, and then connected to a mainboard through a packaging substrate and a tin ball, or can be connected to the mainboard through gold wire and lead pin.

[0097] In some embodiments, the semiconductor package structure comprises a substrate and a plurality of chip-level wafers stacked on the substrate, each chip-level wafer comprising a first surface and a second surface oppositely arranged, the first surface being provided with a solder pad, a first passivation layer and a wiring layer being formed on the first surface, the wiring layer being electrically connected to the solder pad;

[0098] The chip-level wafer is provided with a tapered hole, the width of the tapered hole gradually decreases from the second surface to the first surface;

[0099] The tapered hole is filled with a metal connecting column, one end of the metal connecting column is exposed outside the tapered hole, and the other end of the metal connecting column passes through the first passivation layer and is electrically connected to the wiring layer;

[0100] The adjacent chip-level wafers are electrically connected through the wiring layer on one chip-level wafer and the metal connecting column on the other chip-level wafer.

[0101] In some embodiments, the tapering angle of the hole wall of the tapered hole is 70°-88°.

[0102] The specific structure of the chip-level wafer in the semiconductor package structure or the related features of the tapered hole and the like in the semiconductor package structure can be known from the processing method of the semiconductor package structure, and will not be described in detail here.

[0103] In the above embodiments, the focus is on the differences between the various embodiments, and the optimization features that are different between the various embodiments can be combined to form a more optimal embodiment without contradiction. In view of the brevity of the writing, this will not be described here.

[0104] The embodiments of the application are described above in combination with the drawings, but the application is not limited to the above specific embodiments, the above specific embodiments are only illustrative and not restrictive, and those skilled in the art can make many forms under the inspiration of the application without departing from the scope of the application and the protection scope of the claims, all of which belong to the protection of the application.

Claims

1. A method for fabricating a semiconductor packaging structure, characterized in that, Includes the following steps: A wafer is provided, the wafer including a first surface and a second surface disposed opposite to each other, the first surface of the wafer exposing solder pads; A patterned first passivation layer and a wiring layer are sequentially formed on the first surface, wherein the wiring layer is electrically connected to the solder pad; A passivation layer patterned in a passivation layer is formed on the second surface; Using the second passivation layer as a mask, the wafer is etched under preset process conditions to form a tapered hole penetrating the wafer. From the second surface to the first surface, the width of the tapered hole gradually decreases, exposing the first passivation layer. The preset process conditions include: using a lower electrode power of less than or equal to 50W in plasma etching. Based on the tapered hole, an opening is formed by etching on the first passivation layer, and the opening is connected to the tapered hole; A metal connecting post is formed in the tapered hole and the window, the tapered hole exposing one end of the metal connecting post, and the other end of the metal connecting post being electrically connected to the wiring layer.

2. The method for processing the semiconductor packaging structure according to claim 1, characterized in that, The inclination angle of the wall of the tapered hole is 70° to 88°; The preset process conditions also include: the upper electrode power is greater than or equal to 500W, the etching gas used includes sulfur hexafluoride and oxygen, and the chamber pressure is less than or equal to 500 mTorr.

3. The method for processing the semiconductor packaging structure according to claim 2, characterized in that, The inclination angle of the wall of the tapered hole is 82° to 88°; When etching to form the tapered hole, the preset process conditions include: the lower electrode power is 5-50W, the upper electrode power is 500-5000W, the etching gas includes sulfur hexafluoride and oxygen, the flow rate of sulfur hexafluoride is 10-1000 sccm, the flow rate of oxygen is 10-1000 sccm, and the chamber pressure is 5-500 mTorr.

4. The method for processing a semiconductor packaging structure according to claim 2, characterized in that, The inclination angle of the wall of the tapered hole is 70° to 79°; When etching to form the tapered hole, the preset process conditions include: the lower electrode power is 5-45W, the upper electrode power is 500-5000W, the etching gas used includes octafluorocyclobutane, the flow rate of octafluorocyclobutane is 10-1000 sccm, the flow rate of sulfur hexafluoride is 10-1000 sccm, the flow rate of oxygen is 10-1000 sccm, and the chamber pressure is 5-500 mTorr.

5. The method for processing the semiconductor packaging structure according to claim 1, characterized in that, The step of sequentially forming a patterned first passivation layer and a wiring layer on the first surface includes: A patterned photoresist layer is formed on the first surface, and the first passivation layer is etched using the patterned photoresist layer as a mask to form the patterned first passivation layer on the first surface; wherein, when etching the first passivation layer, the chamber pressure is 1-30 mTorr, the upper electrode power is 600-3000W, the lower electrode power is 50-500W, and the etching gas includes argon and fluorocarbon gas, the flow rate of argon is 10-100 sccm, and the flow rate of fluorocarbon gas is 10-100 sccm.

6. The method for processing the semiconductor packaging structure according to claim 5, characterized in that, After forming the patterned first passivation layer, the process further includes: Metal is deposited in the trenches of the first passivation layer to form a metal layer, the metal layer comprising a titanium metal layer and a copper metal layer; The wiring layer is formed by electroplating copper on the metal layer, and the wiring layer extends outside the trench.

7. The method for processing a semiconductor packaging structure according to any one of claims 1 to 6, characterized in that, The metal connecting post is formed in the tapered hole and the window, the tapered hole exposing one end of the metal connecting post, and the other end of the metal connecting post is electrically connected to the wiring layer, including: A stop layer is formed on the sidewalls and bottom of the tapered hole and the window; The stop layer is etched back to remove the stop layer located at the bottom; A barrier layer is formed on the stop layer; A seed layer is formed on the barrier layer; Based on the stop layer, the blocking layer and the seed layer, metal is filled into the conical hole and the opening to form metal connecting posts in the conical hole and the opening, and the metal connecting posts are electrically connected to the wiring layer; The second surface is etched so that one end of the metal connecting post is exposed from the tapered hole.

8. The method for processing the semiconductor packaging structure according to claim 7, characterized in that, After etching the second surface to expose one end of the metal connecting post through the tapered hole, the process further includes: A third passivation layer is formed on the second surface, and the third passivation layer is etched to obtain a chip-level wafer; Multiple chip-level wafers are stacked to complete layer-by-layer interconnection, resulting in a semiconductor packaging structure.

9. A semiconductor packaging structure, manufactured using the processing method according to any one of claims 1 to 8, characterized in that, The semiconductor packaging structure includes a substrate and a plurality of chip-level wafers stacked on the substrate. The chip-level wafers include a first surface and a second surface disposed opposite to each other. The first surface is provided with a bonding pad, and a first passivation layer and a wiring layer are formed on the first surface. The wiring layer is electrically connected to the bonding pad. The chip-scale wafer is provided with a tapered hole, and the width of the tapered hole gradually decreases from the second surface to the first surface to expose the first passivation layer; The first passivation layer has a window, and the window communicates with the tapered hole; Both the conical hole and the window are filled with metal connecting posts. One end of the metal connecting post is exposed outside the conical hole, and the other end of the metal connecting post passes through the window of the first passivation layer and is electrically connected to the wiring layer. Adjacent chip-level wafers are electrically connected to the metal interconnects on the other through the wiring layer on one wafer.

10. The semiconductor packaging structure according to claim 9, characterized in that, The inclination angle of the wall of the tapered hole is 70° to 88°.

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