Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region; forming a first gate dielectric structure on the first region; forming a first barrier layer on the first gate dielectric structure; modifying the first barrier layer to form a modified layer; forming a first diffusion layer on the modified layer, the first diffusion layer having polarized atoms therein; and annealing the first diffusion layer and a second diffusion layer to drive the polarized atoms in the first diffusion layer to diffuse into the first gate dielectric structure to form a first polarized layer. By modifying the first barrier layer to form the modified layer, the modified layer can enhance or weaken its blocking effect on polarized atoms, thereby avoiding the need to adjust the blocking effect on polarized atoms by the number of stacked first barrier layers, simplifying the manufacturing process, and also avoiding the problem of having too many stacked first barrier layers making it difficult to fill in between adjacent fin structures, thereby effectively improving the performance of the resulting semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] MOS (metal-oxide-semiconductor) transistors are one of the most important components in modern integrated circuits. Their basic structure consists of a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, which includes a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; and doped source and drain regions located in the semiconductor substrate on both sides of the gate structure. MOS transistors include PMOS and NMOS transistors.

[0003] In order to meet the switching speed requirements of different transistors in integrated circuit design, it is necessary to form multiple transistors with different threshold voltages.

[0004] To reduce and adjust the threshold voltages of PMOS and NMOS transistors, corresponding work function layers are formed on the gate dielectric surfaces of these transistors. The work function layers of PMOS transistors are required to have a higher work function, while those of NMOS transistors are required to have a lower work function. The work function layers of PMOS and NMOS transistors are made of different materials to meet the respective work function adjustment requirements.

[0005] Moreover, PMOS transistors may also require a variety of different threshold voltages. The current common practice in the industry is to adjust the thickness of the work function layer of the PMOS transistor. For example, the thickness of the work function layer of the PMOS low threshold voltage transistor is thicker than the thickness of the work function layer of the PMOS standard threshold voltage transistor.

[0006] However, the use of dipole in the prior art and the method of adjusting the amount of dipole by using the buffer thickness or the thickness of the dipole itself still have the problem that when adjusting the metal work function under FinFET technology, the fin pitch (Fin Pitch) is getting smaller and smaller, and the distance between fins is also getting smaller and smaller (such as Figure 1 As shown in FIG, in some cases, the thickness of the total work function layer exceeds the spacing between the fins, and the work function adjustment capability of the work function layer is limited by the spacing between the fins. Summary of the Invention

[0007] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed multi-threshold voltage fin field effect transistor.

[0008] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region; forming a first gate dielectric structure on the first region; forming a second gate dielectric structure on the second region; forming a first barrier layer on the first gate dielectric structure; forming a second barrier layer on the second gate dielectric structure; performing a modification treatment on the first barrier layer to form a modified layer; forming a first diffusion layer on the modified layer, the first diffusion layer having polarized atoms therein; forming a second diffusion layer on the second barrier layer, the second diffusion layer having the polarized atoms therein; performing a modification treatment on the first diffusion layer and the second diffusion layer; Annealing treatment drives the polarized atoms located in the first diffusion layer to diffuse into the first gate dielectric structure to form a first polarization layer, and drives the polarized atoms located in the second diffusion layer to diffuse into the second gate dielectric structure to form a second polarization layer; after the first polarization layer is formed, a first gate structure is formed on the first region, a first source-drain doped layer is provided in the substrate on both sides of the first gate structure, and a first transistor structure is formed on the first region; after the second polarization layer is formed, a second gate structure is formed on the second region, a second source-drain doped layer is provided in the substrate on both sides of the second gate structure, and a second transistor structure is formed on the second region.

[0009] Optionally, the substrate further includes: a third region.

[0010] Optionally, before forming the first gate dielectric structure and the second gate dielectric structure, it also includes: forming a dielectric layer on the substrate, the dielectric layer having a first opening, a second opening and a third opening, the first opening being located on the first region, the second opening being located on the second region, and the third opening being located on the third region.

[0011] Optionally, during the process of forming the first gate dielectric structure and the second gate dielectric structure, the method further includes: forming a third gate dielectric structure on the third region.

[0012] Optionally, the method for forming the first barrier layer and the second barrier layer includes: forming an initial barrier layer on the first gate dielectric structure, the second gate dielectric structure and the third gate dielectric structure; removing the initial barrier layer located on the third gate dielectric structure, forming the first barrier layer on the first gate dielectric structure, and forming the second barrier layer on the second gate dielectric structure.

[0013] Optionally, during the process of forming the first diffusion layer and the second diffusion layer, the method further includes: forming a third diffusion layer on the third gate dielectric structure, wherein the third diffusion layer has the polarized atoms.

[0014] Optionally, the first diffusion layer, the second diffusion layer and the third diffusion layer are formed simultaneously.

[0015] Optionally, during the annealing process on the first diffusion layer and the second diffusion layer, the method further includes: annealing the third diffusion layer to drive the polarized atoms in the third diffusion layer to diffuse into the third gate dielectric structure to form a third polarized layer.

[0016] Optionally, after forming the first polarization layer, the second polarization layer, and the third polarization layer, the method further includes: removing the first diffusion layer, the second diffusion layer, the third diffusion layer, the modified layer, and the second barrier layer.

[0017] Optionally, the polarizable atoms include: La, Ce, Nb, Mg, Sc or Al.

[0018] Optionally, the first gate dielectric structure includes: a first gate oxide layer and a first gate dielectric layer located on the first gate oxide layer; the second gate dielectric structure includes: a second gate oxide layer and a second gate dielectric layer located on the second gate oxide layer; the third gate dielectric structure includes: a third gate oxide layer and a third gate dielectric layer located on the third gate oxide layer.

[0019] Optionally, the first gate dielectric structure includes a first gate oxide layer; the second gate dielectric structure includes a second gate oxide layer; and the third gate dielectric structure includes a third gate oxide layer.

[0020] Optionally, after forming the first polarization layer, the second polarization layer and the third polarization layer, the method further includes: forming a first gate dielectric layer on the first polarization layer; forming a second gate dielectric layer on the second polarization layer; and forming a third gate dielectric layer on the third polarization layer.

[0021] Optionally, the first gate oxide layer, the second gate oxide layer and the third gate oxide layer are made of the same material, and the material of the first gate oxide layer, the second gate oxide layer and the third gate oxide layer includes silicon oxide.

[0022] Optionally, the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer are made of the same material, and the materials of the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer include high-K dielectric materials, and the high-K dielectric materials include: lanthanum oxide, cerium oxide or hafnium oxide.

[0023] Optionally, the first barrier layer and the second barrier layer are made of the same material; the material of the first barrier layer and the second barrier layer includes: titanium nitride or titanium oxynitride.

[0024] Optionally, when the material of the first barrier layer is titanium oxynitride, the modification method includes: performing nitrogen ion implantation on the first barrier layer to form the modified layer.

[0025] Optionally, the content of the polarized atoms in the first polarization layer is 3% to 8%; the content of the polarized atoms in the second polarization layer is 0.3% to 3%; and the content of the polarized atoms in the third polarization layer is 8% to 15%.

[0026] Optionally, when the material of the first barrier layer is titanium nitride, the modification method includes: performing oxidation treatment on the first barrier layer to form the modified layer.

[0027] Optionally, the content of the polarized atoms in the first polarization layer is 0.1% to 3%; the content of the polarized atoms in the second polarization layer is 3% to 8%; and the content of the polarized atoms in the third polarization layer is 8% to 15%.

[0028] Optionally, after forming the third polarization layer, the method further includes: forming a third gate structure on the third region, wherein the substrate on both sides of the third gate structure has a third source-drain doping layer, and forming a third transistor structure on the third region.

[0029] Optionally, the first gate structure includes: a first work function layer and a first gate layer located on the first work function layer.

[0030] Optionally, the second gate structure includes: a second work function layer and a second gate layer located on the second work function layer.

[0031] Optionally, the third gate structure includes: a third work function layer and a third gate layer located on the third work function layer.

[0032] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0033] In the formation method of the technical solution of the present invention, the first barrier layer is modified to form a modified layer. The formed modified layer can enhance or weaken the blocking effect on polarized atoms, thereby avoiding using the number of stacked layers of the first barrier layer to adjust the blocking effect on the polarized atoms, simplifying the process steps, and also avoiding the problem of too many stacked layers of the first barrier layer making it difficult to fill in between adjacent fin structures, thereby effectively improving the performance of the semiconductor structure finally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a structural diagram of a semiconductor structure;

[0035] Figure 2 and Figure 3 It is a structural diagram of a semiconductor structure;

[0036] Figures 4 to 17It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention.

[0037] Figures 18 and 19 It is a schematic structural diagram of each step of another embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0038] As described in the background art, there are still many problems in the process of forming a multi-threshold voltage FinFET in the prior art.

[0039] With the further development of semiconductor technology, the size of integrated circuit devices is getting smaller and smaller, and the corresponding spacing between adjacent fin structures is also getting smaller and smaller. In the existing technology, the corresponding threshold voltage is adjusted by the number of stacked work function layers. However, due to the small spacing between adjacent fin structures, it is difficult for work function layers with a large number of stacked layers to be filled between the adjacent fin structures, making it difficult for the threshold voltage to reach the requirement, thereby affecting the performance of the final semiconductor structure.

[0040] In order to solve the above problems, another method for forming a semiconductor structure is proposed, which will be described in detail below with reference to the accompanying drawings.

[0041] Please refer to Figure 2 , providing a substrate 100; forming a dielectric layer 101 on the substrate 100, wherein a first opening 102, a second opening 103 and a third opening 104 are formed in the dielectric layer 101, wherein the first opening 102, the second opening 103 and the third opening 104 expose the top surface of the substrate 100; forming a first gate dielectric structure 105 in the first opening 102; forming a second gate dielectric structure 106 in the second opening 103; forming a third gate dielectric structure 107 in the third opening 104; forming a first gate dielectric structure 108 in the first opening 102; forming a second gate dielectric structure 109 in the second opening 103; forming a third gate dielectric structure 109 in the third opening 104; forming a first gate dielectric structure 109 in the first opening 102; forming a second ... Several first barrier layers 108 are formed on the gate dielectric structure 105; several second barrier layers 109 are formed on the second gate dielectric structure 106; a first diffusion layer 110 is formed on the first barrier layer 108, and the first diffusion layer 110 has polarized atoms therein; a second diffusion layer 111 is formed on the second barrier layer 109, and the second diffusion layer 111 has the polarized atoms therein; a third diffusion layer 112 is formed on the third gate dielectric structure 107, and the third diffusion layer 112 has the polarized atoms therein.

[0042] Please refer to Figure 3 , the first diffusion layer 110, the second diffusion layer 111 and the third diffusion layer 112 are annealed to drive the polarized atoms to diffuse into the first gate dielectric structure 105, the second gate dielectric structure 106 and the third gate dielectric structure 107 respectively, to form a first polarization layer 113, a second polarization layer 114 and a third polarization layer 115.

[0043] In this embodiment, the first polarization layer 113, the second polarization layer 114 and the third polarization layer 115 are formed with polarized atoms, and the threshold voltage is jointly adjusted by forming chemical bonds between the polarized atoms and the corresponding gate dielectric structure, and the number of stacked layers of the subsequently formed work function layers, so that the number of stacked layers of the work function layers is not the only factor affecting the threshold voltage, thereby effectively reducing the number of stacked layers of the work function layers.

[0044] However, to form transistors with different threshold voltages, different gate dielectric structures require different polarized atom contents. In this embodiment, the number of stacked layers of the first barrier layer 108 and the second barrier layer 109 is controlled to control the polarized atom contents ultimately diffused into the first gate dielectric structure 105 and the second gate dielectric structure 106. Because the spacing between adjacent fin structures is relatively small, barrier layers with a large number of stacked layers are difficult to fill between adjacent fin structures, making it difficult to achieve the required threshold voltage, thereby affecting the performance of the resulting semiconductor structure.

[0045] On this basis, the present invention provides a method for forming a semiconductor structure, by modifying the first barrier layer to form a modified layer, the formed modified layer can enhance or weaken the blocking effect on polarized atoms, thereby avoiding using the number of stacked layers of the first barrier layer to adjust the blocking effect on the polarized atoms, simplifying the process steps, and also avoiding the problem of too many stacked layers of the first barrier layer making it difficult to fill in between adjacent fin structures, thereby effectively improving the performance of the semiconductor structure finally formed.

[0046] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] Figures 4 to 17 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0048] Please refer to Figure 4 and Figure 5 , Figure 4 is a top view of the semiconductor structure. Figure 5 It is along Figure 4 A schematic cross-sectional view taken along line AA shows a substrate comprising a first region I and a second region II.

[0049] In this embodiment, the substrate further includes a third region III, the first region I is located between the second region II and the third region III, and the first region I, the second region II, and the third region III are used to form transistor structures with different threshold voltages.

[0050] In this embodiment, the base includes a substrate 200 and a plurality of separate fin structures 201 located on the substrate 200 .

[0051] In other embodiments, the fin structure may further include a plurality of channel layers arranged at a certain distance along the normal direction of the substrate surface; in other embodiments, the fin structure may not be provided.

[0052] In this embodiment, the method for forming the substrate 200 and the fin structure 201 includes: providing an initial substrate (not shown), the initial substrate having a mask layer (not shown), the mask layer exposing a portion of the top surface of the initial substrate; etching the initial substrate using the mask layer as a mask to form the substrate 200 and the fin structure 201 located on the substrate 200.

[0053] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0054] In this embodiment, the material of the fin structure 201 is silicon; in other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0055] Please refer to Figure 6 , Figure 6 and Figure 5 In the same viewing direction, an isolation layer 202 is formed on the substrate 200 , the isolation layer 202 covers a portion of the sidewall of the fin 201 , and the top surface of the isolation layer 202 is lower than the top surface of the fin 201 .

[0056] In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate 200; etching and removing a portion of the initial isolation layer to form the isolation layer 202, wherein the top surface of the isolation layer 202 is lower than the top surface of the fin 201.

[0057] The isolation layer 202 is made of an insulating material, which includes silicon oxide or silicon oxynitride. In this embodiment, the isolation layer 202 is made of silicon oxide.

[0058] Please refer to Figure 7 After forming the isolation layer 202, a first dummy gate structure 203, a second dummy gate structure 204 and a third dummy gate structure 205 are formed on the substrate 200 across the fin structure 201, wherein the first dummy gate structure 203 is located on the first region I, the second dummy gate structure 204 is located on the second region II, and the third dummy gate structure 205 is located on the third region III.

[0059] It should be noted that, in order to facilitate clear description in the drawings, the number of dummy gate structures formed on each region is set to be one; however, in the actual production process, multiple gate structures are formed on each region.

[0060] In this embodiment, the method for forming the first dummy gate structure 203 includes: forming a first dummy gate dielectric layer on the isolation layer 202; forming a first dummy gate layer on the first dummy gate dielectric layer; and forming a first sidewall (not marked) on the sidewalls of the first dummy gate dielectric layer and the first dummy gate layer.

[0061] In this embodiment, the material of the first dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the first dummy gate dielectric layer may also be silicon oxynitride.

[0062] In this embodiment, the material of the first dummy gate layer is silicon.

[0063] In this embodiment, the method for forming the second dummy gate structure 204 includes: forming a second dummy gate dielectric layer on the isolation layer 202; forming a second dummy gate layer on the second dummy gate dielectric layer; and forming a second sidewall (not marked) on the sidewalls of the second dummy gate dielectric layer and the second dummy gate layer.

[0064] In this embodiment, the method for forming the third dummy gate structure 205 includes: forming a third dummy gate dielectric layer on the isolation layer; forming a third dummy gate layer on the third dummy gate dielectric layer; and forming a third sidewall (not marked) on the sidewalls of the third dummy gate dielectric layer and the third dummy gate layer.

[0065] In this embodiment, the material of the second dummy gate dielectric layer and the third dummy gate dielectric layer is the same as that of the first dummy gate dielectric layer, and the material of the second dummy gate layer and the third dummy gate layer is also the same as that of the first dummy gate layer.

[0066] In this embodiment, the first dummy gate structure 203 , the second dummy gate structure 204 and the third dummy gate structure 205 are formed simultaneously, which can effectively improve production efficiency.

[0067] Please refer to Figure 8 After forming the first dummy gate structure 203, the second dummy gate structure 204 and the third dummy gate structure 205, the fin structure 201 is etched using the first dummy gate structure 203, the second dummy gate structure 204 and the third dummy gate structure 205 as masks to form a plurality of source and drain openings (not marked) in the fin structure 201; and the source and drain doping layer 206 is formed in the source and drain openings.

[0068] In this embodiment, the source-drain doped layer 206 includes: a first source-drain doped layer located in the first region I fin structure 201; a first source-drain doped layer located in the second region II fin structure 201; and a first source-drain doped layer located in the third region III fin structure 201.

[0069] In this embodiment, the method for forming the source-drain doped layer 206 includes: forming an epitaxial layer in the source-drain opening using an epitaxial growth process; in-situ doping the epitaxial layer during the epitaxial growth process, and doping source-drain ions into the epitaxial layer to form the source-drain doped layer 206.

[0070] The source and drain ions include P-type ions or N-type ions. In this embodiment, the source and drain ion types of the source and drain doping layers formed in the first region, the second region, and the third region are different; in other embodiments, the source and drain ion types of the source and drain doping layers formed in the first region, the second region, and the third region may also be the same.

[0071] Please refer to Figure 9 After forming the source / drain doping layer 206 , a dielectric layer 207 is formed on the substrate 200 , and the dielectric layer 207 covers the sidewalls of the first dummy gate structure 203 , the second dummy gate structure 204 and the third dummy gate structure 205 .

[0072] In this embodiment, the material of the dielectric layer 207 is silicon oxide; in other embodiments, the material of the dielectric layer can also be low-K dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-K dielectric material (referring to a dielectric material with a relative dielectric constant lower than 2.5).

[0073] Please refer to Figure 10 After forming the dielectric layer 207, the first dummy gate structure 203 is removed, and a first opening 208 is formed in the dielectric layer 207, and the first opening 208 is located on the first region I; the second dummy gate structure 204 is removed, and a second opening 209 is formed in the dielectric layer 207, and the second opening 209 is located on the second region II; the third dummy gate structure 205 is removed, and a third opening 210 is formed in the dielectric layer 207, and the third opening 210 is located on the third region III.

[0074] In this embodiment, specifically, the first dummy gate dielectric layer and the first dummy gate layer of the first dummy gate structure 203 are removed; the second dummy gate dielectric layer and the second dummy gate layer of the second dummy gate structure 204 are removed; and the third dummy gate dielectric layer and the third dummy gate layer of the third dummy gate structure 205 are removed.

[0075] Please refer to Figure 11After forming the first opening 208 , the second opening 209 and the third opening 210 , a first gate dielectric structure is formed on the first region I; and a second gate dielectric structure is formed on the second region II.

[0076] In this embodiment, the process of forming the first gate dielectric structure and the second gate dielectric structure further includes: forming a third gate dielectric structure on the third region III.

[0077] In this embodiment, the first gate dielectric structure is specifically located in the first opening 208 , the second gate dielectric structure is specifically located in the second opening 209 , and the third gate dielectric structure is specifically located in the third opening 210 .

[0078] In this embodiment, the first gate dielectric structure includes: a first gate oxide layer 211 and a first gate dielectric layer 212 located on the first gate oxide layer 211; the second gate dielectric structure includes: a second gate oxide layer 213 and a second gate dielectric layer 214 located on the second gate oxide layer 213; and the third gate dielectric structure includes: a third gate oxide layer 215 and a third gate dielectric layer 216 located on the third gate oxide layer 215.

[0079] In this embodiment, the first gate oxide layer 211 , the second gate oxide layer 213 and the third gate oxide layer 215 are made of the same material, which includes silicon oxide.

[0080] The first gate dielectric layer 212, the second gate dielectric layer 214, and the third gate dielectric layer 216 are made of the same material. The first gate dielectric layer 212, the second gate dielectric layer 214, and the third gate dielectric layer 216 are made of a high-K dielectric material, such as lanthanum oxide, cerium oxide, or hafnium oxide. In this embodiment, the first gate dielectric layer 212, the second gate dielectric layer 214, and the third gate dielectric layer 216 are each made of hafnium oxide.

[0081] Please refer to Figure 12 After forming the first gate dielectric structure, the second gate dielectric structure and the third gate dielectric structure, a first barrier layer 217 is formed on the first gate dielectric structure; and a second barrier layer 218 is formed on the second gate dielectric structure.

[0082] In this embodiment, the method for forming the first barrier layer 217 and the second barrier layer 218 includes: forming an initial barrier layer (not shown) on the first gate dielectric structure, the second gate dielectric structure and the third gate dielectric structure; removing the initial barrier layer located on the third gate dielectric structure, forming the first barrier layer 217 on the first gate dielectric structure, and forming the second barrier layer 218 on the second gate dielectric structure.

[0083] In this embodiment, the first barrier layer 217 and the second barrier layer 218 are used to block the diffusion of polarized atoms in the subsequent diffusion layer.

[0084] In this embodiment, the first barrier layer 217 and the second barrier layer 218 are made of the same material, titanium oxynitride. In other embodiments, the first barrier layer 217 and the second barrier layer 218 may also be made of titanium nitride.

[0085] Please refer to Figure 13 , the first barrier layer 217 is modified to form a modified layer 219.

[0086] By modifying the first barrier layer 217 to form a modified layer 219, the modified layer 219 can enhance or weaken the blocking effect on polarized atoms, thereby avoiding using the number of stacked layers of the first barrier layer 217 to adjust the blocking effect on the polarized atoms, simplifying the process steps, and also avoiding the problem of too many stacked layers of the first barrier layer 217 making it difficult to fill in between the adjacent fin structures, thereby effectively improving the performance of the semiconductor structure finally formed.

[0087] The specific principle of the modification process is to change the nitrogen ion and oxygen ion content in the first barrier layer 217. When the nitrogen ion content in the modified layer 219 is high, its corresponding barrier capability is weaker, thereby increasing the content of polarized atoms that subsequently diffuse into the first gate dielectric structure. Conversely, when the oxygen ion content in the modified layer 219 is high, its corresponding barrier capability is stronger, thereby decreasing the content of polarized atoms that subsequently diffuse into the first gate dielectric structure.

[0088] In this embodiment, the material of the first barrier layer 217 is titanium oxynitride, and the modification method includes: performing nitrogen ion implantation on the first barrier layer 217 to form the modified layer 219 .

[0089] By implanting nitrogen ions into the first barrier layer 217, the nitrogen ion content in the modified layer 219 is increased, thereby reducing the barrier capability of the modified layer 219. Since the second barrier layer 217 has not been modified, the barrier capability of the modified layer 219 is lower than that of the second barrier layer 218. As a result, the content of polarized atoms subsequently diffused into the first gate dielectric structure is greater than that of the second gate dielectric structure. Since no barrier layer is formed on the third gate dielectric structure, the content of polarized atoms subsequently diffused into the third gate dielectric structure is the highest.

[0090] In other embodiments, the material of the first barrier layer is titanium nitride, and the modification method includes: performing an oxidation treatment on the first barrier layer to form the modified layer.

[0091] By oxidizing the first barrier layer, the oxygen ion content in the resulting modified layer is increased, thereby enhancing the barrier capability of the modified layer. Since the second barrier layer has been modified, the barrier capability of the modified layer is higher than that of the second barrier layer, resulting in a lower content of polarized atoms subsequently diffused into the first gate dielectric structure than in the second gate dielectric structure. Since no barrier layer is formed on the third gate dielectric structure, the content of polarized atoms subsequently diffused into the third gate dielectric structure is the highest.

[0092] Please refer to Figure 14 A first diffusion layer 220 is formed on the modified layer 219 , wherein the first diffusion layer 220 has polarized atoms therein; and a second diffusion layer 221 is formed on the second barrier layer 218 , wherein the second diffusion layer 221 has the polarized atoms therein.

[0093] In this embodiment, the process of forming the first diffusion layer 220 and the second diffusion layer 221 further includes: forming a third diffusion layer 222 on the third gate dielectric structure, wherein the third diffusion layer 222 has the polarized atoms.

[0094] In this embodiment, the first diffusion layer 220, the second diffusion layer 221, and the third diffusion layer 222 are formed simultaneously. The first diffusion layer 220, the second diffusion layer 221, and the third diffusion layer 222 are formed simultaneously through a global process, which can effectively reduce the number of manufacturing processes and improve production efficiency.

[0095] In this embodiment, the first diffusion layer 220, the second diffusion layer 221 and the third diffusion layer 222 are made of lanthanum oxide. In other embodiments, the first diffusion layer 220, the second diffusion layer 221 and the third diffusion layer 222 may also be made of cerium oxide.

[0096] The polarizable atoms include La, Ce, Nb, Mg, Sc or Al. In this embodiment, the polarizable atoms are La (lanthanum).

[0097] Please refer to Figure 15 , the first diffusion layer 220 and the second diffusion layer 221 are annealed to drive the polarized atoms located in the first diffusion layer 220 to diffuse into the first gate dielectric structure to form a first polarized layer 223, and drive the polarized atoms located in the second diffusion layer 221 to diffuse into the second gate dielectric structure to form a second polarized layer 224.

[0098] In this embodiment, the process of annealing the first diffusion layer 220 and the second diffusion layer 221 further includes: annealing the third diffusion layer 222 to drive the polarized atoms in the third diffusion layer 222 to diffuse into the third gate dielectric structure to form a third polarized layer 225 .

[0099] The first polarization layer 223, the second polarization layer 224 and the third polarization layer 225 are formed with polarized atoms, and the threshold voltage is jointly adjusted by forming chemical bonds between the polarized atoms and the corresponding gate dielectric structure, and the number of stacked layers of the subsequently formed work function layers, so that the number of stacked layers of the work function layers is not the only factor affecting the threshold voltage, thereby effectively reducing the number of stacked layers of subsequent work function layers.

[0100] In this embodiment, because the first and second barrier layers 217 and 218 are made of titanium oxynitride and the modification treatment involves nitrogen ion implantation, the first polarization layer 223 contains a relatively high content of polarized atoms, the second polarization layer 224 contains the least polarized atoms, and the third polarization layer 225 contains the most polarized atoms. The polarized atom content in the first polarization layer 223 is 3% to 8%, the polarized atom content in the second polarization layer 224 is 0.1% to 3%, and the polarized atom content in the third polarization layer 225 is 8% to 15%.

[0101] Since the contents of polarized atoms in the first polarization layer 223 , the second polarization layer 224 and the third polarization layer 225 are different, the corresponding threshold voltages are also different.

[0102] In other embodiments, the material of the first and second barrier layers may also be titanium nitride, and the modification treatment is an oxidation treatment. Therefore, the first polarization layer has the least polarized atom content, the second polarization layer has a greater polarized atom content, and the third polarization layer has the greatest polarized atom content. The polarized atom content in the first polarization layer is 0.1% to 3%; the polarized atom content in the second polarization layer is 3% to 8%; and the polarized atom content in the third polarization layer is 8% to 15%.

[0103] Please refer to Figure 16 After forming the first polarization layer 223 , the second polarization layer 224 and the third polarization layer 225 , the method further includes removing the first diffusion layer 220 , the second diffusion layer 221 , the third diffusion layer 222 , the modified layer 219 and the second barrier layer 218 .

[0104] The process for removing the first diffusion layer 220, the second diffusion layer 221, the third diffusion layer 222, the modified layer 219, and the second barrier layer 218 employs one or a combination of wet etching and dry etching. In this embodiment, the process for removing the first diffusion layer 220, the second diffusion layer 221, the third diffusion layer 222, the modified layer 219, and the second barrier layer 218 employs a dry etching process.

[0105] Please refer to Figure 17 After removing the first diffusion layer 220, the second diffusion layer 221, the third diffusion layer 222, the modified layer 219 and the second barrier layer 218, a first gate structure 226 is formed on the first region I; a second gate structure 227 is formed on the second region II; and a third gate structure 228 is formed on the third region III.

[0106] In this embodiment, the first source-drain doped layer is located in the fin structure 201 on both sides of the first gate structure 226, and a first transistor structure is formed on the first region I through the first gate structure 226 and the first source-drain doped layer on both sides of the first gate structure 226; the second source-drain doped layer is located in the fin structure 201 on both sides of the second gate structure 227, and a second transistor structure is formed on the second region II through the second gate structure 227 and the second source-drain doped layer on both sides of the second gate structure 227; the third source-drain doped layer is located in the fin structure 201 on both sides of the third gate structure 228, and a third transistor structure is formed on the third region III through the third gate structure 228 and the third source-drain doped layer on both sides of the third gate structure 228.

[0107] In this embodiment, the first gate structure 226 is specifically located on the surface of the first polarization layer 223 . The first gate structure 226 includes a first work function layer and a first gate layer (not labeled) located on the first work function layer.

[0108] In this embodiment, the second gate structure 227 is specifically located on the surface of the second polarization layer 224 . The second gate structure 227 includes a second work function layer and a second gate layer (not labeled) located on the second work function layer.

[0109] In this embodiment, the third gate structure 228 is specifically located on the surface of the third polarization layer 225 . The third gate structure 228 includes a third work function layer and a third gate layer (not labeled) located on the third work function layer.

[0110] Figures 18 and 19 It is a structural schematic diagram of a semiconductor structure forming process according to another embodiment of the present invention.

[0111] This embodiment further describes a method for forming a semiconductor structure based on the above embodiment. This embodiment differs from the above embodiment in that: the first gate dielectric structure includes a first gate oxide layer 211; the second gate dielectric structure includes a second gate oxide layer 213; and the third gate dielectric structure includes a third gate oxide layer 215. This will be described in detail below with reference to the accompanying drawings.

[0112] Please refer to Figure 18 After forming the first polarization layer 223 , the second polarization layer 224 and the third polarization layer 225 , a first gate dielectric layer 212 is formed on the first polarization layer 223 ; a second gate dielectric layer 214 is formed on the second polarization layer 224 ; and a third gate dielectric layer 216 is formed on the third polarization layer 225 .

[0113] The first gate dielectric layer 212, the second gate dielectric layer 214, and the third gate dielectric layer 216 are made of the same material. The first gate dielectric layer 212, the second gate dielectric layer 214, and the third gate dielectric layer 216 are made of a high-K dielectric material, such as lanthanum oxide, cerium oxide, or hafnium oxide. In this embodiment, the first gate dielectric layer 212, the second gate dielectric layer 214, and the third gate dielectric layer 216 are each made of hafnium oxide.

[0114] Please refer to Figure 19 After forming the first gate dielectric layer 212, the second gate dielectric layer 214 and the third gate dielectric layer 216, a first gate structure 226 is formed on the first region I; a second gate structure 227 is formed on the second region II; and a third gate structure 228 is formed on the third region III.

[0115] In this embodiment, the first gate structure 226 is specifically located on the surface of the first gate dielectric layer 212 . The first gate structure 226 includes a first work function layer and a first gate layer (not labeled) located on the first work function layer.

[0116] In this embodiment, the second gate structure 227 is specifically located on the surface of the second gate dielectric layer 214 . The second gate structure 227 includes a second work function layer and a second gate layer (not labeled) located on the second work function layer.

[0117] In this embodiment, the third gate structure 228 is specifically located on the surface of the third gate dielectric layer 216 . The third gate structure 228 includes a third work function layer and a third gate layer (not labeled) located on the third work function layer.

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate comprising a first region and a second region; forming a first gate dielectric structure on the first region; forming a second gate dielectric structure on the second region; forming a first barrier layer on the first gate dielectric structure; forming a second barrier layer on the second gate dielectric structure; performing a modification treatment on the first barrier layer to form a modified layer; forming a first diffusion layer on the modified layer, wherein the first diffusion layer has polarized atoms; forming a second diffusion layer on the second barrier layer, wherein the second diffusion layer has the polarized atoms; Annealing the first diffusion layer and the second diffusion layer to drive the polarized atoms in the first diffusion layer to diffuse into the first gate dielectric structure to form a first polarized layer, and drive the polarized atoms in the second diffusion layer to diffuse into the second gate dielectric structure to form a second polarized layer; After forming the first polarization layer, forming a first gate structure on the first region, wherein the substrate on both sides of the first gate structure has a first source-drain doped layer, and forming a first transistor structure on the first region; After forming the second polarization layer, a second gate structure is formed on the second region, a second source-drain doped layer is provided in the substrate on both sides of the second gate structure, and a second transistor structure is formed on the second region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The substrate further includes: a third region.

3. The method for forming a semiconductor structure according to claim 2, wherein: Before forming the first gate dielectric structure and the second gate dielectric structure, the method further includes: forming a dielectric layer on the substrate, wherein the dielectric layer has a first opening, a second opening, and a third opening, wherein the first opening is located on the first region, the second opening is located on the second region, and the third opening is located on the third region.

4. The method for forming a semiconductor structure according to claim 2, wherein: The process of forming the first gate dielectric structure and the second gate dielectric structure further includes: forming a third gate dielectric structure on the third region.

5. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the first barrier layer and the second barrier layer includes: forming an initial barrier layer on the first gate dielectric structure, the second gate dielectric structure and the third gate dielectric structure; removing the initial barrier layer located on the third gate dielectric structure, forming the first barrier layer on the first gate dielectric structure, and forming the second barrier layer on the second gate dielectric structure.

6. The method for forming a semiconductor structure according to claim 4, wherein: The process of forming the first diffusion layer and the second diffusion layer further includes: forming a third diffusion layer on the third gate dielectric structure, wherein the third diffusion layer has the polarized atoms.

7. The method for forming a semiconductor structure according to claim 6, wherein: The first diffusion layer, the second diffusion layer and the third diffusion layer are formed simultaneously.

8. The method for forming a semiconductor structure according to claim 7, wherein: The process of annealing the first diffusion layer and the second diffusion layer further includes: annealing the third diffusion layer to drive the polarized atoms in the third diffusion layer to diffuse into the third gate dielectric structure to form a third polarized layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: After forming the first polarization layer, the second polarization layer and the third polarization layer, the method further includes removing the first diffusion layer, the second diffusion layer, the third diffusion layer, the modified layer and the second barrier layer.

10. The method for forming a semiconductor structure according to claim 1 or 6, wherein: The polarizable atoms include La, Ce, Nb, Mg, Sc or Al.

11. The method for forming a semiconductor structure according to claim 4, wherein: The first gate dielectric structure includes: a first gate oxide layer and a first gate dielectric layer located on the first gate oxide layer; the second gate dielectric structure includes: a second gate oxide layer and a second gate dielectric layer located on the second gate oxide layer; the third gate dielectric structure includes: a third gate oxide layer and a third gate dielectric layer located on the third gate oxide layer.

12. The method for forming a semiconductor structure according to claim 9, wherein: The first gate dielectric structure includes a first gate oxide layer; the second gate dielectric structure includes a second gate oxide layer; and the third gate dielectric structure includes a third gate oxide layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: After forming the first polarization layer, the second polarization layer and the third polarization layer, the method further includes: forming a first gate dielectric layer on the first polarization layer; forming a second gate dielectric layer on the second polarization layer; and forming a third gate dielectric layer on the third polarization layer.

14. The method for forming a semiconductor structure according to claim 11 or 12, wherein: The first gate oxide layer, the second gate oxide layer and the third gate oxide layer are made of the same material, and the material of the first gate oxide layer, the second gate oxide layer and the third gate oxide layer includes silicon oxide.

15. The method for forming a semiconductor structure according to claim 11 or 13, wherein: The first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer are made of the same material. The first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer include high-K dielectric materials. The high-K dielectric materials include lanthanum oxide, cerium oxide or hafnium oxide.

16. The method for forming a semiconductor structure according to claim 8, wherein: The first barrier layer and the second barrier layer are made of the same material; the material of the first barrier layer and the second barrier layer includes titanium nitride or titanium oxynitride.

17. The method for forming a semiconductor structure according to claim 16, wherein: When the material of the first barrier layer is titanium oxynitride, the modification method includes: performing nitrogen ion implantation on the first barrier layer to form the modified layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: The content of the polarized atoms in the first polarization layer is 3% to 8%; the content of the polarized atoms in the second polarization layer is 0.3% to 3%; and the content of the polarized atoms in the third polarization layer is 8% to 15%.

19. The method for forming a semiconductor structure according to claim 16, wherein: When the material of the first barrier layer is titanium nitride, the modification method includes: performing oxidation treatment on the first barrier layer to form the modified layer.

20. The method for forming a semiconductor structure according to claim 19, wherein: The content of the polarized atoms in the first polarization layer is 0.1% to 3%; the content of the polarized atoms in the second polarization layer is 3% to 8%; and the content of the polarized atoms in the third polarization layer is 8% to 15%.

21. The method for forming a semiconductor structure according to claim 8, wherein: After forming the third polarization layer, the method further includes: forming a third gate structure on the third region, wherein the substrate on both sides of the third gate structure has a third source-drain doping layer, and forming a third transistor structure on the third region.

22. The method for forming a semiconductor structure according to claim 1, wherein: The first gate structure includes a first work function layer and a first gate layer located on the first work function layer.

23. The method for forming a semiconductor structure according to claim 1, wherein: The second gate structure includes a second work function layer and a second gate layer located on the second work function layer.

24. The method for forming a semiconductor structure according to claim 21, wherein: The third gate structure includes a third work function layer and a third gate layer located on the third work function layer.

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