Semiconductor package structure

Abstract

The application relates to a semiconductor packaging structure. The semiconductor packaging structure comprises a substrate and a first electronic component embedded in the substrate, the substrate having a first conductive via, the first conductive via being electrically connected with the first electronic component, wherein the first conductive via is physically separated from the first electronic component. The above technical scheme of the application can at least ensure the electrical connection between the via and the electronic component.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure. Background Technology

[0002] With the evolution of semiconductor packaging technology, various packaging structures are constantly being innovated, and the overall package size is becoming smaller and smaller while the functions are becoming more and more numerous. Therefore, a power package is usually needed to control various components. To some extent, semiconductor embedded in substrate (SESUB) is an inevitable trend for the packaging industry to move towards component integration in the future.

[0003] In the current SESUB process, during the sandblasting process for forming micro vias, a problem has been found where electrical disconnection occurs due to opening. For example... Figure 1 As shown, this is mainly due to the excessive thickness of the resin material 20 above the die 10, which prevents the pre-set sandblasting process from opening the aperture 12 to the die 10. However, the main reasons for the excessive thickness of the resin material 20 above the die 10 are the deviation from the manufacturing process and the inherent error of the resin material 20 itself. Summary of the Invention

[0004] To address the aforementioned problems in related technologies, this invention proposes a semiconductor packaging structure that ensures electrical connection between vias and electronic components.

[0005] According to one aspect of the present invention, a semiconductor package structure is provided, including a substrate and a first electronic component embedded in the substrate. The substrate has a first conductive via electrically connected to the first electronic component, wherein the first conductive via is physically separated from the first electronic component.

[0006] In some embodiments, the lower surface of the first conductive via is physically separated from the first electronic component.

[0007] In some embodiments, the substrate includes a dielectric layer covering a first electronic component, and the first conductive via is separated from the first electronic component by the dielectric layer.

[0008] In some embodiments, a conductive post is provided on the surface of the first electronic component adjacent to the first conductive via, and the conductive post extends from the first electronic component into the first conductive via.

[0009] In some embodiments, the first conductive via partially exposes the conductive post.

[0010] In some embodiments, the semiconductor package structure further comprises a third electronic element disposed on the substrate and electrically connected with the first electronic element; and a molding compound covering the third electronic element and the substrate.

[0011] In some embodiments, the substrate further has a second conductive via, the first conductive via and the second conductive via are not equal in depth.

[0012] In some embodiments, the first conductive via and the second conductive via are not equal in upper surface height.

[0013] In some embodiments, the second conductive via is in physical contact and electrically connected with the first electronic element.

[0014] In some embodiments, the semiconductor package structure further comprises a second electronic element embedded in the substrate; and a second conductive via in physical contact and electrically connected with the second electronic element.

[0015] The above technical solution of the present application, by disposing the conductive pillar on the first electronic element, can compensate the thickness error of the dielectric layer pressing. Specifically, since the error value of the conductive pillar is less than the error value of the dielectric layer pressing, the compensation effect can be achieved. When the depth of the first conductive via is not enough to reach the first electronic element, the first conductive via can still be electrically connected with the first electronic element. BRIEF DESCRIPTION OF DRAWINGS

[0016] Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings in which: It should be noted that the various components are not necessarily drawn to scale. Indeed, the dimensions of the various components can be arbitrarily increased or decreased for the sake of discussion. It should be understood that the detailed description is but one implementation of the present application and is not intended to limit the scope of the present application.

[0017] Figure 1 is a schematic view of an opening of a prior semiconductor package structure.

[0018] Figure 2 is a schematic view of a semiconductor package structure according to an embodiment of the present application.

[0019] Figure 3 is a schematic view of a semiconductor package structure according to another embodiment of the present application.

[0020] Figures 4 to 7 is a schematic view of a plurality of stages of a method of forming a semiconductor package structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments, or examples, for implementing various aspects of the provided subject matter. Although each of the various embodiments can represent a pioneering advancement in the field of the invention, they are described in terms of a specific example to simplify the present disclosure. Of course, those skilled in the art will recognize that these are simply examples and are not intended to limit the scope of the application in any way. For example, in the following description, forming a first component over or on a second component can include embodiments in which the first component and the second component are in direct contact, as well as embodiments in which additional components are formed between the first component and the second component such that the first component and the second component can not be in direct contact. Also, the application can refer to a number and / or letter in various examples. Such repetition is only for the sake of simplicity and clarity and does not itself imply a relationship between the various embodiments and / or configurations discussed.

[0022] Figure 2 is a schematic view of a semiconductor package structure according to an embodiment of the present application. In Figure 2 In the package structure 100 shown, a substrate 110 and a first electronic component 122 embedded in the substrate 110 are included. The substrate 110 has a first conductive via 142 therein, which is electrically connected to the first electronic component 122. Also, the first conductive via 142 is physically separated from the first electronic component 122, i.e., the first conductive via 142 does not directly contact the first electronic component 122. As shown Figure 2 As shown, a lower surface of the first conductive via 142 is physically separated from the first electronic component 122.

[0023] The substrate 110 includes a dielectric layer 130 covering the first electronic component 122. In some embodiments, the material of the dielectric layer 130 includes, but is not limited to, a resin material, polyimide (PI), or polypropylene (PP). The dielectric layer 130 is filled between the lower surface of the first conductive via 142 and the first electronic component 122, such that the first conductive via 142 is separated from the first electronic component 122 by the dielectric layer 130.

[0024] A conductive pillar 150 is disposed on an upper surface of the first electronic component 122 adjacent to the first conductive via 142. The conductive pillar 150 can be disposed on a pad 128 at the upper surface of the first electronic component 122. The conductive pillar 150 extends from the pad 128 of the first electronic component 122 into the first conductive via 142. The conductive pillar 150 extends from the first electronic component 122 into the first conductive via 142, such that the first conductive via 142 covers an upper surface and an upper portion of a sidewall of the conductive pillar 150 and exposes a lower portion of the sidewall of the conductive pillar 150 to electrically connect the first electronic component 122 with the first conductive via 142 through the conductive pillar 150.

[0025] In some embodiments, the material of the conductive pillar 150 can be copper. In some embodiments, the width of the conductive pillar 150 can be in the range of 40 pm to 200 pm, for example, can be in the range of 50 pm to 60 pm. In some embodiments, the height of the conductive pillar 150 can be in the range of 3 pm to 200 pm, for example, can be in the range of 10 pm to 15 pm.

[0026] The above technical solution of the present application, by arranging the conductive pillar 150 on the first electronic element 122, can compensate for the thickness error of the dielectric layer 130 lamination. Specifically, since the error value of the conductive pillar 150 is less than the error value of the dielectric layer 130 lamination, the compensation effect can be achieved. When the depth of the first conductive via 142 is not enough to reach the first electronic element 122, it can still ensure that the first conductive via 142 can be electrically connected with the first electronic element 122.

[0027] With continued reference to Figure 2 As shown, the packaging structure 100 also includes a second electronic element 124 embedded in the substrate 110, and the dielectric layer 130 also covers the second electronic element 124.

[0028] The substrate 110 can also have a second conductive via which is not equal in depth to the first conductive via 142. The second conductive via can also be not equal in height to the first conductive via 142. In some embodiments, the second conductive via which is not equal in depth to the first conductive via 142 can be a via which is in physical and electrical contact with the first electronic element 122. In yet some embodiments, the second conductive via can be a second conductive via 144 which is in physical and electrical contact with the second electronic element 124. Above the dielectric layer 130 is covered with a copper clad laminate (CCL) layer 162. Below the first electronic element 122 and the second electronic element 124 is arranged another CCL layer 164. The first electronic element 122 and the second electronic element 124 are attached to the underlying CCL layer 164 through an attachment layer 168. In some embodiments, the material of the attachment layer 168 can be the same as or different from the material of the dielectric layer 130.

[0029] A first circuit layer 181 is provided on the CCL layer 162. A second circuit layer 182 is provided on the dielectric layer 130. The upper CCL layer 162 has vias 172 interconnecting the first circuit layer 181 and the second circuit layer 182. The first conductive via 142 and the second conductive via 144 electrically connect the first electronic component 122 and the second electronic component 124 to the second circuit layer 182, respectively. The lower CCL layer 164 has a third circuit layer 183 on top and a fourth circuit layer 184 on bottom. The substrate 110 has a through-hole 176 interconnecting the second circuit layer 182 and the third circuit layer 183 through the dielectric layer 130 and the attachment layer 168. The lower CCL layer 164 has vias 174 interconnecting the third circuit layer 183 and the fourth circuit layer 184.

[0030] In some embodiments, the thickness of the dielectric layer 130 over the first electronic component 122 and the second electronic component 124 can be different, and the upper surface of the dielectric layer 130 is the upper surface of the substrate 110, thus the upper surface of the substrate 110 is not flat. The first conductive via 142 and the second conductive via 144 can have different depths. The lower surfaces of the first conductive via 142 and the second conductive via 144 can be at different heights. The upper surfaces of the first conductive via 142 and the second conductive via 144 can be at different heights. In some embodiments, the second conductive via 144 can also be provided on the first electronic component 122, and the first electronic component 122 can have the first conductive via 142 and the second conductive via 144 with different depths, wherein the lower surfaces of the first conductive via 142 and the second conductive via 144 are at different heights. The upper surfaces of the first conductive via 142 and the second conductive via 144 are at different heights.

[0031] In some embodiments, the thickness of the dielectric layer 130 over the first electronic component 122 is greater than the thickness of the dielectric layer 130 over the second electronic component 124, and the first conductive via 142 does not extend to the first electronic component 122 and does not directly contact the first electronic component 122. The thickness of the dielectric layer 130 over the second electronic component 124 is thinner, and the second conductive via 144 can extend to the second electronic component 124 and physically contact the second electronic component 124.

[0032] A conductive pillar 150 is also provided on the upper surface of the second electronic component 124 adjacent to the second conductive via 144. The conductive pillar 150 can be provided on a pad 129 at the upper surface of the second electronic component 124. The conductive pillar 150 over the second electronic component 124 extends from the pad 129 of the second electronic component 124 into the second conductive via 144. The first conductive via 142 covers the upper surface and all sidewalls of the conductive pillar 150.

[0033] Figure 3 is a schematic diagram of a semiconductor package structure according to an embodiment of the present application. InFigure 3 In the illustrated embodiment, a third electronic component 126 is further disposed above the substrate 110. The third electronic component 126 is electrically connected to the first electronic component 122. The third electronic component 126 can be an active component or a passive component. The third electronic component 126 can be electrically connected to the first electronic component 122 through a through-hole 172 and a first conductive through-hole 142. A molding compound 190 covers the third electronic component 126 and the substrate 110. In some embodiments, the material of the molding compound 190 can specifically be an epoxy molding compound. Figure 3 The diagram shows a third electronic component 126 positioned above the substrate 110. In other embodiments, the third electronic component 126 may also be positioned below the substrate 110 and electrically connected to the first electronic component 122. In other embodiments, additional electronic components electrically connected to the second electronic component 124 may be positioned above or below the substrate 110. Figure 2 Other aspects of the illustrated embodiments may be related to Figure 2 The embodiments shown are similar and will not be described again here.

[0034] Embodiments of the present invention also provide a method for forming a semiconductor package structure. Figures 4 to 7 This is a schematic diagram of multiple stages of a method for forming a semiconductor package structure according to an embodiment of the present invention.

[0035] First refer to Figure 4 As shown, a carrier 302 is provided, and a CCL layer 164 and a circuit layer 183 located on the CCL layer 164 are formed on the carrier 302. A first electronic component 122 and a second electronic component 124 are attached to the CCL layer 164 through an attachment layer 168. The surfaces of the first electronic component 122 and the second electronic component 124 having pads 128 and 129 face upward. Each of the pads 128 and 129 of the first electronic component 122 and the second electronic component 124 has a protruding conductive post 150. A dielectric layer 130 is formed on the attachment layer 168 and covers the first electronic component 122, the second electronic component 124, and the conductive post 150 above them.

[0036] like Figure 4 As shown, the upper surface of dielectric layer 130 is not flat. The thickness of dielectric layer 130 covering the first electronic component 122 and the second electronic component 124 may be different. In the illustrated embodiment, the dielectric layer 130 above the first electronic component 122 is thicker than the dielectric layer 130 above the second electronic component 124.

[0037] Then as Figure 5As shown, a first opening 148 is formed above the first electronic component 122 and a second opening 149 is formed above the second electronic component 124 in the dielectric layer 130. In some embodiments, the first opening 148 and the second opening 149 can be formed using a sandblasting process or a laser engraving process. Since the thickness of the dielectric layer 130 above the first electronic component 122 is thicker than that above the second electronic component 124, when the second opening 149 above the second electronic component 124 reaches the second electronic component 124, the first opening 148 above the first electronic component 122 does not penetrate the dielectric layer 130 to reach the first electronic component 122. The bottom surface of the first opening 148 and the bottom surface of the second opening 149 are not at the same height; the bottom surface of the first opening 148 is higher than the bottom surface of the second opening 149. The second opening 149 can expose a portion of the pads 129 of the second electronic component 124, and the second opening 149 exposes the entire sidewall of the conductive pillars 150 on the second electronic component 124. The first opening 148 does not expose the pad 128 of the first electronic component 122, and a dielectric layer 130 is provided between the bottom surface of the first opening 148 and the pad 128 of the first electronic component 122. The first opening 148 can expose the upper surface and upper part of the sidewall of the conductive pillar 150 on the first electronic component 122.

[0038] like Figure 6 As shown, a first conductive via 142 and a second conductive via 144 are formed in the first opening 148 and the second opening 149, respectively. Furthermore, a through-hole 176 can be formed through the dielectric layer 130 and the attachment layer 168. A second circuit layer 182 is formed on the upper surface of the dielectric layer 130, connecting to the first conductive via 142, the second conductive via 144, and the through-hole 176. A CCL layer 162 is then formed covering the dielectric layer 130 and the second circuit layer 182.

[0039] The first conductive via 142 covers the upper surface and upper part of the sidewall of the conductive post 150 on the first electronic component 122, thus allowing the first electronic component 122 to be electrically connected to the first conductive via 142 through the conductive post 150. The second conductive via 144 covers the upper surface and all sidewalls of the conductive post 150 on the second electronic component 124.

[0040] like Figure 7 As shown, the carrier 302 is removed to form vias 172 and 174 through the CCL layers 162 and 164. Then, circuit layers 181 and 184 are formed on the upper surface of the CCL layer 162 and the lower surface of the CCL layer 164, respectively, thus forming the final package structure. Furthermore, in an embodiment not shown, after forming the circuit layers 181 and 184, a third electronic component electrically connected to the first electronic component 122 and a molding compound covering the third electronic component (as shown in reference) can be formed on the CCL layer 162. Figure 3 (As described).

[0041] The above method of the present application can compensate the thickness error of the dielectric layer 130 by setting the conductive pillar 150 on the first electronic component 122. When the depth of the first conductive via 142 is not enough to reach the first electronic component 122, the first conductive via 142 can still be ensured to be electrically connected with the first electronic component 122. The working window is increased, and the yield can also be increased. In addition, by setting the conductive pillar, the sandblasting times of the sandblasting process can be reduced. That is, the opening can be completed with fewer sandblasting times, and the aperture will be smaller. If the subsequent process is to use a laser process to open the hole, since the copper thickness is increased, the laser process can also be achieved.

[0042] The above summary of features of several embodiments enables those skilled in the art to better understand the various aspects of the present disclosure. Those skilled in the art should understand that other processes and structures can be easily designed or modified using the present application as a basis to achieve the same purpose and / or achieve the same advantages as the embodiments described in the present application. Those skilled in the art should also realize that these equivalent structures do not deviate from the spirit and scope of the present application, and various changes, substitutions and modifications can be made without deviating from the spirit and scope of the present application.

Claims

1. A semiconductor packaging structure, characterized in that, The device includes a substrate and a first electronic component and a second electronic component embedded in the substrate. The substrate includes a dielectric layer covering the first electronic component and the second electronic component, and the upper surface of the dielectric layer is not flat. The substrate has a first conductive via and a second conductive via. The first conductive via is electrically connected to a conductive post on the first electronic component, and the second conductive via is electrically connected to the first electronic component or another conductive post on the second electronic component. The lower surfaces of the first conductive via and the second conductive via are not at the same height. The conductive post and the other conductive post extend into the first conductive via and the second conductive via, respectively. The first conductive via is physically separated from the first electronic component.

2. The semiconductor packaging structure according to claim 1, characterized in that, The lower surface of the first conductive via is physically separated from the first electronic component.

3. The semiconductor packaging structure according to claim 1, characterized in that, The first conductive via is separated from the first electronic component by the dielectric layer.

4. The semiconductor packaging structure according to claim 1, characterized in that, The conductive post is disposed on the surface of the first electronic component adjacent to the first conductive via, and the conductive post extends from the first electronic component into the first conductive via.

5. The semiconductor packaging structure according to claim 4, characterized in that, The first conductive via partially exposes the conductive post.

6. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: A third electronic component is disposed on the substrate and electrically connected to the first electronic component; Molding compound, covering the third electronic component and the substrate.

7. The semiconductor packaging structure according to claim 1 or 6, characterized in that, The depths of the first conductive via and the second conductive via are not equal.

8. The semiconductor packaging structure according to claim 7, characterized in that, The upper surfaces of the first conductive via and the second conductive via are not at the same height.

9. The semiconductor packaging structure according to claim 8, characterized in that, The second conductive via is in physical contact and electrically connected to the first electronic component.

10. The semiconductor packaging structure according to claim 8, characterized in that, The second conductive via is in physical contact and electrically connected to the second electronic component.

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