Semiconductor structure

Abstract

A semiconductor structure includes a first inductor, a second inductor, and a first input / output (I / O) pad. The first I / O pad couples the first inductor and the second inductor. The first I / O pad, the magnetic field center axis of the first inductor, and the magnetic field center axis of the second inductor are sequentially arranged along a first direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and in particular to a semiconductor structure of an integrated inductor. Background Art

[0002] Inductors are important components used in integrated circuits to achieve impedance matching and other functions. With the development of integrated circuits, integrated inductors have gradually replaced traditional discrete components and are widely used in integrated circuits. However, as the size of integrated circuits shrinks, in addition to the increased complexity of integrated circuit manufacturing, the configuration of components in integrated circuits is becoming more and more important. Therefore, maintaining the same performance and using less area to configure integrated inductors without increasing process complexity has become a problem that the field is eager to solve. Summary of the invention

[0003] The present invention discloses a semiconductor structure, including a first inductor, a second inductor and a first input / output (I / O) pad. The first I / O pad couples the first inductor and the second inductor. The first I / O pad, the magnetic field center axis of the first inductor and the magnetic field center axis of the second inductor are sequentially arranged along a first direction.

[0004] The present invention further discloses a semiconductor structure, including a first inductor and a second inductor. The first inductor has a first portion, a second portion and a third portion. The second inductor has a fourth portion, a fifth portion and a sixth portion. The first portion, the second portion and the third portion surround the fourth portion. The fourth portion, the fifth portion and the sixth portion surround the first portion.

[0005] The semiconductor structure of the present invention can be used to set up the integrated inductor in a smaller area without affecting the performance, and form a symmetrical structure. Compared with the prior art, the semiconductor structure of the present invention can reduce the setting area of ​​the integrated inductor, and because it has a symmetrical structure, the complexity of manufacturing the integrated inductor is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 4 is a schematic diagram of a semiconductor structure in some embodiments of the present invention.

[0007] Figure 2 FIG. 4 is a schematic diagram of a semiconductor structure in some embodiments of the present invention.

[0008] Figure 3A to Figure 3D FIG. 4 is a layout diagram of an inductor structure in some embodiments of the present invention.

[0009] Figure 4A to Figure 4D FIG. 4 is a layout diagram of an inductor structure in some embodiments of the present invention. DETAILED DESCRIPTION

[0010] refer to Figure 1 . Figure 1 Schematic diagram of a semiconductor structure 10 in some embodiments of the present invention. The semiconductor structure 10 is used to reduce the attenuation of high-frequency signals passing through input / output (I / O) pads in an integrated circuit, in other words, to improve the bandwidth and high-frequency gain of the signal. Figure 1 The semiconductor structure 10 in the embodiment includes two I / O pads (I / O pad 11, I / O pad 12), which correspond to two inductors (I / O pad 11 corresponds to and is coupled to inductors L1 and L2; I / O pad 12 corresponds to and is coupled to inductors L3 and L4), inductors L1 and L3 are coupled to circuit 14; inductors L2 and L4 are coupled to circuit 13. In some embodiments, circuit 13 and circuit 14 may be transmitter circuits or receiver circuits, but are not limited thereto. It should be noted that Figure 1 The embodiment is not intended to limit the number of I / O pads. The basic unit of the semiconductor structure of the present application is an I / O pad and two corresponding inductors. Figure 1 Two I / O pads are shown in the figure to more clearly show their relative positions.

[0011] For example, the input impedance of the signal can be changed by changing the inductance of the inductor L1 and the inductor L2. After proper design, the bandwidth and high-frequency gain of the signal can be improved by implementing impedance matching. In the relevant field, the inductor L1 and the inductor L2 are also called peaking inductors. In some embodiments, the inductor L1 and the inductor L2 can have the same or different inductances. As the die area continues to shrink with the advancement of the process, the width of the I / O pad and the distance between the I / O pads are also reduced. The inductor structure of the present application can reduce the overall area of ​​the inductor L1 and the inductor L2, so that the inductor L1 and the inductor L2 have a narrower width as a whole to meet the current narrower I / O pad width and I / O pad spacing, without letting the peaking inductor limit the placement of the I / O pad.

[0012] Figure 2 Schematic diagram of a semiconductor structure 10 in some embodiments of the present invention, wherein the inductors L1-L4 are represented by a layout diagram for the convenience of explaining the present application. The reference numerals H1, H2, H3 and H4 respectively represent the approximate positions of the central axes of the magnetic fields generated by the inductors L1-L4 when a signal passes through. Figure 2As shown, the I / O pad 11, the magnetic field center axis H1 and the magnetic field center axis H2 are arranged in sequence along the Y direction; the I / O pad 12, the magnetic field center axis H3 and the magnetic field center axis H4 are arranged in sequence along the Y direction. The magnetic field center axis H1 and the magnetic field center axis H3 are arranged in sequence along the X direction; the magnetic field center axis H2 and the magnetic field center axis H4 are arranged in sequence along the X direction.

[0013] Inductor L1, inductor L2 and I / O pad 11 have widths W1, W2 and W3 in the X direction, respectively. In some embodiments, widths W1 and W2 are not greater than W3. In some embodiments, as Figure 2 As shown, widths W1 and W2 are substantially equal. In some embodiments, the size and configuration of I / O pad 11 , inductor L1 , and inductor L2 are substantially the same as the size and configuration of I / O pad 12 , inductor L3 , and inductor L4 .

[0014] Inductors L1 and L2 are arranged in multiple conductive layers. Figure 3A to Figure 3D The inductor L1 (eg Figure 2 Layout diagram of each part structure in different conductive layers; Figure 4A to Figure 4D The inductor L2 (as Figure 2 ) is a layout diagram of the various structures in different conductive layers. Specifically, Figure 3A FIG. 4 shows a layout diagram of the windings of the complete inductor L1 on the conductive layer C1 and the conductive layer C2 (shown in an overlapping manner); Figure 3B Only the layout diagram of the winding of the inductor L1 on the conductive layer C1 is shown; Figure 3C Only the layout diagram of the via holes of the inductor L1 on the connection layer CV is shown, and the connection layer CV is between the conductive layers C1 and C2; Figure 3D Only the layout diagram of the winding of the inductor L1 on the conductive layer C2 is shown.

[0015] Please refer to Figure 3A to Figure 3D The inductor L1 includes a first part P1, a second part P2 and a third part P3. The first part P1 is the main coil part of the inductor L1, which is arranged in the winding of the conductive layer C1. Figure 3B As shown, and the winding arranged in the conductive layer C2 is as shown Figure 3D The second portion P2 and the third portion P3 are disposed on the conductive layer C2. Figure 3DAs shown. The conductive layer C1 and the conductive layer C2 are disposed above a substrate (not shown), and the conductive layer C1 is disposed above the conductive layer C2, that is, the conductive layer C2 is disposed between the substrate and the conductive layer C1. In the present embodiment, the conductive layer C1 includes aluminum, such as an aluminum-redistribution layer (AL-RDL); the conductive layer C2 includes copper, such as an ultra thick metal (UTM) layer including copper, which is located at the top of the multiple copper metal layers. However, the present application is not limited thereto. In some embodiments, the conductive layer C1 and the conductive layer C2 may both be copper metal layers. The conductive layer C1 is coupled to the conductive layer C2 through the connecting layer CV. In the present embodiment, the winding of the inductor L1 disposed on the conductive layer C1 and the winding of the inductor L1 disposed on the conductive layer C2 are interconnected through vias V1 and V2 on the connecting layer CV.

[0016] The number of turns of the winding of the first part P1 of the inductor L1 configured on the conductive layer C1 and the number of turns of the winding configured on the conductive layer C2 can be determined according to requirements. Figure 3B , it can be clearly seen that the winding of the first part P1 disposed on the conductive layer C1 has an end point N1 and an end point N2, and the end point N1 is used to couple the previous embodiment (such as Figure 1 , 2 ) shown in the I / O pad 11, the terminal N2 is connected to the Figure 3C The vias V1 and V2 are coupled to Figure 3D The first portion P1 shown is a winding disposed on the conductive layer C2. Figure 3D , it can be clearly seen that the winding of the first part P1 disposed on the conductive layer C2 has an end point N3, and the end point N3 is Figure 3C The vias V1 and V2 are coupled to Figure 3B The first portion P1 shown is a winding disposed on the conductive layer C1. The second portion P2 and the third portion P3 are extensions of the inductor L1. The first portion P1, the second portion P2 and the third portion P3 of the inductor L1 are connected on the conductive layer C2, and the third portion P3 has a terminal N4 for coupling to the circuit 14. Based on the above configuration, the I / O pad 11 is coupled to the inductor L1 through the conductive layer C1, and the inductor L1 is coupled to the previous embodiment (such as Figure 1 , 2 ) shown in the circuit 14.

[0017] In this embodiment, according to the winding direction of the inductor L1 winding, when a signal enters the inductor L1 from the terminal N1 in the form of a positive current and leaves the inductor L1 from the terminal N4, a magnetic field with a Z direction (a direction passing through the drawing) is generated at the magnetic field center axis H1 of the inductor L1.

[0018] Similarly, Figure 4A FIG. 4 shows a layout diagram of the windings of the complete inductor L2 on the conductive layer C1 and the conductive layer C2 (shown in an overlapping manner); Figure 4B Only the layout diagram of the winding of the inductor L2 on the conductive layer C1 is shown; Figure 4C Only the layout diagram of the via holes of the inductor L2 on the connection layer CV is shown, and the connection layer CV is between the conductive layers C1 and C2; Figure 4D Only the layout diagram of the winding of the inductor L2 on the conductive layer C2 is shown.

[0019] Please refer to Figure 4A to Figure 4D , the inductor L2 includes a fourth part P4, a fifth part P5 and a sixth part P6. The fourth part P4 is the main coil part of the inductor L2, which is arranged in the winding of the conductive layer C1. Figure 4B As shown, and the winding arranged in the conductive layer C2 is as shown Figure 4D The fifth part P5 and the sixth part P6 are provided with a conductive layer C1. Figure 4B The conductive layer C1 is coupled to the conductive layer C2 through the connection layer CV. In this embodiment, the winding of the inductor L2 disposed on the conductive layer C1 and the winding of the inductor L2 disposed on the conductive layer C2 are connected to each other through the vias V3 and V4 on the connection layer CV.

[0020] The number of winding turns of the fourth portion P4 of the inductor L2 configured on the conductive layer C1 and the number of winding turns configured on the conductive layer C2 can be determined according to requirements. The fifth portion P5 and the sixth portion P6 are extensions of the inductor L2. Figure 4B , it can be clearly seen that the winding of the fourth part P4 disposed on the conductive layer C1 is connected to the fifth part P5 and the sixth part P6 on the conductive layer C1, and the sixth part P6 has an end point N5 for coupling to the previous embodiment (such as Figure 1 , 2 ) shown in the I / O pad 11, the fourth portion P4 further has a terminal N6, the terminal N6 is connected to the Figure 4C The vias V3 and V4 are coupled to Figure 4D The fourth portion P4 is shown as a winding disposed on the conductive layer C2. Figure 4D It can be clearly seen that the winding disposed on the conductive layer C2 in the fourth portion P4 has an end point N7 and an end point N8. The end point N7 is Figure 4C The vias V3 and V4 are coupled to Figure 4B The fourth portion P4 is disposed on the conductive layer C1, and the terminal N8 is coupled to the previous embodiment (such as Figure 1 , Figure 2 ) as shown in the circuit 13. Based on the above configuration, the I / O pad 11 is coupled to the inductor L2 through the conductive layer C1, and the inductor L2 is coupled to the circuit 13 through the conductive layer C2.

[0021] In this embodiment, according to the winding direction of the inductor L2 winding, when the signal enters the inductor L2 from the terminal N5 in the form of a positive current and leaves the inductor L2 from the terminal N8, a magnetic field with a -Z direction (a direction penetrating into the drawing) is generated at the magnetic field center axis H2 of the inductor L2.

[0022] Therefore, when referring to Figure 3A and Figure 4A It can be known that the first part P1, the second part P2 and the third part P3 surround the three sides of the fourth part P4, and the fourth part P4, the fifth part P5 and the sixth part P6 surround the three sides of the first part P1. Since the terminal N1 of the inductor L1 and the terminal N5 of the inductor L2 are both coupled to the I / O pad 11, in some embodiments, the terminal N1 and the terminal N5 can be a common point. The terminal N4 of the inductor L1 and the terminal N8 of the inductor L2 are adjacent to each other but electrically separated from each other.

[0023] Inductor L1 and inductor L2 receive signals at I / O pad 11. According to the winding direction of inductor L1 and inductor L2, the magnetic field generated by inductor L1 is opposite to the magnetic field generated by inductor L2. Generally speaking, high-frequency signals are input to the chip in the form of differential signals, such as Figure 2 For example, I / O pad 11 and I / O pad 12 are a differential pair, so the current I1 flowing into inductor L1 and inductor L2 and the current I2 flowing into inductor L3 and inductor L4 have opposite polarities. For example, current I1 is positive and current I2 is negative, so the following is caused: Figure 2 The indicated magnetic field directions, i.e., the magnetic field center axis H1 and the magnetic field center axis H4 generate a magnetic field in the Z direction; the magnetic field center axis H2 and the magnetic field center axis H3 generate a magnetic field in the -Z direction. In this way, the magnetic field generated by each inductor is opposite to the magnetic field generated by the adjacent inductor. For example, the magnetic field generated by inductor L1 is opposite to the magnetic field generated by the adjacent inductors L2 and L3, which helps to suppress magnetic field radiation to avoid interference with other electronic components. Therefore, there is no need to change the design of the peak inductance corresponding to the adjacent I / O pads in order to reduce electromagnetic waves, and the basic unit of the semiconductor structure of the present application, i.e., inductors L1 and L2 (or inductors L3 and L4), can be completely replicated.

[0024] As mentioned above, in some embodiments, the size and structure of the I / O pad 11, the inductor L1, and the inductor L2 are substantially the same as the size and structure of the I / O pad 12, the inductor L3, and the inductor L4. Therefore, according to the detailed description of the inductor L1 and the inductor L2 in the above embodiments, the implementation of the inductor L3 and the inductor L4 should be understood by those skilled in the art, and will not be described in detail hereinafter.

[0025]

Explanation of symbols

[0026] 10: Semiconductor structure

[0027] 11: I / O pads

[0028] 12: I / O pads

[0029] 13: Circuit

[0030] 14: Circuit

[0031] L1: Inductor

[0032] L2: Inductor

[0033] L3: Inductor

[0034] L4: Inductor

[0035] W1: Width

[0036] W2: Width

[0037] W3: Width

[0038] H1: central axis of magnetic field

[0039] H2: central axis of magnetic field

[0040] H3: magnetic field center axis

[0041] H4: Magnetic field center axis

[0042] X: Direction

[0043] Y: direction

[0044] I1: Current

[0045] I2: Current

[0046] P1: Part

[0047] P2: Part

[0048] P3: Part

[0049] P4: Part

[0050] P5: Part

[0051] P6: Part

[0052] N1: Endpoint

[0053] N2: Endpoint

[0054] N3: Endpoint

[0055] N4: Endpoint

[0056] N5: Endpoint

[0057] N6: Endpoint

[0058] N7: Endpoint

[0059] N8: Endpoints

[0060] C1: Conductive layer

[0061] C2: Conductive layer

[0062] CV: Connection layer

[0063] V1: Via hole

[0064] V2: Via hole

[0065] V3: Via hole

[0066] V4: Via hole

Claims

1. A semiconductor structure comprising: substrate; First inductor; A second inductor, wherein the first inductor and the second inductor are alternately disposed on a first conductive layer and a second conductive layer on the substrate, and the second conductive layer is located between the first conductive layer and the substrate; and A first input-output pad is coupled to the first inductor and the second inductor. The first input-output pad, the magnetic field center axis of the first inductor, and the magnetic field center axis of the second inductor are sequentially arranged along a first direction.

2. The semiconductor structure of claim 1, wherein The direction of the magnetic field generated by the first inductor is opposite to the direction of the magnetic field generated by the second inductor. The first inductor, the second inductor and the first input-output pad have a first width, a second width and a third width in a second direction perpendicular to the first direction, respectively, and the first width and the second width are less than or equal to the third width, and The inductance value of the first inductor is different from the inductance value of the second inductor.

3. The semiconductor structure of claim 1 , further comprising: A first circuit coupled to the first inductor; as well as The second circuit is coupled to the second inductor.

4. The semiconductor structure of claim 1, wherein The first input-output pad is coupled to the first inductor and the second inductor through the first conductive layer, and The first conductive layer includes aluminum, and the second conductive layer includes copper.

5. The semiconductor structure of claim 1, further comprising: The third inductor; Fourth inductor; and The second input-output pad is coupled to the third inductor and the fourth inductor. wherein the third inductor is the same as the first inductor, the fourth inductor is the same as the second inductor, and the third inductor and the fourth inductor are adjacent to the first inductor and the second inductor respectively, and The second input-output pad, the magnetic field center axis of the third inductor, and the magnetic field center axis of the fourth inductor are sequentially arranged along the first direction.

6. A semiconductor structure comprising: substrate; A first inductor having a first portion, a second portion and a third portion, wherein the first portion is disposed on the first conductive layer and the second conductive layer of the semiconductor structure, the second portion and the third portion are disposed on the second conductive layer, and the second conductive layer is located between the substrate and the first conductive layer; and The second inductor has a fourth portion, a fifth portion and a sixth portion, the fourth portion is disposed on the first conductive layer and the second conductive layer, and the fifth portion and the sixth portion are disposed on the first conductive layer. The first part, the second part and the third part surround the fourth part, and the fourth part, the fifth part and the sixth part surround the first part.

7. The semiconductor structure as claimed in claim 6, wherein a first terminal of the first inductor is coupled to a second terminal of the second inductor, and the semiconductor structure further comprises: A first input / output pad is coupled to the first terminal and the second terminal. The width of the first inductor and the width of the second inductor are smaller than or equal to the width of the first input / output pad.

8. The semiconductor structure as described in claim 7, wherein the first terminal and the second terminal are arranged in the first conductive layer, wherein the third terminal of the first inductor is located on the other side relative to the first terminal, and the fourth terminal of the second inductor is located on the other side relative to the second terminal, and the third terminal and the fourth terminal are arranged in the second conductive layer.

9. The semiconductor structure of claim 7, further comprising: The third inductor; Fourth inductor; and The second input-output pad is coupled to the third inductor and the fourth inductor. The first input / output pad, the first inductor, the second inductor, the second input / output pad, the third inductor, and the fourth inductor are arranged side by side, and The first inductor and the fourth inductor generate a first magnetic field direction, and the second inductor and the third inductor generate a second magnetic field direction opposite to the first magnetic field direction.

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