Multilayer stacked high bandwidth memory package structure and packaging method

Abstract

The application provides a multilayer stacked high-width-band memory package structure and a packaging method, the package structure comprising a substrate, a plastic package layer and a plurality of first memory chips, the substrate being provided with a plurality of first conductive vias, the plurality of first memory chips being provided with a plurality of second conductive vias electrically connected with the first conductive vias; the surface of the first memory chip facing the substrate is provided with a first conductive bump and a second conductive bump in sequence at the position corresponding to the second conductive via, and the surface of the first memory chip away from the substrate is provided with a first pad at the position corresponding to the second conductive via; the second conductive bump and the first pad of every two adjacent layers of the first memory chips are nested and connected, so that the plurality of first memory chips are insulated and stacked on the substrate; and the plastic package layer wraps the plurality of first memory chips and the substrate. The second conductive bump and the first pad are nested, the deformation of the second conductive bump can be reduced, the interval of the second conductive bump can be reduced, and the interconnection of ultra-fine interval is realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor packaging, and particularly relates to a multi-layer stacked high-bandwidth memory packaging structure and a packaging method. BACKGROUND

[0002] With the development of cloud computing and mobile interconnection, the demand for servers such as data centers has increased sharply. High-end servers require high-capacity, high-bandwidth and low-power memory devices. In order to meet this demand, companies have successively launched multi-layer stacked memory packaging products based on three-dimensional stacking technology. As shown in the figure, the multi-layer stacked memory packaging stack structure uses a through silicon via 2 to vertically interconnect a plurality of memory chips 1, a plurality of memory chips 1 are welded together through a bump 3, the memory chips 1 are stacked on a substrate 4, there is a non-conductive adhesive 5 between the chips, the entire memory chip structure is protected by a plastic encapsulation layer 6, and finally the package is connected to the outside by solder balls 7. Due to the high density and short vertical interconnection distance of the through silicon via 2, the data transmission speed is greatly improved. Figure 1

[0003] Currently, the multi-layer stacked memory multi-chip stack uses a thermal compression bonding (TCB) process, which connects the bump 3 to the chip back pad 8 by rapidly heating, and the chip back pad 8 is connected to the through silicon via 2 of the chip. The composition of the bump is mainly copper-tin structure, and the main composition of the chip back pad is nickel-gold structure. The final stacked structure is protected by the plastic encapsulation layer 6.

[0004] In the case of using copper-tin bumps, due to the deformation of tin during reflow, in order to prevent short circuit between the bumps, the spacing between the bumps 3 and the height of the tin need to be strictly controlled.

[0005] Currently, the spacing is more than 40um, when the spacing is reduced to less than 25um, due to the small amount of tin, it is fully converted to intermetallic compound under thermal load conditions, resulting in reliability failure.

[0006] In order to improve the storage capacity and data throughput speed, it is necessary to increase the number of chip stacks and the number of pins, but in the current micro-bump mechanism, due to the limitation of bump height and spacing, there is limited space for continuous improvement. To solve this problem, multi-chip stacking technology based on hybrid bonding is currently being developed, but hybrid bonding requires high-precision chemical mechanical polishing process, which is high in cost, and hybrid bonding requires high surface flatness of the chip, which is difficult to control the yield rate in actual production.

[0007] In view of the above problems, it is necessary to propose a multi-layer stacked high-bandwidth memory packaging structure and a packaging method which is reasonable in design and can effectively solve the above problems. SUMMARY ​

[0008] The present application aims to at least solve one of the technical problems existing in the prior art, and provide a multi-layer stacked high-width-band memory packaging structure and a packaging method.

[0009] An aspect of the present application provides a multi-layer stacked high-width-band memory packaging structure, which comprises a substrate, a plastic packaging layer and a plurality of first memory chips, wherein the substrate is provided with a plurality of first conductive vias, and the plurality of first memory chips are provided with a plurality of second conductive vias electrically connected with the first conductive vias.

[0010] The first memory chip is provided with a first conductive bump and a second conductive bump in sequence at a position corresponding to the second conductive via on a surface of the first memory chip facing the substrate, and is provided with a first pad at a position corresponding to the second conductive via on a surface of the first memory chip away from the substrate.

[0011] The second conductive bump and the first pad of every two adjacent layers of the first memory chips are nestedly connected, so that the plurality of first memory chips are insulated and stacked on the substrate.

[0012] The plastic packaging layer wraps the plurality of first memory chips and the substrate.

[0013] Optionally, a protrusion is arranged on a side of the first pad facing the second conductive bump, and a groove is arranged on a side of the second conductive bump facing the first pad, and the protrusion is inserted into the groove.

[0014] Optionally, the second conductive bump is in a columnar structure.

[0015] Optionally, a first passivation layer and a first dielectric layer are arranged in sequence on a surface of the first memory chip facing the substrate, and the first conductive bump is arranged above the first passivation layer and the first dielectric layer.

[0016] A second passivation layer is arranged on a surface of the first memory chip away from the substrate, and the first pad is arranged on the second passivation layer.

[0017] Optionally, a second pad is arranged on a surface of the substrate facing the first memory chip, and the second pad is nestedly connected with the second conductive bump on the first memory chip close to the substrate.

[0018] Optionally, plastic packaging material is filled between every two adjacent layers of the first memory chips and between the first memory chips and the substrate, and the plastic packaging material wraps the first pad, the second pad, the first conductive bump and the second conductive bump.

[0019] Optionally, the packaging structure is further provided with solder balls, the solder balls are arranged on the surface of the substrate away from the first memory chip, and the solder balls are electrically connected with the first conductive vias.

[0020] Optionally, the first conductive via and the second conductive via are both through silicon vias.

[0021] Optionally, the material of the second conductive bump is metal tin material.

[0022] Another aspect of the present application provides a multilayer stacked high bandwidth memory packaging method, the multilayer stacked high bandwidth memory packaging structure is the packaging structure described above, and the method comprises:

[0023] providing a substrate and a plurality of first memory chips, the substrate is provided with a plurality of first conductive vias, and the plurality of first memory chips are provided with a plurality of second conductive vias electrically connected with the first conductive vias;

[0024] forming a first conductive bump and a second conductive bump in sequence at the position corresponding to the second conductive via on the surface of the first memory chip facing the substrate;

[0025] forming a first pad at the position corresponding to the second conductive via on the surface of the first memory chip away from the substrate;

[0026] nesting the second conductive bump and the first pad of every adjacent two first memory chips by a hot-press welding process, so as to stack the plurality of first memory chips in sequence on the substrate;

[0027] reflow soldering the plurality of first memory chips and the substrate after the stacking is completed by a reflow soldering process;

[0028] forming a plastic encapsulation layer, the plastic encapsulation layer wrapping the plurality of first memory chips and the substrate.

[0029] The multilayer stacked high bandwidth memory packaging structure and packaging method of the present application, the first conductive bump and the second conductive bump are arranged in sequence at the position corresponding to the second conductive via on the first surface of the first memory chip facing the substrate, and the first pad is arranged at the position corresponding to the second conductive via on the second surface of the first memory chip away from the substrate; the second conductive bump and the first pad of every adjacent two first memory chips are nested and connected, so that the plurality of first memory chips are stacked in sequence on the substrate. The packaging structure of the present application can reduce the deformation of the second conductive bump by nesting the second conductive bump and the first pad, so as to reduce the interval of the second conductive bump, i.e. the interval between the first memory chips, and realize the interconnection of ultra-fine pitch. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A structural schematic diagram of a multi-layer stacked high bandwidth memory package structure in the prior art;

[0031] Figure 2 A structural schematic diagram of a multi-layer stacked high bandwidth memory package structure in an embodiment of the present application;

[0032] Figure 3 A structural schematic diagram of a structure in which a second conductive bump and a first pad are nested in another embodiment of the present application;

[0033] Figure 4 A structural schematic diagram of a first pad in another embodiment of the present application;

[0034] Figure 5 A flowchart of a multi-layer stacked high bandwidth memory packaging method in another embodiment of the present application;

[0035] Figures 6 to 13 A packaging process schematic diagram of a multi-layer stacked high bandwidth memory package structure in another embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0037] As shown in Figure 2 An aspect of the present application provides a multi-layer stacked high bandwidth memory package structure 100, which comprises a substrate 110, a plastic encapsulation layer 140 and a plurality of first memory chips 120. The substrate 110 is provided with a plurality of first conductive vias 111, and the first memory chip 120 is provided with a plurality of second conductive vias 130. The first conductive vias 111 and the second conductive vias 130 can both be through silicon vias. The vertical electrical interconnection of the through silicon vias is realized by using a through silicon via technology, thereby reducing the package height. In this embodiment, the cross-sectional size of the plurality of first conductive vias 111 on the substrate 110 is greater than the cross-sectional size of the plurality of second conductive vias 130 on the first memory chip 120. In this embodiment, the first memory chip 120 is a dynamic random access memory chip, and can also be other memory chips. The present embodiment is not limited in this regard.

[0038] The first memory chip 120 is provided with a first conductive bump 124 and a second conductive bump 125 in sequence at a position corresponding to the second conductive via 130 on the surface of the substrate 110, and the first memory chip 120 is provided with a first pad 127 at a position corresponding to the second conductive via 130 on the surface away from the substrate 110. It should be noted that in the embodiment, the material of the first conductive bump 124 can be copper, and the material of the second conductive bump 125 can be tin.

[0039] Further preferably, as shown in Figure 3 The second conductive bump 125 is in a columnar structure, that is, the tin bump is in a columnar structure, which can be a cylindrical structure or a prismatic structure, and the embodiment is not limited in particular. The original form of the second conductive bump 125 is in a columnar structure, which is different from the spherical form of the traditional conductive bump. In this way, the lateral width can be reduced under the same volume, and the form of the second conductive bump 125 can remain basically unchanged when being nested with the first pad 127. Therefore, the pitch of the second conductive bump 125 can be reduced, and the connection with a center distance of less than 20 um can be realized.

[0040] The second conductive bump 125 and the pad 127 of each adjacent two first memory chips 120 are nested and connected, so that the plurality of first memory chips 120 are insulated and stacked on the substrate 110.

[0041] It should be noted that the second conductive bump 125 and the first pad 127 of each adjacent two first memory chips 120 are nested and connected by a hot-press welding process, so that the plurality of first memory chips 120 are insulated and stacked on the substrate 110. The plurality of first memory chips 120 and the substrate 110 after being stacked are put into an acid reflow furnace for reflow. In an acid gas environment, the oxide of the second conductive bump 125, that is, the oxide of the tin bump, can be completely removed without melting. Since the second conductive bump 125 and the first pad 127 have been welded, the deformation of the second conductive bump 125, that is, the tin bump, is small during reflow in the acid reflow furnace, and the tin bump will not be shortened. During the entire reflow process, the tin bump can basically maintain the form without change under the action of the tension on the upper and lower surfaces. In this way, the pitch of the tin bump can be reduced, and the connection with a center distance of less than 20 um can be realized.

[0042] The plastic sealing layer 140 wraps the plurality of first memory chips 120 and the substrate 110. The plastic sealing method can be a film layer vacuum pressing or a traditional plastic sealing process, and the embodiment is not limited in particular. After the plastic sealing is completed, cutting is performed to form a final independent multi-layer stacked high-width-band memory package structure.

[0043] Exemplarily, as shown in Figure 3 andFigure 4 As shown, the first pad 127 is provided with a protrusion 127a on the side facing the second conductive bump 125, and the second conductive bump 125 is provided with a groove 125a on the side facing the first pad 127, and the protrusion 127a is inserted into the groove 125a, that is, the protrusion 127a in the second conductive bump 125 and the groove 125a on the pad 127 are nested and connected. As shown in the figure, Figure 4 As shown, the size of the protrusion 127a is generally 3um-5um, and the height of the protrusion 127a is 5um or less. In this embodiment, the protrusion 127a is a square prism, that is, the cross section is a square, and the cross section of the protrusion 127a can also be other shapes, which can be selected according to actual needs.

[0044] As shown, Figure 2 As shown, the first memory chip 120 is provided with a first passivation layer 121 and a first dielectric layer 122 in sequence on the surface facing the substrate 110, and the first conductive bump 124 is arranged on the first passivation layer 121 and the first dielectric layer 122. The first memory chip 120 is provided with a second passivation layer 126 on the side facing away from the substrate 110, and the first pad 127 is arranged on the second passivation layer 126.

[0045] Specifically, the first memory chip 120 is provided with a first passivation layer 121 and a first dielectric layer 122 in sequence on the surface facing the substrate 110, and then the first passivation layer 121 and the first dielectric layer 122 are patterned to form a plurality of openings, and the first conductive bump 124 is arranged at the opening, and the second conductive bump 125 is arranged on the conductive bump 124. Similarly, the second passivation layer 126 is patterned to form a plurality of openings, and the first pad 127 is arranged at the plurality of openings.

[0046] It should be noted that in this embodiment, the first passivation layer 121 and the second passivation layer 126 can both be silicon dioxide material, or other materials that can play a passivation role, which is not limited in this embodiment. The first pad 127 in this embodiment is made of copper material, and the first conductive bump 124 is also made of copper material.

[0047] As shown, Figure 2As shown, the surface of the substrate 110 facing the first memory chip 120 is provided with a second pad 112, which is nestedly connected with the second conductive bump 127 on the first memory chip 120 close to the substrate 110. In this embodiment, the second pad 112 is a pad of the same structure as the first pad 127, and is also provided with a bump, which is nestedly connected with the second conductive bump 127. The substrate 110 and the first memory chip 120 are also nestedly connected through the second pad 112 and the second conductive bump 127, so that the deformation of the second conductive bump 127 can be reduced during packaging, the pitch of the second conductive bump 127 is reduced, that is, the pitch between the substrate 110 and the first memory chip 120 is reduced, and the connection of 20 um center distance is further realized.

[0048] It should be noted that the topmost chip can be the first memory chip 120 or other chips. In this embodiment, the topmost chip is also the first memory chip 120. The thickness of the topmost first memory chip 120 is thicker than that of other layers of first memory chips 120, which mainly protects the plurality of first memory chips 120 of other layers. Therefore, the topmost first memory chip 120 is not provided with a conductive via. Moreover, the topmost first memory chip 120 is only provided with the first conductive bump 124 and the second conductive bump 125 facing the surface of the substrate 110, and the first conductive bump 124 and the second conductive bump 125 are nestedly connected with the first pad 127 on the first memory chip 120 of the adjacent layer.

[0049] As shown in the figure, Figure 2 As shown, the plastic encapsulating material is filled between every two adjacent layers of first memory chips 120 and between the first memory chip 120 and the substrate 110, and the plastic encapsulating material wraps the first pad 127, the second pad 112, the first conductive bump 124 and the second conductive bump 125. By using the plastic encapsulating material to replace the existing non-conductive glue filled between the substrate and the first memory chip and between the upper and lower two layers of first memory chips, the short circuit between the pad and the second conductive bump is prevented. Since the plastic encapsulating material is relatively low in price compared with the non-conductive glue, the production cost is saved.

[0050] As shown in the figure, Figure 2 As shown, the packaging structure 100 is also provided with a solder ball 150, which is arranged on the surface of the substrate 110 away from the first memory chip 120, and the solder ball 150 is electrically connected with the first conductive via 111. The packaging structure 100 is electrically connected with the outside through the solder ball 150.

[0051] As shown in the figure, Figure 5 As shown, one aspect of the present application provides a multi-layer stacked high-width-band memory packaging method S100, which comprises:

[0052] S110, providing a substrate and a plurality of first memory chips, the substrate being provided with a plurality of first conductive vias, the plurality of first memory chips being provided with a plurality of second conductive vias electrically connected with the first conductive vias.

[0053] Specifically, as shown in Figure 11 , Figure 11 and Figure 13 , a substrate 110 and a plurality of first memory chips 120 are provided, the substrate 110 is provided with a plurality of first conductive vias 111, and the first memory chips 120 are provided with a plurality of second conductive vias 130, wherein the first conductive vias 111 and the second conductive vias 130 can both be through silicon vias, vertical electrical interconnection of the through silicon vias is achieved by using a through silicon via technology, and the packaging height is reduced. In the embodiment, the cross-sectional size of the plurality of first conductive vias 111 on the substrate 110 is greater than the cross-sectional size of the plurality of second conductive vias 130 on the first memory chips 120. In the embodiment, the first memory chips 120 are dynamic random access memory chips, and can also be other memory chips, and the embodiment is not limited in particular.

[0054] S120, sequentially forming a first conductive bump and a second conductive bump at a position corresponding to the second conductive via on a surface of the first memory chip facing the substrate;

[0055] Specifically, step S120 includes the following steps.

[0056] First, sequentially forming a first passivation layer and a first dielectric layer on a surface of the first memory chip facing the substrate.

[0057] As shown in Figure 6 , a first passivation layer 121 and a first dielectric layer 122 are sequentially coated on a surface of the first memory chip 120 facing the substrate 110, that is, the front surface of the first memory chip 120, wherein the material of the first passivation layer 121 can be silicon dioxide, and the material of the first dielectric layer 122 can be polyimide (PI), polybenzoxazole (PBO), etc., and in the embodiment, the material of the first dielectric layer 122 is polyimide (PI). The coating method is usually wafer spin coating, and the embodiment is not limited in particular.

[0058] Second, forming a photoresist layer on the first dielectric layer, and patterning the photoresist layer to form a plurality of first openings corresponding to the plurality of conductive vias.

[0059] Specifically, as shown in Figure 6As shown, a photoresist layer 123 is coated on the surface of the first dielectric layer 122. The photoresist layer 123 is patterned by exposure and development to form a plurality of first openings (not shown in the figure), wherein the plurality of first openings correspond to a plurality of second conductive vias 130 on the first memory chip 120.

[0060] Furthermore, the first conductive bump and the second conductive bump are sequentially formed at the plurality of first openings.

[0061] Specifically, such as Figure 6 As shown, a first conductive bump 124 and a second conductive bump 125 are sequentially formed at multiple first openings through an electroplating process. The first conductive bump 124 and the second conductive bump 125 are electrically connected to the second conductive via 130. In this embodiment, the first conductive bump 124 can be made of copper, and the second conductive bump 125 can be made of tin. Using tin for the second conductive bump 125 can keep the packaging cost at a low level.

[0062] Finally, the photoresist layer is removed.

[0063] For example, the surface of the second conductive bump protrudes beyond the surface of the photoresist layer; before removing the photoresist layer, the method further includes:

[0064] The second conductive bump is ground so that the surface of the second conductive bump is flush with the surface of the photoresist layer.

[0065] Specifically, when first conductive bumps 124 and second conductive bumps 125 are sequentially formed at multiple first openings through an electroplating process, the surface of the second conductive bump 125 protrudes from the surface of the photoresist layer 123. At this time, before removing the photoresist layer 123, the surface of the second conductive bump 125 needs to be ground to make the height of the second conductive bump 125 the same as the height of the photoresist layer 123. Figure 7 As shown, this means that the second conductive bump 125 is made into a columnar structure, which can be either a cylindrical structure or a prismatic structure. The original shape of the second conductive bump 125 is a columnar structure, unlike the spherical shape of traditional conductive bumps, which reduces the lateral width within the same volume. Figure 8 As shown, the surface of the second conductive bump 125 is ground so that the height of the second conductive bump 125 is the same as the height of the photoresist layer 123, and then the photoresist 123 is removed.

[0066] S130. A first pad is formed on the surface of the first memory chip away from the substrate at the position corresponding to the second conductive via.

[0067] It should be noted that when the thickness of the first memory chip 120 is very thin and the plurality of second conductive vias 130 can be exposed, the first memory chip 120 does not need to be thinned, but in the embodiment, as shown in Figure 9 the first memory chip 120 needs to be thinned first to expose the second conductive vias 130 on the first memory chip 120.

[0068] Specifically, step S130 includes the following steps.

[0069] First, the surface of the first memory chip away from the substrate is thinned.

[0070] Specifically, as shown in Figure 9 the surface of the first memory chip 120 away from the substrate 110, that is, the back surface of the first memory chip 120, is thinned to expose the plurality of second conductive vias 130 on the back surface of the first memory chip 120. The thinning can be performed by grinding or other methods, which are not limited in the embodiment.

[0071] Second, a second passivation layer is formed on the surface of the first memory chip away from the substrate, and the second passivation layer is patterned to form a plurality of second openings corresponding to the plurality of conductive vias.

[0072] Specifically, as shown in Figure 10 a back surface via process is performed on the back surface of the thinned first memory chip 120 to form a second passivation layer 126, and a photolithography process is performed on the second passivation layer 126 to form a plurality of second openings (not labeled in the figure), wherein the plurality of second openings are arranged corresponding to the plurality of second conductive vias 130. In the embodiment, the material of the second passivation layer 126 can be silicon dioxide or other materials that can play a passivation role, which are not limited in the embodiment.

[0073] Finally, the first pads are formed at the plurality of second openings.

[0074] Specifically, as shown in Figure 10 the first pads 127 are formed at the plurality of second openings by an electroplating process. The shape of the first pads 127 is generally circular or square, as shown in Figure 3 and Figure 4 In the embodiment, the first pads 127 are copper pads, and the first pads 127 have a cylindrical structure. The material of the first pads 127 can be selected according to actual needs, which are not limited in the embodiment.

[0075] S140, nesting the second conductive bump and the first pad of each two adjacent first memory chips by a thermal compression bonding process to sequentially insulate stack the plurality of first memory chips on the substrate.

[0076] Specifically, as shown in Figure 3 and Figure 11 the second conductive bump 125 and the first pad 127 of each two adjacent first memory chips 120 are nested by a thermal compression bonding process, and then, as shown in Figure 11 the plurality of first memory chips 120 are sequentially insulate stacked on the substrate 110 by a thermal compression bonding process. When the plurality of first memory chips 120 are stacked to form a stacked module, the plurality of first memory chips 120 should be stacked to form a plurality of stacked modules, so it is necessary to first separate the plurality of stacked modules to form independent first memory chip 120 stacked modules, and then stack the plurality of independent first memory chip stacked modules on the substrate 110 by a thermal compression bonding process.

[0077] For example, the nesting the second conductive bump and the first pad of each two adjacent first memory chips by a thermal compression bonding process comprises:

[0078] Specifically, a photoresist layer is coated on the first pad 127, and a photoetching and etching process is used to pattern the first pad 127 to form a protrusion 127a in the central region of the first pad 127. The size of the protrusion 127a is generally 3-5 um, and the height of the protrusion 127a is less than 5 um. In this embodiment, the protrusion 127a is a square prism.

[0079] Secondly, the protrusion of each two adjacent first memory chips is pressed into the second conductive bump by a thermal compression bonding process.

[0080] Specifically, as shown in Figure 3 the protrusion 127a is formed on the first pad 127, and the protrusion 127a of each two adjacent first memory chips 120 is pressed into the second conductive bump 125 by a thermal compression bonding process.

[0081] For example, the melting point of the first conductive bump 124 is greater than the melting point of the second conductive bump 125, and the temperature of the thermal compression bonding process is less than the melting point of the second conductive bump 125.

[0082] Specifically, the temperature of the heat pressing welding process is lower than the melting point of the second conductive bump 125, in this embodiment, since the second conductive bump 127 is a tin bump, it is generally set to 180-210℃, which can ensure the low modulus of the tin bump, so that the bump 127a is embedded in the tin bump, and the two adjacent first memory chips 120 are fixed, while the shape of the tin bump remains basically unchanged.

[0083] It should be noted that the surface of the substrate 110 facing the first memory chip 120 is provided with a second pad 112, which is nestedly connected with the second conductive bump 127 on the first memory chip 120 close to the substrate 110. In this embodiment, the second pad 112 is a pad with the same structure as the first pad 127, which is also provided with a bump nestedly connected with the second conductive bump 127. The nested connection between the substrate 110 and the first memory chip 120 is also achieved through the second pad 112 and the second conductive bump 127, so that the deformation of the second conductive bump 127 can be reduced during packaging, the pitch of the second conductive bump 127 can be reduced, that is, the pitch between the substrate 110 and the first memory chip 120 can be reduced, and the connection with a center distance of less than 20um can be further achieved.

[0084] S150, reflow soldering the stacked first memory chips and the substrate through a reflow soldering process.

[0085] For example, the reflow soldering of the stacked first memory chips and the substrate through a reflow soldering process includes:

[0086] In an acidic gas environment, the stacked first memory chips and the substrate are reflow soldered through a reflow soldering process.

[0087] Specifically, the stacked first memory chips 120 and the substrate 110 are put into an acidic reflow furnace for reflow. In an acidic gas environment, the oxide of the second conductive bump 125, that is, the oxide of the tin bump, can be completely removed without melting. Since the second conductive bump 125 and the first pad 127 have been soldered, the deformation of the second conductive bump 125, that is, the tin bump, is small during reflow in the acidic reflow furnace, and the tin bump will not be shortened. During the entire reflow process, the second conductive bump 125 can basically maintain the columnar shape under the action of the tension on the upper and lower surfaces, so that the pitch of the tin bump can be reduced, and the connection with a center distance of less than 20um can be achieved.

[0088] It should be noted that the acidic gas can be carbon dioxide, chlorine, hydrogen sulfide, hydrogen chloride, sulfur dioxide, etc., which is not limited in this embodiment.

[0089] S160. A molding layer is formed, wherein the molding layer encapsulates the plurality of first memory chips and the substrate.

[0090] like Figure 12 As shown, multiple first memory chips 120 and substrate 110 that have completed reflow soldering are encapsulated using molding compound to form a molding layer 140, resulting in a memory chip package. The package is then cut to form a high-bandwidth memory package. The molding method can be vacuum lamination or a traditional molding process; this embodiment does not specify a particular method.

[0091] For example, such as Figure 12 As shown, during the formation of the molding compound 140, molding compound is filled between the plurality of first memory chips 120 and between the first memory chips 120 and the substrate 110. The molding compound encapsulates the first pad 127, the second pad 115, the first conductive bump 124, and the second conductive bump 125. By using molding compound instead of existing non-conductive adhesive to fill the space between the buffer and the first memory chips, and between adjacent first memory chips, short circuits between the pads and the second conductive bumps are prevented. Since molding compound is cheaper than non-conductive adhesive, production costs are saved.

[0092] For example, such as Figure 13 As shown, after forming the encapsulation layer 140, solder balls 150 are formed on the surface of the substrate 110 opposite to the first memory chip 110. The solder balls 150 correspond to and are electrically connected to the first conductive via. The encapsulation structure 100 is electrically connected to the outside world through the solder balls 150. After forming the solder balls 150, they are cut to form the final independent multilayer stacked high-bandwidth memory encapsulation structure.

[0093] This invention discloses a multilayer stacked high-bandwidth memory packaging method. This method uses a thermoforming process to nest the second conductive bumps and first pads of every two adjacent first memory chips, thereby sequentially and insulatedly stacking multiple first memory chips on a substrate. A reflow soldering process is then used to reflow solder the stacked first memory chips and the substrate, forming a molding compound that encapsulates the multiple first memory chips and the substrate. This invention, through a two-step soldering process, nests the second conductive bumps and first pads, reducing deformation of the second conductive bumps. This reduces the spacing between the second conductive bumps, thereby reducing the distance between the first memory chips and achieving interconnections with a center-to-center distance of less than 20µm.

[0094] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A multi-layer stacked high-bandwidth memory packaging structure, characterized in that, The packaging structure includes a substrate, a molding layer, and a plurality of first memory chips, wherein the substrate is provided with a plurality of first conductive vias, and the plurality of first memory chips are provided with a plurality of second conductive vias electrically connected to the first conductive vias; At the location of the second conductive via on the surface of the first memory chip facing the substrate, a first conductive bump and a second conductive bump are sequentially disposed. At the location of the second conductive via on the surface of the first memory chip facing away from the substrate, a first pad is disposed. The second conductive bump has a columnar structure. The second conductive bumps and the first pads of each two adjacent layers of the first memory chips are nested and connected by a thermo-press welding process to reduce the deformation of the second conductive bumps and achieve ultra-fine pitch interconnection, so that the plurality of first memory chips are stacked insulatedly on the substrate; wherein, the melting point of the first conductive bump is greater than the melting point of the second conductive bump, and the temperature of the thermo-press welding process is less than the melting point of the second conductive bump. In an acidic gas environment, the plurality of first memory chips are insulatedly stacked on the substrate by a reflow soldering process. The molding compound encapsulates the plurality of first memory chips and the substrate.

2. The packaging structure according to claim 1, characterized in that, The first pad has a protrusion on the side facing the second conductive bump, and the second conductive bump has a groove on the side facing the first pad, with the protrusion inserted into the groove.

3. The packaging structure according to claim 1, characterized in that, The first memory chip is further provided with a first passivation layer and a first dielectric layer on the side facing the substrate, and the first conductive bump is disposed on the first passivation layer and the first dielectric layer. The first memory chip has a second passivation layer on the side facing away from the substrate, and the first pad is disposed on the second passivation layer.

4. The packaging structure according to claim 3, characterized in that, The substrate has a second pad on its surface facing the first memory chip, and the second pad is nested and connected to a second conductive bump on the first memory chip near the substrate.

5. The packaging structure according to claim 4, characterized in that, A molding compound is filled between each pair of adjacent first memory chips and between the first memory chip and the substrate. The molding compound encapsulates the first pad, the second pad, the first conductive bump, and the second conductive bump.

6. The packaging structure according to any one of claims 1 to 5, characterized in that, The packaging structure is further provided with solder balls, which are disposed on the surface of the substrate opposite to the first memory chip, and the solder balls are electrically connected to the first conductive via.

7. The packaging structure according to any one of claims 1 to 5, characterized in that, Both the first conductive via and the second conductive via are through-silicon vias.

8. The packaging structure according to any one of claims 1 to 5, characterized in that, The second conductive bump is made of tin.

9. A method for packaging multi-layer stacked high-bandwidth memory, characterized in that, The multi-layer stacked high-bandwidth memory packaging structure is the packaging structure according to any one of claims 1 to 8, and the method includes: A substrate and a plurality of first memory chips are provided. The substrate is provided with a plurality of first conductive vias, and the plurality of first memory chips are provided with a plurality of second conductive vias electrically connected to the first conductive vias. At the location corresponding to the second conductive via on the surface of the first memory chip facing the substrate, a first conductive bump and a second conductive bump are sequentially formed; wherein, the second conductive bump has a columnar structure; A first pad is formed on the surface of the first memory chip facing away from the substrate at the location corresponding to the second conductive via. By using a thermocompression welding process, the second conductive bumps and the first pads of every two adjacent first memory chips are nested together to reduce the deformation of the second conductive bumps and achieve ultra-fine pitch interconnection, so as to sequentially and insulately stack the plurality of first memory chips on the substrate; wherein, the melting point of the first conductive bump is greater than the melting point of the second conductive bump, and the temperature of the thermocompression welding process is less than the melting point of the second conductive bump. In an acidic gas environment, the stacked first memory chips and the substrate are reflow soldered using a reflow soldering process. A molding compound is formed, which encapsulates the plurality of first memory chips and the substrate.

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