Semiconductor structure, three-dimensional memory and preparation method thereof

Abstract

The present application provides a semiconductor structure, a three-dimensional memory and a preparation method thereof, the method comprising: forming a stacked structure on a substrate, and forming a first trench penetrating the stacked structure and extending into the substrate; forming a first insulating layer, a sacrificial layer, and a second insulating layer in sequence on the inner surface of the first trench; forming a second trench penetrating the second insulating layer and exposing the sacrificial layer; removing the sacrificial layer, and filling a conductive layer in a gap formed by removing the sacrificial layer; and filling the second trench with an insulating material.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and manufacturing, and more specifically, to semiconductor structures, three-dimensional memory structures, and methods for preparing the same. Background Art

[0002] 3D memory typically consists of a memory array consisting of multiple layers of vertically stacked data storage cells, and a sealing structure surrounding the memory array, such as a seal ring (SR). The seal ring protects the memory array from shear stress generated during the packaging process, as well as the effects of external moisture on the memory array during manufacturing and use. It also provides electrostatic protection for the memory array. In short, the seal ring plays a crucial role in ensuring the reliability of 3D memory and is an indispensable structure for 3D memory.

[0003] In related art, a sealing ring is prepared based on a traditional step structure, wherein a sealing area located near the step area is formed while forming an insulating layer on the step structure, and a sealing ring is formed by etching the insulating layer in the sealing area and filling it with a conductive material.

[0004] Traditional staircase structures are formed by performing multiple trim-etch and chop cycles on the stacked structure. However, with the advent of the big data era, memory chip capacity requirements are increasing, and the number of vertically stacked memory cell layers in three-dimensional memory is increasing. This makes the manufacturing process of traditional staircase structures increasingly difficult. A new staircase contact (SCT) architecture has been proposed in the field of three-dimensional memory, and a new sealing ring fabrication method based on this staircase contact architecture is needed. Summary of the Invention

[0005] On the one hand, an embodiment of the present application provides a method for preparing a three-dimensional memory, the method comprising: forming a stacked structure on a substrate, and forming a first trench that penetrates the stacked structure and extends into the substrate; forming a first insulating layer, a sacrificial layer, and a second insulating layer in sequence on the inner surface of the first trench; forming a second trench that penetrates the second insulating layer and exposes the sacrificial layer; removing the sacrificial layer, and filling a conductive layer in the gap formed by removing the sacrificial layer; and filling the second trench with an insulating material.

[0006] In one embodiment, the steps of sequentially forming a first insulating layer, a sacrificial layer, and a second insulating layer on the inner surface of the first trench include: forming the first insulating layer on the inner surface of the first trench; removing the bottom portion of the first insulating layer covering the substrate to expose the substrate; forming the sacrificial layer on the first insulating layer and the exposed substrate; and filling the remaining space of the first trench with the second insulating layer.

[0007] In one embodiment, removing the sacrificial layer includes removing the sacrificial layer through the second trench.

[0008] In one embodiment, the gap includes a first gap and a second gap extending along the stacking direction of the stacked structure, and there is a gap between the first gap and the second gap, wherein filling the gap formed by removing the sacrificial layer with a conductive layer also includes: removing the portion of the conductive layer located outside the first gap and the second gap.

[0009] In one embodiment, the stacked structure includes alternately stacked gate sacrificial layers and dielectric layers, and the gate sacrificial layers are made of the same material as the sacrificial layer.

[0010] In one embodiment, a cross section of the first trench, the first insulating layer, the sacrificial layer, the second insulating layer, the second trench, and the conductive layer in a direction parallel to the substrate is arranged in a ring shape.

[0011] On the other hand, an embodiment of the present application provides a semiconductor structure, which includes a substrate; a stacked structure located on the substrate; and a sealing structure that penetrates the stacked structure and extends to the substrate, wherein the sealing structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer stacked in a direction perpendicular to the penetration direction, wherein the first conductive layer and the second conductive layer are the same, and the first insulating layer and the third insulating layer are the same.

[0012] In one embodiment, the sealing structure further includes a filling layer penetrating the second insulating layer.

[0013] In one embodiment, cross-sections of the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, and the third insulating layer in a direction parallel to the substrate are ring-shaped.

[0014] On the other hand, the present application also provides a three-dimensional memory, which includes the semiconductor structure as described above.

[0015] The method for preparing a three-dimensional memory provided in an embodiment of the present application is a new method for preparing a sealing ring based on a new step contact architecture. Compared with traditional methods for preparing three-dimensional memory, the method for preparing the three-dimensional memory of the present application has a simple process and a high chip yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0017] Figure 1 is a cross-sectional schematic diagram of a three-dimensional memory 10' of the related art;

[0018] Figure 2 is a flow chart of a method for preparing a three-dimensional memory according to an exemplary embodiment of the present application;

[0019] Figure 3 A top view schematically illustrating the distribution of the sealing area, step contact area, and core area of a three-dimensional memory;

[0020] Figures 4 to 21B is a process diagram of a method for preparing a three-dimensional memory according to an exemplary embodiment of the present application; and

[0021] Figure 22 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0022] For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features. Therefore, without departing from the teachings of this application, the first groove discussed below can also be referred to as the second groove, and vice versa.

[0024] In the accompanying drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The drawings are for illustration purposes only and are not drawn strictly to scale. For example, the thickness of the substrate and laminated structure are not to scale as would be used in actual production. As used herein, the terms "substantially," "approximately," and similar terms are intended to indicate approximations, not degrees, and are intended to account for the inherent variations in measured or calculated values that would be recognized by one of ordinary skill in the art.

[0025] It should also be understood that the terms "comprises," "including," "having," "includes," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than modifying the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplary" is intended to refer to an example or illustration.

[0026] Unless otherwise defined, all words used herein (including engineering terms and scientific and technological terms) have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that, unless otherwise specified in this application, words defined in commonly used dictionaries should be interpreted as having the same meaning as they do in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0027] It should be noted that, unless otherwise specified or inconsistent with the context, the embodiments and features of the embodiments in this application may be combined with each other. Furthermore, unless expressly limited or inconsistent with the context, the specific steps included in the methods described in this application are not necessarily limited to the order in which they are described, but may be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0028] Figure 1 1 is a cross-sectional diagram of a three-dimensional memory 10' in an embodiment. Figure 1As shown, a three-dimensional memory device 10' may include a substrate 10a and a stacked structure 20a formed on the substrate 10a. The stacked structure 20a includes dielectric layers 201a and gate layers 202a alternately stacked on the substrate 10a. Specifically, the structure of the three-dimensional memory device 10' may be functionally divided into a sealing region 101a, a step region 102a, and a core region 103a. As an example, the sealing region 101a may include multiple sealing rings 501a, which typically surround the step region 102a and the core region 103a. The step region 102a may include multiple conductive pillars 502a, each of which reaches a predetermined depth in the gate layer 202a and leads out of the gate layer 202a. The number of conductive pillars 502a is related to the number of gate layers 202a. The core region 103a may include multiple channel structures 402a for storing data. The core region 103a may further include a plurality of gate line slits 601a. The functions of the gate line slits 601a include but are not limited to providing a path for an etchant for replacing a sacrificial layer (not shown) in the stacked structure 20a with the gate layer 202a. Figure 1 Only two dielectric layers 201 a , two gate layers 202 a , two channel structures 402 a and one gate line gap 601 a are schematically shown in the figure, and the actual number is not limited thereto.

[0029] In one embodiment, the seal region 101a may include two seal rings 501a, wherein the cross-sectional contour of the seal rings 501a in a direction parallel to the substrate 10a may be a closed ring. The three-dimensional memory device 10' further includes an insulating layer 30a covering the portion of the stacked structure 20a located in the step region 102a and the surrounding area. Exemplarily, the insulating layer 30a and the dielectric layer 201a may be made of the same material. Within the insulating layer 30a, the seal rings 501a and the conductive pillars 502a may be fabricated together using the same process.

[0030] However, as the number of stacking layers increases, e.g. Figure 1 The traditional step region shown in the figure is becoming increasingly difficult to process. Currently, a new step contact architecture has been proposed in the field of 3D memory. Based on this step contact architecture, the seal ring, an essential and important structure of 3D memory, also needs to explore new fabrication methods.

[0031] Some embodiments of the present application provide a method 1000 for preparing a three-dimensional memory. Figure 2 FIG. 1 shows a flow chart of a method 1000 for preparing a three-dimensional memory according to an exemplary embodiment of the present application. Figure 2 As shown, the method 1000 includes:

[0032] S101: forming a stacked structure on a substrate, and forming a first trench penetrating the stacked structure and extending into the substrate;

[0033] S102: forming a first insulating layer, a sacrificial layer, and a second insulating layer in sequence on the inner surface of the first trench;

[0034] S103: forming a second trench penetrating the second insulating layer and exposing the sacrificial layer;

[0035] S104: removing the sacrificial layer, and filling the gap formed by removing the sacrificial layer with a conductive layer; and

[0036] S105: filling the second trench with an insulating material.

[0037] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. In addition, some of the steps may be performed simultaneously or in different steps. Figure 2 Executed in the order shown.

[0038] Figure 3 The top view of the distribution of the sealing area 101, the step contact area 102 and the core area 103 of a three-dimensional memory is schematically shown. The core area 103 may include the entire area surrounded by the sealing area 101 except the step contact area 102. Figure 3 The structures of the sealing area 101 and the step contact area 102 at A are described in detail.

[0039] S101 , forming a stacked structure on a substrate, and forming a first trench penetrating the stacked structure and extending into the substrate.

[0040] The following combination Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 6A and Figure 6B Introduce step S101.

[0041] Figure 4 It is a schematic cross-sectional view of a structure formed after a stacked structure 20 is formed on a substrate 10 according to a preparation method in one embodiment of the present application.

[0042] like Figure 4 As shown, step S101 of forming the stacked structure 20 on the substrate 10 may, for example, include: preparing the substrate 10 and forming the stacked structure 20 on one side of the substrate 10 .

[0043] Specifically, in one embodiment of the present application, the preparation material of the substrate 10 can be selected from any suitable semiconductor material, for example, it can be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or gallium arsenide and other III-V compounds.

[0044] In one embodiment of the present application, the substrate 10 may be, for example, a composite substrate for supporting a device structure thereon. Figure 4 The substrate 10 is schematically shown as comprising a five-layer structure, but the present application is not limited thereto. The substrate 10 may be configured to comprise multiple layers of different materials as required. In one embodiment of the present application, the substrate 10 may be formed by sequentially depositing multiple layers made of different materials using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0045] After forming the substrate 10, a stacked structure 20 may be formed on one side of the substrate 10 through one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, CVD, PVD, ALD, or any combination thereof, and are not limited in this application. The stacked structure 20 may include multiple pairs of gate sacrificial layers 200 and dielectric layers 201, stacked alternately. For example, the stacked structure 20 may include 64, 128, or more pairs of gate sacrificial layers 200 and dielectric layers 201. In some embodiments, the gate sacrificial layers 200 and dielectric layers 201 may, respectively, include a first dielectric material and a second dielectric material different from the first dielectric material. For example, the gate sacrificial layer 200 may include silicon nitride, and the dielectric layer 201 may include a silicon oxide layer. The greater the number of stacked layers 20, the higher the integration density and the greater the number of memory cells formed therefrom. The number and stack height of the stacked structures 20 can be designed based on actual storage requirements and are not specifically limited in this application.

[0046] The preparation method of a single stacked structure is described above. In fact, as the storage capacity demand of three-dimensional memory continues to increase, the storage stack is gradually increasing. In order to break through the limitations of traditional process limits, a double stacking technology or a multi-stack technology can also be used to form a stacked structure by stacking multiple sub-stacked structures in sequence in the direction of the thickness of the stacked structure, wherein each sub-stacked structure may include a plurality of gate sacrificial layers and dielectric layers that are alternately stacked. The number of layers of each sub-stacked structure may be the same or different. Since the content and structure involved in the preparation process of the single stacked structure described above can be fully or partially applied to the stacked structure formed by multiple sub-stacked structures described here, the related or similar content will not be repeated. However, it can be understood by those skilled in the art that the subsequent preparation process can be carried out on the basis of a multi-stacked structure or a single stacked structure.

[0047] For the convenience of description, we will Figure 4 The substrate 10 , the stacked structure 20 and the structures to be subsequently formed thereon are divided into a step contact area 102 and a sealing area 101 .

[0048] Figure 5A and Figure 5B are schematic cross-sectional views of a structure formed after forming a plurality of virtual channel structures 30 in a stacked structure 20 according to a preparation method in one embodiment of the present application, wherein Figure 5A yes Figure 5B Schematic cross-section at CC; Figure 5B yes Figure 5A Schematic diagram of the cross section at BB in the middle.

[0049] In some embodiments of the present application, Figure 5A and Figure 5B As shown, step S101 may also include forming multiple dummy channel structures 30 in the step contact region 102. The dummy channel structures 30 do not actually serve as memory cells, but rather serve a purpose, such as supporting the stacked layers or implementing process variation control during fabrication, to ensure that each step in the formation of the internal structure of the three-dimensional memory can be carried out safely and efficiently. The dummy channel structures 30 may include a dummy channel material layer that extends through the stacked structure 20. The dummy channel material layer can support the structure of the step contact region 102, making the structure of the three-dimensional memory less prone to collapse. Exemplarily, the functions of the dummy channel structures 30 include, but are not limited to, providing mechanical support or load balancing.

[0050] In some embodiments of the present application, the dummy channel structure 30 can have the same structure as the channel structure (not shown) of the core region (not shown) and can be formed using existing conventional processes together with the channel structure of the core region used as the memory cell. Detailed description thereof is omitted here. The dummy channel structure 30 of the step contact region 102 is typically disposed around the wordline contact portion (formed in a subsequent process step) to provide protection and support for the wordline contact portion.

[0051] Figure 6A and Figure 6B are schematic cross-sectional views of a structure formed after forming a first trench 41 and a plurality of word line contact openings 51 in a stacked structure 20 according to a preparation method according to an embodiment of the present application, wherein Figure 6A yes Figure 6B Schematic cross-section at CC; Figure 6B yes Figure 6A Schematic diagram of the cross section at BB in the middle.

[0052] In some implementations of step S101, Figure 6A and Figure 6B As shown, in this step, a first trench 41 is formed, wherein the first trench 41 penetrates the portion of the stacked structure 20 located in the sealing area 101 and extends into the substrate 10 .

[0053] In some implementations of step S101, Figure 6A and Figure 6B As shown, step S101 may further include forming a plurality of word line contact openings 51, Figure 6A Only three word line contact openings 501, 502 and 503 are schematically shown. Figure 6B Only six word line contact openings are schematically shown. It is understood that the number of word line contact openings 51 is related to the number of control gates ultimately formed and is not limited to the number exemplified herein. Each word line contact opening 51 penetrates a portion of the stacked structure 20 located in the step contact region 102 in a direction close to the substrate 10 and reaches the gate sacrificial layer 200 at a predetermined depth (see FIG. Figure 6B As an example, different word line contact openings 51 respectively reach different predetermined depths of the gate sacrificial layer 200 .

[0054] In some embodiments, the first trench 41 and the word line contact opening 51 can be fabricated using the same process and method, that is, the first trench 41 and the word line contact opening 51 can be formed simultaneously. For example, the first trench 41 and the word line contact opening 51 can be formed using, for example, a dry etching process or a combination of dry and wet etching processes. Other fabrication processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed.

[0055] In some embodiments, the first trench 41 may be an annular trench that penetrates the stacked structure 20 and extends into the substrate 10 . The cross section of the annular trench in a direction parallel to the substrate 10 may be closed.

[0056] In some embodiments, the word line contact opening 51 may have a columnar shape that penetrates a portion of the stacked structure 20 and reaches a predetermined depth in the gate sacrificial layer 200. The cross-sectional shape of the columnar shape in the direction parallel to the substrate 10 is not limited to a circle or a square, and the relative position is not limited to a circle or a square. Figure 6A and Figure 6B The example method can be freely designed according to actual usage.

[0057] S102 , forming a first insulating layer and a sacrificial layer in sequence on the inner surface of the first trench.

[0058] Figure 7A and Figure 7B 1 shows a cross-sectional schematic diagram of a structure formed after forming a first insulating layer 411 on the inner surface of the first trench 41 and forming a word line contact insulating layer 511 in a plurality of word line contact openings 51 according to a preparation method according to an embodiment of the present application, wherein: Figure 7A yes Figure 7B Schematic cross-section at CC; Figure 7B yes Figure 7A Schematic diagram of the cross section at BB in the middle.

[0059] In some implementations of step S102, Figure 7A and Figure 7B As shown, in this step, a first insulating layer 411 is formed on the inner surface of the first trench 41 . In some embodiments of step S102 , this step may further include forming a word line contact insulating layer 511 in the word line contact opening 51 .

[0060] In some embodiments, the materials and preparation processes of the first insulating layer 411 and the word line contact insulating layer 511 can be the same. For example, the materials of the first insulating layer 411 and the word line contact insulating layer 511 can be insulating materials, such as silicon oxide. The preparation processes of the first insulating layer 411 and the word line contact insulating layer 511 can use thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. When the materials of the first insulating layer 411 and the word line contact insulating layer 511 are the same, the first insulating layer 411 and the word line contact insulating layer 511 can be simultaneously prepared using the same process.

[0061] Figure 8 A cross-sectional schematic diagram of a structure formed by removing the word line contact insulating layer 511 located at the bottom of multiple word line contact openings 51 and removing the bottom portion of the first insulating layer 411 covering the substrate 10 according to a preparation method in accordance with an embodiment of the present application is shown.

[0062] refer to Figure 8 In some embodiments, step S102 may further include: removing the word line contact insulating layer 511 at the bottom of the plurality of word line contact openings 51 to expose the gate sacrificial layer 200 respectively reached by the plurality of word line contact openings 51, so that the word line contact sacrificial layer 512 (see Figure 9A and Figure 9B ) can contact the gate sacrificial layer 200 to prepare for the subsequent formation of word line contacts. For example, an anisotropic etching process (eg, dry etching process) can be used to etch the word line contact insulating layer 511 at the bottom of the plurality of word line contact openings 51.

[0063] refer to Figure 8 In some embodiments of step S102, the step may further include removing the bottom portion of the first insulating layer 411 near the substrate 10 to expose the substrate 10. For example, an anisotropic etching process (e.g., a dry etching process) may be used to etch the first insulating layer 411, and this may be performed together with the above-mentioned step of removing the word line contact insulating layer 511 located at the bottom of the plurality of word line contact openings 51 to expose the gate sacrificial layer 200 respectively reached by the plurality of word line contact openings 51. Alternatively, in some other embodiments of step S102, the step of removing the bottom portion of the first insulating layer 411 near the substrate 10 to expose the substrate 10 may be omitted.

[0064] In some implementations of step S102, Figure 9A and Figure 9B As shown, Figure 9A yes Figure 9B Schematic cross-section at CC; Figure 9B yes Figure 9A This step further includes forming a sacrificial layer 412 after forming the first insulating layer 411. In some embodiments of step S102, this step may further include forming a word line contact sacrificial layer 512 after forming the word line contact insulating layer 511.

[0065] refer to Figure 9A and Figure 9B In some embodiments of step S102, the materials and preparation processes of the sacrificial layer 412 and the word line contact sacrificial layer 512 may also be the same. For example, the material of the sacrificial layer 412 and the word line contact sacrificial layer 512 may be the same as the material of the gate sacrificial layer 200, which may be a nitride, such as silicon nitride. The preparation process of the sacrificial layer 412 and the word line contact sacrificial layer 512 may adopt a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Therefore, when the materials of the sacrificial layer 412 and the word line contact sacrificial layer 512 are the same, the sacrificial layer 412 and the word line contact sacrificial layer 512 may be simultaneously prepared using the same process.

[0066] In some implementations of step S102, Figure 10A and Figure 10B As shown, Figure 10A yes Figure 10B Schematic cross-section at CC; Figure 10B yes Figure 10A In this step, the second insulating layer 413 may be filled in the remaining space of the first trench 41 . In some embodiments of step S102 , the word line contact filling layer 513 may be formed in the remaining space of the word line contact opening 51 .

[0067] The second insulating layer 413 and the word line contact filling layer 513 may be made of dielectric materials such as silicon oxide, and may be filled in the remaining space of the first trench 41 and the word line contact opening 51 respectively using deposition processes such as CVD, PVD, ALD or any combination thereof.

[0068] As an option, in some other implementations of step S102 , the second insulating layer 413 does not need to fill the remaining space of the first trench 41 , and only needs to cover the sacrificial layer 412 to a certain thickness.

[0069] As an option, in some other implementations of step S102 , the word line contact filling layer 513 may not necessarily fill the remaining space of the word line contact opening 51 , but only needs to cover the word line contact sacrificial layer 512 and the gate sacrificial layer 200 to a certain thickness.

[0070] S103, forming a second trench penetrating the second insulating layer and exposing the sacrificial layer .

[0071] In some implementations of step S103, Figure 11A and Figure 11B As shown, Figure 11A yes Figure 11B Schematic cross-section at CC; Figure 11B yes Figure 11A In step S103, a second trench 42 is formed that penetrates the second insulating layer 413 and exposes the sacrificial layer 412. In one embodiment of the present application, reference is made to Figure 11B The second trench 42 penetrates the second insulating layer 413 and penetrates the bottom portion of the sacrificial layer 412 close to the substrate 10. Alternatively, in some other embodiments of step S103, the second trench 42 may penetrate only the second insulating layer 413 without penetrating the sacrificial layer 412, as long as the bottom portion of the sacrificial layer 412 close to the substrate 10 is exposed.

[0072] In some implementations of step S103, Figure 11A and Figure 11B As shown, step S103 may further include forming a plurality of word line trenches 52 that sequentially penetrate the word line contact filling layer 513, the stacked structure 20 and extend into the substrate 10, wherein the plurality of word line trenches 52 extend to a core region (not shown) in a direction parallel to the substrate 10.

[0073] In some embodiments of step S103 , the step may further include forming a plurality of gate line gaps (not shown) that penetrate the stacked structure 20 located in the core region (not shown) and extend to the substrate 10 .

[0074] In some embodiments of step S103, the step may further include forming a plurality of gate line gaps 61 penetrating the stacked structure 20 located in the step contact region 102 and extending into the substrate 10. Figure 11A and Figure 11B Only one gate line gap 61 is schematically shown. The number and arrangement of the gate line gaps 61 can be set according to actual needs.

[0075] In an exemplary embodiment, when the second insulating layer 413 , the word line contact filling layer 513 and the stacked structure 20 are made of the same material or have the same etching selectivity, etching processes may be performed simultaneously to form the second trench 42 , the word line trench 52 and the gate line slit 61 .

[0076] In an exemplary embodiment, the second trench 42, the word line trench 52, and the gate line slit 61 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. Other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed. In a direction parallel to the substrate 10, the second trench 42, the word line trench 52, and the gate line slit 61 can each have a trench shape that penetrates the stacked structure 20 and extends to the substrate 10.

[0077] In one embodiment of the present application, step S103 further includes the step of forming a word line contact portion. Figures 12A to 17B Specific steps for forming word line contacts are introduced.

[0078] Because the second trench 42 of the sealing area 101 and the gate gap (not shown) of the core area do not need to be used as a word line contact portion, the second trench 42 and the gate gap (not shown) of the core area can be filled with a dielectric material such as polysilicon to cover and protect the second trench 42 and the gate gap of the core area. Figure 12A and Figure 12B As shown, Figure 12A yes Figure 12B Schematic cross-section at CC; Figure 12B yes Figure 12A Schematic cross-sectional view at DD in FIG. A filling layer 303 can be formed in the second trench 42 and the gate gap (not shown) in the core region by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. It will be understood that when the filling layer 303 is formed in the second trench 42 and the gate gap (not shown) in the core region, the filling layer 303 will also be formed on the word line trench 52, the gate line gap 61, and the surface of the stacked structure 20 away from the substrate 10. The filling layer 303 on the surface of the stacked structure 20 away from the substrate 10 is not shown.

[0079] Next, Figure 13A and Figure 13B As shown, Figure 13A yes Figure 13B Schematic cross-section at CC; Figure 13B yes Figure 13A Schematic cross-sectional view at DD in FIG. For example, chemical mechanical polishing, dry etching, dry etching, wet etching, or a combination thereof can be used to remove the filling layer 303 within the word line trench 52, within the gate gap 61, and on the surface of the stacked structure 20 away from the substrate 10, and the surface of the stacked structure 20 is planarized.

[0080] Next, refer to Figure 14A and Figure 14B ,in Figure 14A yes Figure 14B The cross-sectional diagram at EE in the middle, Figure 14B yes Figure 14A Schematic cross-sectional view at DD in FIG. Recess etching is used to remove portions of the wordline contact sacrificial layer 512 and the gate sacrificial layer 200 based on the gate line gap 61 and the wordline trench 52. It is understood that when the wordline contact sacrificial layer 512 and the gate sacrificial layer 200 are made of the same material or have the same etching selectivity, and when the gate sacrificial layer 200 and the dielectric layer 201 in the stacked structure 20 are respectively composed of silicon nitride and silicon oxide, a phosphoric acid solution can be used as an etchant in the wet etching, and a gas mixture of one or more of C4F8, C4F6, CH2F2 and O2 can be used in the vapor phase etching. Due to the selectivity of the etchant, this etching removes the gate sacrificial layer 200 and the wordline contact sacrificial layer 512 relative to the dielectric layer 201.

[0081] During the etching step, refer again to 13A and Figure 13B , the etchant fills the gate line gap 61 and the word line trench 52. The end of the gate sacrificial layer 200 in the stacked structure 20 is exposed in the opening of the gate line gap 61, and the end of the gate sacrificial layer 200 in the word line trench 52 except for the area around the word line contact insulating layer 511 is also exposed to the etchant. In addition, the end of the word line contact sacrificial layer 512 is also exposed to the etchant, and the word line contact sacrificial layer 512 between the word line contact insulating layer 511 and the word line contact filling layer 513 is not exposed to the etchant (refer to Figure 13A Therefore, the etchant gradually etches the gate sacrificial layer 200 and the word line contact sacrificial layer 512 from the gate line gap 61 and the word line groove 52 to the stacked structure 20 and the inner portion of the stacked structure 20 to form the word line opening 70 (refer to Figure 14A and Figure 14B ).

[0082] Next, refer to Figure 15A and Figure 15B ,in Figure 15A yes Figure 15B The cross-sectional diagram at EE in the middle, Figure 15B yes Figure 15A In the cross-sectional view at DD in FIG, gate line gap 61 and word line trench 52 are used as deposition channels. A suitable deposition method, such as atomic layer deposition (ALD), is used to fill the gate line gap 61, word line trench 52, and word line opening 70 with conductive material to form a word line, i.e., gate layer 202. Subsequently, recess etching can be used to remove a portion of the gate layer 202 to form a recess 80.

[0083] Next, refer to Figure 16A and Figure 16B ,in Figure 16Ayes Figure 16B The cross-sectional diagram at EE in the middle, Figure 16B yes Figure 16A DD in FIG, a dielectric layer 203 is formed covering the gate layer 202 to prevent short circuits between the upper and lower gate layers 202. For example, the dielectric layer 203 can be formed in the gate line gap 61, the word line trench 52, and the recess 80 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The dielectric layer 203 can be made of the same material as the dielectric layer 202.

[0084] Next, refer to Figure 17A and Figure 17B ,in Figure 17A yes Figure 17B The cross-sectional diagram at EE in the middle, Figure 17B yes Figure 17A In the cross-sectional view at DD in FIG, a filling layer 303 may be formed in the remaining space between the gate line gap 61 and the word line trench 52 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0085] Next, refer to Figure 18A and Figure 18B ,in Figure 18A yes Figure 18B The cross-sectional diagram at EE in the middle, Figure 18B yes Figure 18A As shown in the cross-sectional schematic diagram at DD, a chemical mechanical polishing process, a dry etching process, a dry etching process, a wet etching process, or a combination thereof can be used to remove the filling layer 303 of the second groove 42, expose the second groove 42 again, and planarize the surface of the stacked structure 20 to prepare for the subsequent preparation of the sealing area 101 structure based on the second groove 42.

[0086] S104, removing the sacrificial layer, and filling the gap formed by removing the sacrificial layer with a conductive layer.

[0087] In some implementations of step S104, Figure 19A 、 19B , 20A and 20B, wherein Figure 19A yes Figure 19B The cross-sectional diagram at EE in the middle, Figure 19B yes Figure 19A The cross-sectional view at DD in this step is as follows: Figure 20A yes Figure 20B The cross-sectional diagram at EE in the middle, Figure 20B yes Figure 20A The cross-sectional diagram at DD in the figure. Figure 19A and Figure 19B As shown, the sacrificial layer 412 is removed, and then Figure 20A and Figure 20BAs shown, a conductive layer 414 is filled into the void 90 formed by removing the sacrificial layer 412. The second trench 42 can be used as a passage for providing an etchant and a chemical precursor, and a process such as wet etching is used to remove the sacrificial layer 412 to form the void 90. It will be understood that the void 90 formed by removing the sacrificial layer 412 may include a first void 901 and a second void 902. Thus, the conductive layer 414 formed by filling the void 90 may include a first conductive layer 4141 located in the first void 901 and a second conductive layer 4142 located in the second void 902.

[0088] A thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to fill the first void 901 and the second void 902 with conductive material. It is understood that while forming the first conductive layer 4141 and the second conductive layer 4142, conductive material is also formed at other locations in the second trench 42. The conductive material is then etched back so that the conductive material only exists in the first void 901 and the second void 902. According to one example, the first conductive layer 4141 and the second conductive layer 4142 may have recesses 903 and 904 relative to the second insulating layer 413 in a direction parallel to the substrate 10 (see FIG. 1 ). Figure 20B ).

[0089] For example, the conductive layer 414 may be made of a conductive material such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide. The aforementioned conductive material may also be other materials that can be used to prepare a conductive layer, and this application does not limit this.

[0090] In some embodiments of step S104, it may also include: removing the gate line sacrificial layer 200 based on the gate gap in the core area to form a sacrificial gap (not shown), and forming a gate layer (not shown) in the sacrificial gap. The gate gap can be used as a path to provide an etchant and a chemical precursor, and a process such as wet etching is used to remove all gate sacrificial layers 200 in the core area of the stacked structure 20 to form a sacrificial gap. A thin film deposition process such as CVD, PVD, ALD or any combination thereof can be used to form a gate layer in the sacrificial gap. The gate layer can be made of a conductive material, such as any one or combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon or silicide. In some embodiments of the present application, the preparation of the gate layer in the core area and the conductive layer 414 in the sealing area 101 can be carried out simultaneously.

[0091] S105 , filling the second trench with an insulating material.

[0092] In some implementations of step S105, Figure 21A and Figure 21B As shown, Figure 21A yes Figure 21B The cross-sectional diagram at EE in the middle, Figure 21B yes Figure 21A In the cross-sectional view at DD in FIG, in this step, an insulating material is filled in the second trench 42 to form a filling layer 303. The same material as the dielectric layer 201 or the second insulating layer 413 can be selected to fill the gate gap, such as silicon oxide.

[0093] In one embodiment of the present application, Figure 21A and Figure 21B As shown, before forming the filling layer 303, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to fill the second trench 42 with the second insulating layer 413. It will be understood that filling the second trench 42 also fills the inward recesses 903 and 904 of the first conductive layer 4141 and the second conductive layer 4142 relative to the second insulating layer 413 in a direction parallel to the substrate 10. Furthermore, the second insulating layer 413 can be etched to form a trench structure, and the filling layer 303 can be formed in the trench structure.

[0094] In one embodiment of the present application, after forming the conductive layer 414 and the gate layer (not shown) in the core region, while filling the second trench 42 with insulating material, the gate line gaps (not shown) in the core region may be filled with insulating material.

[0095] In one embodiment of the present application, the first insulating layer 411 , the conductive layer 414 and the second insulating layer 413 may have an annular shape that penetrates the stacked structure 20 and extends into the substrate 10 , and the cross section of the annular shape parallel to the substrate 10 may be closed.

[0096] The subsequent process of the method for preparing a three-dimensional memory also includes steps such as forming peripheral circuits in the three-dimensional memory. The embodiments and process flow in this application only illustrate the intermediate of forming a three-dimensional memory having a stepped contact area and a sealing area.

[0097] Figure 22 A schematic cross-sectional view of a semiconductor structure 2000 according to an exemplary embodiment of the present application is shown.

[0098] like Figure 22 As shown, a semiconductor structure 2000 according to an exemplary embodiment of the present application may include a substrate 10, a stacked structure 20 located on the substrate 10, and a sealing structure 600 penetrating the stacked structure 20. The stacked structure 20 may be located on one side of the substrate 10 and may include a plurality of pairs of gate sacrificial layers 200 and dielectric layers 201 alternately stacked with each other.

[0099] The sealing structure 600 extends through the stacked structure 20 and includes a first insulating layer 411, a first conductive layer 4141, a second insulating layer 413, a second conductive layer 4142, and a third insulating layer 411', stacked and arranged perpendicular to the direction of penetration. In an example, the first conductive layer 4141 and the second conductive layer 4142 can be formed of the same material, and the first insulating layer 411 and the third insulating layer 411' can be formed of the same material. The first insulating layer 411 separates the first conductive layer 4141 from the stacked structure 20, the third insulating layer 411' separates the second conductive layer 4142 from the stacked structure 20, and the second insulating layer 413 separates the adjacent first conductive layer 4141 and the second conductive layer 4142. In other words, the first conductive layer 4141 and the second conductive layer 4142 are independent of each other.

[0100] In an exemplary embodiment, the sealing structure 600 further includes a filling layer 303 penetrating the second insulating layer 413. For example, the filling layer 303 may be made of a semiconductor material such as silicon (eg, amorphous silicon, polycrystalline silicon, or single crystal silicon).

[0101] In an exemplary embodiment, the first insulating layer 411 , the first conductive layer 4141 , the second insulating layer 413 , the second conductive layer 4142 , and the third insulating layer 411 ′ have a ring-like shape in cross-section in a direction parallel to the substrate 10 .

[0102] In an exemplary embodiment, the materials of the first insulating layer 411, the second insulating layer 413, and the third insulating layer 411' may be the same. As an example, the materials of the first insulating layer 411, the second insulating layer 413, and the third insulating layer 411' may be a high dielectric constant material including hafnium dioxide, lanthanum oxide, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium oxysilicate, silicon oxide, silicon nitride, zirconium dioxide, strontium titanate, or zirconium oxysilicate.

[0103] Exemplarily, the material of the first conductive layer 4141 and the second conductive layer 4142 may include, for example, tungsten, cobalt, copper, aluminum, or any combination thereof.

[0104] The present application also provides a three-dimensional memory including the semiconductor structure 2000 as described above.

[0105] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also includes other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the technical concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions in this application.

Claims

1. A method for preparing a three-dimensional memory, wherein: The method comprises: forming a stacked structure on a substrate, the stacked structure comprising a sealing area, a step contact area and a core area surrounded by the sealing area; forming a first trench in the sealing area that penetrates the stacked structure and extends into the substrate; forming a first insulating layer, a sacrificial layer, and a second insulating layer in sequence on the inner surface of the first trench, and removing a bottom portion of the first insulating layer covering the substrate; forming a second trench penetrating the second insulating layer and exposing the sacrificial layer, wherein the second trench penetrates a portion of the sacrificial layer close to the substrate; removing the sacrificial layer and filling a conductive layer in a gap formed by removing the sacrificial layer; and filling the second trench with insulating material, The first insulating layer, the conductive layer and the second insulating layer form a sealed structure of the three-dimensional memory.

2. The method according to claim 1, wherein The steps of sequentially forming a first insulating layer, a sacrificial layer, and a second insulating layer on the inner surface of the first trench, and removing a bottom portion of the first insulating layer covering the substrate include: forming the first insulating layer on the inner surface of the first trench; removing a bottom portion of the first insulating layer covering the substrate to expose the substrate; forming the sacrificial layer on the first insulating layer and the exposed substrate; and The remaining space of the first trench is filled with the second insulating layer.

3. The method according to claim 1, wherein Removing the sacrificial layer includes: The sacrificial layer is removed through the second trench.

4. The method according to claim 1, wherein The gap includes a first gap and a second gap extending along a stacking direction of the stacked structure, with a gap between the first gap and the second gap, wherein filling the gap formed by removing the sacrificial layer with a conductive layer further comprises: The portion of the conductive layer outside the first gap and the second gap is removed.

5. The method according to claim 1, wherein The stacked structure includes alternately stacked gate sacrificial layers and dielectric layers, wherein the gate sacrificial layers are made of the same material as the sacrificial layers.

6. The method according to any one of claims 1 to 5, wherein: The cross-section of the first trench, the first insulating layer, the sacrificial layer, the second insulating layer, the second trench, and the conductive layer in a direction parallel to the substrate is arranged in a ring shape.

7. Semiconductor structures, including: substrate; a stacked structure located on the substrate, wherein the stacked structure comprises a sealing area, and a step contact area and a core area surrounded by the sealing area; as well as A sealing structure is located in the sealing area, penetrates the stacked structure and extends to the substrate, wherein the sealing structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer stacked along a direction perpendicular to the penetration direction, wherein the first conductive layer and the second conductive layer are the same, and the first insulating layer and the third insulating layer are the same.

8. The semiconductor structure according to claim 7, wherein: The sealing structure further includes a filling layer penetrating the second insulating layer.

9. The semiconductor structure according to claim 7, wherein: The first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, and the third insulating layer have a ring-shaped cross section in a direction parallel to the substrate.

10. A three-dimensional memory comprising the semiconductor structure according to any one of claims 7 to 9.

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