Display panel and display device

Abstract

This application discloses a display panel and a display device. The display panel includes an active layer, a gate layer and a metal layer. It can quickly pull down the falling edge of the scan signal in the first scan line when the rising edge of the scan signal pulse arrives in the second scan line. The newly added structures such as low-potential traces, control traces and pull-down transistors are constructed between the first data line and the second data line, which can complete the layout with less space and maximize the aperture ratio.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] With the development of display technology, refresh rate has increasingly become one of the important indicators for measuring display effect. High refresh rate screens can bring a smoother visual experience, reduce eye fatigue, and as various application software adapts to high refresh rate screens, consumers can also obtain a better viewing and entertainment experience from high refresh rate screens. The refresh rate of traditional display devices is generally 60Hz. In recent years, with the development of technology, display devices with refresh rates of 90Hz, 120Hz, 150Hz and even higher have emerged. From the perspective of panel design, achieving a higher refresh rate is affected by factors such as device performance, driving capability, and charging rate. For example, in progressive scan, the falling edge of the previous line scan signal will cause a shutdown delay due to the line load. When the progressive scan speed is faster, display crosstalk caused by charging abnormalities can occur.

[0003] Specifically, in conventional gate progressive scan, the on-time of each line is the reciprocal of the refresh rate. If the refresh rate is f, then the on-time of each scan pulse is t = 1 / f. Therefore, the higher the refresh rate f, the shorter the on-time of each scan pulse. For example, when f = 60Hz, t = 16.67ms; when f = 150Hz, t = 6.67ms. Because the falling edge of the scan pulse is delayed, and the on-time of the scan pulse shortens with increasing refresh rate, the falling edge of the scan pulse cannot reach the ideal potential at the end of the on-time. This causes the write transistor in the pixel circuit to remain on, meaning it is still transmitting data signals, which can lead to display abnormalities. Figure 1 As shown, when the rising edge of the pulse of the next row of sub-pixels, i.e. the N+1th level scan signal G(N+1), arrives, the potential of the Nth level scan signal G(N) is still unable to turn off the write transistor in the previous row of pixel circuit.

[0004] Therefore, it is necessary to propose a display panel in which the falling edge time of the scan signal is shorter in the display area, while achieving the highest possible aperture ratio.

[0005] It should be noted that the above description of the background technology is merely for the purpose of facilitating a clear and complete understanding of the technical solutions of this application. Therefore, it should not be assumed that the technical solutions mentioned above are known to those skilled in the art simply because they appear in the background technology of this application. Summary of the Invention

[0006] This application provides a display panel and display device to alleviate the technical problems of long falling edge time and low aperture ratio of the scan signal in the display area.

[0007] In a first aspect, this application provides a display panel comprising an active layer, a gate layer, and a metal layer. The active layer includes a source connection region and a drain connection region of a pull-down transistor. The gate layer includes the gate of the pull-down transistor, a first scan line, and a second scan line. The second scan line is electrically connected to the gate of the pull-down transistor, and the first scan line and the second scan line are arranged adjacent to each other along a first direction. The metal layer includes a low-potential trace, a control trace, a first data line, and a second data line. One end of the control trace is electrically connected to the source connection region of the pull-down transistor, and the other end of the control trace is electrically connected to the first scan line. The low-potential trace is electrically connected to the drain connection region of the pull-down transistor. The first data line and the second data line are arranged adjacent to each other along a second direction. In the second direction, the low-potential trace, the control trace, and the pull-down transistor are all located between the first data line and the second data line.

[0008] In some embodiments, the low-potential trace is close to one of the first data line or the second data line, and the control trace is close to the other of the first data line or the second data line; and in the metal layer, the low-potential trace is a continuous metal pattern.

[0009] In some embodiments, the low-potential trace includes a first winding portion that is close to the drain connection region of the pull-down transistor and is far from the first data line or the second data line.

[0010] In some embodiments, the control trace includes a bend that extends toward the projection of the source connection region of the pull-down transistor onto the metal layer, and the bend at least partially overlaps with the projection of the source connection region of the pull-down transistor onto the metal layer in the thickness direction of the display panel.

[0011] In some embodiments, the projection of the source connection region of the pull-down transistor onto the active layer is located on one side of the second scan line and close to the first scan line; the projection of the drain connection region of the pull-down transistor onto the active layer is located on the other side of the second scan line and far from the first scan line.

[0012] In some embodiments, the active layer further includes a semiconductor structure for writing transistors, the semiconductor structure including a patterned integrally formed first straight portion, a second straight portion, and a third straight portion; in the thickness direction, the projection of the first straight portion onto the metal layer overlaps with a first data line, the projection of the second straight portion onto the metal layer at least partially overlaps with a broken portion of a control trace, and the projection of the third straight portion onto the metal layer at least partially overlaps with a second scan line; the extension direction of the first straight portion is consistent with the extension direction of the third straight portion, and the first straight portion and the third straight portion are both located on the same side of the second straight portion.

[0013] In some embodiments, if the control trace is close to the first data line, at least a portion of the control trace is located between the first straight portion and the third straight portion in the second direction; or, if the low-potential trace is close to the first data line, the first winding portion of the low-potential trace includes a patterned integrally formed first trace portion, a second trace portion, and a third trace portion, the first trace portion extending along the second direction; the second trace portion extending along the first direction, and the projection of the second trace portion in the thickness direction is located between the write transistor and the pull-down transistor; the third trace portion extending along the second direction, the third trace portion and the first trace portion are both located on the same side of the second trace portion, and the projection of the third trace portion on the active layer does not overlap with the semiconductor structure.

[0014] In each embodiment, the display panel further includes a first via, through which the first straight portion is electrically connected to the first data line, and the projection of the first via in the second direction overlaps with the second trace portion, but does not overlap with the first trace portion or the third trace portion.

[0015] In some embodiments, the low-potential trace is close to the first data line, and the extension direction of the low-potential trace corresponds to the extension direction of the first data line; the drain connection region, the channel region, and the source connection region of the pull-down transistor are arranged sequentially along the second direction, and the projection of the low-potential trace on the active layer at least partially overlaps with the drain connection region of the pull-down transistor; the active layer also includes a semiconductor structure for writing transistors, and in the second direction, the projection of the semiconductor structure on the metal layer is located on one side of the low-potential trace and away from the control trace; the projection of the semiconductor structure on the metal layer partially overlaps with the first data line.

[0016] Secondly, this application provides a display device including the display panel in at least one of the above embodiments; wherein, a low-potential trace is used to transmit a low-potential signal, a first scan line is used to transmit a first scan signal, and a second scan line is used to transmit a second scan signal; in the same frame, the pulse of the first scan signal is earlier than the pulse of the second scan signal.

[0017] The display panel and display device provided in this application, by electrically connecting the second scan line to the gate of the pull-down transistor, electrically connecting one end of the control line to the source connection region of the pull-down transistor, electrically connecting the other end of the control line to the first scan line, and electrically connecting the low-potential line to the drain connection region of the pull-down transistor, can quickly pull down the falling edge of the scan signal in the first scan line when the rising edge of the scan signal pulse arrives in the second scan line, thereby shortening the time taken for the falling edge of the scan signal in the display area; at the same time, by constructing the low-potential line, control line, and pull-down transistor, these newly added structures, between the first data line and the second data line, the layout can be completed with less space, thereby maximizing the aperture ratio. Attached Figure Description

[0018] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0019] Figure 1 This is a schematic diagram of the waveform of the scanning signal in a traditional technical solution.

[0020] Figure 2 This is a schematic diagram illustrating the electrical principle of a display panel provided in an embodiment of this application.

[0021] Figure 3 for Figure 2 The waveform diagram of the scanning signal in the display panel is shown.

[0022] Figure 4 A schematic diagram of the cross-sectional structure of the pull-down transistor, control trace, low-potential trace, and data line provided in the embodiments of this application.

[0023] Figure 5 This is a schematic diagram of a first layout design for a display panel provided in an embodiment of this application.

[0024] Figure 6 This is a schematic diagram of a second layout design for a display panel provided in an embodiment of this application.

[0025] Figure 7 This is a schematic diagram of a third layout design for a display panel provided in an embodiment of this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0027] In view of Figure 1 The conventional technical solution shown has the drawback of a long falling edge time for the scanning signal within the display area. This embodiment provides a display panel, please refer to [link / reference]. Figures 2 to 7 ,like Figure 1 As shown, the display panel can be divided into a display area AA and a non-display area NA. A gate driving circuit 10 is constructed in the non-display area NA. Multiple scan lines originating from the output terminals of the gate driving circuit 10 extend into the display area AA. These scan lines are arranged sequentially along the first direction DR1. For example, the Nth scan line GL1 is used to transmit the Nth level scan signal G(N), the N+1th scan line GL2 is used to transmit the N+1th level scan signal G(N+1), and the N+2th scan line GL3 is used to transmit the N+2th level scan signal G(N+2). The falling edge of the Nth level scan signal G(N) can be at the same time or close to the rising edge of the N+1th level scan signal G(N+1).

[0028] A pull-down module 20 is provided in the display area AA. The pull-down module 20 may include multiple pull-down transistors T1. One of the sources or drains of the pull-down transistors T1 may be electrically connected to the low-potential trace VGLL used to transmit the low-potential signal VGL. The other source or drain of the pull-down transistor T1 may be electrically connected to one end of the control trace CTRL. The other end of the control trace CTRL may be electrically connected to the Nth scan line GL1. The gate of the pull-down transistor T1 may be electrically connected to the (N+1)th scan line GL2. N may be a positive integer. As N changes, the pull-down transistors T1 may be distributed at different positions in the display area AA to shorten the falling edge time of each scan signal in the display area AA.

[0029] Adding the pull-down module 20 can effectively reduce the time required for the scan signal to decrease from a high level to a low level. For example, compared to Figure 1 In other words, Figure 3 When the rising edge of the N+1 level scan signal G(N+1) arrives, the falling edge of the N level scan signal G(N) can be quickly pulled down to a predetermined low potential, which can significantly improve the crosstalk phenomenon of the data signal.

[0030] Among them, the pull-down transistor T1 can preferably be an N-channel thin-film transistor.

[0031] like Figure 4 As shown, the display panel may include, in its thickness direction, a substrate BP1, an active layer POLY1, a gate insulating layer GI1, a gate layer GE1, an insulating layer JY1, and a metal layer SD1 stacked sequentially.

[0032] The active layer POLY1 may include the source connection region T1S of the pull-down transistor, the channel region T1Z of the pull-down transistor, and the drain connection region T1D of the pull-down transistor.

[0033] The gate layer GE1 may include the gate T1G of the pull-down transistor.

[0034] The metal layer SD1 may include a control trace CTRL, a low-potential trace VGLL, and a data line DL. The control trace CTRL may be electrically connected to the source connection region T1S of the pull-down transistor, and the low-potential trace VGLL may be electrically connected to the drain connection region T1D of the pull-down transistor.

[0035] like Figures 5 to 7 As shown in any of the embodiments, in one embodiment, the first data line DL1 and the second data line DL2 are arranged adjacent to each other along the second direction DR2; and on the second direction DR2, the low-potential trace VGLL, the control trace CTRL, and the pull-down transistor T1 are all located between the first data line DL1 and the second data line DL2. It can be understood that this allows for the layout of these newly added structures, such as the low-potential trace VGLL, the control trace CTRL, and the pull-down transistor T1, to be completed with less space, thereby maximizing the aperture ratio.

[0036] In one embodiment, the low-potential trace VGLL is positioned close to either the first data line DL1 or the second data line DL2, while the control trace CTRL is positioned close to the other of the first data line DL1 or the second data line DL2; and in the metal layer SD1, the low-potential trace VGLL is a continuous metal pattern. It is understood that constructing the low-potential trace VGLL as a continuous metal pattern in the metal layer SD1 can reduce or avoid the use of vias to connect multiple trace segments that are the same low-potential trace VGLL, that is, it can reduce or avoid trace switching operations under the black matrix.

[0037] The low-potential trace VGLL may include a first main trunk VG1 and a first winding portion VG2. The first winding portion VG2 is close to the drain connection region T1D of the pull-down transistor T1, which can shorten the trace distance between the first winding portion VG2 and the drain connection region T1D of the pull-down transistor T1. The first winding portion VG2 is far away from the second data line DL2, which facilitates the placement of a via K2 at this location to avoid short-circuiting between the via K2 and the low-potential trace VGLL.

[0038] The routing path of the first main trunk VG1 can be parallel or approximately parallel to the routing path of the corresponding position of the first data line DL1 or the second data line DL2 that is close to it.

[0039] In one embodiment, the control trace CTRL may include a second main trunk CR1, a bend CR2, a second winding CR3, and a third winding CR4. The bend CR2 extends toward the projection of the source connection region T1S of the pull-down transistor T1 onto the metal layer SD1, and in the thickness direction DR3 of the display panel, the bend CR2 and the projection of the source connection region T1S of the pull-down transistor T1 onto the metal layer SD1 at least partially overlap, so that the electrical connection between the source connection region T1S of the pull-down transistor T1 and the control trace CTRL can be achieved with minimal space.

[0040] Specifically, a via K1 can be provided at the location of the first data line DL1 corresponding to the second winding portion CR3, without causing an electrical short circuit between the control trace CTRL and the first data line DL1. Similarly, a via can also be provided at the location of the first data line DL1 corresponding to the third winding portion CR4.

[0041] like Figure 5 , Figure 6 As shown, the projection of the source connection region T1S of the pull-down transistor T1 onto the active layer is located on one side of the (N+1)th scan line GL2 and close to the Nth scan line GL1; the projection of the drain connection region T1D of the pull-down transistor T1 onto the active layer is located on the other side of the (N+1)th scan line GL2 and far from the first scan line Nth scan line GL1. Thus, the pull-down transistor T1 can be constructed in a narrower space on the second direction DR2.

[0042] The active layer may further include a semiconductor structure 30 for writing transistors. The semiconductor structure 30 includes a patterned, integrally formed first straight portion 31, a second straight portion 32, and a third straight portion 33. In the thickness direction DR3, the projection of the first straight portion 31 onto the metal layer overlaps with the first data line DL1, the projection of the second straight portion 32 onto the metal layer at least partially overlaps with the broken line portion CR2 of the control trace CTRL, and the projection of the third straight portion 33 onto the metal layer at least partially overlaps with the (N+1)th scan line GL2. The extension direction of the first straight portion 31 is consistent with the extension direction of the third straight portion 33, and the first straight portion 31 and the third straight portion 33 are both located on the same side of the second straight portion 32.

[0043] like Figure 5 As shown, the control trace CTRL is close to the first data line DL1, and at least a portion of the control trace CTRL is located between the first straight section 31 and the third straight section 33 in the second direction DR2.

[0044] like Figure 6As shown, the low-potential trace VGLL is close to the first data line DL1. The first winding portion VG2 of the low-potential trace VGLL includes a patterned integrally formed first trace portion VG21, a second trace portion VG22, and a third trace portion VG23. The first trace portion VG21 extends along the second direction DR2, and the projection of the first trace portion VG21 on the active layer at least partially overlaps with the second straight section 32, thus reducing the space occupied in the first direction DR1. The second trace portion VG22 extends along the first direction DR1, and the projection of the second trace portion VG22 on the thickness direction DR3 is located between the write transistor and the pull-down transistor T1. The third trace portion VG23 extends along the second direction DR2. The third trace portion VG23 and the first trace portion VG21 are both located on the same side of the second trace portion VG22, and the projection of the third trace portion VG23 on the active layer does not overlap with the semiconductor structure 30.

[0045] This allows the write transistor to be constructed as a U-shaped thin-film transistor, and it also increases the distance between the first straight section 31 and the third straight section 33, so that the second main trunk CR1 of the control trace CTRL can pass through the semiconductor structure 30 and avoid lateral overlap with the N+1th scan line GL2 in the first direction DR1, thereby reducing the coupling effect between the two and reducing the load on at least one of them.

[0046] like Figure 5 and Figure 6 As shown, the display panel also includes a first via K1. The first straight section 31 is electrically connected to the first data line DL1 through the first via K1. The projection of the first via K1 on the second direction DR2 overlaps with the second trace section VG22, but does not overlap with the first trace section VG21 or the third trace section VG23. In this way, a part of the semiconductor structure 30 can be placed in the opening of the first winding section VG2, and the first via K1 can be avoided to prevent unwanted electrical short circuits.

[0047] like Figure 7 As shown, in one embodiment, the low-potential line VGLL is close to the first data line DL1, and the extension direction of the low-potential line VGLL corresponds to the extension direction of the first data line DL1; the drain connection region T1D, the channel region T1Z, and the source connection region T1S of the pull-down transistor T1 are arranged sequentially along the second direction DR2, and the projection of the low-potential line VGLL on the active layer at least partially overlaps with the drain connection region T1D of the pull-down transistor T1; the active layer also includes a semiconductor structure 30 for writing transistors, and on the second direction DR2, the projection of the semiconductor structure 30 on the metal layer is located on one side of the low-potential line VGLL and away from the control line CTRL; the projection of the semiconductor structure 30 on the metal layer partially overlaps with the first data line DL1.

[0048] It should be noted that, in this embodiment, the semiconductor structure 30 can be configured on the side of the first data line DL1 away from the second data line DL2. This allows the structure of the pull-down transistor T1 in the active layer to be arranged laterally, parallel to the N+1th scan line GL2, thus avoiding mutual overlap in the thickness direction DR3.

[0049] In one embodiment, this embodiment provides a display device including the display panel of at least one of the above embodiments; wherein, a low-potential trace is used to transmit a low-potential signal, a first scan line is used to transmit a first scan signal, and a second scan line is used to transmit a second scan signal; in the same frame, the pulse of the first scan signal is earlier than the pulse of the second scan signal.

[0050] It is understood that in this embodiment, the falling edge of the scanning signal in the first scanning line can be quickly pulled down when the rising edge of the scanning signal pulse arrives in the second scanning line, which can shorten the time taken for the falling edge of the scanning signal in the display area; at the same time, by constructing new structures such as low-potential traces, control traces and pull-down transistors between the first data line and the second data line, the layout can be completed with less space, and the aperture ratio can be increased as much as possible.

[0051] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0052] The display panel and display device provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, include: An active layer, the active layer including a source connection region of a pull-down transistor and a drain connection region of the pull-down transistor; A gate layer, the gate layer including the gate of the pull-down transistor, a first scan line and a second scan line, the second scan line being electrically connected to the gate of the pull-down transistor, and the first scan line and the second scan line being arranged adjacent to each other along a first direction; as well as A metal layer, the metal layer including a low-potential trace, a control trace, a first data line and a second data line, one end of the control trace being electrically connected to the source connection region of the pull-down transistor, the other end of the control trace being electrically connected to the first scan line, the low-potential trace being electrically connected to the drain connection region of the pull-down transistor, and the first data line and the second data line being arranged adjacent to each other along a second direction. In the second direction, the low-potential trace, the control trace, and the pull-down transistor are all located between the first data line and the second data line.

2. The display panel according to claim 1, characterized in that, The low-potential trace is located near one of the first data line or the second data line, and the control trace is located near the other of the first data line or the second data line; and in the metal layer, the low-potential trace is a continuous metal pattern.

3. The display panel according to claim 2, characterized in that, The low-potential trace includes a first winding portion, which is close to the drain connection region of the pull-down transistor and is far away from the first data line or the second data line.

4. The display panel according to claim 3, characterized in that, The control trace includes a bend, which extends toward the projection of the source connection region of the pull-down transistor onto the metal layer, and in the thickness direction of the display panel, the bend at least partially overlaps with the projection of the source connection region of the pull-down transistor onto the metal layer.

5. The display panel according to any one of claims 1 to 4, characterized in that, The projection of the source connection region of the pull-down transistor onto the active layer is located on one side of the second scan line and close to the first scan line; The projection of the drain connection region of the pull-down transistor onto the active layer is located on the other side of the second scan line and away from the first scan line.

6. The display panel according to claim 4, characterized in that, The active layer further includes a semiconductor structure for writing transistors, the semiconductor structure including a patterned integrally formed first linear portion, a second linear portion and a third linear portion; In the thickness direction, the projection of the first straight line portion on the metal layer overlaps with the first data line, the projection of the second straight line portion on the metal layer at least partially overlaps with the broken line portion of the control trace, and the projection of the third straight line portion on the metal layer at least partially overlaps with the second scan line. The extension direction of the first straight section is consistent with the extension direction of the third straight section, and the first straight section and the third straight section are both located on the same side of the second straight section.

7. The display panel according to claim 6, characterized in that, When the control trace is close to the first data line, at least a portion of the control trace is located between the first straight section and the third straight section in the second direction.

8. The display panel according to claim 6, characterized in that, When the low-potential trace is close to the first data line, the first winding portion of the low-potential trace includes a patterned integrally formed first trace portion, a second trace portion, and a third trace portion. The first trace portion extends along the second direction; the second trace portion extends along the first direction, and the projection of the second trace portion in the thickness direction is located between the write transistor and the pull-down transistor; the third trace portion extends along the second direction, and the third trace portion and the first trace portion are both located on the same side of the second trace portion, and the projection of the third trace portion on the active layer does not overlap with the semiconductor structure.

9. The display panel according to claim 8, characterized in that, The display panel also includes: The first via is electrically connected to the first data line through the first straight section, and the projection of the first via in the second direction overlaps with the second trace section, but does not overlap with the first trace section or the third trace section.

10. The display panel according to claim 2, characterized in that, The low-potential trace is close to the first data line, and the extension direction of the low-potential trace is the same as the extension direction of the first data line; the drain connection region, the channel region, and the source connection region of the pull-down transistor are arranged sequentially along the second direction, and the projection of the low-potential trace on the active layer at least partially overlaps with the drain connection region of the pull-down transistor. The active layer further includes a semiconductor structure for writing transistors, wherein, in the second direction, the projection of the semiconductor structure onto the metal layer is located on one side of the low-potential trace and away from the control trace; The projection of the semiconductor structure onto the metal layer partially overlaps with the first data line.

11. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 10; The low-potential trace is used to transmit a low-potential signal, the first scan line is used to transmit a first scan signal, and the second scan line is used to transmit a second scan signal; in the same frame, the pulse of the first scan signal is earlier than the pulse of the second scan signal.

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