logic circuits, inverters, followers, and complex logic circuits

Abstract

The application discloses a compound-based pure depletion type logic circuit and a compound logic circuit, belongs to the field of semiconductors, and is characterized in that: an input signal is connected through a level conversion circuit, and the input signal is divided and subjected to level shifting to output a first logic signal; a first logic signal is subjected to inversion by a depletion type HEMT transistor to output a second logic signal; the inversion circuit is powered by a single power supply; and therefore, the peripheral power supply circuit of the compound-based pure depletion type logic circuit is simplified.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a logic circuit, inverter, follower and composite logic circuit. Background Technology

[0002] In microwave integrated circuits, control logic circuits are essential unit circuits used to implement digital logic control functions such as switching on and off, and attenuation / phase shift switching. Compound-based high electron mobility transistors (HEMTs) and metal-semiconductor field-effect transistors (MESFETs) have significant advantages such as high characteristic frequency, fast switching speed, good noise performance, and high output power, and are widely used.

[0003] Related compound-based pure depletion logic circuits, such as Figure 1 As shown, diodes D1, D2, and D3 are connected in series in phase. The anode of diode D1 is connected to the input signal. The cathode of diode D3 is connected to the drain of the third depletion-type MESFET transistor M3 and the gate of the first depletion-type MESFET transistor M1. The source and gate of the third depletion-type MESFET transistor M3 are connected to the negative voltage power supply Vss. The drain of the first depletion-type MESFET transistor M1, the source of the second depletion-type MESFET transistor M2, and the gate of the second depletion-type MESFET transistor M2 together serve as the output of the pure depletion-type logic circuit. The drain of the second depletion-type MESFET transistor M2 is connected to the positive voltage power supply VDD, and the source of the first depletion-type MESFET transistor M1 is connected to the power supply ground. Therefore, the related compound-based pure depletion-type logic circuit requires dual power supplies, resulting in complex external power supply circuitry. Summary of the Invention

[0004] The purpose of this application is to provide a logic circuit, inverter, follower, and compound logic circuit that aims to solve the problem of complex external power supply circuits in related compound-based pure depletion logic circuits.

[0005] This application provides a logic circuit, including:

[0006] A level conversion circuit is configured to receive an input signal and perform voltage division and level shifting on the input signal to output a first logic signal;

[0007] An inverting circuit, connected to the level conversion circuit, is configured to invert the first logic signal based on a depletion-mode HEMT transistor to output a second logic signal. The inverting circuit is powered by a single power supply.

[0008] The logic circuit described therein is a pure depletion logic circuit based on compounds.

[0009] In one embodiment, the single power supply is a positive voltage power supply, the inverting circuit is connected to the positive voltage power supply, and the positive voltage power supply is configured to provide a positive voltage.

[0010] The inverting circuit is specifically configured to invert the first logic signal based on the depletion-type HEMT transistor according to the positive voltage, so as to output the second logic signal.

[0011] In one embodiment, the inverting circuit includes a first load, a first depletion-type HEMT transistor, a first diode, and a first resistor;

[0012] The first end of the first resistor serves as the input terminal of the inverting circuit and is connected to the level conversion circuit to input the first logic signal;

[0013] The second terminal of the first resistor is connected to the gate of the first depletion-type HEMT transistor, the source of the first depletion-type HEMT transistor is connected to the anode of the first diode, and the cathode of the first diode is connected to the power supply ground.

[0014] The drain of the first depletion-type HEMT transistor and the first terminal of the first load together serve as the output terminal of the inverting circuit to output the second logic signal;

[0015] The second terminal of the first load serves as the positive voltage input terminal of the inverting circuit and is connected to the positive voltage power supply to input the positive voltage.

[0016] In one embodiment, the level shifting circuit includes n first level shifting elements, a second resistor, and a third resistor;

[0017] n first level shifting elements are connected in series in phase; n is a positive integer;

[0018] The positive terminal of the first level shifting element is used as the input signal input terminal of the level conversion circuit to receive the input signal;

[0019] The negative terminal of the nth first level shifting element is connected to the first terminal of the second resistor;

[0020] The second end of the second resistor and the first end of the third resistor together serve as the first logic signal output terminal of the level conversion circuit, and are connected to the inverting circuit to output the first logic signal;

[0021] The second end of the third resistor is connected to the power supply ground.

[0022] In one embodiment, the first level shifting element includes a compound-based diode and / or a compound-based HEMT transistor;

[0023] When the first level shifting element includes the compound-based HEMT transistor, the drain of the compound-based HEMT transistor, the source of the compound-based HEMT transistor, or the drain of the compound-based HEMT transistor and the source of the compound-based HEMT transistor are shorted to serve as the negative terminal of the first level shifting element, and the gate of the compound-based HEMT transistor serves as the positive terminal of the first level shifting element.

[0024] In one embodiment, the single power supply is a negative voltage power supply, and both the inverting circuit and the level conversion circuit are connected to the negative voltage power supply, which is configured to provide a negative voltage.

[0025] The inverting circuit is specifically configured to invert the first logic signal based on the depletion-type HEMT transistor according to the negative voltage, so as to output the second logic signal;

[0026] The level conversion circuit is specifically configured to receive the input signal and the negative voltage, and to perform voltage division and level shifting on the input signal according to the negative voltage to output the first logic signal.

[0027] In one embodiment, the inverting circuit includes a second load, a second depletion-type HEMT transistor, a third diode, and a fourth resistor;

[0028] The first end of the fourth resistor serves as the input terminal of the inverting circuit and is connected to the level conversion circuit to input the first logic signal.

[0029] The second terminal of the fourth resistor is connected to the gate of the second depletion-type HEMT transistor, and the source of the second depletion-type HEMT transistor is connected to the positive terminal of the third diode.

[0030] The negative terminal of the third diode serves as the negative voltage input terminal of the inverting circuit and is connected to the negative voltage power supply to receive the negative voltage.

[0031] The drain of the second depletion-type HEMT transistor and the first terminal of the second load together serve as the output terminal of the inverting circuit to output the second logic signal;

[0032] The second terminal of the second load is connected to the power supply ground.

[0033] In one embodiment, the level shifting circuit includes n second level shifting elements, a fifth resistor, and a sixth resistor;

[0034] n second-level shifting elements are connected in series in phase; n is a positive integer;

[0035] The positive terminal of the first second level shifting element serves as the input signal input terminal of the level conversion circuit to receive the input signal;

[0036] The negative terminal of the nth second level shifting element is connected to the first terminal of the fifth resistor;

[0037] The second end of the fifth resistor and the first end of the sixth resistor together serve as the first logic signal output terminal of the level conversion circuit, and are connected to the inverting circuit to output the first logic signal;

[0038] The second end of the sixth resistor serves as the negative voltage input terminal of the level conversion circuit and is connected to the negative voltage power supply to receive the negative voltage.

[0039] In one embodiment, the second level shifting element includes a compound-based diode and / or a compound-based HEMT transistor;

[0040] When the second level shifting element includes the compound-based HEMT transistor, the drain of the compound-based HEMT transistor, the source of the compound-based HEMT transistor, or the drain of the compound-based HEMT transistor and the source of the compound-based HEMT transistor are shorted to serve as the negative terminal of the second level shifting element, and the gate of the compound-based HEMT transistor serves as the positive terminal of the second level shifting element.

[0041] In one embodiment, the compound includes GaAs, GaN, and InP.

[0042] This application also provides an inverter, which includes an odd number of cascaded logic circuits from any of the above embodiments.

[0043] This application also provides a follower, which includes an even number of cascaded logic circuits from any of the above embodiments.

[0044] This application embodiment also provides a composite logic circuit, including a first logic circuit, a second logic circuit, and a third logic circuit, wherein:

[0045] The first logic circuit includes K cascaded logic circuits as described above;

[0046] The second logic circuit includes L cascaded logic circuits as described above;

[0047] The third logic circuit includes M cascaded logic circuits as described above;

[0048] Wherein, the sum of K and L is odd; the sum of K and M is even; and K, L, and M are all positive integers.

[0049] The output terminal of the first logic circuit is connected to the input terminal of the second logic circuit and the input terminal of the third logic circuit, and the input terminal of the first logic circuit is connected to the input signal.

[0050] The beneficial effects of this invention embodiment compared with the prior art are as follows: the level conversion circuit receives the input signal and performs voltage division and level shifting on the input signal to output a first logic signal; the inverting circuit inverts the first logic signal based on a depletion-type HEMT transistor to output a second logic signal, and the inverting circuit is powered by a single power supply; thus, the peripheral power supply circuit of the compound-based pure depletion-type logic circuit is simplified. Attached Figure Description

[0051] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is an example circuit schematic of a compound-based pure depletion logic circuit in the relevant technology.

[0053] Figure 2 A schematic diagram of a compound-based pure depletion logic circuit provided in an embodiment of this application;

[0054] Figure 3 Another schematic diagram of a compound-based pure depletion logic circuit provided in an embodiment of this application;

[0055] Figure 4 An example circuit schematic of a compound-based pure depletion logic circuit provided in an embodiment of this application;

[0056] Figure 5 Another schematic diagram of a compound-based pure depletion logic circuit provided in an embodiment of this application;

[0057] Figure 6 Another example circuit schematic of a compound-based pure depletion logic circuit provided for an embodiment of this application;

[0058] Figure 7 This is a schematic diagram of a composite logic circuit provided in an embodiment of this application. Detailed Implementation

[0059] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0060] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0061] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0062] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0063] Figure 2 A schematic diagram of a compound-based pure depletion logic circuit according to a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0064] The above-mentioned compound-based pure depletion logic circuit includes a level shifting circuit 11 and an inverting circuit 12.

[0065] The level conversion circuit 11 is configured to receive an input signal and perform voltage division and level shifting on the input signal to output a first logic signal.

[0066] The inverter circuit 12, connected to the level conversion circuit 11, is configured to invert the first logic signal based on the depletion-type HEMT transistor to output the second logic signal; the inverter circuit 12 is powered by a single power supply.

[0067] In a specific implementation, the inverter circuit 12 is configured to invert and amplify the first logic signal based on a depletion-type HEMT transistor to output a second logic signal.

[0068] By way of example and not limitation, compounds include GaAs, GaN, and InP.

[0069] In specific implementation, such as Figure 3 As shown, the single power supply is a positive voltage power supply VDD. The inverter circuit 12 can be connected only to the positive voltage power supply VDD, which is configured to provide a positive voltage. Specifically, the inverter circuit 12 is configured to invert the first logic signal based on the positive voltage using a depletion-type HEMT transistor to output a second logic signal.

[0070] Among them, the second logic signal output according to the positive voltage is a positive voltage signal. Therefore, the compound-based pure depletion logic circuit connected to the positive voltage power supply VDD can be used to construct various logic gate circuits, and can also be used as a control circuit to drive compound-based switching devices and / or as a gate drive circuit for active transistors in active circuits.

[0071] Figure 4 An example circuit structure of a compound-based pure depletion logic circuit provided in an embodiment of the present invention is shown. For ease of explanation, only the parts relevant to the embodiment of the present invention are shown, and are described in detail below:

[0072] The inverter circuit 12 includes a first load X1, a first depletion-type HEMT transistor M1, a first diode D1, and a first resistor R1;

[0073] The first end of the first resistor R1 serves as the input terminal of the inverter circuit 12 and is connected to the level conversion circuit 11 to input a first logic signal; the second end of the first resistor R1 is connected to the gate of the first depletion-type HEMT transistor M1, the source of the first depletion-type HEMT transistor M1 is connected to the anode of the first diode D1, and the cathode of the first diode D1 is connected to the power supply ground; the drain of the first depletion-type HEMT transistor M1 and the first end of the first load X1 together serve as the output terminal of the inverter circuit 12 to output a second logic signal; the second end of the first load X1 serves as the positive voltage input terminal of the inverter circuit 12 and is connected to the positive voltage power supply VDD to input a positive voltage.

[0074] The first load X1 can be implemented in two ways. The first implementation is as follows: Figure 4 As shown, it includes a third depletion-type HEMT transistor M3 and a seventh resistor R7; the gate of the third depletion-type HEMT transistor M3 and the first terminal of the seventh resistor R7 together serve as the first terminal of the first load X1, the source of the third depletion-type HEMT transistor M3 is connected to the second terminal of the seventh resistor R7, and the drain of the third depletion-type HEMT transistor M3 serves as the second terminal of the first load X1. A second embodiment includes only the first load resistor Rz1 (not shown in the figure for this embodiment).

[0075] Because of the choke device (first resistor R1), the power consumption is low and the first depletion-type HEMT transistor M1 is protected.

[0076] The level conversion circuit 11 includes n first level shifting elements D2, second resistors R2 and third resistors R3.

[0077] n first level shifting elements D2 are connected in series in phase; n is a positive integer; the positive terminal of the first first level shifting element serves as the input signal input terminal of the level conversion circuit 11 to receive the input signal; the negative terminal of the nth first level shifting element is connected to the first terminal of the second resistor R2; the second terminal of the second resistor R2 and the first terminal of the third resistor R3 together serve as the first logic signal output terminal of the level conversion circuit 11, connected to the inverting circuit 12 to output the first logic signal; the second terminal of the third resistor R3 is connected to the power supply ground. In specific implementations, the arrangement order of the second resistor R2 and the n first level shifting elements D2 can also be determined according to design requirements.

[0078] Because of the choke devices (second resistor R2 and third resistor R3), power consumption can be optimized by adjusting the resistance values ​​of the second resistor R2 and the third resistor R3.

[0079] The first level shifting element D2 includes a compound-based diode and / or a compound-based HEMT transistor.

[0080] When the first level shifting element D2 includes a compound-based HEMT transistor, the drain of the compound-based HEMT transistor, the source of the compound-based HEMT transistor, or the drain of the compound-based HEMT transistor is shorted to the source of the compound-based HEMT transistor to serve as the negative terminal of the first level shifting element D2, and the gate of the compound-based HEMT transistor serves as the positive terminal of the first level shifting element D2.

[0081] The following is based on the working principle. Figure 4 Further explanation is provided below:

[0082] The first logic voltage is the voltage VA at node A. When Vin is greater than or equal to n*Von, the voltage VA at node A satisfies the following formula:

[0083] VA = (Vin - n * Von) * R3 / (R2 + R3) where Von is the on-state voltage of the first level shifting element D2, n is a positive integer, and Vin is the voltage of the input signal.

[0084] Since the current flowing through the first resistor R1 is relatively small, the voltage VB at node B is approximately equal to the voltage VA at node A. Therefore, the voltage transfer characteristics of the inverting circuit are as follows: When the voltage VA at node A increases, and when it exceeds the sum of the threshold voltage of the first depletion-type HEMT transistor M1 and the turn-on voltage of the first diode D1, both the first depletion-type HEMT transistor M1 and the first diode D1 turn on simultaneously, and the voltage of the second logic signal Vout1 output by the inverting circuit 12 begins to decrease. As the voltage VA at node A gradually increases after exceeding the flip point, the voltage of the second logic signal Vout1 output by the inverting circuit 12 gradually approaches the turn-on voltage (low level) of the first diode D1.

[0085] For example, with a positive voltage VDD of 3.3V, a single first level shifting element D2, a first resistor R1 of 384 ohms, a second resistor R2 of 4921 ohms, a third resistor R3 of 9780 ohms, and a seventh resistor R7 of 257 ohms, the circuit design parameters are as follows:

[0086] When the input signal Vin is high, such as 3.3V, the voltage VA of node A is 1.518V, the voltage VB of node B is 1.518V, and the second logic signal Vout1 is 1.141V, thus achieving a low-level output.

[0087] When the input signal Vin is low, such as 0V, the voltage VA of node A is 0V, the voltage VB of node B is 0V, and the second logic signal Vout1 is 3.276V, thus achieving a high-level output.

[0088] It is worth noting that when the output signal Vout1 of the first depletion-type HEMT transistor M1 drops by 10%, the voltage VA of node A is about 0.4V, and the noise margin is low. Therefore, the noise margin is improved by setting n first level shifting elements D2, and the inversion point of the input signal is adjustable by setting the voltage division ratio of the second resistor R2 and the third resistor R3.

[0089] When Vin is less than n*Von, VA = 0V, and the output signal Vout1 of the inverter circuit is high.

[0090] It should be noted that the input signal in this embodiment is compatible with TTL signal, the high level of the input signal is the TTL high level, and the low level of the input signal is the TTL low level; the low level of the second logic signal Vout1 is the conduction voltage of the first diode D1, and the high level of the second logic signal Vout1 is a positive voltage close to VDD.

[0091] In specific implementation, such as Figure 5 As shown, the single power supply is a negative voltage power supply Vss. Both the inverter circuit 12 and the level conversion circuit 11 can be connected only to the negative voltage power supply Vss. The negative voltage power supply Vss is configured to provide a negative voltage. The inverter circuit 12 is specifically configured to invert the first logic signal based on the negative voltage using a depletion-type HEMT transistor to output a second logic signal. The level conversion circuit 11 is specifically configured to receive the input signal and the negative voltage, and to divide and level-shift the input signal based on the negative voltage to output the first logic signal.

[0092] Among them, the second logic signal output according to the negative voltage is a negative voltage signal. Therefore, the compound-based pure depletion logic circuit connected to the negative voltage power supply Vss can be used to construct various logic circuits, and can also be used as a control circuit to drive compound-based switching devices and / or as a gate drive circuit for active transistors in active circuits.

[0093] Figure 6 This paper illustrates another example circuit structure of a compound-based pure depletion logic circuit provided in an embodiment of the present invention. For ease of explanation, only the parts relevant to the embodiments of the present invention are shown, and are described in detail below:

[0094] The inverting circuit 12 includes a second load X2, a second depletion-type HEMT transistor M2, a third diode D3, and a fourth resistor R4.

[0095] The first terminal of the fourth resistor R4 serves as the input terminal of the inverter circuit 12 and is connected to the level conversion circuit 11 to input the first logic signal; the second terminal of the fourth resistor R4 is connected to the gate of the second depletion-type HEMT transistor M2, and the source of the second depletion-type HEMT transistor M2 is connected to the anode of the third diode D3; the cathode of the third diode D3 serves as the negative voltage input terminal of the inverter circuit 12 and is connected to the negative voltage power supply Vss to apply the negative voltage; the drain of the second depletion-type HEMT transistor M2 and the first terminal of the second load X2 together serve as the output terminal of the inverter circuit 12 to output the second logic signal; the second terminal of the second load X2 is connected to the power supply ground.

[0096] The second load X2 can be implemented in two ways. The first implementation is as follows: Figure 6As shown, it includes a fourth depletion-type HEMT transistor M4 and an eighth resistor R8; the gate of the fourth depletion-type HEMT transistor M4 and the first terminal of the eighth resistor R8 together serve as the first terminal of the second load X2, the source of the fourth depletion-type HEMT transistor M4 is connected to the second terminal of the eighth resistor R8, and the drain of the fourth depletion-type HEMT transistor M4 serves as the second terminal of the second load X2. A second embodiment includes only the second load resistor Rz2 (not shown in the figure for this embodiment).

[0097] Because of the choke device (fourth resistor R4), the power consumption can be optimized and the second depletion-type HEMT transistor M2 can be protected by adjusting the resistance value of the fourth resistor R4.

[0098] The level conversion circuit 11 includes n second level shifting elements D4, a fifth resistor R5, and a sixth resistor R6.

[0099] n second-level shifting elements D4 are connected in series in phase; n is a positive integer; the positive terminal of the first second-level shifting element serves as the input signal input terminal of the level conversion circuit 11 to receive the input signal; the negative terminal of the nth second-level shifting element is connected to the first terminal of the fifth resistor R5; the second terminal of the fifth resistor R5 and the first terminal of the sixth resistor R6 together serve as the first logic signal output terminal of the level conversion circuit 11, connected to the inverting circuit 12 to output the first logic signal; the second terminal of the sixth resistor R6 serves as the negative voltage input terminal of the level conversion circuit 11, connected to the negative voltage power supply Vss to receive the negative voltage. In specific implementations, the arrangement order of the fifth resistor R5 and the n second-level shifting elements D4 can also be determined according to design requirements.

[0100] Because of the choke devices (resistor R5 and resistor R6), power consumption can be optimized by adjusting the resistance values ​​of resistor R5 and resistor R6.

[0101] The second level shifting element D4 includes a compound-based diode and / or a compound-based HEMT transistor.

[0102] When the second level shifting element D4 includes a compound-based HEMT transistor, the drain of the compound-based HEMT transistor, the source of the compound-based HEMT transistor, or the drain of the compound-based HEMT transistor is shorted to the source of the compound-based HEMT transistor to serve as the negative terminal of the second level shifting element D4, and the gate of the compound-based HEMT transistor serves as the positive terminal of the second level shifting element D4.

[0103] The following is based on the working principle. Figure 6 Further explanation is provided below:

[0104] The first logic voltage is the voltage VC at node C, and the voltage VC at node C satisfies the following formula:

[0105] VC=(Vin-n*Von-Vss)R6 / (R5+R6)+Vss

[0106] Where Von is the turn-on voltage of the second level shifting element D4, Vss is the negative voltage, n is a positive integer, and Vin is the voltage of the input signal.

[0107] Since the current flowing through the fourth resistor R4 is relatively small, the voltage VD at node D is approximately equal to the voltage VC at node C.

[0108] The voltage transfer characteristics of the inverting circuit are as follows: When the voltage VC at node C increases, and the voltage difference between VC and the negative voltage Vss is greater than the sum of the threshold voltage of the second depletion-type HEMT transistor M2 and the turn-on voltage of the third diode D3, both the second depletion-type HEMT transistor M2 and the third diode D3 turn on simultaneously, and the voltage of the second logic signal Vout2 output by the inverting circuit 12 begins to decrease. As the voltage VC at node C gradually increases after exceeding the flip point, the voltage of the second logic signal Vout2 output by the inverting circuit 12 gradually approaches the sum of the turn-on voltage of the third diode D3 and the negative voltage Vss (low level).

[0109] When (Vin-Vss) is less than n*Von, VC=VSS, and the output signal Vout2 of the inverter circuit is high (approximately 0V).

[0110] It should be noted that the input signal in this embodiment is compatible with TTL signals. The low level voltage of the second logic signal Vout2 is the sum of the conduction voltage of the third diode D3 and the negative voltage Vss (the low level voltage of the second logic signal Vout2 is a negative voltage value), and the high level voltage of the second logic signal Vout2 is approximately 0V.

[0111] For example, if the negative voltage Vss is -4V, there are four second level shifting elements D4, the fourth resistor R4 is 384 ohms, the fifth resistor R5 is 1464 ohms, the sixth resistor R6 is 5731 ohms, and the eighth resistor R8 is 257 ohms, the circuit design parameters are as follows:

[0112] When the input signal Vin is high, such as 3.3V, the voltage VC at node C is -3.1V, the voltage VD at node D is -3.1V, and the second logic signal Vout2 is -2.84V, thus achieving a low-level output.

[0113] When the input signal Vin is low, such as 0V, the voltage VC at node C is -3.9V, the voltage VD at node D is -3.9V, and the second logic signal Vout2 is -0.1V, thus achieving a high-level output.

[0114] It is worth noting that when the output signal of the second depletion-type HEMT transistor M2 drops by 10%, the input signal is about 1V and the voltage VC at node C is about -3.6V. Therefore, by setting n second level shifting elements D4 to adapt to the level of the TTL signal, and by setting the fifth resistor R5 and the sixth resistor R6, the inversion point of the input signal is adjustable.

[0115] This application also provides an inverter, which includes an odd number of cascaded compound-based pure depletion logic circuits as described above.

[0116] This application also provides a follower, which includes an even number of cascaded compound-based pure depletion logic circuits as described above.

[0117] This application also provides a composite logic circuit, such as... Figure 7 As shown, it includes a first logic circuit 10, a second logic circuit 20 and a third logic circuit 30. The output terminal of the first logic circuit 10 is connected to the input terminal of the second logic circuit 20 and the input terminal of the third logic circuit 30. The input terminal of the first logic circuit 10 is connected to the input signal.

[0118] The first logic circuit 10 includes K cascaded compound-based pure depletion logic circuits; the second logic circuit 20 includes L cascaded compound-based pure depletion logic circuits; and the third logic circuit 30 includes M cascaded compound-based pure depletion logic circuits. The sum of K and L is odd; the sum of K and M is even; and K, L, and M are all positive integers.

[0119] The aforementioned composite logic circuit can both invert and follow input signals, enriching its functionality. Furthermore, by using multiple cascaded compound-based pure depletion logic circuits, the transition times for inversion and following are reduced (both rising and falling edge times are shortened), improving their response speed.

[0120] In this embodiment of the invention, the input signal is received through a level conversion circuit, and the input signal is divided and level shifted to output a first logic signal; the inverting circuit inverts the first logic signal based on a depletion-type HEMT transistor to output a second logic signal; the inverting circuit is powered by a single power supply; thus, the external power supply circuit of the compound-based pure depletion-type logic circuit is simplified.

[0121] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0122] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A logic circuit, characterized in that, include: A level conversion circuit is configured to receive an input signal and perform voltage division and level shifting on the input signal to output a first logic signal; An inverting circuit, connected to the level conversion circuit, is configured to invert the first logic signal based on a depletion-mode HEMT transistor to output a second logic signal. The inverting circuit is powered by a single power supply. The logic circuit described therein is a pure depletion logic circuit based on compounds; The single power supply is a positive voltage power supply, the inverting circuit is connected to the positive voltage power supply, and the positive voltage power supply is configured to provide a positive voltage. The inverting circuit is specifically configured to invert the first logic signal based on the positive voltage of the depletion-type HEMT transistor to output the second logic signal. The inverting circuit includes a first load, a first depletion-type HEMT transistor, a first diode, and a first resistor. The first terminal of the first resistor serves as the input terminal of the inverting circuit and is connected to the level conversion circuit to input the first logic signal. The second terminal of the first resistor is connected to the gate of the first depletion-type HEMT transistor, the source of the first depletion-type HEMT transistor is connected to the anode of the first diode, and the cathode of the first diode is connected to the power supply ground. The drain of the depletion-type HEMT transistor and the first terminal of the first load together serve as the output terminal of the inverting circuit to output the second logic signal; the second terminal of the first load serves as the positive voltage input terminal of the inverting circuit and is connected to the positive voltage power supply to input the positive voltage; the first load includes a third depletion-type HEMT transistor and a seventh resistor; the gate of the third depletion-type HEMT transistor and the first terminal of the seventh resistor together serve as the first terminal of the first load, the source of the third depletion-type HEMT transistor is connected to the second terminal of the seventh resistor, and the drain of the third depletion-type HEMT transistor serves as the second terminal of the first load; The level conversion circuit includes n first level shifting elements, a second resistor, and a third resistor; n first level shifting elements are connected in series in phase; n is a positive integer; The positive terminal of the first level shifting element is used as the input signal input terminal of the level conversion circuit to receive the input signal; The negative terminal of the nth first level shifting element is connected to the first terminal of the second resistor; The second end of the second resistor and the first end of the third resistor together serve as the first logic signal output terminal of the level conversion circuit, and are connected to the inverting circuit to output the first logic signal; The second terminal of the third resistor is connected to the power supply ground; or The single power supply is a negative voltage power supply, and both the inverting circuit and the level conversion circuit are connected to the negative voltage power supply. The negative voltage power supply is configured to provide a negative voltage. The inverting circuit is specifically configured to invert the first logic signal based on the depletion-type HEMT transistor according to the negative voltage, so as to output the second logic signal. The inverting circuit includes a second load, a second depletion-type HEMT transistor, a third diode, and a fourth resistor. The first terminal of the fourth resistor serves as the input terminal of the inverting circuit and is connected to the level conversion circuit to input the first logic signal. The second terminal of the fourth resistor is connected to the gate of the second depletion-type HEMT transistor, and the source of the second depletion-type HEMT transistor is connected to the anode of the third diode. The cathode of the third diode serves as the input terminal of the inverting circuit. A negative voltage input terminal is connected to a negative voltage power supply to receive a negative voltage; the drain of the second depletion-type HEMT transistor and the first terminal of the second load together serve as the output terminal of the inverting circuit to output the second logic signal; the second terminal of the second load is connected to the power supply ground; the second load includes a fourth depletion-type HEMT transistor and an eighth resistor; the gate of the fourth depletion-type HEMT transistor and the first terminal of the eighth resistor together serve as the first terminal of the second load, the source of the fourth depletion-type HEMT transistor is connected to the second terminal of the eighth resistor, and the drain of the fourth depletion-type HEMT transistor serves as the second terminal of the second load; The level conversion circuit includes n second level shifting elements, a fifth resistor, and a sixth resistor; n second-level shifting elements are connected in series in phase; n is a positive integer; The positive terminal of the first second level shifting element serves as the input signal input terminal of the level conversion circuit to receive the input signal; The negative terminal of the nth second level shifting element is connected to the first terminal of the fifth resistor; The second end of the fifth resistor and the first end of the sixth resistor together serve as the first logic signal output terminal of the level conversion circuit, and are connected to the inverting circuit to output the first logic signal; The second end of the sixth resistor serves as the negative voltage input terminal of the level conversion circuit and is connected to the negative voltage power supply to receive the negative voltage. The level conversion circuit is specifically configured to receive the input signal and the negative voltage, and to perform voltage division and level shifting on the input signal according to the negative voltage to output the first logic signal.

2. The logic circuit as described in claim 1, characterized in that, The first level shifting element includes a compound-based diode and / or a compound-based HEMT transistor; When the first level shifting element includes the compound-based HEMT transistor, the drain of the compound-based HEMT transistor, the source of the compound-based HEMT transistor, or the drain of the compound-based HEMT transistor and the source of the compound-based HEMT transistor are shorted to serve as the negative terminal of the first level shifting element, and the gate of the compound-based HEMT transistor serves as the positive terminal of the first level shifting element.

3. The logic circuit as described in claim 1, characterized in that, The second level shifting element includes a compound-based diode and / or a compound-based HEMT transistor; When the second level shifting element includes the compound-based HEMT transistor, the drain of the compound-based HEMT transistor, the source of the compound-based HEMT transistor, or the drain of the compound-based HEMT transistor and the source of the compound-based HEMT transistor are shorted to serve as the negative terminal of the second level shifting element, and the gate of the compound-based HEMT transistor serves as the positive terminal of the second level shifting element.

4. The logic circuit as described in claim 1, characterized in that, The compounds include GaAs, GaN, and InP.

5. An inverter, characterized in that, The inverter comprises an odd number of cascaded logic circuits as described in any one of claims 1 to 4.

6. A follower, characterized in that, The follower comprises an even number of cascaded logic circuits as described in any one of claims 1 to 4.

7. A composite logic circuit, characterized in that, It includes a first logic circuit, a second logic circuit, and a third logic circuit, wherein: The first logic circuit includes K cascaded logic circuits as described in any one of claims 1 to 4; The second logic circuit includes L cascaded logic circuits as described in any one of claims 1 to 4; The third logic circuit includes M cascaded logic circuits as described in any one of claims 1 to 4; Wherein, the sum of K and L is odd; the sum of K and M is even; and K, L, and M are all positive integers. The output terminal of the first logic circuit is connected to the input terminal of the second logic circuit and the input terminal of the third logic circuit, and the input terminal of the first logic circuit is connected to the input signal.

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