Multi-channel oversampling noise shaping successive incremental analog-to-digital converter and conversion method

Abstract

The present application discloses a multi-channel oversampling noise shaping successive progressive analog-to-digital converter and a conversion method, comprising a sampling switch group connected to input analog signals one by one, a multi-stage integrator connected through sampling nodes, and a comparator, wherein a feedback circuit for noise shaping successive progressive is arranged between the output end of the comparator and the sampling node; by multiplexing Sar ADC and operational amplifier, the circuit complexity and area are reduced by k times, which helps to reduce costs; by using the same capacitor array, operational amplifier, and comparator, the performance consistency between multiple channels is good, ensuring the consistency of performance of the multi-channel sampling system, and having the characteristics of low power consumption and high performance, which meets many application scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuits, in particular to an analog-to-digital converter, and specifically to a multi-channel oversampling noise shaping successive-step analog-to-digital converter and a conversion method. Background Art

[0002] Analog-to-digital converter, or A / D converter, or ADC for short, usually refers to an electronic component that converts analog signals into digital signals. A common analog-to-digital converter converts an input voltage signal into an output digital signal. Since the digital signal itself has no practical meaning, it only represents a relative size. Therefore, any analog-to-digital converter needs a reference analog quantity as the conversion standard. The more common reference standard is the maximum convertible signal size. Multi-channel analog-to-digital converters (ADCs) are required for multi-signal acquisition, measurement, monitoring and other application scenarios. Multi-channel ADCs can be implemented by a single-chip solution or by multiple chips to measure signals separately. In terms of cost and performance consistency, a single-chip multi-channel solution is generally a better choice. Traditional high-precision ADCs generally use a delta-sigma architecture. This architecture is an oversampling architecture ADC, which generally uses multiple active integrators to achieve noise shaping (noise-shaping) to effectively suppress the quantization noise power within the signal bandwidth. The integrator has a memory effect and cannot be directly used for multiplexing, that is, each signal channel requires an ADC. The successive-addition (SAR) ADC is a Nyquist ADC, and its output codeword is only related to the current conversion result. This architecture can be used for multiplexing more conveniently, and can periodically switch between multiple channels to complete the task of collecting multiple signals. However, the disadvantage of this architecture is that it is limited by the matching accuracy of the digital-to-analog converter (DAC), and its effective accuracy is generally limited to 10 to 12 bits.

[0003] The noise-shaping successive-step (Noise-Shaping SAR) analog-to-digital converter (ADC) is an emerging low-power, high-precision ADC architecture. This hybrid architecture combines the advantages of the two ADCs in a relatively balanced manner: the low power consumption of the charge redistribution SAR ADC and the high precision of noise shaping. Through the quantization of the multi-bit SAR ADC, a portion of the signal-to-noise ratio is obtained more linearly; this reduces the requirements for noise shaping, thereby avoiding the need for a higher loop filter order and / or a higher oversampling rate as in the traditional delta-sigma ADC. By reducing the number of integrators used and the operating frequency of the circuit, this architecture can achieve the advantages of higher performance and lower power consumption. However, because this architecture also has an integrator, the circuit has a memory effect, which is also not a Nyquist property and cannot be directly used in multiplexing scenarios. Summary of the invention

[0004] In order to solve the problems existing in the prior art mentioned in the background technology, the present application provides a multi-channel oversampling noise shaping successive incremental analog-to-digital converter and a conversion method, which are used to reduce the complexity of the overall circuit of the multi-channel ADC, reduce the circuit area, and improve the accuracy and consistency of signal conversion.

[0005] In order to achieve the above purpose, the technical solution adopted in this application is:

[0006] A multi-channel oversampling noise shaping successive progressive analog-to-digital converter comprises a sampling switch group connected to input analog signals one by one, a multi-stage integrator connected through a sampling node, and a comparator, wherein a feedback circuit for noise shaping successive progressive is arranged between the output end of the comparator and the sampling node;

[0007] The successive progressive feedback circuit includes a digital circuit control unit, a mismatch error shaping unit, a feedback switch group and a capacitor array, wherein the digital circuit control unit includes a SAR logic module and a timing generation module for controlling the sampling switch group, the feedback switch group, the mismatch error shaping unit, the multi-stage integrator and the comparator; the mismatch error shaping unit includes a DWA module and an MES module, and a multi-channel multiplexing controller MUX for controlling and selecting any DWAk in the DWA module and any MESk in the MES module; the capacitor array is connected to a reference voltage through the feedback switch group, and the reference voltage is composed of Vrefp, Vcm and Vrefn, wherein Vrefp+Vrefn=2Vcm. It is worth noting that the use of this setting is only one of the options. Without affecting the technical implementation, those skilled in the art can freely define it artificially, as long as it meets the requirements of the invention for successive progressive comparison. The setting of the reference voltage should not be understood as a limitation on the quantization process of the present application.

[0008] As a preferred setting method of the present application, the capacitor array includes a first capacitor array and a second capacitor array, the feedback switch group includes a first feedback switch group and a second feedback switch group, the first capacitor array is connected to the multi-channel multiplexing controller MUX through the first feedback switch group and receives the feedback signal of the MES module; the second capacitor array is connected to the multi-channel multiplexing controller MUX through the second feedback switch group and receives the feedback signal of the DWA module.

[0009] Still further preferably, the MES module further includes a first register for storing a connection mode between a first feedback switch group and a first capacitor array that needs to be configured for any channel.

[0010] Furthermore, the DWA module further includes a second register for storing a connection mode between a second feedback switch group and a second capacitor array that needs to be configured for any channel.

[0011] As a preferred configuration, the first capacitor array is a binary capacitor array, and the second capacitor array is an array of capacitor units with equal capacitance.

[0012] As one of the configurations that can be adopted in the present application, the multi-stage integrator is composed of a first integrator and a second integrator, the first integrator includes a first operational amplifier Amp1 and an integrating capacitor Cint1k, the negative electrode of the integrating capacitor Cint1k is respectively connected to the sampling node through a first path provided with a switch Phak and a second path consisting of a switch Phs1 and a switch Phs1k arranged in series, and is connected to the + input pin of the first operational amplifier Amp1 through the switch Phs1k, the - input pin of the first operational amplifier Amp1 is connected to Vcm, and the output end of the first operational amplifier Amp1 is connected to the positive electrode of the integrating capacitor Cint1k through another independent switch Phs1k;

[0013] The second integrator includes a second operational amplifier Amp2 and an integrating capacitor Cint2k, the negative electrode of the integrating capacitor Cint2k is connected to the positive electrode of the integrating capacitor Cint1k through another switch Phak, and is connected to the output end of the first operational amplifier Amp1 through switches Phs2k and Phs2 connected in series, and is also connected to the + input pin of the second operational amplifier Amp2 through the switch Phs2k, the - input pin of the second operational amplifier Amp2 is connected to Vcm, the output end of the second operational amplifier Amp2 is connected to the inverting input end of the comparator through another switch Phak, and the non-inverting input end of the comparator is connected to Vcm. It is worth noting that the above-mentioned two-stage integrator setting is only one of the optional preferred setting schemes of the multi-stage integrator. According to the above-mentioned disclosed technical content and the technical inspiration of the multi-stage integrator setting, technical personnel in this field can optionally choose a three-stage integrator or a four-stage integrator setting architecture based on actual needs and processing the residual capacitance on the capacitor array after each sampling to reduce the overall error. The working principle is no different from the above two-stage integrator in essence and will not be elaborated here.

[0014] In order to better realize analog-to-digital conversion, the present application also provides an available multi-channel analog-to-digital conversion method, which is specifically implemented by the above-mentioned multi-channel oversampling noise shaping successive incremental analog-to-digital converter, specifically including:

[0015] STP100, sampling steps: During the first sampling, the feedback switch group connects the lower plates of the capacitor array to the Vcm point; the digital circuit control unit sends a sampling signal to trigger any sampling switch Clksk in the sampling switch group connected to the analog input signal Vink to be sampled to be turned on, and the analog signal enters the analog-to-digital converter;

[0016] STP200, progressive steps: Each progressive process includes:

[0017] STP210, comparison steps: Compare the voltage V of the capacitor array through the comparator DAC , the sum of the first integrator output voltage Vout1 and the second integrator output voltage Vout2 and the common mode voltage Vcm and output the result 1 or 0;

[0018] STP220, feedback step: Feedback the result of the comparator 500 to the SAR logic module in the digital circuit control unit 600, and at the same time, input it into DWA1 and MES1 respectively for noise shaping. The SAR logic module changes the feedback switch group to connect the lower plates of the capacitor array to the state of the Vcm point according to the output result 1 or 0, so that the value of Vink+1 input to the comparator 500 after the above sampling is closer to the common mode voltage Vcm;

[0019] STP230, integration step: after multiple repetitions of steps STP100-STP200, the first integrator integrates the residue on the capacitor array and stores it on the integration capacitor Cint1k, and the second integrator integrates the charge on the sampling capacitor CS2 and stores it on the integration capacitor Cint2k;

[0020] And STP300, output step: after looping the above steps STP100-STP200 within the conversion period T set by the timing generation module, the values ​​of the same-direction input terminal and the reverse input terminal of the comparator tend to be equal and finally output, where k∈[1,2,3……k], and the period T is set by the timing generation module.

[0021] Beneficial effects:

[0022] 1. Reusing Sar ADC and operational amplifiers reduces circuit complexity and area by a factor of k, which helps reduce costs.

[0023] 2. Using the same capacitor array, op amp, and comparator, the performance consistency between multiple channels is good, ensuring the consistent performance of the multi-channel sampling system.

[0024] 3. It has the characteristics of low power consumption and high performance, meeting many application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0026] Figure 1 It is the overall framework diagram of the present invention.

[0027] Figure 2 yes Figure 1 Circuit diagram of the .

[0028] Figure 3 This is a schematic diagram of a single conversion operation (the figure shows the kth channel).

[0029] Figure 4 It is a timing diagram of the present invention.

[0030] In the figure: 100-sampling switch group; 200-sampling node; 300-first integrator; 400-second integrator; 500-comparator; 600-digital circuit control unit; 700-mismatch error shaping unit; 800-1-first feedback switch group; 800-2-second feedback switch group; 900-1-first capacitor array; 900-2-second capacitor array. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0033] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0034] In the description of the present application, it should be noted that the terms "first", "second", etc., if appearing in the description of the present application, are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0035] Embodiment 1:

[0036] Combination Figure 1 and Figure 2 As shown, a multi-channel oversampling noise shaping successive incremental analog-to-digital converter includes a sampling switch group 100 connected to the input analog signals one by one, a multi-stage integrator connected through a sampling node 200, and a comparator 500, wherein a feedback circuit for noise shaping successive incremental is arranged between the output end of the comparator 500 and the sampling node 200;

[0037] The successive progressive feedback circuit includes a digital circuit control unit 600, a mismatch error shaping unit 700, a feedback switch group and a capacitor array. The digital circuit control unit 600 includes a SAR logic module and a timing generation module for controlling the sampling switch group 100, the feedback switch group, the mismatch error shaping unit 700, the multi-stage integrator and the comparator 500; the mismatch error shaping unit 700 includes a DWA module and an MES module, and a multi-channel multiplexing controller MUX for controlling and selecting any DWAk in the DWA modules and any MESk in the MES modules; the capacitor array is connected to a reference voltage through the feedback switch group, and the reference voltage is composed of Vrefp, Vcm and Vrefn, wherein Vrefp+Vrefn=2Vcm.

[0038] Working principle:

[0039] like Figure 2 As shown, in this embodiment, for the convenience of explanation, the circuit diagram shown is a single-ended implementation, and the actual circuit is a differential circuit; and under the teaching and inspiration of this embodiment, the architecture disclosed by this embodiment can also be expanded to more integrators, such as the use of three-stage or four-stage integrators, which is also a conventional transformation or selection, and will not be repeated here. When the entire analog-to-digital converter ADC is sampling, the voltage on the capacitor array and the multi-stage integrator of the CDAC (Capacitive DAC) is accumulated and input into the comparator 500 for comparison, and the compared values ​​are respectively subjected to noise shaping through the DWA module and the MES module and are input into the comparator 500 for cyclic comparison by flipping the capacitor array, and finally outputting Dout, thereby achieving the purpose of accurate conversion.

[0040] Beneficial effects:

[0041] Compared with the existing delta-sigma architecture ADC and Nyquist ADC, the multichannel oversampling noise shaping successive progressive analog-to-digital converter (Multichannel Noise-Shaping SAR ADC) provided by the embodiment can reuse the entire digital circuit control unit 600 and CDAC, thereby significantly reducing the complexity of the circuit. Under the premise of reusing the capacitor array of CDAC, the circuit area can be reduced by K times (here k is the number of successive progressive times), greatly reducing the production investment cost without affecting the actual signal conversion accuracy. The multichannel multiplexing controller MUX used in this embodiment controls four MUX modules, such as Figure 2 As shown, MUX1a and MUX1b are used to control the DWA module (Data-Weighted Averaging), and MUX2a and MUX2b are used to control the MES module (Mismatch Error Shaping). In this embodiment, the MESk represents k groups of MES, namely (MES1, MES2, MES3, MES4...MESk), and DWAk represents k groups of DWA, namely (DWA1, DWA2, DWA3, DWA4...DWAk), so that when multiple channels reuse the same capacitor array, the consistency of performance between multiple channels can be guaranteed, and the consistency of sampling system performance can be guaranteed. In this way, the simplicity, reliability and low cost of the circuit are taken into account at the same time, and the power consumption of the circuit is also lower.

[0042] Embodiment 2:

[0043] In conjunction with the instruction manual Figure 1-Figure 4 As shown, this embodiment further refines the circuit structure based on the above-mentioned embodiment 1, as follows: the capacitor array includes a first capacitor array 900-1 and a second capacitor array 900-2, the feedback switch group includes a first feedback switch group 800-1 and a second feedback switch group 800-2, the first capacitor array 900-1 is connected to the multi-channel multiplexing controller MUX through the first feedback switch group 800-1 and receives the feedback signal of the MES module; the second capacitor array 900-2 is connected to the multi-channel multiplexing controller MUX through the second feedback switch group 800-2 and receives the feedback signal of the DWA module. The MES module also includes a first register for storing the connection mode between the first feedback switch group 800-1 and the first capacitor array 900-1 that needs to be configured for any channel.

[0044] Furthermore, the DWA module further includes a second register for storing the connection mode between the second feedback switch group 800-2 and the second capacitor array 900-2 required to be configured for any channel. The first capacitor array 900-1 is a binary capacitor array, and the second capacitor array 900-2 is an array of equal-capacitance capacitor units.

[0045] As one of the configurations that can be adopted in the present application, the multi-stage integrator is composed of a first integrator 300 and a second integrator 400, the first integrator 300 includes a first operational amplifier Amp1 and an integrating capacitor Cint1k, the negative electrode of the integrating capacitor Cint1k is respectively connected to the sampling node 200 through a first path provided with a switch Phak and a second path consisting of a switch Phs1 and a switch Phs1k arranged in series, and is connected to the + input pin of the first operational amplifier Amp1 through the switch Phs1k, the - input pin of the first operational amplifier Amp1 is connected to Vcm, and the output end of the first operational amplifier Amp1 is connected to the positive electrode of the integrating capacitor Cint1k through another independent switch Phs1k;

[0046] The second integrator 400 includes a second operational amplifier Amp2 and an integrating capacitor Cint2k, the negative electrode of the integrating capacitor Cint2k is connected to the positive electrode of the integrating capacitor Cint1k through another switch Phak, and is connected to the output end of the first operational amplifier Amp1 through switches Phs2k and Phs2 connected in series, and is also connected to the + input pin of the second operational amplifier Amp2 through the switch Phs2k, the - input pin of the second operational amplifier Amp2 is connected to Vcm, the output end of the second operational amplifier Amp2 is connected to the inverting input end of the comparator 500 through another switch Phak, and the non-inverting input end of the comparator 500 is connected to Vcm. It is worth noting that the above-mentioned two-stage integrator setting is only one of the optional preferred setting schemes of the multi-stage integrator. According to the above-mentioned disclosed technical content and the technical inspiration of the multi-stage integrator setting, technical personnel in this field can optionally choose a three-stage integrator or a four-stage integrator setting architecture based on actual needs and processing the residual capacitance on the capacitor array after each sampling to reduce the overall error. The working principle is no different from the above two-stage integrator in essence and will not be elaborated here.

[0047] The biggest advantage of adopting the above structure is that multiple channels can reuse CDAC, the first operational amplifier Amp1, the second operational amplifier Amp2, the comparator 500, the SAR logic module and the timing generation module, as well as the second feedback switch group 800-2 for controlling the flipping of the second capacitor array 900-2, and the first feedback switch group 800-1 for controlling the first capacitor array 900-1. Compared with the existing various ADC architecture settings, this structure can realize sequential or periodic conversion in the process of multi-channel analog signal conversion. In the process of converting a certain channel signal, the capacitor array that occupies the most area is structurally shared. In this way, the consistency of conversion performance can be maintained between multiple different channels, avoiding different errors introduced by different capacitor arrays, so that although the conversion results between multi-channel signals adopt the same architecture, there are obvious differences due to the different capacitor arrays; furthermore, the performance consistency of the multi-channel sampling system can be ensured.

[0048] The specific working principle is as follows Figure 4As shown, in the Clks1 phase (specifically, Vin1 is the analog signal input), the entire ADC performs sampling, and then the Pha1 switch is turned on, and the voltages on the Cint11 and Cint21 integration capacitors and the sampled voltages on the capacitor array are accumulated. Since Pha1 is in the on state at this time, the voltage is directly input to the inverting input terminal of the comparator 500. At this time, the comparator 500 compares the sampled voltage inputted at the reverse input terminal with the common-mode voltage Vcm at the forward input terminal, and outputs the result of this comparison (1 or 0), thereby controlling the second feedback switch group 800-2 through DWA1 to disconnect the common-mode voltage Vcm and turn on the reference voltage Vrefp or Vrefn, thereby realizing the flipping of the second capacitor array 900-2; similarly, the first feedback switch group 800-1 is controlled through the MES1 module to disconnect the common-mode voltage Vcm and turn on the reference voltage Vrefp or Vrefn, thereby realizing the flipping of the first capacitor array 900-1. After completing one capacitor flipping, one quantization is completed. The above steps are repeated, and the flipped capacitor array realizes the successive comparison of the input comparator 500, thereby, as each progressive conversion is completed, the final output Dout is generated after the (i+j)-bit quantization is completed. At this time, the phases Phs1 and Phs2 integrate the residual capacitance on the capacitor array (specifically, the first capacitor array 900-1 and the second capacitor array 900-2). It is worth noting that in the phase Phs11, integration is performed on Cint11; in the phase Phs21, integration is performed on Cint21. Similarly, in the phase Phs1k, integration is performed on Cint1k; in the phase Phs2k, integration is performed on Cint2k. In this way, the residuals of different channels can be stored on different capacitors to form noise shaping for each channel. After the integration is completed, the voltage of the residual on the capacitor array on the corresponding integrating capacitor is accumulated through capacitive coupling, thereby preparing for the next noise shaping. Further, under the guidance of the above principles, since only the same operational amplifier (herein referring to the first operational amplifier Amp1 and / or the second operational amplifier Amp2, respectively) is shared, see the attached for details. Figure 2 As shown, similarly, in the Phak phase, the voltages on the Cint1k and Cint2k integration capacitors and the sampled voltages on the capacitor arrays (specifically the first capacitor array 900-1 and the second capacitor array 900-2) are accumulated and input to the comparator 500. At the same time, the corresponding DWAk module and MESk module are selected for the corresponding k channel, and each channel is operated cyclically to complete the high-precision quantization of each channel signal.

[0049] Although according to the above-mentioned sampling, integration, comparison and noise shaping structure, in order to achieve high-precision quantization of the output signal, it is necessary to arrange independent DWAk (specifically including DWA1, DWA2, DWA3, DWA4...DWAk) and MESk modules (specifically including MES1, MES2, MES3, MES4...MESk) for each channel to avoid the mixing of errors between multiple channels due to residual capacitance during multi-channel conversion, which will generate more noise / error and reduce the quantization accuracy. In order to achieve high-precision quantization output between multi-channel signal conversion, it is inevitable that the above-mentioned DWA module and MES module cannot be reused. Only in this way can the in-band mismatch error be suppressed as much as possible and a higher linearity be achieved. Since they are all simple logic circuits, especially when the DWA bit number is low and the MES bit number is high, it can be easily implemented using some logic circuits. Even if the DWA module and MES module are not reused, the overhead is not high. Compared with the technical effect that it can meet the multi-channel precise quantization output, the added cost of the above-mentioned DWA module and MES module is negligible. In this sense, the technical effect achieved by the improvement of its architecture is significant.

[0050] Embodiment 3:

[0051] In order to better realize analog-to-digital conversion, this embodiment provides an available multi-channel analog-to-digital conversion method, which is specifically implemented by using the above-mentioned multi-channel oversampling noise shaping successive incremental analog-to-digital converter, and specifically includes:

[0052] STP100, sampling steps: During the first sampling, the feedback switch group connects the lower plates of the capacitor array to the Vcm point; the digital circuit control unit 600 sends a sampling signal to trigger any sampling switch Clksk in the sampling switch group connected to the analog input signal Vink to be sampled to be turned on, and the analog signal enters the analog-to-digital converter;

[0053] STP200, progressive steps: Each progressive process includes:

[0054] STP210, comparison step: compare the voltage V of the capacitor array through the comparator 500 DAC , the sum of the output voltage Vout1 of the first integrator 300 and the output voltage Vout2 of the second integrator 400 and the common mode voltage Vcm and outputs the result 1 or 0;

[0055] STP220, feedback step: Feedback the result of the comparator 500 to the SAR logic module in the digital circuit control unit 600, and at the same time, input it into DWA1 and MES1 respectively for noise shaping. The SAR logic module changes the feedback switch group to connect the lower plates of the capacitor array to the state of the Vcm point according to the output result 1 or 0, so that the value of Vink+1 input to the comparator 500 after the above sampling is closer to the common mode voltage Vcm;

[0056] STP230, integration step: after multiple repetitions of the above steps STP100-STP200, the first integrator (300) integrates the residue on the capacitor array and stores it on the integration capacitor Cint1k, and the second integrator (400) integrates the charge on the sampling capacitor CS2 and stores it on the integration capacitor Cint2k;

[0057] And STP300, output step: after looping the above steps STP100-STP200 within the conversion period T set by the timing generation module, the values ​​of the same-direction input terminal and the reverse input terminal of the comparator (500) tend to be equal and finally output, where k∈[1,2,3...k].

[0058] In conjunction with the instruction manual Figure 3 As shown, taking k=1 as an example, the analog signal input terminal Vin1 provides an analog signal, the switch Clks1 is turned on, and the sampling state is entered. At this time, the voltage Vtotal at the inverting input terminal of the comparator 500 is Vtotal=V DAC+Vout1+Vout2 is compared with the common-mode voltage Vcm at the positive input terminal and the comparison result is output; at this time, the first noise shaping and progressive steps are entered, and the DWA1 used in the channel corresponding to Vin1 controls the second feedback switch group 800-2 to disconnect the common-mode voltage Vcm and turn on the reference voltage Vrefp or Vrefn, thereby realizing the flipping of the second capacitor array 900-2, and the specific configuration rule of the flipping is determined according to the configuration stored in the second register; similarly, the first feedback switch group 800-1 is controlled by the MES1 module to disconnect the common-mode voltage Vcm and turn on the reference voltage Vrefp or Vrefn, thereby realizing the flipping of the first capacitor array 900-1, and the specific configuration rule of the flipping is determined according to the configuration stored in the first register; after completing one capacitor flipping, one quantization is completed. At this time, the residual capacitance on the capacitor array (specifically the first capacitor array 900-1 and the second capacitor array 900-2) is integrated in the phases Phs1 and Phs2. It is worth noting that the integration is performed on Cint11 in the phase Phs11; the integration is performed on Cint21 in the phase Phs21; similarly, the integration is performed on Cint1k in the phase Phs1k; and the integration is performed on Cint2k in the phase Phs2k. In this way, the residuals of different channels can be stored in different capacitors to form noise shaping for each channel. After the integration is completed, the voltage of the residual on the capacitor array on the corresponding integration capacitor is accumulated through capacitive coupling, so as to prepare for the next noise shaping. The above steps are repeated, and the The capacitor array realizes the successive comparison of the input comparator 500, so that as each progressive conversion is completed, the final output Dout is generated after the quantization of (i+j) bits is completed. It is worth noting that the parameters of the sampling capacitor CS2 should be set / selected according to the actual circuit requirements, especially the CDAC signal-to-noise ratio. Those skilled in the art can flexibly select in the prior art without violating the present invention while taking into account the successive precise quantization and the reduction of quantization noise. The sampling capacitor CS2 is not a fixed value, and under the inspiration of the technical content disclosed in this application, those skilled in the art can have a variety of optional solutions based on the disclosed analog-to-digital converter architecture, which will not be repeated here.

[0059] After completing the conversion of a channel signal, switch Clks1 is turned off and switch Clks2 is turned on. The above process is repeated to perform the same conversion on the analog signal of the input signal Vin2. At the Phs12 phase, it is integrated on Cint12; at the Phs22 phase, it is integrated on Cint22 to complete the above-mentioned successive and gradual operations.

[0060] Similarly, the phase of Phs1k is integrated on Cint1k; the phase of Phs2k is integrated on Cint2k until all analog signals of the K channel are sequentially or periodically accurately quantized, converted and output. This achieves multi-channel analog signal conversion, and the full sharing of CDAC and SAR logic modules. The significant technical effects obtained are as described in the above embodiment, which will not be described in detail here.

[0061] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A multi-channel oversampling noise shaping successive-step analog-to-digital converter, characterized in that: It comprises a sampling switch group (100) connected to the input analog signals one by one, a multi-stage integrator connected via a sampling node (200), and a comparator (500), wherein a feedback circuit for noise shaping is arranged between the output end of the comparator (500) and the sampling node (200); The successive feedback circuit comprises a digital circuit control unit (600), a mismatch error shaping unit (700), a feedback switch group and a capacitor array, wherein the digital circuit control unit (600) comprises a SAR logic module and a timing generation module for controlling the sampling switch group (100), the feedback switch group, the mismatch error shaping unit (700), a multi-stage integrator and a comparator (500); the mismatch error shaping unit (700) comprises a DWA module and an MES module, and a multi-channel multiplexing controller MUX for controlling and selecting any one DWAk in the DWA modules and any one MESk in the MES modules; the capacitor array is connected to a reference voltage through the feedback switch group, the reference voltage consisting of Vrefp, Vcm and Vrefn, wherein Vrefp+Vrefn=2Vcm.

2. The multi-channel oversampling noise shaping successive incremental analog-to-digital converter according to claim 1, characterized in that: The capacitor array comprises a first capacitor array (900-1) and a second capacitor array (900-2); the feedback switch group comprises a first feedback switch group (800-1) and a second feedback switch group (800-2); the first capacitor array (900-1) is connected to a multi-channel multiplexing controller MUX through the first feedback switch group (800-1) and receives a feedback signal from an MES module; the second capacitor array (900-2) is connected to the multi-channel multiplexing controller MUX through the second feedback switch group (800-2) and receives a feedback signal from a DWA module.

3. The multi-channel oversampling noise shaping successive incremental analog-to-digital converter according to claim 2, characterized in that: The MES module also includes a first register for storing a connection mode between a first feedback switch group (800-1) and a first capacitor array (900-1) that needs to be configured for any channel.

4. The multi-channel oversampling noise shaping successive incremental analog-to-digital converter according to claim 2 or 3, characterized in that: The DWA module also includes a second register for storing a connection mode between a second feedback switch group (800-2) and a second capacitor array (900-2) that needs to be configured for any channel.

5. The multi-channel oversampling noise shaping successive incremental analog-to-digital converter according to claim 4, characterized in that: The first capacitor array (900-1) is a binary capacitor array, and the second capacitor array (900-2) is an array of capacitor units with equal capacitance.

6. The multi-channel oversampling noise shaping successive incremental analog-to-digital converter according to claim 5, characterized in that: The multi-stage integrator is composed of a first integrator (300) and a second integrator (400), wherein the first integrator (300) comprises a first operational amplifier Amp1 and an integrating capacitor Cint1k, wherein the negative electrode of the integrating capacitor Cint1k is respectively connected to the sampling node (200) via a first path provided with a switch Phak and a second path consisting of a switch Phs1 and a switch Phs1k which are arranged in series, and is connected to the + input pin of the first operational amplifier Amp1 via the switch Phs1k, the - input pin of the first operational amplifier Amp1 is connected to Vcm, and the output end of the first operational amplifier Amp1 is connected to the positive electrode of the integrating capacitor Cint1k via another independent switch Phs1k; The second integrator (400) comprises a second operational amplifier Amp2 and an integrating capacitor Cint2k, the negative electrode of the integrating capacitor Cint2k is connected to the positive electrode of the integrating capacitor Cint1k via another switch Phak, is connected to the output end of the first operational amplifier Amp1 via a switch Phs2k and a switch Phs2 connected in series, is also connected to the + input pin of the second operational amplifier Amp2 via the switch Phs2k, the - input pin of the second operational amplifier Amp2 is connected to Vcm, the output end of the second operational amplifier Amp2 is connected to the inverting input end of the comparator (500) via another switch Phak, and the non-inverting input end of the comparator (500) is connected to Vcm.

7. A multi-channel analog-to-digital conversion method, characterized in that: The method is implemented by using the multi-channel oversampling noise shaping successive-step analog-to-digital converter as claimed in claim 6, specifically comprising: STP100, sampling steps: during the first sampling, the feedback switch group connects the lower plates of the capacitor array to the Vcm point; the digital circuit control unit (600) sends a sampling signal to trigger any sampling switch Clksk in the sampling switch group connected to the analog input signal Vink to be sampled to be turned on, and the analog signal enters the analog-to-digital converter; STP200, progressive steps: Each progressive process includes: STP210, comparison steps: Compare the voltage V of the capacitor array through the comparator (500) DAC , the sum of the output voltage Vout1 of the first integrator (300) and the output voltage Vout2 of the second integrator (400) and the common mode voltage Vcm and output the result 1 or 0; STP220, feedback step: feeding back the result of the comparator (500) to the SAR logic module in the digital circuit control unit (600), and at the same time, inputting the result into DWA1 and MES1 for noise shaping respectively, and the SAR logic module changes the state of the feedback switch group to connect the lower plates of the capacitor array to the point Vcm according to the output result 1 or 0, so that the value of Vin2 input to the comparator (500) after the above sampling is closer to the common mode voltage Vcm; STP230, integration step: after the above steps STP100-STP220 are repeated multiple times, the first integrator (300) integrates the residue on the capacitor array and stores it on the integration capacitor Cint1k, and the second integrator (400) integrates the charge on the sampling capacitor CS2 and stores it on the integration capacitor Cint2k; And STP300, output step: after looping the above steps STP100-STP230 within the conversion period T set by the timing generation module, the values ​​of the same-direction input terminal and the reverse input terminal of the comparator (500) tend to be equal and finally output, where k∈[1,2,3...k].

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