Direct printing and self-aligned dual patterning of nanosheets

Abstract

A method of forming a semiconductor structure, comprising forming a nanosheet stack comprising alternating layers of sacrificial material and channel material on a substrate, the channel material layers providing nanosheet channels for one or more nanosheet field effect transistors. The method also includes: forming a hard mask stack on the nanosheet stack; and forming a patterned layer on the hard mask stack. The method further includes patterning a photolithography mask over the patterned layer, the photolithography mask defining (i) one or more first regions for directly printing one or more fins having a first width in the nanosheet stack and the substrate; and (ii) one or more second regions for using self-aligned double patterning to set a spacing between two or more fins having a second width in the nanosheet stack and the substrate. The second width is less than the first width.

Description

Technical Field

[0001] This application relates to semiconductors and, more particularly, to techniques for forming semiconductor structures. Background Art

[0002] Semiconductors and integrated circuit chips have become ubiquitous in many products, especially as they continue to reduce cost and size. There is a continuing desire to reduce the size of structural features and / or provide a greater number of structural features for a given chip size. Generally, miniaturization allows for improved performance at lower power levels and lower costs. This technology is at or near atomic-scale scaling for certain micro-devices such as logic gates, field effect transistors (FETs), and capacitors. Summary of the Invention

[0003] Embodiments of the present invention provide techniques for forming both direct-print and self-aligned double-patterning nanosheets using the same mask.

[0004] In one aspect of the present invention, a method of forming a semiconductor structure includes: forming a nanosheet stack including alternating layers of sacrificial material and channel material over a substrate, the channel material layers providing nanosheet channels for one or more nanosheet field effect transistors. The method further includes: forming a hard mask stack over the nanosheet stack; and forming a patterned layer over the hard mask stack. The method further includes patterning a photolithography mask over the patterned layer, the photolithography mask defining (i) one or more first regions for directly printing one or more fins having a first width in the nanosheet stack and the substrate; and (ii) one or more second regions for setting a spacing between two or more fins having a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.

[0005] In another aspect, a method of forming a semiconductor structure includes: forming a nanosheet stack including alternating layers of sacrificial material and channel material over a substrate, the layers of the channel material providing nanosheet channels for one or more nanosheet field effect transistors. The method further includes: forming a hard mask stack over the nanosheet stack; and forming a patterned layer over the hard mask stack. The method further includes patterning a photolithography mask over the patterned layer, the photolithography mask covering (i) one or more first regions of a top surface of the patterned layer for directly printing one or more fins having a first width in the nanosheet stack and the substrate, and (ii) the patterned layer for setting a spacing between two or more fins having a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.

[0006] In another aspect, a method of forming a semiconductor structure includes: forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of the channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method further includes: forming a hard mask stack over the nanosheet stack; and forming a patterned layer over the hard mask stack. The method further includes patterning a photolithography mask over the patterned layer, the photolithography mask using self-aligned double patterning to expose (i) one or more first regions of the top surface of the patterned layer that are for directly printing one or more fins having a first width in the nanosheet stack and the substrate, and (ii) one or more second regions of the top surface of the patterned layer that are for setting a spacing between two or more fins having a second width in the nanosheet stack and the substrate. The second width is less than the first width.

[0007] In another aspect, a semiconductor structure includes a substrate and a nanosheet stack disposed over the substrate, the nanosheet stack including alternating layers of a sacrificial material and a channel material, the layers of the channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The semiconductor structure further includes a hard mask stack disposed over the nanosheet stack and a patterned layer disposed over the hard mask stack. The semiconductor structure further includes a photolithography mask disposed over the patterned layer, the photolithography mask defining (i) one or more first regions that are for directly printing one or more fins having a first width in the nanosheet stack and the substrate; and (ii) one or more second regions that are for setting a spacing between two or more fins having a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A side cross-sectional view of a semiconductor stack according to an embodiment of the present invention is shown.

[0009] Figure 2 A side cross-sectional view of the structure after patterning a photolithography mask according to an embodiment of the present invention is shown. Figure 1 is shown.

[0010] Figure 3 A side cross-sectional view of the structure after etching an exposed portion of the patterned layer and removing the photolithography mask according to an embodiment of the present invention is shown. Figure 2 is shown.

[0011] Figure 4Shows a side cross-sectional view of the structure after forming the spacer material according to an embodiment of the present invention. Figure 3

[0012] Figure 5 Shows a side cross-sectional view of the structure after the spacer material is re-etched according to an embodiment of the present invention. Figure 4

[0013] Figure 6 Shows a side cross-sectional view of the structure after patterning the blocking mask and removing the exposed patterned mandrel according to an embodiment of the present invention. Figure 5

[0014] Figure 7 Shows a side cross-sectional view of the structure after removing the blocking mask according to an embodiment of the present invention. Figure 6

[0015] Figure 8 Depicts a side cross-sectional view of the structure after patterning an additional blocking mask and removing the exposed portion of the spacer material according to an embodiment of the present invention. Figure 7

[0016] Figure 9 Shows a side cross-sectional view of the structure after removing the additional blocking mask according to an embodiment of the present invention. Figure 8

[0017] Figure 10 Shows a side cross-sectional view of the structure after etching the top hard mask layer according to an embodiment of the present invention. Figure 9

[0018] Figure 11 Shows a side cross-sectional view of the structure after removing the remaining patterned mandrel according to an embodiment of the present invention. Figure 10

[0019] Figure 12 Shows a side cross-sectional view of the structure after etching the remaining spacer material and the topmost remaining hard mask layer according to an embodiment of the present invention. Figure 11

[0020] Figure 13 Shows a side cross-sectional view of the structure after etching the last hard mask layer according to an embodiment of the present invention. Figure 12

[0021] Figure 14 Depicts a side cross-sectional view of the structure after opening the liner layer and etching the exposed portion of the nanosheet stack and a portion of the substrate according to an embodiment of the present invention. Figure 13

[0022] Figure 15 ​​​​​​​​​​​Shows a side cross-sectional view of the structure after patterning a lithography mask according to an embodiment of the present invention. Figure 1 of the structure.

[0023] Figure 16 Shows a side cross-sectional view of the structure after removing the exposed portion of the patterned layer and removing the lithography mask according to an embodiment of the present invention. Figure 15 of the structure.

[0024] Figure 17 Depicts a side cross-sectional view of the structure after filling and etch-back of an oxide material according to an embodiment of the present invention. Figure 16 of the structure.

[0025] Figure 18 Depicts a side cross-sectional view of the structure after patterning a blocking mask to expose a portion of the oxide material according to an embodiment of the present invention. Figure 17 of the structure.

[0026] Figure 19 Depicts a side cross-sectional view of the structure after removing the exposed portion of the oxide material and after removing the blocking mask according to an embodiment of the present invention. Figure 18 of the structure.

[0027] Figure 20 Depicts a side cross-sectional view of the structure after depositing and etch-back of spacers according to an embodiment of the present invention. Figure 19 of the structure.

[0028] Figure 21 Shows a side cross-sectional view of the structure after removing the remaining portion of the patterned layer according to an embodiment of the present invention. Figure 20 of the structure.

[0029] Figure 22 Depicts a side cross-sectional view of the structure after opening the top hard mask layer according to an embodiment of the present invention. Figure 21 of the structure.

[0030] Figure 23 Depicts a side cross-sectional view of the structure after etching the exposed portion of the nanosheet stack and a portion of the substrate according to an embodiment of the present invention. Figure 22 of the structure. Detailed Description

[0031] The illustrative embodiments of the present invention may be described herein in the context of an illustrative method for forming both direct print and self-aligned double-patterned nanosheets using the same mask. However, it should be understood that the embodiments of the present invention are not limited to the illustrative method, apparatus, system, and device, but are more broadly applicable to other suitable methods, apparatus, systems, and devices.

[0032] A FET is a transistor having a source, a gate, and a drain and having an operation that depends on the flow of majority carriers along a channel that extends between the source and the drain through the gate. The current through the channel between the source and the drain can be controlled by a lateral electric field under the gate. The length of the gate determines the speed at which the FET switches and can be approximately the same as the length of the channel, such as the distance between the source and the drain.

[0033] In some FETs, more than one gate or a multi-gate arrangement can be used to control the channel. Multi-gate FETs are promising candidates for scaling complementary metal oxide semiconductor (CMOS) FET technology. However, the smaller size associated with multi-gate FETs (compared to single-gate FETs) requires performance issues with greater control over such things as short-channel effects, punch-through, metal oxide semiconductor (MOS) leakage current, and parasitic resistance present in multi-gate FETs.

[0034] Different techniques can be used to reduce the size of a FET. One technique is by using a finned channel in a FinFET device. Prior to the emergence of FinFET arrangements, CMOS devices were generally substantially planar along the surface of a semiconductor substrate, except for the FET gate disposed on top of the channel. FinFETs utilize a vertical channel structure, increasing the surface area of the channel exposed to the gate. Thus, in a FinFET structure, the gate can more effectively control the channel because the gate extends over more than one side or surface of the channel. In some FinFET arrangements, the gate surrounds three surfaces of a three-dimensional channel rather than being disposed only on the top surface of a conventional planar channel.

[0035] Another technique useful for reducing the size of a FET is by using stacked nanosheet channels formed on a semiconductor substrate. The stacked nanosheets can be two-dimensional nanostructures, such as sheets having a thickness range on the order of 1 to 100 nanometers (nm). Nanosheets and nanowires are viable options for scaling down to 7 nm and beyond. The general process flow for forming a nanosheet stack involves removing a sacrificial layer that can be formed of silicon germanium (SiGe) between sheets of a channel material that can be formed of silicon (Si).

[0036] Process options for nanosheet printing can rely on direct printing with a single mask, or direct printing and self-aligned double patterning (SADP) with a two-mask processing solution. For small nanosheet widths used in some devices (e.g., static random access memory (SRAM) structures), the variability generated with direct printing processes may not be sufficient for device operation. As an example, when the dimensions approach the fin width, SADP may be required. However, nanosheet stacks offer different advantages that enable the use of different device widths. Multiple mask solutions (e.g., for direct printing and SADP) are problematic because multiple masks result in overlap (OL) degradation. This OL degradation can be partially attributed to split levels that cause downstream effects (e.g., in parasitic capacitance) for different device features (e.g., gate and source / drain coverage, etc.).

[0037] As described above, some device structures (such as SRAM structures) benefit from varying nanosheet widths. SRAM is a type of memory device that provides high speed, low power consumption, and simple operation. Different from dynamic random access memory (DRAM), SRAM does not require periodic refreshing of the stored data and has a straightforward design. SRAM cells can be formed using different numbers of transistors.

[0038] The six-transistor (6T) SRAM cell is widely used as the main memory in microprocessor circuits. The 6T SRAM cell can include a first n-type FET device (nFET) connected to a first bit line node (BL), a first output node (Q), and a word line node (WL). The second nFET device of the 6T SRAM cell is connected to the Q node, a ground node (e.g., VSS), and a second output node (Q’). The first p-type FET device (pFET) is connected to the Q node, the Q’ node, and a voltage source or power supply node (e.g., VDD). The second pFET device is connected to the VDD node, the Q node, and the Q’ node. The third nFET device is connected to the VSS node, the Q node, and the Q’ node. The fourth nFET device is connected to the second bit line node (BLB), the WL node, and the Q’ node. The first and fourth nFET devices are the pass gate (PG) transistors of the 6T SRAM cell, the second and third nFET devices are the pull-down (PD) transistors of the 6T SRAM cell, and the first and second pFET devices are the pull-up (PU) transistors of the 6T SRAM cell.

[0039] In a 6T SRAM cell formed using nanosheet transistors, it may be desirable to use different nanosheet widths for the various nFET and pFET devices in the cell. For example, for the nFET devices of the 6T SRAM cell, the nanosheet width may be larger than for the pFET devices of the 6T SRAM cell. However, it should be understood that this is not a requirement, and the embodiments are not limited to forming a smaller nanosheet width for the pFET than for the nFET devices. Further, the techniques described herein are not limited to use in forming SRAM structures, but are more generally applicable to forming nanosheet FETs in which different nanosheet widths are desired.

[0040] A description will now be given Figures 1 - 23 of an illustrative process for forming nanosheets of different widths using both direct printing and SADP using the same mask in more detail.

[0041] Figure 1 A side cross-sectional view 100 of a semiconductor stack is shown, which includes a substrate 102, a nanosheet stack including alternating layers 104 and 106 of sacrificial material and channel material, a substrate layer 108, hard mask layers 110, 112, and 114, and a patterned layer 116.

[0042] The substrate 102 may be a semiconductor structure formed of bulk silicon (Si), but other suitable materials may also be used, such as various silicon-containing materials. Illustrative examples of silicon-containing materials suitable for the substrate 102 include, but are not limited to, Si, silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), polysilicon, epitaxial silicon, amorphous silicon, and multi-layers thereof. Although silicon is the main semiconductor material used in wafer fabrication, alternative semiconductor materials may be employed, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), cadmium telluride (CdTe), and zinc selenide (ZnSe). In alternative embodiments, the substrate 102 may be a silicon-on-insulator (SOI) wafer. As is known in the art, an SOI wafer includes an SOI layer separated from the substrate by a buried insulator. Suitable substrate materials include, but are not limited to, Si, strained Si, silicon carbide (SiC), Ge, SiGe, SiGeC, Si alloys, Ge alloys, GaAs, indium arsenide (InAs), indium phosphide (InP), or any combination thereof. Suitable dielectric materials for the buried insulator include, but are not limited to, oxide materials, such as silicon dioxide (SiO2). When the buried insulator is an oxide, the buried insulator may also be referred to as a buried oxide or BOX.

[0043] The substrate 102 may have a width or a horizontal thickness (in the X-X' direction) that varies as needed (e.g., based on the number of device structures to be formed). The substrate 102 may have a height or a vertical thickness (in the Y-Y' direction) ranging from 300 micrometers (μm) to 1000 μm.

[0044] A nanosheet stack including alternating layers of a sacrificial material 104 and a channel material 106 is formed over the substrate 102. Although Figure 1 an example is shown where there are three sacrificial layers 104 and three channel layers 106 in the nanosheet stack, it should be understood that the nanosheet stack may include more or fewer alternating layers of the sacrificial material and the channel material.

[0045] The sacrificial layer 104 may be formed of any suitable material that can be selectively etched relative to the channel material 106. If the channel layer 106 is Si, the sacrificial layer 104 may be SiGe. If the channel layer 106 is indium gallium arsenide (InGaAs), the sacrificial layer 104 may be indium aluminum arsenide (InAlAs). Various other combinations of III-V materials may be used. The material of the sacrificial layer 104 is a material that can be selectively removed relative to the material of the channel layer 106. The sacrificial layer 104 and the channel layer 106 may each have a thickness in the range of 4 nm to 15 nm. The nanosheet stack of the sacrificial layer 104 and the channel layer 106 may be epitaxially grown over the substrate 102.

[0046] A liner layer 108 is formed over the nanosheet stack as shown (e.g., such as using chemical vapor deposition (CVD), physical vapor deposition (PVD), or another suitable oxide deposition process). The liner layer 108 may be formed of an oxide such as silicon dioxide (SiO2). The liner layer 108 may have a height or a vertical thickness (in the Y-Y' direction) in the range of 1 nm to 10 nm.

[0047] Hard mask layers 110, 112, and 114 are formed over liner layer 108. In some embodiments, hard mask layers 110 and 114 are nitride materials such as silicon nitride (SiN), while hard mask layer 112 is an oxide material such as SiO2. In such a case, hard mask layers 110, 112, and 114 together provide a nitride-oxide-nitride (NON) hard mask. The hard mask layers 110, 112, and 114 can be formed using high density plasma (HDP) CVD (HDPCVD), plasma enhanced CVD (PECVD), CVD, etc. Hard mask layer 110 can have a height or vertical thickness (in the Y-Y' direction) in the range of 10 nm to 50 nm. Hard mask layer 112 can have a height or vertical thickness (in the Y-Y' direction) in the range of 10 nm to 50 nm. Hard mask layer 114 can have a height or vertical thickness (in the Y-Y' direction) in the range of 10 nm to 50 nm.

[0048] Patterned layer 116 is formed over hard mask layer 114. Patterned layer 116 can be formed of amorphous silicon (a-Si) or another suitable material such as amorphous carbon (a-C). Patterned layer 116 can be formed using any suitable deposition process such as CVD, PVD, etc. Patterned layer 116 can have a height or vertical thickness (in the Y-Y' direction) in the range of 10 nm to 200 nm.

[0049] Figure 2 is shown Figure 1 The structure of is then lithographically patterned and etched to form a side cross-sectional view 200 of a photomask having portions 118-1, 118-2, and 118-3 (collectively photomask 118) over patterned layer 116 as shown. Photomask 118 can be formed of photoresist. Photomask 118 can have a height or vertical thickness (in the Y-Y' direction) in the range of 20 nm to 1000 nm.

[0050] The width or horizontal thickness (in the X-X' direction) of photomask portions 118-1 and 118-3 can be in the range of 5 nm to 2000 nm. After the processing described below, photomask portions 118-1 and 118-3 provide direct print control of the width of nanosheets for underlying device structures. For example, photomask portions 118-1 and 118-3 can be used to control the device width of underlying n-type FETs (nFETs) formed from an underlying nanosheet stack.

[0051] The width or horizontal thickness (in the X-X' direction) of the photolithography mask portion 118-2 can range from 5 nm to 200 nm. The photolithography mask portion 118-2 provides SADP control of the width of the nanosheets for the following device structure after the processes described below. For example, the photolithography mask portion 118-2 can be used to control the device width of the underlying p-type FET (pFET) formed from the underlying nanosheet stack.

[0052] As will be described in further detail below, Figure 2 the number and size of the portions of the photolithography mask 118 in are used for a specific arrangement of forming nanosheet FETs from the underlying nanosheet stack (e.g., a pair of nFET devices using direct printing with the photolithography mask portions 118-1 and 118-3, and a pair of pFET devices using SADP with the photolithography mask portion 118-2). It should be understood that various other combinations of forming nanosheet FETs with different widths can be formed using different numbers and sizes of mask layers.

[0053] Figure 3 shows the Figure 2 side cross-sectional view 300 of the structure after the etched portion of the patterned layer 116 exposed through the photolithography mask 118 (e.g., using a-Si reactive ion etching (RIE)). Then the photolithography mask 118 is removed. As a result, the mandrels 116-1, 116-2, and 116-3 of the patterned layer 116 are retained.

[0054] Figure 4 shows the Figure 3 side cross-sectional view 400 of the structure after forming the spacer material 120. Atomic layer deposition (ALD) or other suitable processes can be used to form the spacer material 120. The spacer material 120 can be formed of an oxide such as a metal oxide, SiO2, etc. The spacer material 120 can have a uniform thickness in the range of 5 nm to 60 nm. The thickness of the spacer material 120 controls the size of the FET (e.g., pFET) formed from the underlying nanosheet stack, as described in further detail below.

[0055] Figure 5 shows the Figure 4 side cross-sectional view 500 of the structure where sidewall spacers 120' are generated on the sidewalls of the patterned mandrels 116-1, 116-2, and 116-3 after the spacer material 120 is etched back.

[0056] Figure 6 shows theFigure 5 Side cross-sectional view 600 of the structure. This step can be referred to as the "pFET opening" step, in which the spacer material 120' exposed by the blocking mask 122 is used to form a pFET device from the underlying nanosheet stack (e.g., using SADP). The blocking mask 122 can be formed of a suitable organic planarization layer (OPL) material using spin coating or other suitable processes. The height or vertical thickness of the blocking mask 122 (in the Y-Y' direction) can be in the range of 100 nm to 1000 nm. Figure 6 The structure is further shown after removing the exposed patterned mandrel 116-2, for example, using reactive ion etching (RIE).

[0057] Figure 7 Shown is after removing the blocking mask 122 Figure 6 Side cross-sectional view 700 of the structure. The blocking mask 122 can be removed using dry ashing, wet cleaning, etc.

[0058] Figure 8 Side cross-sectional view 800 is shown after patterning another blocking mask 124 to cover the spacer material 120' around the removed patterned mandrel 116-2, exposing the patterned mandrels 116-1 and 116-3, and the spacer material 120' on the sidewalls of the patterned mandrels 116-1 and 116-3. The blocking mask 124 can be formed of a material similar to the blocking mask 122, have a similar process, and have a similar size (in the Y-Y' direction). This step can be referred to as the "nFET opening" step, in which the patterned mandrels 116-1 and 116-2 are used to directly print an nFET device from the underlying nanosheet stack. Figure 8 Also shown is removing the spacer material 120' around the sidewalls of the patterned mandrels 116-1 and 116-3.

[0059] Figure 9 Shown is after removing the blocking mask 124 Figure 8 Side cross-sectional view 900 of the structure. The blocking mask 124 can be removed using a process similar to that described above for the removal of the blocking mask 122.

[0060] Figure 10 Shown is after etching the hard mask layer 114 exposed by the remaining patterned mandrels 116-1 and 116-3 and the remaining spacer sidewalls 120'. Figure 9 Side cross-sectional view 1000 of the structure. The hard mask layer 114 can be etched using RIE or other suitable processes. Thus, only the hard mask layer 114' remains under the patterned mandrels 116-1 and 116-3 and the remaining sidewall spacers 120'.

[0061] Figure 11 Side cross-sectional view 1100 of the structure after removal of patterned mandrels 116-1 and 116-3 is shown. The patterned mandrels 116-1 and 116-3 can be removed using a process similar to the process described above for the removal of the patterned mandrel 116-2. Figure 10

[0062] Figure 12 Side cross-sectional view 1200 of the structure after etching the remaining sidewall spacers 120’ and hard mask layer 112 is shown, such that the hard mask layer 112’ remains only under the hard mask layer 114’. As described above, both the hard mask layer 112 and the sidewall spacers 120’ can be formed of an oxide and can be removed using RIE or other suitable processes. Figure 11

[0063] Figure 13 Side cross-sectional view 1300 of the structure after etching the hard mask layer 110 and exposing the liner layer 108 as shown is shown, such that the hard mask layer 110’ remains only under the hard mask layer 112’. The hard mask layer 110 can be etched using a process similar to the process described above for the etching of the hard mask layer 114. This step also removes the remaining hard mask layer 114’, which, as described above, can be formed of the same material (e.g., nitride) as the hard mask layer 110. Figure 12

[0064] Figure 14 Side cross-sectional view 1400 of the structure after the liner layer 108 is opened and the exposed portion of the nanosheet stack is etched into a portion of the substrate 102 is shown. The liner layer 108, which can be formed of an oxide, can be opened using a process similar to the process described above for the etching of the hard mask layer 112. This step also removes the remaining hard mask layer 112’. Figure 13

[0065] The sacrificial layer 104 and the channel layer 106 of the nanosheet stack together with the substrate 102 can be etched using RIE or another suitable process, such that portions 104’, 106’ and 102’ of these layers remain as shown. Etching the substrate 102 to form the substrate 102’ results in the formation of fins 103-1 to 103-4 above the substrate 102’ and under the remaining portions of the sacrificial layer 104’ and the channel layer 106’ of the nanosheet stack.

[0066] As described above, in some embodiments, fins 103-1 and 103-4 can be used to form nFET nanosheet transistors, while fins 103-2 and 103-3 are used to form pFET nanosheet transistors. Advantageously, the use of direct printing for fins 103-1 and 103-4 and the use of SADP for fins 103-2 and 103-3 require only a single lithography mask for the placement of the main defining features, thereby reducing the OL penalty reduction or degradation that would otherwise affect gate and source / drain patterning (e.g., affecting the parasitic capacitance of the resulting structure). Further, such techniques allow for the formation of devices with different nanosheet widths, enabling further scaling of various devices (e.g., including SRAM structures).

[0067] Figures 15 - 23 Another process is shown for forming nanosheet devices of different widths with respect to the Figure 1 structure using both direct printing and SADP. While Figures 2 - 14 depicts a "positive" tone process for forming the Figure 14 structure, Figures 15 - 23 depicts a "negative" tone process for forming the Figure 23 structure.

[0068] Figure 15 FIG. Figure 1 1500 shows a side cross-sectional view of the

[0069] Figure 16 structure after patterning lithography mask 1518, which can be formed of a material similar to that described above with respect to lithography mask 118 and with a similar dimension (in the Y-Y' direction). Although lithography mask 118 provides a positive tone for defining where the underlying patterned layer 116 will remain (e.g., patterned mandrels 116-1, 116-2, and 116-3), lithography mask 1518 provides a negative tone for defining where the underlying patterned layer 116 will remain after the further processing described below. Figure 3 Figure 15 Figure 15 FIG. 1600 shows a side cross-sectional view of the

[0070] Figure 17 structure resulting in patterned mandrels 1516 as shown after removing the exposed portions of the patterned layer 116 (e.g., using a process similar to that described above with reference to Figure 16Side cross-sectional view 1700 of the structure. The oxide material 1517 can be formed using spin coating, deposition filling, or other suitable processes to overfill the space formed by removing or etching the exposed portion of the patterned layer 116 (e.g., to fill the space between the patterned mandrels 1516). Etch back is used to planarize the oxide material 1517 to match the top surface of the patterned mandrels 1516. The oxide material 1517 can include silicon oxide (SiOx), metal oxides, etc.

[0071] Figure 18 shows after patterning the block mask 1519 Figure 17 Side cross-sectional view 1800 of a structure with the blocking mask exposing a portion of oxide material 1517 in the middle of the structure (e.g., where a pFET device will be formed from an underlying nanosheet stack as described above). Blocking mask 1519 can be formed of similar materials, using similar processing and having similar dimensions (in the Y-Y' direction) as blocking masks 122 and 124.

[0072] Figure 19 shows the exposed portion of oxide layer 1517 after removal so that oxide layer 1517' remains Figure 18 Side cross-sectional view of structure 1900. Block mask 1519 is then removed using a process similar to that described above with respect to the removal of block masks 122 and 124.

[0073] Figure 20 shows after deposition and etch-back of spacer material 1520 Figure 19 Side cross-sectional view of structure 2000. Spacer material 1520 may be formed of similar materials and similar dimensions as described above with respect to spacer material 120.

[0074] Figure 21 Shown after removal of patterned mandrel 1516 Figure 20 Side cross-sectional view 2100 of the structure using processing similar to that described above with respect to removing patterned layer 116 and patterned mandrels 116-1, 116-2, and 116-3.

[0075] Figure 22 shows the hard mask layers 114, 112 and 110 after opening through the remaining oxide layer 1517' and the spacer material 1520 exposed Figure 21 Side cross-sectional view 2200 of the structure. The exposed portions of the hard mask layers 114, 112, and 110 may be used in conjunction with the above Figures 9 - 13 Removal of the liner layer 108 is also performed using a process similar to that described above for etching these layers. Thus, Figure 22The structures respectively include the remaining portions 1508, 1510, and 1512 of the liner layer 108, the hard mask layer 110, and the hard mask layer 112.

[0076] Figure 23 Shown is a side cross-sectional view 2300 of the structure after etching the exposed portions of the nanosheet stack into a portion of the substrate 102 such that portions 1506, 1504, and 1502 are respectively retained in the channel layer 106, the sacrificial layer 104, and the substrate 102. Figure 22 This forms fins 1503-1, 1503-2, 1503-3, and 1504-4 (collectively referred to as fins 1504) similar to the fin 103. The sacrificial layer 104 and the channel layer 106 of the nanosheet stack together with the substrate 102 can be etched using a process similar to that described above with respect to Figure 14 Shown.

[0077] Similar to Figure 14 In the structure of, fins 1503-1 and 1503-4 can be used to form nFET nanosheet transistors, while fins 1503-2 and 1503-3 are used to form pFET nanosheet transistors. Advantageously, the use of direct printing for fins 1503-1 and 1503-4 and the use of SADP for fins 1503-2 and 1503-3 only require a single lithography mask for the placement of the main defining features, thereby reducing or degrading the OL penalty that would otherwise affect gate and source / drain patterning (e.g., affecting the parasitic capacitance of the resulting structure). Further, such techniques allow the formation of devices with different nanosheet widths, enabling further scaling of various devices (e.g., including SRAM structures).

[0078] Figure 14 And 23 The structures shown in can be subjected to different additional processes to form nanosheet FETs. This can include, for example, the formation of shallow trench isolation (STI) regions around the fins 103 / 1503, the formation and patterning of dummy gate structures, the epitaxial growth of source / drain regions, the formation of inner spacers, the removal of the sacrificial layer using a replacement metal gate (RMG) process to form the gate structure, the formation of contacts to the gate structure and the source / drain regions, etc.

[0079] In some embodiments, a method of forming a semiconductor structure includes: forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of the channel material providing nanosheet channels for one or more nanosheet FETs. The method further includes: forming a hard mask stack over the nanosheet stack; and forming a patterned layer over the hard mask stack. The method further includes patterning a photolithography mask over the patterned layer, the photolithography mask defining (i) one or more first regions for directly printing one or more fins having a first width in the nanosheet stack and the substrate; and (ii) one or more second regions for setting a spacing between two or more fins having a second width in the nanosheet stack and the substrate using SADP. The second width is less than the first width.

[0080] In some embodiments, the photolithography mask is patterned on the patterned layer such that the photolithography material covers the one or more first regions and the one or more second regions. In other embodiments, the photolithography mask is patterned on the patterned layer such that the photolithography material exposes the one or more first regions and the one or more second regions.

[0081] The hard mask stack may include a liner oxide layer and a NON hard mask stack over the liner oxide layer. The patterned layer may comprise a-Si.

[0082] In some embodiments, a method of forming a semiconductor structure includes: forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of the channel material providing nanosheet channels for one or more nanosheet FETs. The method further includes: forming a hard mask stack over the nanosheet stack; and forming a patterned layer over the hard mask stack. The method further includes patterning a photolithography mask above the patterned layer, the photolithography mask covering (i) one or more first regions of a top surface of the patterned layer for directly printing one or more fins having a first width in the nanosheet stack and the substrate; and (ii) one or more second regions of the top surface of the patterned layer for setting a spacing between two or more fins having a second width in the nanosheet stack and the substrate using SADP. The second width is less than the first width.

[0083] The method may further include etching portions of the patterned layer exposed by the photolithography mask to form a plurality of patterned mandrels, and removing the photolithography mask.

[0084] The method may further include: depositing a spacer material over a portion of the top surface of the plurality of patterned mandrels and the hard mask stack, the spacer material being exposed by etching the portions of the patterned layer exposed by the lithography mask; and etch-back the spacer material to remove the spacer material from the top surface of the plurality of patterned mandrels and from the portions of the top surface of the hard mask layer, leaving sidewall spacers surrounding the plurality of patterned mandrels.

[0085] The method may further include forming a first blocking mask that covers at least a first subgroup of the plurality of patterned mandrels and the sidewall spacers surrounding the first subgroup of the plurality of patterned mandrels, and exposes at least a second subgroup of the plurality of patterned mandrels and the sidewall spacers surrounding the second subgroup of the plurality of patterned mandrels. The first subgroup of the plurality of patterned mandrels provides direct printing of one or more fins of a first width, and the second subgroup of the plurality of patterned mandrels provides SADP for setting the spacing between two or more fins of a second width.

[0086] The method may further include removing the second subgroup of the plurality of patterned mandrels, leaving the sidewall spacers surrounding the second subgroup of the plurality of patterned mandrels, and removing the first blocking mask.

[0087] The method may further include forming a second blocking mask that covers the sidewall spacers surrounding the second subgroup of the plurality of patterned mandrels and exposes the first subgroup of the plurality of patterned mandrels and the sidewall spacers surrounding the first subgroup of the plurality of patterned mandrels.

[0088] The method may further include removing the sidewall spacers surrounding the first subgroup of the plurality of patterned mandrels exposed by the second blocking mask, and removing the second blocking mask.

[0089] The method may further include etching at least a portion of the hard mask stack, the nanosheet stack, and the substrate to form one or more fins of the first width under the first subgroup of the plurality of patterned mandrels and one or more fins of the second width under the remaining sidewall spacers.

[0090] In some embodiments, a method of forming a semiconductor structure includes: forming a nanosheet stack including alternating layers of sacrificial material and channel material over a substrate, the layers of the channel material providing nanosheet channels for one or more nanosheet FETs. The method further includes: forming a hard mask stack over the nanosheet stack; and forming a patterned layer over the hard mask stack. The method further includes patterning a lithography mask above the patterned layer, the lithography mask using SADP to expose (i) one or more first regions of the top surface of the patterned layer for direct printing of one or more fins having a first width in the nanosheet stack and the substrate, and (ii) one or more second regions of the top surface of the patterned layer for setting the spacing between two or more fins having a second width in the nanosheet stack and the substrate. The second width is less than the first width.

[0091] The method may further include etching portions of the patterned layer exposed by the lithography mask to form a plurality of patterned mandrels, and removing the lithography mask.

[0092] The method may further include depositing an oxide material over portions of the top surface of the hard mask stack exposed by etching portions of the patterned layer exposed by the lithography mask, and back-etching the oxide material to form a plurality of oxide mandrels over the top surface of the hard mask stack between the plurality of patterned mandrels.

[0093] The method may further include forming a blocking mask covering at least a first subgroup of the plurality of oxide mandrels and exposing at least a second subgroup of the plurality of oxide mandrels. The first subgroup of the plurality of oxide mandrels provides direct printing of one or more fins having a first width, and the second subgroup of the plurality of oxide mandrels provides SADP for setting the spacing between two or more fins having a second width.

[0094] The method may further include removing the second subgroup of the plurality of oxide mandrels, and removing the blocking mask.

[0095] The method may further include forming a spacer material over portions of the top surface of the hard mask stack exposed by removing the second subgroup of the plurality of oxide mandrels and over the top surfaces of the first subgroup of the plurality of oxide mandrels and the plurality of patterned mandrels, and back-etching the spacer material to form sidewall spacers adjacent to the sidewalls of the plurality of patterned mandrels exposed by removing the second subgroup of the plurality of oxide mandrels.

[0096] The method may further include removing the plurality of patterned mandrels, and etching at least a portion of the hard mask stack, the nanosheet stack, and the substrate to form the one or more fins having the first width under the first subgroup of the plurality of oxide mandrels and the one or more fins having the second width under the sidewall spacers.

[0097] In some embodiments, a semiconductor structure includes a substrate and a nanosheet stack disposed on the substrate, the nanosheet stack including alternating layers of sacrificial material and channel material, the channel material layers providing nanosheet channels for one or more nanosheet FETs. The semiconductor structure further includes a hard mask stack disposed on the nanosheet stack and a patterned layer disposed on the hard mask stack. The semiconductor structure further includes a lithography mask disposed on the patterned layer, the lithography mask defining (i) one or more first regions for directly printing one or more fins having a first width in the nanosheet stack and the substrate; and (ii) one or more second regions for setting a spacing between two or more fins having a second width in the nanosheet stack and the substrate using SADP. The second width is less than the first width.

[0098] In some embodiments, the lithography mask covers one or more first regions and one or more second regions. In other embodiments, the lithography mask exposes one or more first regions and one or more second regions.

[0099] The nanosheet stacks above the one or more fins of the first width can provide channels for nFETs, and the nanosheet stacks disposed above the one or more fins of the second width can provide channels for pFETs.

[0100] It should be understood that the various layers, structures, and regions shown in the figures are schematic diagrams not drawn to scale. Additionally, for ease of explanation, one or more layers, structures, and regions of the type commonly used to form semiconductor devices or structures may not be explicitly shown in a given figure. This does not mean that any layers, structures, or regions not explicitly shown are omitted from an actual semiconductor structure. Furthermore, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. Specifically, with regard to semiconductor processing steps, it is emphasized that the description provided herein is not intended to cover all processing steps that may be required to form a functional semiconductor integrated circuit device. Instead, for the sake of brevity of description, certain processing steps commonly used to form semiconductor devices, such as wet cleaning and annealing steps, are purposefully not described herein.

[0101] In addition, the same or similar reference numerals are used throughout the drawings to denote the same or similar features, elements, or structures, and thus, a detailed description of the same or similar features, elements, or structures is not repeated for each drawing. It should be understood that terms such as "about" or "substantially" with respect to thickness, width, percentage, range, etc. as used herein mean being close to or approximate, but not precisely. For example, as used herein, the term "about" or "substantially" means there is a small margin of error, such as ±5%, preferably less than 2% or 1% or less than the quantity.

[0102] In the above description, various materials and dimensions are provided for different elements. Unless otherwise indicated, such materials are given by way of example only and the embodiments are not limited to the specific examples given. Similarly, unless otherwise indicated, all dimensions are given by way of example only and the embodiments are not limited to the specific dimensions or ranges given.

[0103] The semiconductor device and method of forming the same according to the above technology can be used in various applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing the embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones and smart phones), solid-state media storage devices, functional circuits, etc. Systems and hardware incorporating the semiconductor device are intended embodiments of the present invention. Given the teachings provided herein, those of ordinary skill in the art will be able to envision other implementations and applications of the embodiments of the present invention.

[0104] In some embodiments, the above technology is used in combination with semiconductor devices that may require or otherwise utilize, for example, complementary metal oxide semiconductor (CMOS), metal oxide semiconductor field effect transistor (MOSFET), and / or fin field effect transistor (FinFET). As non-limiting examples, the semiconductor device may include, but is not limited to, CMOS, MOSFET, and FinFET devices, and / or semiconductor devices using CMOS, MOSFET, and / or FinFET technologies.

[0105] The above-described various structures can be implemented in an integrated circuit. The resulting integrated circuit chip can be distributed by the manufacturer in the form of an original wafer (i.e., as a single wafer having multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier having leads fixed to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier having surface or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products having a display, keyboard, or other input device and a central processing unit.

[0106] The description of the various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein were chosen to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for forming a semiconductor structure, comprising: forming a nanosheet stack comprising alternating layers of sacrificial material and channel material over the substrate, the layers of channel material providing a nanosheet channel for one or more nanosheet field effect transistors; forming a hard mask stack over the nanosheet stack; forming a patterned layer over the hard mask stack; as well as patterning a photolithographic mask on the patterned layer, the photolithographic mask defining: (i) one or more first regions for directly printing one or more fins having a first width in the nanosheet stack and the substrate, and (ii) one or more second regions for setting a spacing between two or more fins having a second width in the nanosheet stack and the substrate using self-aligned double patterning; The second width is smaller than the first width.

2. The method according to claim 1, wherein: The photolithographic mask is patterned on the patterned layer such that a photolithographic material covers the one or more first regions and the one or more second regions.

3. The method according to claim 1, wherein: The photolithographic mask is patterned on the patterned layer such that a photolithographic material exposes the one or more first regions and the one or more second regions. 4 . The method of claim 1 , wherein the hard mask stack comprises a pad oxide layer and a nitride-oxide-nitride hard mask stack over the pad oxide layer. The method of claim 1 , wherein the patterned layer comprises amorphous silicon (a-Si).

6. The method according to claim 2, further comprising: etching portions of the patterned layer exposed by the photolithographic mask to form a plurality of patterned mandrels; as well as The photolithography mask is removed.

7. The method according to claim 6, further comprising: depositing a spacer material on portions of the top surfaces of the plurality of patterned mandrels and the hard mask stack exposed by etching portions of the patterned layer exposed by the photolithographic mask; as well as The spacer material is etched back to remove the spacer material from top surfaces of the plurality of patterned mandrels and to remove the spacer material from portions of the top surface of the hard mask layer, leaving sidewall spacers surrounding the plurality of patterned mandrels.

8. The method according to claim 7, further comprising: A first blocking mask is formed, the first blocking mask covering at least a first subset of the plurality of patterned mandrels and the sidewall spacers surrounding the first subset of the plurality of patterned mandrels, and exposing at least a second subset of the plurality of patterned mandrels and the sidewall spacers surrounding the second subset of the plurality of patterned mandrels, wherein the first subset of the plurality of patterned mandrels provides direct printing of one or more fins of the first width, and the second subset of the plurality of patterned mandrels provides self-aligned double patterning for setting the spacing between the two or more fins of the second width.

9. The method according to claim 8, further comprising: removing the second subset of the plurality of patterned mandrels leaving the sidewall spacers surrounding the second subset of the plurality of patterned mandrels; as well as The first block mask is removed.

10. The method according to claim 9, further comprising: A second block mask is formed that covers the sidewall spacers surrounding the second subset of the plurality of patterned mandrels and exposes the first subset of the plurality of patterned mandrels and the sidewall spacers surrounding the first subset of the plurality of patterned mandrels.

11. The method according to claim 10, further comprising: removing the sidewall spacers surrounding the first subset of the plurality of patterned mandrels exposed by the second block mask; as well as The second block mask is removed.

12. The method according to claim 11, further comprising: Etching the hard mask stack, the nanosheet stack, and at least a portion of the substrate to form the one or more fins having the first width below the first subset of the plurality of patterned mandrels and to form the one or more fins having the second width below the remaining sidewall spacers.

13. The method according to claim 3, further comprising: etching portions of the patterned layer exposed by the photolithographic mask to form a plurality of patterned mandrels; as well as The photolithography mask is removed.

14. The method according to claim 13, further comprising: depositing an oxide material on portions of the top surface of the hard mask stack exposed by etching portions of the patterned layer exposed by the photolithographic mask; as well as The oxide material is etched back to form a plurality of oxide mandrels over the top surface of the hard mask stack between the plurality of patterned mandrels.

15. The method according to claim 14, further comprising: A blocking mask is formed covering at least a first subset of the plurality of oxide mandrels and exposing at least a second subset of the plurality of oxide mandrels, wherein the first subset of the plurality of oxide mandrels provides direct printing of one or more fins of a first width and the second subset of the plurality of oxide mandrels provides self-aligned double patterning for setting a spacing between two or more fins of the second width.

16. The method according to claim 15, further comprising: removing said second subset of said plurality of oxide mandrels; as well as The block mask is removed.

17. The method according to claim 16, further comprising: forming a spacer material over portions of the top surface of the hard mask stack exposed by removing the second subset of the plurality of oxide mandrels and over top surfaces of the first subset of the plurality of oxide mandrels and the plurality of patterned mandrels; as well as The spacer material is etched back to form sidewall spacers adjacent to sidewalls of the plurality of patterned mandrels exposed by removing the second subset of the plurality of oxide mandrels. The method of claim 17 , further comprising removing the plurality of patterned mandrels.

19. The method according to claim 18, further comprising: The hard mask stack, the nanosheet stack, and at least a portion of the substrate are etched to form the one or more fins having the first width below the first subset of the plurality of oxide mandrels and to form the one or more fins having the second width below the sidewall spacers.

20. A semiconductor structure comprising: substrate; a nanosheet stack disposed on the substrate, the nanosheet stack comprising alternating layers of sacrificial material and channel material, the layers of channel material providing a nanosheet channel for one or more nanosheet field effect transistors; a hard mask stack disposed over the nanosheet stack; a patterned layer disposed over the hard mask stack; as well as a photolithographic mask disposed over the patterned layer, the photolithographic mask defining: (i) one or more first regions for directly printing one or more fins having a first width in the nanosheet stack and the substrate; and (ii) one or more second regions for providing a spacing between two or more fins having a second width in the nanosheet stack and the substrate using self-aligned double patterning; The second width is smaller than the first width.

21. The semiconductor structure of claim 20, wherein the photolithography mask covers the one or more first regions and the one or more second regions.

22. The semiconductor structure of claim 20, wherein the photolithography mask exposes the one or more first regions and the one or more second regions.

23. The semiconductor structure of claim 20, wherein: The nanosheet stack on the one or more fins of the first width provides a channel for an n-type nanosheet field effect transistor, and the nanosheet stack arranged on the one or more fins of the second width provides a channel for a p-type nanosheet field effect transistor.

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