Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a heterojunction field-effect transistor, comprising, in an upper portion of a channel layer of a first nitride semiconductor, a barrier layer of a second nitride semiconductor heterojunctioned with the first nitride semiconductor; an n-type first impurity region and an n-type second impurity region disposed at a distance from each other with the barrier layer interposed therebetween; a source electrode and a drain electrode disposed on the first impurity region and the second impurity region; an insulating film disposed in contact with at least a region of the barrier layer other than an edge portion on a source electrode side; a gate insulating film covering the insulating film disposed in contact with at least the edge portion of the barrier layer and with regions of the barrier layer other than the edge portion; and a gate electrode disposed on the gate insulating film in a manner covering a portion of a region on the insulating film and a region of the edge portion of the barrier layer, wherein the sheet resistance caused by 2DEG generated at an interface between the channel layer and the barrier layer at an edge portion of the barrier layer is 10 kΩ / sq or greater.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and in particular to a heterojunction field-effect transistor composed of a semiconductor including a nitride. Background Art

[0002] As a conventional field effect transistor composed of a semiconductor containing nitride (nitride semiconductor), for example, a heterojunction field effect transistor composed of a nitride semiconductor disclosed in Patent Document 1 can be cited. In the case of this heterojunction field effect transistor, a channel layer of GaN (gallium nitride) and a barrier layer of AlGaN (aluminum gallium nitride) are sequentially formed on a substrate, and a source electrode, a drain electrode, and a gate electrode are formed thereon. A high-concentration n-type impurity region is formed in the channel layer and the barrier layer below the source electrode and the drain electrode, and an AlGaN barrier layer is formed on the barrier layer of AlN sandwiched between the high-concentration n-type impurity regions in a manner that covers the region. x O y A gate insulating film is formed of (aluminum gallium oxide), and a gate electrode is formed thereon.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2008-305816 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] The normally-off operation required when using a heterojunction field-effect transistor composed of a nitride semiconductor as a switching element can be achieved using the structure described in Patent Document 1. However, in the above-mentioned structure, in which a high-concentration n-type impurity region is formed in the semiconductor layer from below the gate electrode to below the drain electrode, almost all of the voltage applied between the gate and drain electrodes is applied to the gate electrode and the gate insulating film. Therefore, the upper limit (breakdown voltage) of the voltage that can be applied between the gate and drain electrodes is determined solely by the breakdown voltage of the gate insulating film and cannot be fully increased.

[0008] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a heterojunction field-effect transistor in which a higher voltage can be applied between a gate electrode and a drain electrode.

[0009] Means for solving problems

[0010] The semiconductor device of the present invention comprises: a substrate; a channel layer formed of a first nitride semiconductor and disposed on the substrate; a barrier layer formed of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor and disposed on an upper portion of the channel layer; an n-type first impurity region and an n-type second impurity region disposed on the upper portion of the channel layer with the barrier layer interposed therebetween and spaced apart from each other; a source electrode and a drain electrode disposed on the first impurity region and the second impurity region, respectively; a drift region having an insulating film disposed on the barrier layer except for an edge portion of the barrier layer on a side close to the source electrode so as to be in contact with the barrier layer; and a first impurity region and a second impurity region disposed on the edge portion of the barrier layer. A channel region at a position separated from the second impurity region, on which the insulating film is not formed; a gate insulating film formed on the channel region and the drift region in contact with the buffer layer and the insulating film, respectively; and a gate electrode provided on the gate insulating film on the channel region and a portion of the drift region, wherein the buffer layer in the channel region and the drift region have the same thickness and composition, the sheet resistance caused by the two-dimensional electron gas generated at the interface between the channel layer and the blocking layer in the channel region is greater than 10 kΩ / sq, and the sheet resistance caused by the two-dimensional electron gas generated at the interface between the channel layer and the buffer layer in the drift region is less than 10 kΩ / sq.

[0011] Effects of the Invention

[0012] According to the semiconductor device of the present invention, the two-dimensional electron gas (2DEG) at the heterointerface between the channel layer and the barrier layer in the channel region and the drift region increases. This two-dimensional electron gas is depleted when a high voltage is applied to the drain electrode. Therefore, the applied voltage is applied not only to the gate insulating film but also to this region, enabling a higher voltage to be applied between the gate and drain electrodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a perspective view showing a cross-sectional structure of a semiconductor device according to the first embodiment of the present invention.

[0014] Figure 2 This is an oblique view showing the cross-sectional structure of the sample used for verification.

[0015] Figure 3 Graph showing current-voltage (IV) characteristics measured between a source electrode and a drain electrode in a sample used for verification.

[0016] Figure 4 Graph showing current-voltage (IV) characteristics measured between a source electrode and a drain electrode in a sample used for verification.

[0017] Figure 5 Graph showing the heat treatment temperature dependence of the sheet resistance in the sample used for verification.

[0018] Figure 6 A diagram showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0019] Figure 7 A diagram showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0020] Figure 8 A diagram showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0021] Figure 9 A diagram showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0022] Figure 10 A diagram showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0023] Figure 11 A diagram showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0024] Figure 12 A diagram showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0025] Figure 13 A diagram showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0026] Figure 14 A diagram showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0027] Figure 15 A diagram showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0028] Figure 16 It is a perspective view showing a cross-sectional structure of a semiconductor device according to a second embodiment of the present invention.

[0029] Figure 17 It is a perspective view showing a cross-sectional structure of a semiconductor device according to a third embodiment of the present invention.

[0030] Figure 18 It is a perspective view showing a cross-sectional structure of a semiconductor device according to a fourth embodiment of the present invention.

[0031] Figure 19 It is a perspective view showing the cross-sectional structure of a first modification of the semiconductor device according to the fourth embodiment of the present invention.

[0032] Figure 20 It is a perspective view showing the cross-sectional structure of a second modification of the semiconductor device according to the fourth embodiment of the present invention.

[0033] Figure 21 It is a perspective view showing a cross-sectional structure of a semiconductor device according to a fifth embodiment of the present invention.

[0034] Figure 22 A diagram showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

[0035] Figure 23 A diagram showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

[0036] Figure 24 A diagram showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

[0037] Figure 25 A diagram showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

[0038] Figure 26 A diagram showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

[0039] Figure 27 A diagram showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

[0040] Figure 28 A diagram showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

[0041] Figure 29 A diagram showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

[0042] Figure 30 It is a perspective view showing the cross-sectional structure of a semiconductor device according to a sixth embodiment of the present invention.

[0043] Figure 31 It is a perspective view showing the cross-sectional structure of a modified example of the semiconductor device according to the sixth embodiment of the present invention.

[0044] Figure 32 It is a perspective view showing the cross-sectional structure of a semiconductor device according to a seventh embodiment of the present invention.

[0045] Figure 33 It is a perspective view showing the cross-sectional structure of a semiconductor device according to a seventh embodiment of the present invention.

[0046] Figure 34It is a perspective view showing the cross-sectional structure of a semiconductor device according to a seventh embodiment of the present invention.

[0047] Figure 35 Graph showing current-voltage (IV) characteristics measured between a source electrode and a drain electrode in a sample used for verification.

[0048] Figure 36 Graph showing current-voltage (IV) characteristics measured between a source electrode and a drain electrode in a sample used for verification.

[0049] Figure 37 Graphs showing sheet resistance before and after heat treatment of the semiconductor device according to the seventh embodiment of the present invention.

[0050] Figure 38 Graphs showing sheet resistance before and after heat treatment of the semiconductor device according to the seventh embodiment of the present invention.

[0051] Figure 39 It is a perspective view showing the cross-sectional structure of a first modification of the semiconductor device according to the seventh embodiment of the present invention.

[0052] Figure 40 It is a perspective view showing the cross-sectional structure of a second modification of the semiconductor device according to the seventh embodiment of the present invention.

[0053] Figure 41 It is a perspective view showing the cross-sectional structure of a semiconductor device according to an eighth embodiment of the present invention.

[0054] Figure 42 It is a perspective view showing the cross-sectional structure of a semiconductor device according to a ninth embodiment of the present invention.

[0055] Figure 43 It is a perspective view showing the cross-sectional structure of a semiconductor device according to a tenth embodiment of the present invention.

[0056] Figure 44 It is a perspective view showing the cross-sectional structure of a semiconductor device according to embodiment 11 of the present invention.

[0057] Figure 45 It is a perspective view showing the cross-sectional structure of a semiconductor device according to embodiment 12 of the present invention.

[0058] Figure 46 It is a perspective view showing the cross-sectional structure of a semiconductor device according to embodiment 13 of the present invention.

[0059] Figure 47 It is a perspective view showing the cross-sectional structure of Modification 1 of the semiconductor device according to Embodiment 13 of the present invention.

[0060] Figure 48 It is a perspective view showing the cross-sectional structure of a second modification of the semiconductor device according to the thirteenth embodiment of the present invention. DETAILED DESCRIPTION

[0061] <Implementation Method 1>

[0062] <Device Configuration>

[0063] Figure 1 It is a perspective view showing a cross-sectional structure of a heterojunction field-effect transistor 100 made of a nitride semiconductor according to the first embodiment of the present invention.

[0064] like Figure 1 As shown in FIG, in a heterojunction field-effect transistor 100, for example, a channel layer 3a composed of undoped GaN (a first nitride semiconductor) is stacked on a substrate 1 composed of silicon carbide (SiC) with a buffer layer 2 composed of AlN (aluminum nitride) interposed therebetween. A high-concentration n-type impurity region 5 (a first impurity region) and a high-concentration n-type impurity region 6 (a second impurity region) containing high concentrations of n-type impurities are selectively formed in the upper portion of the channel layer 3a, separated from each other. A barrier layer 4a composed of undoped AlGaN (a second nitride semiconductor) is formed in the upper portion of the channel layer 3a between the high-concentration n-type impurity regions 5 and 6, forming a heterojunction with the channel layer 3a.

[0065] A source electrode 7 and a drain electrode 8 are formed separately from each other on a portion of the high-concentration n-type impurity regions 5 and 6 .

[0066] Outside the edge portions of the high-concentration n-type impurity regions 5 and 6 on the side opposite to the barrier layer 4a, an element isolation region 9 is provided, extending from the outermost surface of the barrier layer 4a to the interior of the buffer layer 2. The element isolation region 9 is formed by zinc (Zn) ion implantation.

[0067] A SiN layer is formed so as to cover the source electrode 7 and a portion of the high-concentration n-type impurity region 5 adjacent to the source electrode 7. a The cap insulating film 10 a is made of silicon nitride. The cap insulating film 10 a is formed to cover the drain electrode 8 and a portion of the high-concentration n-type impurity region 6 adjacent to the drain electrode 8 .

[0068] On the high-concentration n-type impurity region 6 side, a layer of SiO is formed so as to cover the high-concentration n-type impurity region 6 not covered by the cap insulating film 10a and a portion of the upper portion of the barrier layer 4a. bAn electron supply insulating film 11 (silicon oxide film) composed of silicon oxide is formed. Furthermore, the electron supply insulating film 11 is formed on the side of the high-concentration n-type impurity region 5 so as to cover the cap insulating film 10a. In other words, the electron supply insulating film 11 is provided so that a portion of the barrier layer 4a on the side of the high-concentration n-type impurity region 5 and a portion of the adjacent high-concentration n-type impurity region 5 form an opening.

[0069] Furthermore, a layer of AlO is formed so as to cover the entire region including the upper portions of the source electrode 7 and the drain electrode 8. c The gate insulating film 12a is made of (aluminum oxide).

[0070] The gate electrode 13 is formed to cover the gate insulating film 12 a from above a portion of the electron supply insulating film 11 on the source electrode 7 side to above a portion of the electron supply insulating film 11 on the drain electrode side.

[0071] exist Figure 1 In the heterojunction field effect transistor 100 shown in FIG, the channel layer 3a and the barrier layer 4a are composed of undoped GaN and undoped AlGaN, respectively, except for the regions where the high-concentration n-type impurity region 5, the high-concentration n-type impurity region 6, and the element isolation region 9 are formed. That is, the doping amount of elements other than the main elements (Al, Ga, and N) constituting them is at least 1×10 17 cm -3 Designed in the following way.

[0072] In addition, regarding the barrier layer 4a, in a state where only the barrier layer 4a is formed on the channel layer 3a, that is, in a state where the high-concentration n-type impurity region 5, the high-concentration n-type impurity region 6, the element isolation region 9, the source electrode 7, the drain electrode 8, the cap insulating film 10a, the electron supply insulating film 11, the gate insulating film 12a, and the gate electrode 13 are not formed, the sheet resistance Rs due to the 2DEG (two-dimensional electron gas) generated at the interface between the channel layer 3a and the barrier layer 4a is 0. ch The Al composition and thickness are designed so as to achieve a sufficiently high value, that is, at least 1 kΩ / sq. For example, when the Al composition and thickness of the AlGaN barrier layer 4a are 15% and 7 nm, or 20% and 5 nm, or 100% and 1 nm, the sheet resistance Rs is ch By making the sheet resistance Rs ch By setting such a value, the leakage current value in the off state of the transistor becomes a sufficiently low value to not hinder the operation, for example, 1 microampere or less. chDefined as the intrinsic sheet resistance of the barrier layer 4a.

[0073] In addition, in the high-concentration n-type impurity region 5 and the high-concentration n-type impurity region 6, the sheet resistance Rs of these regions is nd The doping concentration and thickness are designed so that the leakage current value in the transistor's on state is low enough to not hinder its operation, that is, to be at least 1 kΩ / sq or less. For example, if the doping dose is 1×10 15 cm -2 To dope Si and Ge as donor dopants, Rs nd Become less than 1kΩ / sq.

[0074] By forming such a structure, the following effects are obtained. That is, the structure is as follows: the barrier layer 4a sandwiched between the high-concentration n-type impurity region 5 and the high-concentration n-type impurity region 6 has a structure in which the upper surface is in contact with the gate insulating film 12a on the source electrode 7 side and in contact with the electron supply insulating film 11 on the drain electrode 8 side. In other words, the type of insulating film in contact with the barrier layer 4a is different in the channel region A where the barrier layer 4a is in contact with the gate insulating film 12a and the drift region B where the barrier layer 4a is in contact with the electron supply insulating film 11. b The interface between the (electron supply insulating film 11) and AlGaN induces a large amount of positive charge, so the 2DEG at the interface between the barrier layer 4a and the channel layer 3a in the drift region B increases, and the sheet resistance Rs caused by the 2DEG generated at the interface between the channel layer 3a and the barrier layer 4a in the drift region B can be reduced. dr Reduce to below 10kΩ / sq. This will be described in detail later.

[0075] On the other hand, in AlO c The interface between the gate insulating film 12a and AlGaN, and the interface between the gate insulating film 12a and SiO b Compared with the interface of the electron supply insulating film 11, it is difficult to induce positive charges. Therefore, in the channel region A, the 2DEG generated at the interface of the channel layer 3a and the barrier layer 4a does not increase, and the sheet resistance Rs ch Maintaining a sufficiently high value, that is, a value of at least 10 kΩ / sq or higher will be described in detail later.

[0076] In this configuration, by using the source electrode 7 as a reference potential (ground) and varying the voltage applied to the gate electrode 13 (gate voltage), the concentration of the 2DEG generated at the interface between the barrier layer 4a and the channel layer 3a in the channel region A can be controlled. Specifically, when no gate voltage is applied or when a negative voltage is applied, the concentration of the 2DEG is maintained at a sufficiently low level that, even when a positive voltage (drain voltage) is applied to the drain electrode 8, no current (drain current) flows through the drain electrode 8. On the other hand, when the gate voltage is positive, the concentration of the 2DEG increases, and the entire region from the source electrode 7 to the drain electrode 8 has a sufficiently low resistance, resulting in a large leakage current when a positive voltage is applied to the drain electrode 8. In other words, normally-off operation is achieved as a transistor. Furthermore, when the drain voltage is increased, when no gate voltage is applied or when a negative voltage is applied (off state), the 2DEG generated between the barrier layer 4a and the channel layer 3a in the drift region B is depleted, causing the depletion layer to extend into the drift region B. Therefore, the voltage applied between the gate electrode 13 and the drain electrode 8 is dispersed not only to the gate insulating film 12a but also to the drift region B. As a result, a large drain voltage can be applied, the withstand voltage when turned off is increased, and high-voltage operation of the transistor becomes possible.

[0077] In addition, in the heterojunction field effect transistor 100, the channel region A on the lower side of the gate electrode 13 and the drift region B on the drain electrode 8 side are structured such that the gate electrode 13 is formed on the blocking layer 4a via the electron supply insulating film 11 and the gate insulating film 12a in sequence.

[0078] This configuration can alleviate the electric field concentrated at the drain electrode 8-side end of the gate electrode 13 when a high voltage is applied to the drain electrode 8, allowing application of a higher voltage. Furthermore, the occurrence of current collapse, in which on-resistance excessively increases due to electric field concentration, can be suppressed.

[0079] In the heterojunction field effect transistor 100, the region on the source electrode 7 side with respect to the channel region A below the gate electrode 13 is formed by sequentially passing through the SiN a The cover insulating film 10a, SiO b The electron supply insulating film 11 and AlO c The gate electrode 13 is formed by forming a gate insulating film 12a.

[0080] With such a configuration, when a voltage is applied to the drain electrode 8 , the electric field concentrated at the end of the gate electrode 13 on the source electrode 7 side can be relaxed, thereby suppressing current collapse caused by the electric field concentration.

[0081] Furthermore, in the heterojunction field effect transistor 100 , since the source electrode 7 and the drain electrode 8 are covered with the cap insulating film 10 a , degradation of the source electrode 7 and the drain electrode 8 due to oxidation is prevented, and an increase in on-resistance can be suppressed.

[0082] Furthermore, in the heterojunction field-effect transistor 100, as described above, an electron-supplying insulating film 11 is formed on the blocking layer 4a in the drift region B. The positive charge generated at the interface increases the 2DEG at the interface between the blocking layer 4a and the channel layer 3a in this region, thereby achieving both normally-off operation and a high withstand voltage. Consequently, both normally-off operation and a high withstand voltage can be achieved without doping the blocking layer 4a and the channel layer 3a in the channel region A and the drift region B with any impurities.

[0083] The impurities doped in the blocking layer 4a and the channel layer 3a form deep energy levels within the band gap of the nitride semiconductor, becoming capture energy levels that induce current collapse. Therefore, as long as the doping concentration of the impurities in the blocking layer 4a and the channel layer 3a is suppressed to a sufficiently low level, the occurrence of current collapse caused by the capture energy levels they form can be suppressed.

[0084] For such trapped energy levels, the effect on current collapse can be ignored as long as the energy level density is sufficiently small compared to the carrier density during transistor operation. However, if the trapped energy levels are formed at the same density, the effect cannot be ignored. In heterojunction field effect transistors using nitride semiconductors, at least 1×10 12 cm -2 The above 2DEG is a carrier. Therefore, if the ratio of the current collapse that can be almost ignored is reduced to 1% or less, the trapped energy level density is reduced to 1×10 10 cm -2 As for the thickness of the barrier layer 4a, in order to achieve the above-mentioned design value of sheet resistance, it needs to be 10nm or less. Therefore, if the doping amount of the barrier layer 4a is set to 1×10 16 cm -3 Below this, the influence on the current collapse can be ignored.

[0085] Next, in the drift region B, by forming the electron supply insulating film 11 on the barrier layer 4a, the 2DEG generated at the interface between the channel layer 3a and the barrier layer 4a increases, and the sheet resistance Rs ch The following is the result of verifying this phenomenon.

[0086] Figure 2 The cross-sectional view of the sample 90 used for verification is shown in FIG. Figure 1 Components identical to those of the heterojunction field-effect transistor 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant descriptions are omitted.

[0087] In sample 90, the structure from the substrate 1 to the source electrode 7 and the drain electrode 8 is the same as that of the heterojunction field effect transistor 100, and an electron supply insulating film 11 is formed by covering the source electrode 7 and the drain electrode 8, the high concentration n-type impurity regions 5 and 6 not covered by the source electrode 7 and the drain electrode 8, and the surface of the blocking layer 4a.

[0088] The following describes the method for fabricating Sample 90. A buffer layer 2, a channel layer 3a, and a barrier layer 4a were sequentially grown on a SiC substrate 1 using MOCVD (metal organic chemical vapor deposition). In this verification, two different barrier layer 4a structures were used: an Al composition of 15% and a thickness of 7 nm, and an Al composition of 20% and a thickness of 5 nm.

[0089] Next, using the resist pattern as a mask, ion implantation was performed at a dose of 1×10 15 cm -2 , Si ions are implanted into the desired area under the condition of an injection energy of 50 keV, and then, heat treatment is performed at 1150°C in a nitrogen atmosphere for 5 minutes by the RTA (Rapid Thermal Annealing) method to activate the doped Si ions and form high-concentration n-type impurity regions 5 and 6.

[0090] Next, a source electrode 7 and a drain electrode 8 composed of a metal multilayer film are formed by vapor deposition and lift-off methods.

[0091] Next, Zn ions are implanted into the channel layer 3 a and the barrier layer 4 a outside the high-concentration n-type impurity region 5 and the high-concentration n-type impurity region 6 by ion implantation to form the element isolation region 9 .

[0092] Next, a 10 nm thick electron supply insulating film 11 was formed using plasma CVD to cover the entire region, including the upper portion of the barrier layer 4a sandwiched between the high-concentration n-type impurity regions 5 and 6. After the electron supply insulating film 11 was formed, heat treatment was performed in nitrogen at 300 to 950°C for 30 seconds to form Sample 90.

[0093] At once Figure 3 and Figure 4 For Figure 2 ] The current-voltage (IV) characteristics of sample 90 shown in FIG are measured between the source electrode 7 and the drain electrode 8, with the horizontal axis representing voltage (Voltage: unit V) and the vertical axis representing current density (Current density: unit A / mm).

[0094] exist Figure 3and Figure 4 , shows measurement result C3 (before SiO2 deposition) before forming the electron supply insulating film 11, measurement result C2 (after SiO2 deposition) after forming the electron supply insulating film 11, and measurement result C1 (after 800°C annealing) after heat treatment at 800°C. Note that since two samples were made on the same substrate for measurement, each measurement result shows two characteristics.

[0095] The width of the high-concentration n-type impurity regions 5 and 6 is set to 100 μm, and the distance between the high-concentration n-type impurity regions 5 and 6 is set to 4 μm (L=4 μm). Figure 3 The characteristics of the case where the Al composition and thickness are 20% and 5nm respectively, Figure 4 These are characteristics when the Al composition and thickness are 15% and 7 nm, respectively.

[0096] As from Figure 3 and Figure 4 As can be seen, in both the case where the Al composition of the barrier layer 4a is 20% and the case where it is 15%, before the electron supply insulating film 11 is formed, the Al composition of the barrier layer 4a becomes 1×10 -8 A / mm. The measuring limit of the measuring instrument used for the measurement is 1×10 -8 A / mm, so the current value before the electron supply insulating film 11 is formed is at least 1×10 -8 A / mm or less.

[0097] After forming the electron supply insulating film 11, the current value increased significantly (by more than 4 digits) in all Al compositions. Furthermore, after heat treatment at 800°C, the current value increased further, reaching a value of about 0.1 A / mm in all Al compositions.

[0098] From these results, it was experimentally confirmed that the electron supply insulating film 11 (SiO b ), the 2DEG generated at the interface between the channel layer 3a and the barrier layer 4a increases, which reduces the sheet resistance. b The result is that a large amount of positive charge is induced at the interface with AlGaN. By setting the electron supply insulating film 11, the sheet resistance is reduced, and the current value increases, thereby b The insulating film formed is called an electron-donating insulating film.

[0099] In addition, the electron supply insulating film 11 is represented by SiO b , is a compound of Si (silicon) and O (oxygen). This is because, since it is a deposited film, its composition is not necessarily the same as the general SiO2. a、AlO c The same goes for etc.

[0100] In addition, Figure 5 3 shows the heat treatment temperature dependence of the sheet resistance obtained from IV characteristics measured using different patterns in a range of 2 to 20 μm between the high-concentration n-type impurity regions 5 and 6 .

[0101] exist Figure 5 In the figure, the horizontal axis is set to annealing temperature (Annealing temperature: unit ℃), the vertical axis is set to sheet resistance (Sheet resistance: unit Ω / sq), the characteristics when the Al composition and thickness are 20% and 5nm respectively are represented by ◇, and the characteristics when the Al composition and thickness are 15% and 7nm respectively are represented by ●.

[0102] Depend on Figure 5 It was confirmed that the sheet resistance was reduced by heat treatment after the formation of the electron supply insulating film 11, and it was reduced to 10 kΩ / sq or less by heat treatment at 500-950°C. b The positive charge induced at the interface with AlGaN is increased by heat treatment.

[0103] As described above, in the heterojunction field-effect transistor 100 according to the first embodiment, both the normally-off operation and the high-breakdown voltage operation are achieved.

[0104] <Manufacturing method>

[0105] Next, an example of a method for manufacturing the heterojunction field effect transistor 100 is described using a flowchart showing the manufacturing steps in order. Figures 6 to 15 To explain. Figures 6 to 15 In the Figure 1 Components identical to those of the heterojunction field-effect transistor 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant descriptions are omitted.

[0106] First, in Figure 6 In the process shown in , a buffer layer 2 composed of AlN, a channel layer 3a composed of GaN, and a barrier layer 4a composed of AlGaN are sequentially grown on a SiC substrate 1 using an epitaxial growth method such as MOCVD or MBE (Molecular Beam Epitaxy).

[0107] Secondly, in Figure 7 In the process shown in FIG, a resist pattern or the like is used as a mask, and an ion implantation method or the like is used to implant a 1×10 13 ~1×10 16 cm -2Ions of Si, etc., which will become n-type impurities, are doped into desired regions in the nitride semiconductor at an implantation energy of 10 to 1000 keV. Then, heat treatment is performed in a nitrogen atmosphere at a temperature of 800 to 1500°C, for example, using RTA, to activate the doped ions and form high-concentration n-type impurity regions 5 and 6.

[0108] Secondly, in Figure 8 In the process shown in , a metal multilayer film is deposited on a desired region using evaporation and lift-off methods. Then, the deposited multilayer film is heat treated at a temperature of 500 to 900° C. using an RTA method or the like to alloy the deposited multilayer film, thereby forming a source electrode 7 and a drain electrode 8. Examples of the metal multilayer film include multilayer films of Ti (titanium) and Al. When formed on a high-concentration n-type impurity region, any metal generally used as an electrode can provide an ohmic contact, so there is no particular limitation.

[0109] Secondly, in Figure 9 In the process shown in FIG, Zn ions are implanted outside the region where the transistor is to be formed using an ion implantation method to form an element isolation region 9 extending from the outermost surface of the barrier layer 4a to the interior of the buffer layer 2. The technique of increasing the resistance of GaN by implanting Zn ions is well known and is disclosed, for example, in Toshiyuki Oishi, Naruhisa Miura, Muneyoshi Suita, Takuma Nanjo, Yuji Abe, and Tatsuo Ozeki J. Appl. Phys. Vol. 94, No. 3 1662-1666 (2003).

[0110] Secondly, in Figure 10 In the process shown in FIG. 1 , a SiN layer is deposited on the channel layer 3a on which the source electrode 7 and the drain electrode 8 are formed, for example, using a plasma CVD method. a The cover insulating film 10a is formed.

[0111] Secondly, in Figure 11 In the process shown in FIG, a resist pattern or the like is used as a mask, and wet etching with buffered hydrofluoric acid or the like is employed to remove the cap insulating film 10a from a desired region. The region to be removed is the region extending from the upper portion of a portion of the barrier layer 4a to the upper portion of the edge of the high-concentration n-type impurity region 6 adjacent to the barrier layer 4a.

[0112] Secondly, in Figure 12 In the process shown in FIG. 1 , SiO is deposited on the cap insulating film 10 a and on the high concentration n-type impurity region 6 not covered by the cap insulating film 10 a and on the AlGaN barrier layer 4 a by, for example, plasma CVD. bThen, heat treatment is performed at 700 to 900° C. in a nitrogen atmosphere using, for example, RTA to increase positive charges generated at the interface of the region where the blocking layer 4 a contacts the electron supply insulating film 11 .

[0113] Secondly, in Figure 13 In the process shown in FIG, a resist pattern or the like is used as a mask, and wet etching with buffered hydrofluoric acid or the like is employed to remove the cap insulating film 10a and the electron supply insulating film 11 from desired regions. The region to be removed is the region extending from the upper portion of a portion of the barrier layer 4a on the side of the high-concentration n-type impurity region 5 to the upper portion of the edge of the high-concentration n-type impurity region 5 adjacent to the barrier layer 4a.

[0114] Secondly, in Figure 14 In the process shown in FIG. 1 , an AlO layer is deposited on the electron supply insulating film 11, on the high concentration n-type impurity region 5 not covered by the electron supply insulating film 11, and on the AlGaN barrier layer 4a, for example, using atomic layer deposition. c The gate insulating film 12a is formed.

[0115] Secondly, in Figure 15 In the process shown in FIG, a resist mask RM is formed on the gate insulating film 12a so that the portion where the gate electrode 13 is to be formed becomes the opening OP. Then, a metal film composed of Ni (nickel) is formed on the resist mask RM and in the opening OP by vapor deposition, and the resist mask RM is removed by a lift-off method, thereby forming the gate electrode 13. Figure 1 The heterojunction field effect transistor 100 is shown in FIG.

[0116] The manufacturing process of the heterojunction field effect transistor 100 described above is characterized in that the following steps are carried out in sequence: Figure 10 and Figure 11 The deposition and removal of the cover insulating film 10a are shown in FIG. Figure 12 The deposition of the electron supply insulating film 11 and the heat treatment at 700 to 900° C. shown in FIG. Figure 13 The removal of the cap insulating film 10a and the electron supply insulating film 11 shown in FIG. Figure 14 The deposition of the gate insulating film 12a shown in FIG. Figure 14 The formation of the gate electrode 13 is shown in FIG.

[0117] This not only enables the production of Figure 1 The heterojunction field effect transistor 100 having the structure shown in FIG. 1 also obtains the following effects.

[0118] First, heat treatment at 700 to 900° C. can be performed while the barrier layer 4 a in the channel region A is covered by the cap insulating film 10 a and the barrier layer 4 a in the drift region B is covered by the electron supply insulating film 11 .

[0119] When heat treatment is performed at a high temperature of 700°C or higher, if the barrier layer 4a is exposed to the space during the heat treatment, nitrogen will be separated from the barrier layer 4a, and nitrogen vacancies that are the main cause of electron traps will be generated in the barrier layer 4a. In particular, if there are a large number of such nitrogen vacancies in the channel region A, there is a concern that the leakage current will increase and the current collapse will deteriorate. As for the separation of nitrogen from the AlGaN layer caused by such heat treatment, it can be suppressed by depositing any insulating film on the surface of the AlGaN layer, but it is not completely suppressed, and the effect varies depending on the insulating film material used. In the case of SiN a As for the insulating film composed of SiO, it is a material often used as a cover insulating film during the activation heat treatment after ion implantation. b and AlO c Compared to other insulating film materials, this insulating film material is more effective in suppressing nitrogen desorption from the AlGaN layer. Therefore, this manufacturing method can suppress characteristic degradation caused by nitrogen vacancies.

[0120] In addition, AlO c Since the gate insulating film 12a is formed after the heat treatment at 700 to 900°C, it is possible to avoid the need for heat treatment at high temperatures. c If the gate insulating film 12a is subjected to heat treatment at temperatures above 700°C, partial crystallization progresses, and the grain boundaries become current leakage paths. Even in heterojunction field-effect transistor 100, there is a concern that gate leakage current may increase if the gate insulating film 12a is subjected to heat treatment at temperatures above 700°C. However, this manufacturing method avoids the need for high-temperature heat treatment, thereby achieving low leakage current.

[0121] Furthermore, in the region on the drain electrode 8 side below the gate electrode 13, a configuration can be formed in which the gate electrode 13 is formed on the blocking layer 4a via the electron supply insulating film and the gate insulating film 12a in this order. This can alleviate the concentration of electric fields on the drain electrode 8-side end of the gate electrode 13 when a high voltage is applied to the drain electrode 8, allowing the application of higher voltages. Furthermore, the occurrence of current collapse caused by electric field concentration can be suppressed.

[0122] Furthermore, in the region on the source electrode 7 side below the gate electrode 13, a configuration can be formed in which the gate electrode 13 is formed on the high-concentration n-type impurity region 5 via the cap insulating film 10a, the electron supply insulating film 11, and the gate insulating film 12a in this order. This can alleviate the concentration of electric field at the end of the gate electrode 13 on the source electrode 7 side when a voltage is applied to the gate electrode 13, thereby suppressing the occurrence of current collapse caused by this electric field concentration.

[0123] It should be explained that Figure 1 Only the minimum structure required for operating as a transistor is disclosed, and the device is finally completed by forming a protective film, a field plate electrode, wiring, a dummy bridge, a via hole, etc.

[0124] In addition, Figure 7 The high-concentration n-type impurity regions 5 and 6 shown in FIG are not necessarily formed by ion implantation, but may be formed by etching or epitaxial growth methods such as MOCVD or MBE.

[0125] In addition, Figure 9 As for the formation of the element separation region 9 shown in the figure, it is not necessarily carried out by ion implantation. Etching can also be used to remove the area from the outermost surface of the barrier layer 4a to the buffer layer 2, so that the area where the transistor is made is a table-type structure, and the removed area is used as the element separation region 9.

[0126] In addition, the above manufacturing process is not necessarily carried out in the order described, and the order can be changed. Figure 7 After forming the high concentration n-type impurity regions 5 and 6 shown in FIG. Figure 9 The formation of the element isolation region 9 shown in FIG.

[0127] <Implementation Method 2>

[0128] Figure 16 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 200 made of a nitride semiconductor according to a second embodiment of the present invention. Figure 16 For use with Figure 1 The same components as those of the heterojunction field-effect transistor 100 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0129] exist Figure 1 In the heterojunction field effect transistor 100 shown in FIG, the region on the source electrode 7 side under the gate electrode 13 is formed by sequentially passing through the SiN a The cover insulating film 10a, SiO b The electron supply insulating film 11 and AlO c The gate insulating film 12a is formed with a gate electrode 13. Figure 16 In the heterojunction field effect transistor 200 shown in FIG, a gate electrode 13 is formed on the high-concentration n-type impurity region 5 via an electron supply insulating film and a gate insulating film 12 a in this order.

[0130] Even in such a configuration, when a voltage is applied to the drain electrode 8 , the electric field concentration at the end of the gate electrode 13 on the source electrode 7 side can be alleviated, thereby suppressing the occurrence of current collapse due to the electric field concentration.

[0131] It should be noted that, in terms of such a configuration, Figure 11 In the above-described method, the cover insulating film 10 a is removed from the source electrode 7 to a portion of the region where the gate electrode 13 is to be formed when removing the cover insulating film 10 a using the resist pattern.

[0132] <Implementation Method 3>

[0133] Figure 17 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 300 made of a nitride semiconductor according to a third embodiment of the present invention. Figure 17 For use with Figure 1 The same components as those of the heterojunction field-effect transistor 100 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0134] exist Figure 1 In the heterojunction field effect transistor 100 shown in FIG, the region on the source electrode 7 side under the gate electrode 13 is formed by sequentially passing through the SiN a The cover insulating film 10a, SiO b The electron supply insulating film 11 and AlO c The gate insulating film 12a is formed with a gate electrode 13. Figure 17 In the heterojunction field-effect transistor 300 shown in FIG, the gate electrode 13 is formed so as to extend from the upper edge of the high-concentration n-type impurity region 5 on the AlGaN barrier layer 4a side to the upper center of the barrier layer 4a, and its width is narrowed. Therefore, the edge of the gate electrode 13 on the source electrode 7 side is located above the high-concentration n-type impurity region 5 via the gate insulating film 12a. In other words, the region on the source electrode 7 side below the gate electrode 13 is formed on the gate insulating film 12a, similar to the region on the barrier layer 4a serving as the channel region A, and does not form an electric field relaxation structure.

[0135] Therefore, with Figure 1 The heterojunction field effect transistor 100 shown in FIG. Figure 16Compared to the heterojunction field-effect transistor 200 shown in FIG, the effect of alleviating the electric field concentration on the end of the gate electrode 13 on the source electrode 7 side when a voltage is applied to the drain electrode 8 is weakened. Therefore, the effect of suppressing the occurrence of current collapse caused by electric field concentration is also reduced. On the other hand, the area where the gate electrode 13 overlaps with the high-concentration n-type impurity region 5 can be reduced. When the area where the gate electrode 13 overlaps with the high-concentration n-type impurity region 5 is large, the gate capacitance increases accordingly, making high-speed switching difficult. In the heterojunction field-effect transistor 300, the gate capacitance can be reduced.

[0136] In the heterojunction field-effect transistor 300, the edge of the gate electrode 13 on the drain electrode 8 side is located on the stacked film of the electron supply insulating film 11 and the gate insulating film 12a, thus forming an electric field relaxation structure. If high-voltage operation and the occurrence of current collapse are sufficiently suppressed by this alone, the heterojunction field-effect transistor 300 is advantageous in terms of being able to reduce gate capacitance.

[0137] Any of the heterojunction field-effect transistors 100 to 300 can be used depending on desired transistor operation conditions.

[0138] In order to manufacture the heterojunction field effect transistor 300, Figure 15 When forming the gate electrode 13, the width of the opening OP of the resist mask RM is narrowed, and the gate electrode 13 is formed from the upper edge of the AlGaN barrier layer 4a side of the high-concentration n-type impurity region 5 to the upper center of the barrier layer 4a.

[0139] <Implementation Method 4>

[0140] Figure 18 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 400 made of a nitride semiconductor according to a fourth embodiment of the present invention. Figure 18 For use with Figure 1 The same components as those of the heterojunction field-effect transistor 100 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0141] exist Figure 1 In the heterojunction field effect transistor 100 shown in FIG, the source electrode 7 and the drain electrode 8 are made of SiN a The cover insulating film 10a, SiO b The electron supply insulating film 11 and AlO c In the heterojunction field effect transistor 400 , the source electrode 7 and the drain electrode 8 are covered only with the gate insulating film 12 a .

[0142] However, the edge portion of the gate electrode 13 on the source electrode 7 side is located above the high-concentration n-type impurity region 5 via the cap insulating film 10a, the electron supply insulating film 11, and the gate insulating film 12a. In other words, the cap insulating film 10a and the electron supply insulating film 11 are stacked in this order only on the high-concentration n-type impurity region 5 below the edge portion of the gate electrode 13 on the source electrode 7 side, and the gate insulating film 12a covers this stacked film.

[0143] Furthermore, the edge portion of the gate electrode 13 on the drain electrode 8 side is located above the blocking layer 4 a via the electron supply insulating film 11 and the gate insulating film 12 a .

[0144] Even in the heterojunction field-effect transistor 400 having such a structure, similarly to the heterojunction field-effect transistors 100 and 200 , both the normally-off operation and the high-breakdown voltage operation can be achieved.

[0145] In order to manufacture the heterojunction field effect transistor 400, the Figure 11 When the cover insulating film 10a is removed using the resist pattern described above, the cover insulating film 10a is removed so that the cover insulating film 10a remains only on the high concentration n-type impurity region 5 below the edge of the gate electrode 13 on the source electrode 7 side. Figure 13 When removing the electron supply insulating film 11 using the resist pattern as described above, the electron supply insulating film 11 can be removed in such a manner that the electron supply insulating film 11 remains only in the area from the upper part of the blocking layer 4a to the upper part of the edge of the high-concentration n-type impurity region 6 and in the upper part of the cover insulating film 10a on the high-concentration n-type impurity region 5.

[0146] <Variation 1>

[0147] Figure 19 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 401 made of a nitride semiconductor according to a first variation of the fourth embodiment of the present invention. Figure 19 For use with Figure 18 The same components as the heterojunction field-effect transistor 400 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0148] exist Figure 18In the heterojunction field-effect transistor 400 shown in FIG, the edge portion of the gate electrode 13 on the source electrode 7 side is located above the high-concentration n-type impurity region 5 via the cap insulating film 10 a, the electron supply insulating film 11, and the gate insulating film 12 a. In the heterojunction field-effect transistor 401, the edge portion of the gate electrode 13 on the source electrode 7 side is located above the high-concentration n-type impurity region 5 via the electron supply insulating film 11 and the gate insulating film 12 a. That is, the electron supply insulating film 11 is formed on the high-concentration n-type impurity region 5 below the edge portion of the gate electrode 13 on the source electrode 7 side, and the gate insulating film 12 a covers this electron supply insulating film 11.

[0149] The configuration in which the edge portion of the gate electrode 13 on the drain electrode 8 side is located above the blocking layer 4 a via the electron supply insulating film 11 and the gate insulating film 12 a is the same as that of the heterojunction field effect transistor 400 .

[0150] In order to manufacture the heterojunction field effect transistor 401, it is not necessary to use Figure 11 The manufacturing process of the cover insulating film 10a is described using Figure 13 When removing the electron supply insulating film 11 using the resist pattern as described above, the electron supply insulating film 11 can be removed in such a manner that the electron supply insulating film 11 remains only in the area from the upper part of the blocking layer 4a to the upper part of the edge of the high-concentration n-type impurity region 6 and on the lower part of the edge of the gate electrode 13 on the source electrode 7 side.

[0151] <Variation 2>

[0152] Figure 20 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 402 made of a nitride semiconductor according to a second variation of the fourth embodiment of the present invention. Figure 20 For use with Figure 18 The same components as the heterojunction field-effect transistor 400 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0153] exist Figure 18 In the heterojunction field effect transistor 400 shown in the figure, the edge portion of the gate electrode 13 on the source electrode 7 side is located above the high-concentration n-type impurity region 5 via the cap insulating film 10a, the electron supply insulating film 11 and the gate insulating film 12a. In the heterojunction field effect transistor 402, the edge portion of the gate electrode 13 on the source electrode 7 side is located above the high-concentration n-type impurity region 5 via the gate insulating film 12a.

[0154] The configuration in which the edge portion of the gate electrode 13 on the drain electrode 8 side is located above the blocking layer 4 a via the electron supply insulating film 11 and the gate insulating film 12 a is the same as that of the heterojunction field effect transistor 400 .

[0155] Furthermore, the gate electrode 13 is formed so as to extend from the upper edge of the AlGaN barrier layer 4a side of the high-concentration n-type impurity region 5 to the upper center of the barrier layer 4a, and has a narrow width. Specifically, since the edge of the gate electrode 13 on the source electrode 7 side does not have an electric field relaxation structure, the width of the gate electrode 13 is narrowed to reduce gate capacitance.

[0156] In order to make the heterojunction field effect transistor 402, it is not necessary to use Figure 11 The manufacturing process of the cover insulating film 10a is described using Figure 13 When removing the electron supply insulating film 11 using the resist pattern as described above, the electron supply insulating film 11 can be removed in such a manner that the electron supply insulating film 11 remains only in the area from the upper part of the blocking layer 4a to the upper part of the edge of the high-concentration n-type impurity region 6 and on the lower part of the edge of the gate electrode 13 on the source electrode 7 side.

[0157] In addition, when using Figure 15 When forming the gate electrode 13 described above, the width of the opening OP of the resist mask RM is narrowed, and the gate electrode 13 is formed from the upper edge of the AlGaN barrier layer 4a side of the high-concentration n-type impurity region 5 to the upper center of the barrier layer 4a.

[0158] The configurations of the heterojunction field effect transistors 400 , 401 , and 402 described above are effective when the materials constituting the source electrode 7 and the drain electrode 8 are resistant to hydrofluoric acid used when removing the cap insulating film 10 a and the electron supply insulating film 11 .

[0159] When the materials constituting the source electrode 7 and the drain electrode 8 are not resistant to hydrofluoric acid, the structures of the heterojunction field-effect transistors 100 to 300 of the first to third embodiments can be adopted.

[0160] <Implementation Method 5>

[0161] <Device Configuration>

[0162] Figure 21 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 500 made of a nitride semiconductor according to a fifth embodiment of the present invention. Figure 21 For use with Figure 1The same components as those of the heterojunction field-effect transistor 100 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0163] exist Figure 1 In the heterojunction field effect transistor 100 shown in FIG, the source electrode 7 and the drain electrode 8 are made of SiN a The cover insulating film 10a, SiO b The electron supply insulating film 11 and AlO c In the heterojunction field-effect transistor 500, the upper surfaces of the source electrode 7 and the drain electrode 8 are covered only by the gate insulating film 12a, and the stacked film of the cap insulating film 10a, the electron supply insulating film 11, and the gate insulating film 12a is in contact with the side surfaces of the source electrode 7 and the drain electrode 8. Other than this structure, the heterojunction field-effect transistor 500 is identical to the heterojunction field-effect transistor 100. Like the heterojunction field-effect transistor 100, both normally-off operation and high-breakdown voltage operation are achieved.

[0164] <Manufacturing method>

[0165] Next, an example of a method for manufacturing a heterojunction field effect transistor 500 is described using a flowchart showing the manufacturing steps in order. Figure 6 、 Figure 7 、 Figures 22 to 29 It should be explained that Figures 22 to 29 In the Figure 1 Components identical to those of the heterojunction field-effect transistor 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant descriptions are omitted.

[0166] First, as in embodiment 1, Figure 6 As described above, the buffer layer 2 composed of AlN, the channel layer 3 a composed of GaN, and the barrier layer 4 a composed of AlGaN are sequentially grown on the SiC substrate 1 by using an epitaxial growth method such as MOCVD or MBE.

[0167] Secondly, as in embodiment 1, Figure 7 As described above, a resist pattern or the like is used as a mask, and an ion implantation method or the like is used, at an implantation dose of 1×10 13 ~1×10 16 cm -2 Ions of Si, etc., which will become n-type impurities, are doped into desired regions in the nitride semiconductor at an implantation energy of 10 to 1000 keV. Then, heat treatment is performed in a nitrogen atmosphere at a temperature of 800 to 1500°C, for example, using RTA, to activate the doped ions and form high-concentration n-type impurity regions 5 and 6.

[0168] Secondly, in Figure 22In the process shown in FIG, Zn ions are implanted outside the region where the transistor is formed using an ion implantation method to form an element isolation region 9 extending from the outermost surface of the barrier layer 4a to the interior of the buffer layer 2. As described in Embodiment 1, the technique of increasing the resistance of GaN by implanting Zn ions is well known.

[0169] Secondly, in Figure 23 In the process shown in FIG. 1 , SiN is deposited on the channel layer 3a where the element isolation region 9 and the high-concentration n-type impurity regions 5 and 6 are formed, for example, using a plasma CVD method. a The cover insulating film 10a is formed.

[0170] Secondly, in Figure 24 In the process shown in FIG, a resist pattern or the like is used as a mask, and wet etching with buffered hydrofluoric acid or the like is employed to remove the cap insulating film 10a from a desired region. The region to be removed is the region extending from the upper portion of a portion of the barrier layer 4a to the upper portion of the edge of the high-concentration n-type impurity region 6 adjacent to the barrier layer 4a.

[0171] Secondly, in Figure 25 In the process shown in FIG. 1 , SiO is deposited on the cap insulating film 10 a and on the high concentration n-type impurity region 6 not covered by the cap insulating film 10 a and on the AlGaN barrier layer 4 a using, for example, plasma CVD. b The electron supply insulating film 11 is constituted.

[0172] Next, a resist mask is formed on the electron supply insulating film 11, in which the region where the source electrode 7 and the drain electrode 8 are formed becomes an opening. The resist mask is used as an etching mask, and a wet etching method using buffered hydrofluoric acid or the like is adopted to remove the electron supply insulating film 11 and the cover insulating film 10a in the region where the source electrode 7 and the drain electrode 8 are formed.

[0173] Then, a multilayer metal film is deposited on the etching mask and in the opening by vapor deposition, and the etching mask is removed by lift-off, leaving the multilayer metal film in the region where the source electrode 7 and the drain electrode 8 are to be formed. Figure 27 In the process shown in the figure, heat treatment is performed in a nitrogen atmosphere at a temperature of 700 to 900°C using the RTA method, etc., to alloy the deposited multilayer film, thereby forming the source electrode 7 and the drain electrode 8 and increasing the positive charge generated at the interface of the area where the blocking layer 4a contacts the electron supply insulating film 11.

[0174] Examples of metal multilayer films include Ti (titanium) and Al multilayer films. When formed on a high-concentration n-type impurity region, any metal commonly used as an electrode can provide ohmic contact, so there are no particular limitations.

[0175] Secondly, in Figure 27 In the process shown in FIG, a resist pattern or the like is used as a mask, and wet etching with buffered hydrofluoric acid or the like is employed to remove the cap insulating film 10a and the electron supply insulating film 11 from desired regions. The region to be removed is the region extending from the upper portion of a portion of the barrier layer 4a on the side of the high-concentration n-type impurity region 5 to the upper portion of the edge of the high-concentration n-type impurity region 5 adjacent to the barrier layer 4a.

[0176] Secondly, in Figure 28 In the process shown in FIG. 1 , AlO is deposited on the electron supply insulating film 11 and the upper surfaces of the source electrode 7 and the drain electrode 8 not covered by the electron supply insulating film 11, on the high concentration n-type impurity region 5, and on the barrier layer 4a, for example, using atomic layer deposition. c The gate insulating film 12a is formed.

[0177] Secondly, in Figure 29 In the process shown in FIG, a resist mask RM is formed on the gate insulating film 12a, where the portion where the gate electrode 13 is to be formed becomes the opening OP. Then, a metal film composed of Ni is formed on the resist mask RM and in the opening OP by vapor deposition, and the resist mask RM is removed by a lift-off method, thereby forming the gate electrode 13. Figure 21 The heterojunction field effect transistor 500 is shown in FIG.

[0178] In the above-described manufacturing process of the heterojunction field effect transistor 500, as shown in FIG. Figure 26 As shown in FIG, the source electrode 7 and the drain electrode 8 are formed in Figure 25 The manufacturing process is performed after the deposition of the electron supply insulating film 11 shown in . This prevents the source electrode 7 and the drain electrode 8 from being exposed to the hydrofluoric acid used when removing the cap insulating film 10a and the electron supply insulating film 11. This makes it a suitable manufacturing process when the materials constituting the source electrode 7 and the drain electrode 8 are not resistant to hydrofluoric acid.

[0179] <Implementation Method 6>

[0180] Figure 30 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 600 made of a nitride semiconductor according to a sixth embodiment of the present invention. Figure 30 For use with Figure 16 The same components as those of the heterojunction field-effect transistor 200 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0181] At once Figure 30 As for the heterojunction field effect transistor 600 shown in FIG. Figure 1 The heterojunction field effect transistor 100 and Figure 16Compared to the heterojunction field-effect transistor 200 shown in FIG, the region where the high-concentration n-type impurity region 5 is formed is different. Specifically, in the heterojunction field-effect transistors 100 and 200, the high-concentration n-type impurity region 5 is formed from the region below the source electrode 7 to the region below the gate electrode 13. In the heterojunction field-effect transistor 600, the edge of the high-concentration n-type impurity region 5 on the gate electrode 13 side does not reach the region below the gate electrode. In other words, the high-concentration n-type impurity region 5 is not formed below the edge of the gate electrode 13 on the source electrode 7 side.

[0182] In the heterojunction field-effect transistor 600 having such a structure, as in the heterojunction field-effect transistors 100 and 200 , both the normally-off operation and the high-breakdown voltage operation can be achieved.

[0183] On the other hand, since the high-concentration n-type impurity regions 5 and 6 are formed by ion implantation or epitaxial growth, the sheet resistance is lower than the sheet resistance caused by the 2DEG generated between the barrier layer 4a and the channel layer 3a. Therefore, the on-resistance of the heterojunction field-effect transistor 600 in which the high-concentration n-type impurity region 5 does not reach below the gate electrode 13 may be higher than that of the heterojunction field-effect transistors 100 and 200.

[0184] However, as long as the amount of positive charge generated at the interface between the blocking layer 4a and the electron supply insulating film 11 is large enough and the sheet resistance of this region is low enough not to affect the on-resistance of the transistor, the same operating characteristics as those of the heterojunction field-effect transistors 100 and 200 can be obtained.

[0185] Modifications

[0186] Figure 31 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 601 made of a nitride semiconductor according to a modification of the sixth embodiment of the present invention. Figure 31 For use with Figure 30 The same components as the heterojunction field-effect transistor 600 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0187] exist Figure 30 In the heterojunction field effect transistor 600 shown in FIG, the source electrode 7 and the drain electrode 8 are made of SiN a The cover insulating film 10a, SiO b The electron supply insulating film 11 and AlO c In the heterojunction field effect transistor 601 , the source electrode 7 and the drain electrode 8 are covered only by the gate insulating film 12 a .

[0188] However, the edge of the gate electrode 13 on the source electrode 7 side is located above the boundary between the high-concentration n-type impurity region 5 and the barrier layer 4a via the cap insulating film 10a, the electron supply insulating film 11, and the gate insulating film 12a. In other words, the cap insulating film 10a and the electron supply insulating film 11 are stacked in this order only below the edge of the gate electrode 13 on the source electrode 7 side, and the gate insulating film 12a covers this stacked film.

[0189] In the heterojunction field-effect transistor 601 having such a structure, as in the heterojunction field-effect transistors 100 and 200 , both the normally-off operation and the high-breakdown voltage operation can be achieved.

[0190] In addition, as long as the amount of positive charge generated at the interface between the blocking layer 4a and the electron supply insulating film 11 is large enough and the sheet resistance of this region is low enough not to affect the on-resistance of the transistor, the same operating characteristics as those of the heterojunction field-effect transistors 100 and 200 can be obtained.

[0191] <Implementation Method 7>

[0192] <Device Configuration>

[0193] Figure 32 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 700 made of a nitride semiconductor according to a seventh embodiment of the present invention. Figure 32 For use with Figure 1 The same components as those of the heterojunction field-effect transistor 100 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0194] exist Figure 1 In the heterojunction field effect transistor 100 shown in FIG, a gate insulating film 12a is formed on the outermost surface except for the region where the gate electrode 13 is formed; in the heterojunction field effect transistor 700, the gate electrode 13 and the gate insulating film 12a are made of SiN d The gate electrode 13 is covered with the cover insulating film 14a. This prevents the leakage current from being reduced when heat treatment is performed after the gate electrode 13 is formed. This will be described in detail below.

[0195] In the heterojunction field-effect transistor 700 of the seventh embodiment, there is a concern about the reduction of leakage current caused by the formation of interface energy levels between the gate insulating film 12a and the barrier layer 4a on the lower side of the gate electrode 13. With regard to this interface energy level, as disclosed in International Publication No. 2018 / 037530, after forming the gate electrode 13, a heat treatment at 300 to 700°C is performed, thereby reducing it. In addition, as disclosed in International Publication No. 2018 / 220741, after forming the gate electrode 13, a heat treatment at 250 to 300°C is performed while applying a voltage to the gate electrode 13, thereby also reducing it.

[0196] However, in the embodiments 1 to 6 of the present invention, Figure 1 、 Figures 16-21 In the heterojunction field effect transistor described in, if heat treatment is performed in a state where a gate insulating film 12a is formed on the outermost surface of the drift region B after the gate electrode 13 is formed, the concentration of 2DEG generated at the interface between the channel layer 3a and the blocking layer 4a in the drift region B is reduced, and the region becomes highly resistive, resulting in a reduction in leakage current.

[0197] Next, the sheet resistance Rs in the 2DEG generated at the interface between the channel layer 3a and the barrier layer 4a by performing heat treatment on the surface of the drift region B with the gate insulating film 12a formed thereon is verified. ch The phenomenon of rising, and the gate insulating film 12a is formed by SiN d The structure of the cover insulating film 14a is covered to suppress the sheet resistance Rs ch The result of the rising phenomenon.

[0198] Figure 33 and Figure 34 The oblique view of the cross section of the sample 91 and the sample 92 used for verification. Figure 2 The same components as those of the sample 90 shown in FIG. 1 are denoted by the same reference numerals, and redundant descriptions are omitted.

[0199] In Sample 91 , the structure from the substrate 1 to the electron supply insulating film 11 is the same as that of Sample 90 , and a gate insulating film 12 a is formed so as to cover the surface of the electron supply insulating film 11 .

[0200] In terms of such a composition, Figure 2 On the electron supply insulating film 11 of the sample 90 shown in FIG. 1 , for example, AlO is deposited by atomic layer deposition. c The gate insulating film 12a is formed.

[0201] In Sample 92, the structure from the substrate 1 to the gate insulating film 12a is the same as that of Sample 91, and a SiN film is formed to cover the surface of the gate insulating film 12a. d The insulating cover film 14a is formed.

[0202] In terms of such a composition, Figure 33 On the gate insulating film 12a of the surface of the sample 91 shown in FIG. 1 , for example, SiN is deposited by plasma CVD. d The insulating film 14a is formed.

[0203] Figure 35 and Figure 36 Respectively in Figure 33 Sample 91 and Figure 34 ] The current-voltage (IV) characteristics of sample 92 shown in FIG were measured between the source electrode 7 and the drain electrode 8, with the horizontal axis representing voltage (Voltage: unit V) and the vertical axis representing current density (Current density: unit A / mm).

[0204] exist Figure 35 Figure 4 shows measurement results C4 (after Al2O3 deposition) taken immediately after the gate insulating film 12a was deposited, and C5 (after 300°C annealing) taken after the gate insulating film 12a was heat-treated at 300°C for 5 minutes. Note that since two samples were fabricated and measured on the same substrate, each measurement result represents two characteristics.

[0205] exist Figure 36 , the measurement result C6 (SiN d The measurement results are shown in Figure 7 (after deposition) and after heat treatment at 300°C for 5 minutes after deposition of the cover insulating film 14a (after annealing at 300°C). Note that since two samples were made on the same substrate for measurement, each measurement result represents two characteristics.

[0206] The width of the high-concentration n-type impurity regions 5 and 6 is set to 100 μm, and the distance between the high-concentration n-type impurity regions 5 and 6 is set to 4 μm (L=4 μm). Figure 35 、 Figure 36 Graphs 2 and 3 show characteristics of the barrier layer 4a in the case where the Al composition and thickness are 20% and 5 nm, respectively, and in the case where the Al composition and thickness are 15% and 7 nm, respectively.

[0207] In such Figure 35 In the case where the cover insulating film 14a is not formed, the current value is greatly reduced to below 0.05A / mm by heat treatment at 300°C. Figure 36In the case where the cover insulating film 14 a is formed as shown in FIG, although the current value decreases by the heat treatment at 300° C., a value of 0.2 A / mm or more is obtained.

[0208] From these results, it was experimentally confirmed that: c ) is formed on the insulating film 14a (SiN d ), the phenomenon that the sheet resistance increases due to the heat treatment and is caused by the 2DEG generated at the interface between the channel layer 3a and the barrier layer 4a is suppressed.

[0209] Regarding the phenomenon that the sheet resistance increases due to the heat treatment caused by the 2DEG generated at the interface between the channel layer 3a and the barrier layer 4a by the heat treatment after the gate insulating film 12a is formed, it can be said that the heat treatment after the gate insulating film 12a is performed on the SiO b The positive charge induced by the interface with AlGaN is reduced, and with it, the 2DEG generated at the interface between the channel layer 3a and the barrier layer 4a is reduced. b The interface with AlGaN induces a positive charge reduction effect.

[0210] In addition, the cover insulating film 14a is represented as SiN d The reason is that it is a compound of Si (silicon) and N (nitrogen), and since it is a deposited film, its composition is not necessarily the general Si3N4.

[0211] In addition, Figure 37 and Figure 38 , sheet resistance (unit: Ω / sq) obtained from IV characteristics measured using different patterns in a range of 2 to 20 μm between the high-concentration n-type impurity regions 5 and 6 is shown.

[0212] exist Figure 37 In Figure 33 The sheet resistance of sample 91 before and after heat treatment at 300°C is shown as ■ and ◇, respectively. Figure 38 In Figure 34 The sheet resistances before and after the heat treatment at 300° C. in Sample 92 shown in FIG. 5 are denoted by ■ and ◇, respectively.

[0213] Depend on Figure 37 It was confirmed that when the cover insulating film 14a was not formed, the sheet resistance increased by about one digit by the heat treatment at 300°C. Figure 38 It was confirmed that when the cover insulating film 14 a was formed, an increase in sheet resistance was significantly suppressed.

[0214] As described above, in the heterojunction field-effect transistor 700 according to the seventh embodiment, both the normally-off operation and the high-breakdown voltage operation are achieved.

[0215] <Manufacturing method>

[0216] Next, an example of a method for manufacturing the heterojunction field effect transistor 700 is described using a flowchart showing the manufacturing steps in order. Figures 6 to 15 、 Figure 1 、 Figure 32 To explain.

[0217] First, as in embodiment 1, Figures 6 to 15 As explained, Figure 1 The heterojunction field effect transistor 100 is shown in FIG.

[0218] Next, a layer of SiN is deposited on the gate electrode 13 and the gate insulating film 12a by, for example, plasma CVD. d The insulating film 14a is formed to obtain Figure 32 The heterojunction field effect transistor 700 is shown in FIG.

[0219] Next, heat treatment at at least 300° C. is performed to reduce the interface energy level formed between the gate insulating film 12 a and the barrier layer 4 a .

[0220] By performing heat treatment for reducing the interface energy level after forming the cover insulating film 14 a in this manner, it is possible to suppress a decrease in current due to the heat treatment.

[0221] <Variation 1>

[0222] Figure 39 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 701 made of a nitride semiconductor according to a first variation of the seventh embodiment of the present invention. Figure 39 For use with Figure 32 The same components as the heterojunction field-effect transistor 700 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0223] exist Figure 32 In the heterojunction field effect transistor 700 shown in FIG, the cover insulating film 14a is formed so as to cover the entire region of the transistor 700. Figure 39 In the heterojunction field-effect transistor 701 shown in FIG, the cover insulating film 14a is provided so as to fill the space between the side surfaces of the step height difference portion of the gate insulating film 12a from the side surfaces of the gate electrode 13, and is formed so as to cover the upper portion of the drift region B. This configuration is obtained by selectively removing the cover insulating film 14a after forming the heterojunction field-effect transistor 700.

[0224] The reduction in leakage current caused by heat treatment after the gate insulating film 12 a is formed is caused by an increase in resistance in the drift region B. Therefore, if at least this region is covered with the cover insulating film 14 a , the reduction in leakage current can be suppressed.

[0225] <Variation 2>

[0226] Figure 40 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 702 made of a nitride semiconductor according to a second variation of the seventh embodiment of the present invention. It should be noted that this variation is a structure in which the heterojunction field effect transistor 600 according to the sixth embodiment is provided with a covering insulating film 14a. Figure 40 For use with Figure 30 The same components as the heterojunction field-effect transistor 600 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0227] At once Figure 30 As for the heterojunction field effect transistor 600 shown in FIG. Figure 1 The heterojunction field effect transistor 100 shown in FIG. Figure 16 Compared to the heterojunction field-effect transistor 200 shown in FIG, the region in which the high-concentration n-type impurity region 5 is formed is different. Specifically, in the heterojunction field-effect transistors 100 and 200, the high-concentration n-type impurity region 5 is formed from the region below the source electrode 7 to the region below the gate electrode 13. In the heterojunction field-effect transistor 600, the edge of the high-concentration n-type impurity region 5 on the gate electrode 13 side does not reach the region below the gate electrode. In other words, the high-concentration n-type impurity region 5 is not formed below the edge of the gate electrode 13 on the source electrode 7 side.

[0228] In the heterojunction field effect transistor 600 having such a structure, by performing heat treatment after forming the gate insulating film 12a, the resistance is increased even in the region from the high concentration n-type impurity region 5 to the lower side of the gate electrode 13, and the leakage current is reduced. In order to suppress this, as shown in FIG. Figure 40 As shown in FIG, the cover insulating film 14a is formed so as to cover the entire region of the heterojunction field effect transistor 700, and the upper portion of the above region is covered with the cover insulating film 14a.

[0229] <Implementation Method 8>

[0230] Figure 41 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 800 made of a nitride semiconductor according to an eighth embodiment of the present invention. Figure 41 For use with Figure 1The same components as those of the heterojunction field-effect transistor 100 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0231] In the heterojunction field-effect transistors of embodiments 1 to 7 described above, a scheme in which the channel layer 3a is composed of GaN and the barrier layer 4a is composed of AlGaN is described, but GaN and AlGaN are not necessarily used. As for the effects obtained by the heterojunction field-effect transistors of embodiments 1 to 7, the same effects can be obtained even if the channel layer and the barrier layer are composed of nitride semiconductors other than GaN and AlGaN.

[0232] At once Figure 41 In the heterojunction field effect transistor 800 shown in FIG, the channel layer 3a made of GaN and the barrier layer 4a made of AlGaN are respectively made of Al x1 In y1 Ga 1-x1-y1 The channel layer 3 is composed of N (aluminum indium gallium nitride) and Al x2 In y2 Ga 1-x2-y2 The barrier layer 4 is composed of N. In addition, the Al x2 In y2 Ga 1-x2-y2 N and Al constituting the channel layer 3 x1 In y1 Ga 1-x1-y1 Compared with N, the band gap is larger.

[0233] In the case of the heterojunction field effect transistor 800, instead of using Figure 6 The growth of the channel layer 3a and the barrier layer 4a described above is adjusted as In z Al x Ga 1-x-z The flow rate, pressure and temperature (growth conditions) of the raw material gas trimethylindium, trimethylaluminum, trimethylgallium, ammonia, etc. of N (0<x≤1, 0<z≤1) are used to grow the channel layer 3 and the barrier layer 4, thereby forming the channel layer 3 and the barrier layer 4 of the desired composition respectively.

[0234] <Implementation Method 9>

[0235] Figure 42 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 900 made of a nitride semiconductor according to a ninth embodiment of the present invention. Figure 42 For use with Figure 1 The same components as those of the heterojunction field-effect transistor 100 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0236] In the heterojunction field effect transistors of the first to eighth embodiments described above, the cap insulating film 10a is made of SiN a The embodiment of the present invention has been described. If the nitrogen can be suppressed from being released from the nitride semiconductor constituting the barrier layer during the heat treatment at 700°C or above, the cap insulating film does not necessarily need to be made of SiN. a Composition, such as Figure 42 As shown in FIG, for example, AlN d (aluminum nitride) or BN e The cap insulating film 10 is made of an insulating film or semiconductor film made of (boron nitride) or the like. The heterojunction field effect transistor 900 having such a structure can achieve the same effects as those achieved by the heterojunction field effect transistors of Embodiments 1 to 8.

[0237] In the case of the heterojunction field effect transistor 900, instead of using Figure 10 The deposition of the cap insulating film 10a described above is carried out by a sputtering method using a target composed of Al or B, etc. d or BN e The cover insulating film 10 is formed by deposition.

[0238] <Implementation Method 10>

[0239] Figure 43 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 1000 made of a nitride semiconductor according to a tenth embodiment of the present invention. Figure 43 For use with Figure 1 The same components as those of the heterojunction field-effect transistor 100 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0240] In the heterojunction field effect transistors of the first to ninth embodiments described above, the gate insulating film 12a is made of AlO. c The scheme of the structure is described, in which the barrier layer is made of Al x1 In y1 Ga 1-x1-y1 N, if it is composed of an insulator or semiconductor with a larger band gap than that of SiO b Compared with the material with less positive charge formed at the interface with the barrier layer, it is not necessarily made of AlO c Composition, such as Figure 43 As shown in, for example, AlGa f O a N g The gate insulating film 12 is made of (aluminum gallium oxynitride).

[0241] The heterojunction field-effect transistor 1000 having such a structure can achieve the same effects as those achieved by the heterojunction field-effect transistors of Embodiments 1 to 9.

[0242] In the case of the heterojunction field effect transistor 1000, instead of using Figure 14 The deposition of the gate insulating film 12a is described by adjusting the flow rate, pressure, and temperature (deposition conditions) of trimethylaluminum, trimethylgallium, oxygen, ozone, and nitrogen as the raw material gases of the gate insulating film so that AlGa f O a N g The gate insulating film 12 is formed by deposition.

[0243] <Implementation Method 11>

[0244] Figure 44 This is a perspective view showing a cross-sectional structure of a heterojunction field effect transistor 1100 made of a nitride semiconductor according to Embodiment 11 of the present invention. Figure 44 For use with Figure 1 The same components as those of the heterojunction field-effect transistor 100 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0245] In the heterojunction field effect transistor of the seventh embodiment described above, the cover insulating film 14a is made of SiN d The configuration has been described. If the heat treatment after forming the gate insulating film 12 can be suppressed, the SiO b The reduction of positive charge induced by the interface with AlGaN is not necessarily caused by SiN d Composition, such as Figure 44 As shown in FIG, for example, AlN d (aluminum nitride) or BN e The cover insulating film 14 is made of an insulating film such as (boron nitride) or a semiconductor film. The heterojunction field effect transistor 1100 having such a structure can achieve the same effects as those achieved by the heterojunction field effect transistor of the seventh embodiment.

[0246] In the case of the heterojunction field effect transistor 1100, instead of using Figure 32 The deposition of the cover insulating film 14a described above is carried out by a sputtering method using a target composed of Al or B, etc. d or BN e The cover insulating film 14 is formed by deposition.

[0247] <Implementation Method 12>

[0248] Figure 45This is a perspective view showing a cross-sectional structure of a heterojunction field-effect transistor 1200 made of a nitride semiconductor according to Embodiment 12 of the present invention. Figure 45 For use with Figure 1 The same components as those of the heterojunction field-effect transistor 100 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0249] exist Figure 41 In the heterojunction field effect transistor 800 of the eighth embodiment shown in FIG, the channel layer 3 is made of Al x1 In y1 Ga 1-x1-y1 N constitutes Figure 45 In the heterojunction field effect transistor 1200 shown in FIG, a channel layer 3 is replaced with an Al x1 Ga 1-x1 The channel layer 3b is composed of N(y1=0).

[0250] By having Al x1 Ga 1-x1 The channel layer 3b composed of N and the Al x1 In y1 Ga 1-x1-y1 Compared with the channel layer 3 composed of N, alloy scattering of electrons traveling as carriers at the heterointerface between the channel layer 3b and the barrier layer 4a is suppressed, so the mobility of electrons in the channel formed at the heterointerface is improved, thereby achieving an increase in leakage current.

[0251] Furthermore, using a material with a relatively high Al composition (x1) increases the band gap, making it less susceptible to damage even when high voltages are applied, enabling high-voltage operation. In principle, x1 in this case is within the range of x1 < 1. However, in practice, the difference in Al composition with the barrier layer must be a few percent. Therefore, when using AlN as the barrier layer, x1 is in the range of 0.97 to 0.98. Furthermore, x1 and other compositions are determined by adjusting the mobility and electron concentration to the desired values.

[0252] Furthermore, by reducing the number of constituent elements of the channel layer, crystal growth becomes easier, thereby easily reducing defects in the crystal, thereby improving various characteristics such as leakage current and current collapse caused by defects.

[0253] In this regard, if we focus on the number of elements constituting the channel layer, Figure 1 In the heterojunction field effect transistor 100 of the embodiment 1 shown in FIG, a channel layer 3a is provided which is made of GaN (x1=0, y1=0). By distinguishing the channel layer 3a made of GaN from the channel layer 3a made of Al2O3 and the channel layer 3a made of three elements, the channel layer 3a is provided which is provided with a GaN channel.x1 Ga 1-x1 Compared to a channel layer 3b composed of N, alloy scattering is further suppressed, thereby further improving the mobility of electrons in the channel formed at the heterojunction interface, further increasing the leakage current. Furthermore, crystal growth is facilitated, reducing the amount of impurities unintentionally incorporated into the channel layer 3a, thereby suppressing current collapse, which is primarily caused by electron traps caused by these impurities. Furthermore, this facilitated crystal growth makes it easier to reduce defects in the crystal, thereby improving various properties such as leakage current and current collapse caused by defects.

[0254] It should be noted that in this embodiment, Figure 41 The composition and Figure 45 The composition and Figure 1 The composition and Figure 45 The materials constituting the channel layer have been described in comparison with the configuration of , and needless to say, by replacing the channel layer of other embodiments with the channel layer 3b, the same effect as that of the heterojunction field-effect transistor 1200 of this embodiment can be achieved.

[0255] <Implementation Method 13>

[0256] Figure 46 This is a perspective view showing a cross-sectional structure of a heterojunction field-effect transistor 1300 made of a nitride semiconductor according to Embodiment 13 of the present invention. Figure 46 For use with Figure 1 The same components as those of the heterojunction field-effect transistor 100 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0257] At once Figure 41 As for the heterojunction field effect transistor 800 shown in FIG, x2 In y2 Ga 1-x2-y2 The barrier layer 4 composed of N is Figure 46 In the heterojunction field effect transistor 1300 shown in FIG, a barrier layer 4 is replaced with an Al x2 Ga 1-x2 The barrier layer 4a is composed of N (y2=0).

[0258] By having Al x2 Ga 1-x2The barrier layer 4a composed of N reduces alloy scattering experienced by electrons traveling as carriers at the heterointerface between the channel layer 3 and the barrier layer 4a. This improves electron mobility in the channel formed at the heterointerface, thereby increasing leakage current. Furthermore, reducing the number of elements constituting the barrier layer facilitates crystal growth, thereby facilitating the reduction of defects in the crystal, thereby improving various properties such as leakage current and current collapse caused by defects.

[0259] <Variation 1>

[0260] Figure 47 This is a perspective view showing a cross-sectional structure of a heterojunction field-effect transistor 1301 made of a nitride semiconductor according to Modification 1 of Embodiment 13 of the present invention. Figure 47 For use with Figure 46 The same components as the heterojunction field-effect transistor 1300 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0261] At once Figure 41 As for the heterojunction field effect transistor 800 shown in FIG, x2 In y2 Ga 1-x2-y2 The barrier layer 4 composed of N is Figure 47 In the heterojunction field effect transistor 1301 shown in FIG, a layer composed of In is provided in place of the barrier layer 4. y2 Al y2 The barrier layer 4b is composed of N (x2+y2=1).

[0262] By doing so, y2 Al y2 The barrier layer 4b composed of N reduces alloy scattering experienced by electrons traveling as carriers at the heterointerface between the channel layer 3 and the barrier layer 4b. This improves electron mobility in the channel formed at the heterointerface, thereby increasing leakage current. Furthermore, reducing the number of elements constituting the barrier layer facilitates crystal growth, thereby facilitating the reduction of defects in the crystal, thereby improving various properties such as leakage current and current collapse caused by defects.

[0263] <Variation 2>

[0264] Figure 48 This is a perspective view showing a cross-sectional structure of a heterojunction field-effect transistor 1302 made of a nitride semiconductor according to a second variation of the embodiment 13 of the present invention. Figure 48 For use with Figure 46 The same components as the heterojunction field-effect transistor 1300 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0265] At once Figure 41 As for the heterojunction field effect transistor 800 shown in FIG, x2 In y2 Ga 1-x2-y2 The barrier layer 4 composed of N is Figure 48 The heterojunction field effect transistor 1302 shown in FIG. 1 includes a barrier layer 4 c made of AlN (x2=0, y2=0) instead of the barrier layer 4 .

[0266] By including the AlN barrier layer 4c, electrons traveling as carriers at the heterojunction interface between the channel layer 3 and the barrier layer 4c are further reduced from alloy scattering, thereby further improving the mobility of electrons in the channel formed at the heterojunction interface. Furthermore, by reducing the number of elements constituting the barrier layer, crystal growth is facilitated, thereby easily reducing defects in the crystal, thereby improving various properties such as leakage current and current collapse caused by defects.

[0267] It should be noted that in this embodiment, Figure 41 The composition and Figures 46 to 48 The materials constituting the barrier layer have been described in comparison with the configuration of the embodiment. Needless to say, by replacing the barrier layer of other embodiments with the barrier layer 4b or 4c, the same effects as those of the heterojunction field-effect transistors 1300 to 1302 of this embodiment can be achieved.

[0268] <Implementation Method 14>

[0269] With respect to the heterojunction field-effect transistors of Embodiments 1 to 13 described above, only the configurations that deserve special attention have been described. However, as long as the transistors operate as transistors, the following configurations can be employed.

[0270] When SiC or Si, a material different from the channel layer, is used as the substrate, a buffer layer becomes necessary. However, when GaN, AlGaN, or AlInGaN, the same material as the channel layer, is used as the substrate, a buffer layer is not necessarily required. In addition, the buffer layer is not necessarily undoped.

[0271] Furthermore, by forming the four elements of a channel layer, a barrier layer, an electron supply insulating film, and a gate insulating film on a substrate, the minimum effects described in Embodiments 1 to 13 can be obtained, achieving both normally-off operation and high-breakdown voltage operation.

[0272] Furthermore, while the heterojunction field-effect transistors of Embodiments 1 to 13 describe only the minimum semiconductor layers required for transistor operation, other semiconductor layers may be formed as long as the transistor operates. For example, a nitride semiconductor layer having a composition different from that of the channel layer and barrier layer may be formed below the channel layer.

[0273] In addition, the nitride semiconductor layers other than the channel layer and the barrier layer are not necessarily undoped, and may contain impurities such as Si, Mg (magnesium), Fe (iron), C and Ge (germanium) as long as the amount does not hinder the operation of the transistor.

[0274] The n-type impurities doped into the high-concentration n-type impurity regions 5 and 6 may be impurities that function as n-type dopants in nitride semiconductors such as Si, Ge, oxygen, and nitrogen vacancies.

[0275] Furthermore, although the cap insulating film 10 is formed on the upper sides of the barrier layer 4, the high-concentration n-type impurity region 5, the high-concentration n-type impurity region 6, the source electrode 7, and the drain electrode 8, it may or may not be formed in other regions, as long as it is formed in regions for the purpose of forming the electric field relaxation structure described in Embodiments 1 to 13 and protecting the barrier layer surface during heat treatment. For example, the cap insulating film 10 may or may not be formed on the upper sides of the source electrode 7 and the drain electrode 8.

[0276] In addition, SiO b As for the electron supply insulating film 11, it may or may not be formed in other regions as long as it is formed on the barrier layer 4 in the drift region B. For example, it may or may not be formed on the upper side of the source electrode 7 and the drain electrode 8.

[0277] In addition, SiO b The electron supply insulating film 11 is not necessarily composed of one layer, as long as the insulating film in contact with the barrier layer 4 is made of SiO b The electron supply insulating film may be formed by depositing AlGa c O a N b 、AlO a N b 、AlO a , SiO2, Si3N4 and other materials.

[0278] The gate insulating film 12a may or may not be formed in other regions as long as it is formed at least in the region below the gate electrode 13. For example, it may or may not be formed above the source electrode 7 and the drain electrode 8.

[0279] In addition, the gate insulating film 12a does not necessarily have to be composed of a single layer. As long as the insulating film in contact with the barrier layer 4 is composed of the above-mentioned material, AlGaAs may be deposited thereon. c O a N b 、AlOa N b 、AlO a , SiO2, Si3N4 and other materials.

[0280] In addition, SiN d As for the covering insulating film 14a, as long as it is formed on the barrier layer 4 in the drift region B or on the gate insulating film 12a in the region from the high-concentration n-type impurity region 5 to the gate electrode, it may or may not be formed in other regions. For example, it may or may not be formed on the upper side of the source electrode 7 and the drain electrode 8.

[0281] In addition, SiN d The covering insulating film 14a is not necessarily composed of one layer, as long as the insulating film in contact with the gate insulating film 12a is made of SiO b The electron supply insulating film may be formed by depositing AlGa c O a N b 、AlO a N b 、AlO a , SiO2, Si3N4 and other materials.

[0282] In addition, in the above description, only the minimum structure required for the transistor to operate is disclosed. Finally, a protective film, field plate electrode, wiring, air bridge, via hole, etc. are formed to form a semiconductor device for use.

[0283] While the present invention has been described in detail, the above description is in all aspects illustrative and the present invention is not limited thereto. It will be understood that numerous modifications not shown here are conceivable without departing from the scope of the present invention.

[0284] It should be noted that the present invention can freely combine the various embodiments, or can appropriately modify or omit the various embodiments within the scope of the present invention.

Claims

1. A semiconductor device comprising: substrate; a channel layer provided on the substrate and composed of a first nitride semiconductor; a barrier layer provided on an upper portion of the channel layer and composed of a second nitride semiconductor having a band gap larger than a band gap of the first nitride semiconductor; A first n-type impurity region and a second n-type impurity region are both provided in the upper portion of the channel layer, the first impurity region and the second impurity region are provided with a gap between each other, and the barrier layer is sandwiched between the first impurity region and the second impurity region; a source electrode and a drain electrode, which are respectively disposed on the first impurity region and the second impurity region; a drift region having an insulating film provided on the barrier layer except for an edge portion of the barrier layer on the source electrode side so as to be in contact with the barrier layer; a channel region at an edge portion of the barrier layer and at a position separated from the second impurity region, on which the insulating film is not formed; a gate insulating film formed on the channel region and the drift region in contact with the blocking layer and the insulating film, respectively; and a gate electrode provided on the gate insulating film on the channel region and a portion of the drift region, The barrier layer in the channel region and the barrier layer in the drift region have the same thickness and composition, The sheet resistance caused by the two-dimensional electron gas generated at the interface between the channel layer and the barrier layer in the channel region is 10 kΩ / sq or more. A sheet resistance caused by a two-dimensional electron gas generated at an interface between the channel layer and the barrier layer in the drift region is 10 kΩ / sq or less.

2. The semiconductor device according to claim 1, wherein The channel layer is made of aluminum indium gallium nitride, The barrier layer is composed of aluminum gallium nitride, The insulating film is composed of a silicon oxide film, The gate insulating film is made of aluminum oxide or aluminum gallium oxynitride.

3. The semiconductor device according to claim 1, wherein The channel layer and the barrier layer are doped with elements other than the main elements constituting them in an amount of at least 1×10 17 cm -3 the following.

4. The semiconductor device according to claim 1, wherein The gate insulating film is provided so as to be in contact with an edge portion of the first impurity region on the barrier layer side.

5. The semiconductor device according to claim 1, wherein The insulating film is also formed so as to be in contact with a portion of the first impurity region. The gate insulating film is provided so as to cover from the edge portion of the first impurity region on the barrier layer side to the insulating film. The gate electrode is provided so as to cover the gate insulating film covering the insulating film.

6. The semiconductor device according to claim 1, comprising a cap insulating film provided in contact with at least a portion of the first impurity region. The insulating film is also provided on the cap insulating film, and the gate insulating film and the gate electrode are provided thereon. The cap insulating film is composed of any one of silicon nitride, aluminum nitride, and boron nitride.

7. The semiconductor device according to claim 6, wherein The cap insulating film is also formed so as to be in contact with the source electrode and the drain electrode.

8. The semiconductor device according to claim 1, wherein The channel layer is composed of aluminum gallium nitride, The barrier layer is composed of aluminum gallium nitride, The insulating film is composed of a silicon oxide film, The gate insulating film is made of aluminum oxide or aluminum gallium oxynitride.

9. The semiconductor device according to claim 1, wherein The channel layer is composed of gallium nitride, The barrier layer is composed of aluminum gallium nitride, The insulating film is composed of a silicon oxide film, The gate insulating film is made of aluminum oxide or aluminum gallium oxynitride.

10. The semiconductor device according to any one of claims 1 to 9, further comprising a cover insulating film provided so as to cover at least the gate insulating film above a region of the barrier layer excluding the edge portion. The cover insulating film is made of any one of silicon nitride, aluminum nitride, and boron nitride.

11. A method for manufacturing a semiconductor device, comprising: (a) forming a channel layer composed of a first nitride semiconductor on a substrate; (b) forming a barrier layer composed of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor on an upper portion of the channel layer; (c) forming an n-type first impurity region and an n-type second impurity region in the upper portion of the channel layer with the barrier layer interposed therebetween and spaced apart from each other; (d) forming a source electrode and a drain electrode on the first impurity region and the second impurity region, respectively; (e) forming an insulating film on the barrier layer except for an edge portion of the barrier layer on the source electrode side so as to be in contact with the barrier layer, and performing a heat treatment at 700 to 900° C. to form a drift region; (f) exposing at least the edge portion of the barrier layer to form a channel region; (g) forming a gate insulating film on the channel region and the drift region so as to be in contact with the barrier layer and the insulating film, respectively; and (h) forming a gate electrode on the gate insulating film on the channel region and on a portion of the drift region, Carrying out the steps (e), (f), (g) and (h) in sequence, The barrier layer in the channel region and the barrier layer in the drift region have the same thickness and composition.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: have: Before the step (e), a step of forming a cap insulating film so as to cover at least a region of the barrier layer excluding the edge portion on the source electrode side; The cap insulating film is composed of any one of silicon nitride, aluminum nitride, and boron nitride.

13. The method for manufacturing a semiconductor device according to claim 11 or claim 12, wherein: Also features: After the step (h), a step of (i) forming a cover insulating film so as to cover at least the gate insulating film above the region of the barrier layer excluding the edge portion; and After the step (i), a step of performing a heat treatment at a temperature of at least 300° C. is performed. The cover insulating film is made of any one of silicon nitride, aluminum nitride, and boron nitride.

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