Highly regular logic design for efficient 3D integration related application data

Abstract

An integrated circuit includes an array of unit cells, each unit cell in the array including field effect transistors arranged in a stack. A local interconnect structure forms a select conductive path between select terminals of the field effect transistors to define cell circuitry confined within each unit cell. An array of contacts is disposed on an accessible surface of the unit cell, wherein each contact is electrically coupled to a corresponding electrical node of the cell circuitry.

Description

[0001] This application claims priority to U.S. Provisional Patent Application No. 62 / 879,721, filed July 29, 2019, entitled “Ultra-regular Logic Design for Efficient 3D Integration,” and U.S. Patent Application No. 16 / 847,001, filed April 13, 2020, entitled “HIGHLYREGULAR LOGIC DESIGN FOR EFFICIENT 3D INTEGRATION RELATED APPLICATION DATA,” the entire disclosures of which are incorporated herein by reference. Background Technology

[0002] This disclosure pertains to the manufacture of integrated circuits and microelectronic devices.

[0003] In the fabrication of semiconductor devices (especially at the microscale), various manufacturing processes are performed, such as film deposition, etch mask creation, patterning, material etching and removal, and doping. These processes are repeated to form the desired semiconductor device elements on a substrate. Historically, microfabrication has been used to create transistors on a single plane, forming wiring / metallization layers above the active device plane, and thus, this is characterized as two-dimensional (2D) circuits using 2D fabrication techniques. While miniaturization has greatly increased the number of transistors per unit area in 2D circuits, these miniaturization efforts will face even greater challenges as miniaturization moves into the nanoscale semiconductor device fabrication node. Semiconductor device manufacturers have expressed aspirations for three-dimensional (3D) semiconductor circuits where transistors are stacked on top of each other.

[0004] While critical dimension miniaturization inevitably reaches saturation, 3D integration (3Di) is considered a viable option for continuing semiconductor miniaturization efforts. Two-dimensional transistor density miniaturization cannot be further advanced when the contact-gate pitch reaches its miniaturization limit due to fabrication variability and electrostatic constraints. Even experimental new transistor designs that may one day break these contact-gate pitch miniaturization limits (such as vertical-channel gate-around transistors) have their own miniaturization problems due to resistance, capacitance, and reliability issues, thus limiting the density at which transistors can be wired into circuits.

[0005] 3Di (vertical stacking of multiple devices) aims to break through these miniaturization limits by increasing transistor density in terms of volume rather than area. While this concept has been successfully demonstrated and implemented in the flash memory industry (e.g., 3D NAND), manufacturers of mainstream complementary metal-oxide-semiconductor (CMOS) VLSI for CPU and GPU products remain hesitant to adopt 3D integration as a primary way to drive semiconductor development. The main reason for not adopting 3Di for any application other than niche applications (e.g., memory stacked on top of logic in machine learning accelerators used in artificial intelligence chips) is the known inherent inefficiency of the proposal.

[0006] One approach to successful semiconductor miniaturization is to moderately increase process complexity on a larger number of transistors. In 2D miniaturization, this is achieved by reducing feature size and increasing transistor density while keeping wafer manufacturing costs largely constant. However, 3D integration, which doubles the volumetric density of transistors, has not offered a viable miniaturization solution due to the doubling of manufacturing costs. Successful miniaturization using 3Di lies in fundamentally reducing process and design complexity to minimize the cost increase per node. Summary of the Invention

[0007] An integrated circuit includes an array of unit cells, each unit cell comprising a stacked bulk field-effect transistor. Local interconnect structures form selective conductive paths between select terminals of these field-effect transistors to define a unit circuit system confined within each unit cell. An array of contacts is disposed on an accessible surface of the unit cell, wherein each contact is electrically coupled to a corresponding electrical node of the unit circuit system.

[0008] In an additional or alternative aspect to the inventive concept disclosed herein, the integrated circuit includes a functionalized layer comprising conductive wiring segments formed between selected contacts on respective accessible surfaces of one or more unit cells in the array.

[0009] In another additional or alternative aspect of the inventive concept disclosed herein, these unit cells have a common occupancy space and are positioned in the array such that the diffusion interruption of the unit circuitry surrounding each unit cell is aligned with the diffusion interruption in the adjacent unit cell, thereby forming a continuous space extending across all unit cells in the corresponding columns of the array.

[0010] In yet another additional or alternative aspect of the inventive concept disclosed herein, the integrated circuit includes power walls disposed in these consecutive spaces, which provide power to at least the unit cells in the respective columns of the array.

[0011] In another additional or alternative aspect of the inventive concept disclosed herein, the upper surfaces of these respective power walls are exposed on the accessible surfaces of each unit cell in the column of the array.

[0012] In yet another additional or alternative aspect of the inventive concept disclosed herein, the unit circuit system of all unit cells in the array is identical.

[0013] In another additional or alternative aspect of the inventive concept disclosed herein, the unit circuit system is constructed using similar front-end and intermediate process technologies.

[0014] In yet another additional or alternative aspect of the inventive concept disclosed herein, these front-end and intermediate process steps include a multiplication patterning process.

[0015] In another additional or alternative aspect of the inventive concept disclosed herein, these multiplication patterning processes include directional self-assembly and / or self-aligned multiple exposure patterning techniques.

[0016] In yet another additional or alternative aspect of the inventive concept disclosed herein, these field-effect transistors are stacked in complementary pairs.

[0017] In another additional or alternative aspect of the inventive concept disclosed herein, the gates of these complementary field-effect transistor pairs are connected together.

[0018] In yet another additional or alternative aspect of the inventive concept disclosed herein, the number of complementary pairs in the field-effect transistor stack is greater than one.

[0019] It should be understood that the Summary of this invention does not specify every embodiment and / or incremental novelty aspect of this disclosure or the claimed invention. Rather, the Summary provides only a preliminary discussion of different embodiments and points of novelty corresponding to conventional techniques. The Detailed Description section of this disclosure and the corresponding drawings provide additional details and / or possible perspectives on the invention and its embodiments. Attached Figure Description

[0020] Figure 1 This is a top view illustration of an example unit cell that can demonstrate the principles of this disclosure.

[0021] Figure 2 (including) Figures 2A to 2E ) is revealed Figure 1 The diagram shows the internal 3D structure of the example unit cell.

[0022] Figure 3A This is a diagram of a 10×10 unit cell array based on the principles described in this article, used to highlight the regularity of the front-end process (FEOL) layout and intermediate process (MEOL) layout.

[0023] Figure 3B This is a diagram of a unit cell array based on the principles described herein, depicting only the active channel region and the source / drain contacts.

[0024] Figure 3C This is a diagram of a unit cell array based on the principles described in this paper, depicting a cut mask mesh.

[0025] Figure 3D This is a diagram of a unit cell array based on the principles described in this article, in which only the VDD and VSS power rails are depicted.

[0026] Figure 4 This is a top view illustration of a unit cell based on the principles described in this article, which has been functionalized to form a two-fingered inverter (INV2) logic unit.

[0027] Figure 5 This is a top view illustration of a pair of unit cells that are functionalized as dual-input AND-OR-NOT (AOI22) logic units according to the principles described herein.

[0028] Figure 6 This is a top view illustration of a pair of unit cells functionalized as a dual-input AND (AND2) logic unit according to the principles described herein.

[0029] Figure 7 This is a top view illustration of a pair of unit cells functionalized as dual-input NAND2 logic cells according to the principles described herein, wherein each unit cell has a single CFET pair instead of two CFET pairs in its corresponding active device stack. Detailed Implementation

[0030] The concept of the invention is best described through certain embodiments thereof, which are described in detail herein with reference to the accompanying drawings, in which similar reference numerals refer to similar features. It should be understood that, when used herein, the term "invention" is intended to refer to the inventive concept implied by the embodiments described below, and not merely to the embodiments themselves. It should further be understood that the overall inventive concept is not limited to the illustrative embodiments described below, and the following description should be read with this understanding.

[0031] Furthermore, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment of a construction, process, design, technique, etc., specified herein as exemplary is not necessarily to be construed as being more preferred or advantageous than other such embodiments. The particular quality or suitability of the examples indicated herein as exemplary is neither intentional nor should be inferred.

[0032] The techniques described herein include methods for manufacturing integrated circuits and semiconductor devices that use a common front-end and intermediate process structure for all logic cells, and then functionalize these common unit cells in a shallow metallization layer. One embodiment includes an integrated circuit having an array of unit cells. Each unit cell may have the same unit cell height and the same unit cell width. Each unit cell may have at least two vertical transistor levels, wherein, in a stack, a first field-effect transistor is positioned above a second field-effect transistor. Each field-effect transistor may have a full-around gate channel. Each unit cell may include local interconnect wiring that electrically connects the source / drain to the gate structure. One or more wiring layers may be positioned directly above the unit cell array, wherein at least two different types of functional logic cells may be formed from the array of unit cells. Therefore, such techniques can provide simplified process and reduced cost 3D integration.

[0033] The techniques described herein include those for physically constructing or otherwise realizing integrated circuits as physical objects, including techniques for designing and manufacturing integrated circuits. In fact, those skilled in the art who understand this disclosure will be able to apply the principles described herein to suitable electronic / engineering design automation (EDA) and foundry platforms through which the structures described herein can be physically constructed and / or used as components in a wider range of circuit designs. The techniques described herein are particularly applicable to monolithically integrated 3D CMOS (Complementary Metal-Oxide-Semiconductor) circuits, such as U.S. Provisional Patent Application Serial No. 62 / 727,097, filed September 5, 2018, entitled “Architecture Design and Processes for Manufacturing Monolithically Integrated 3D CMOS Logic and Memory,” which is incorporated herein by reference in its entirety.

[0034] The functionalization of logic can be performed, for example, as a back-to-back (BEOL) operation via a metallization layer above an easily accessible grid of contacts, which provides electrical access to the internal circuit components of the three-dimensional unit cell.

[0035] The embodiments described herein involve a footprint with a common two contact-gate pitches (cpp) across the unit cell width. While this constraint limits the unit cell to a single transistor track with a single diffuse break on each side, this design offers significant miniaturization advantages and helps to significantly reduce complexity. For example, designing all unit cells onto a fixed-width footprint allows for diffuse break alignment across all rows of the corresponding logic block. This arrangement facilitates the formation of local power rails extending into the unoccupied space of the diffuse breaks, thus providing unobstructed access to the device's source region without obstructing signal tracks. This arrangement also provides a highly uniform local layout environment, eliminating device variability dependent on complex layouts, which has become a significant performance degradation factor in advanced technology nodes. Using unit cells with equal widths and, more commonly, equal heights, allows logic functions (which require more transistors than are available in a stack with single-transistor track widths) to be written by optimally adjaculating unit cells horizontally or vertically, providing critical freedom in simplifying wire shapes.

[0036] Figure 1 This is a top view illustration of an example unit 100 that embodies the principles of this disclosure. Figure 1 The cell view depicts the accessible surface 105 of the unit cell 100, on which a plurality of cell contacts 130a to 130j (represented herein as (a plurality of) cell contacts 130) are disposed. Each cell contact 130 is electrically connected to a node of a cell circuit system constructed beneath the accessible surface 105. For example, the unit cell 100 may include a double stack of complementary field-effect transistor (CFET) circuitry, i.e., two pairs of common-gate n-type and p-type transistor pairs in what is referred to herein as an active device stack, wherein one pair of transistors is stacked on top of another pair. Figure 2 illustrates an example of such an active device stack. Figure 1 In an example embodiment, such a device stack can be limited to a cell with a height of 4 tracks (4T) (as shown in tracks 140a to 140d (represented herein as track 140)) and a width of 2 cpp, as... Figure 1As shown. In this dual-stack configuration, four (4) active channels can be established in the respective active regions 150, and these active channels are controlled by voltages applied to cell contacts 130 and interconnections established across these cell contacts, in which, for example, cell contacts 130a and 130c can be connected to the bottom p-diffusion layer, cell contacts 130d and 130e can be connected to the top p-diffusion layer, cell contacts 130f and 130g can be connected to the top n-diffusion layer, cell contacts 130h and 130j can be connected to the bottom n-diffusion layer, and cell contacts 130b and 130i can be connected to the common polysilicon gate of the upper CFET pair and the lower CFET pair, respectively. These contacts can also be viewed as follows: unit contacts 130a and 130c can serve as the source and drain contacts of the p-type transistor in the lower CFET pair, unit contacts 130d and 130e can serve as the source and drain contacts of the p-type transistor in the upper CFET pair, unit contacts 130f and 130g can serve as the source and drain contacts of the n-type transistor in the upper CFET pair, 130h and 130j can serve as the source and drain contacts of the n-type transistor in the lower CFET pair, and unit contacts 130b and 130i can serve as the common gate contacts of the upper and lower CFET pairs. This contact assignment is not essential for practicing the inventive concept described herein; other contact assignments are possible and may depend on the internal structure of the unit cell.

[0037] In addition to the cell contact 130, the accessible surface 105 further exposes the upper surfaces of the VDD power wall 110 and the VSS power wall 120. In some embodiments, the VDD power wall 110 and the VSS power wall 120 are configured as walls extending upward from the substrate surface to the accessible surface 105. Accordingly, local interconnects within the unit cell 100 and wiring at the accessible surface 105 are accessible to the VDD power wall 110 and the VSS power wall 120. Therefore, such local interconnects can be directly connected to the VDD power wall 110 and / or the VSS power wall 120 (e.g., for transistor biasing), rather than making such connections at the accessible surface 105. In some embodiments, the VDD power wall 110 and the VSS power wall 120 may each be located in a single diffusion interruption space, and as... Figure 1 As shown, each can cross the cell boundary so that it can be used by adjacent cells.

[0038] Figure 1The diagram also illustrates four (4) active regions 150 in an exemplary unit cell 100. However, it should be understood that each of the four active regions may include multiple channels in which current flows from the source to the drain (or vice versa). For example, in a gate-all-around (GAA) configuration, each active region 150 may include multiple current-carrying components (e.g., nanowires or nanosheets). Other active regions may also be implemented in embodiments of the invention, typically depending on the technology node used to design and manufacture the unit cell.

[0039] Figure 2 (including) Figures 2A to 2E (This is a diagram showing the internal 3D structure of unit cell 100 through several cross-sectional views.) Figures 2A to 2D Different views are depicted, and these views reference [the following]. Figure 2E , Figure 2E Showing Figure 1 Depicted and referenced in Figure 1 The described accessible surface 105 and unit contact 130. It should be understood that this includes... Figures 2A to 2E Figure 2, which is included, is a schematic illustration and is not drawn to scale.

[0040] Figure 2A The diagram shows a cross-sectional view through the bottom local interconnect 215, local interconnect 235, and top gate polysilicon interconnect 230. The bottom local interconnect connects cell contacts 130a to the source / drain of the bottommost transistor 210a in the active device stack 250. Local interconnect 235 connects cell contacts 130c to the drain / source of the bottommost transistor 210a in the active device stack 250. The top gate polysilicon interconnect connects cell contacts 130b to the common gate of the uppermost CFET pair including transistors 210c and 210d. It should be noted that in some embodiments, the VDD power wall 110 and VSS power wall 120 may be connected to buried power rails (represented by buried power rails 112 and 122, respectively), and the upper surfaces of these two power walls are exposed on the accessible surface 105.

[0041] Figure 2B The diagram shows a cross-sectional view passing through local interconnects 215, 220, 225, and cell contact 130d. Local interconnect 220 connects cell contact 130f to the drain / source of transistor 210c in active device stack 250; local interconnect 225 connects cell contact 130h to the source / drain of transistor 210c in active device stack 250; and cell contact 130d can be directly connected to the source / drain of the uppermost transistor 210d in active device stack 250. Additionally, Figure 2B This shows a cross-sectional view through a portion of the active device stack 250.

[0042] Figure 2C This diagram shows a cross-sectional view of the common gate in the active device stack 250. Each of the upper and lower CFET pairs is connected to the corresponding cell contacts 130b and 130i via polysilicon interconnects 230 and 240.

[0043] Figure 2D The diagram shows a cross-sectional view through local interconnect 225, interconnect 245, and bottom gate polysilicon interconnect 240. Local interconnect 225 connects cell contact 130a to the source / drain of the bottommost transistor 210a in the active device stack 250, interconnect 245 connects cell contact 130j to the drain / source of the topmost transistor 210d in the active device stack 250, and bottom gate polysilicon interconnect 240 connects cell contact 130i to the common gate of the bottommost CFET pair including transistors 210a and 210b.

[0044] According to embodiments of the inventive concept disclosed herein, signal and power connections can be routed on a plane above the active device stack 250 (e.g., on accessible surface 105) to be functionalized as locally conductive wiring on what is referred to herein as a functionalization layer. Local power rails can extend within the space of a single diffused interruption. Therefore, each unit cell can have a uniform size and can optionally have a uniform geometry (including transistors, gates, and local interconnects).

[0045] Figure 3A This is a diagram of a 10×10 unit array 300, used to highlight the regularity of the front-end operation (FEOL) and intermediate-end operation (MEOL) layouts. For identification purposes, in Figure 3A Each cell in array 300 is associated with a column identifier and a row identifier; for example, unit cell 3F refers to the unit cell in column 3 and row F of array 300. It should be observed that array 300 is highly regular in terms of FEOL and MEOL layout, thus allowing for the use of various manufacturing processes to simplify overall manufacturing and reduce costs. In some embodiments, array 300 may be a monolithic integrated circuit, where all unit cells are built on a single substrate (not shown).

[0046] Figure 3B This is an illustration of a unit cell array 300, which depicts only the active channel region (represented by active channel region 310) and the source / drain contacts (represented by source / drain contacts 320). Figure 3B The potential use of low-cost frequency doubling patterning techniques (e.g., directional self-assembly or self-aligned multiple patterning, such as self-aligned dual / triple / quadruple patterning) for imaging these key features is highlighted.

[0047] Figure 3C This is an illustration of a unit cell array 300, depicting a cut mask grid (represented by cut masks 330a and 330b), which can optionally provide a low-cost, high-precision solution for forming the line ends of local interconnects and polysilicon gates.

[0048] Figure 3D This is an illustration of a unit cell array 300, depicting the VDD power rail (represented by VDD power rail 340) and the VSS power rail (represented by VSS power rail 350). It should be understood that these power rails are positioned within the space remaining after the diffusion interruption. Furthermore, in Figure 3D The image shows the macroscopic power rails that supply power to the local power rails (represented by the macroscopic power rail 360).

[0049] Figure 4 This is a top view of unit cell 400, which has been functionalized via back-to-end process (BEOL). Unit cell 400 may have the same internal architecture as unit cell 100 described above. Unit contacts (representatively shown as unit contact 403) may be distributed on accessible surface 401 to connect to the same internal circuitry nodes as similarly positioned unit contacts 130 of unit cell 100. In the example shown, a first metal 415 and a second metal 420 are disposed above accessible surface 401 to connect target-specific unit contacts 403 and form specific logic cells. Figure 4In this case, the specific logic unit is a two-inverted negation (INV2) logic unit. In this example embodiment, three layers of highly regularized unidirectional metal connections are used. First, VDD power taps 430a and 430b and VSS power taps 460a and 460b can connect specific source / drain contacts to local power rails, namely, VDD power rail 425 and VSS power rail 455. On a different local wiring layer, vertically aligned source / drain contacts and / or gate contacts can be connected together by a first metal (represented by first metal connection 415). In yet another local wiring layer, the input / output pins of the logic unit (e.g., top gate contact 405 electrically connected to bottom gate contact 445 as a logic unit input pin, unit contact 440 as an n-type output pin, and unit contact 450 as a p-type output pin) can be constructed via a second metal (represented by second metal connection 420), to which circuit routers can connect other circuit components. In some embodiments, a signal conduction element (represented by 410) may be configured to connect an input pin of a second metal horizontally disposed on an accessible surface 401 to local wiring of a first metal vertically disposed on the accessible surface 401.

[0050] Figure 5 This is a top view illustration of a pair of unit cells 505a and 505b, functionalized as dual-input AND-OR-NOT (AOI22) logic units 500, each unit cell being configured to AND with Figure 1 Same as unit cell 100 in Figure 2. (And...) Figure 4 Similarly, the first metal connection (represented by first metal connection 515) is vertically oriented, the second metal connection (represented by second metal connection 520) is horizontally oriented, and the power tap (represented by power tap 525) is placed as needed. Figure 5 The illustrated embodiment demonstrates the efficient use of the first metal connection 510, namely connecting the output of a p-type "A" transistor to the input of a p-type "B" transistor in a vertical cell adjacency configuration to form an AOI22 logic cell 500.

[0051] Figure 6 This is a top view illustration of a pair of unit cells 605a and 605b, functionalized as a dual-input AND (AND2) logic unit 600. The AND2 logic unit is essentially a dual-input NAND gate (NAND2 in unit cell 605a) connected to a dual-output NOT gate (INV2 in unit cell 605b). Each unit cell can be configured to AND with... Figure 1 The unit 100 is the same as that of 2. Figure 4Similarly, the first metal connection (represented by first metal connection 615) is vertically oriented, the second metal connection (represented by second metal connection 620) is horizontally oriented, and the power tap (represented by power tap 625) is placed as needed. Figure 6 The illustrated embodiment demonstrates the efficient use of the second metal connection 610, namely connecting the output of the NAND2 circuit to the gate of the INV2 circuit in a horizontal cell adjacency configuration to form the AND2 logic cell 600.

[0052] Figure 7 This is a top view illustration of a pair of unit cells 705a and 705b, where each unit cell has a single CFET pair in its respective active device stack rather than... Figure 1 It has two CFET pairs as in embodiment 2. Figure 7 This demonstrates how the design methodology described in this paper can be applied to other 3Di methods. Figure 7 In the illustrated embodiment, a dual-input NAND2 logic unit 700 is constructed using a functionalization technique similar to the functionalization technique described above.

[0053] Table 1 shows a comparison between the sample area reduction achieved using the techniques presented in this paper and the relatively aggressive 5T2D design. It should be noted that the reduction factor demonstrates the significant reduction advantages provided by the techniques presented in this paper.

[0054] unit 2D size 3D size Minimum AOI22 5cpp × 5T = 25 2cpp×4T×2=16 16 / 25＝0.64 NAND2 3cpp × 5T = 15 2cpp × 4T = 8 8 / 15＝0.53 AND 5cpp × 5T = 25 4cpp × 4T = 16 16 / 25＝0.64 INV2 3cpp × 5T = 15 2cpp × 4T = 8 8 / 15＝0.53

[0055] Table 1

[0056] Embodiments of the inventive concepts described herein may include integrated circuits or semiconductor devices having an array of uniform unit cells. The unit cell, with a fixed footprint (width and height), contains all front-end operations (FEOL, e.g., device, source / drain, gate) and intermediate operations (MEOL, e.g., local interconnects) structures. A uniform and fixed-pitch array of contacts can be provided to route all signal and power connections to an accessible plane above the device stack. A set of local power rails extending parallel to the polysilicon gate connections can utilize the space for diffusion interruptions. Logic synthesis can be achieved by horizontally adjaculating unit cells (i.e., forming wide standard logic cells) or vertically adjaculating unit cells (i.e., forming tall standard logic cells). A set of regular and unidirectional metallic shapes can be used to functionalize unit cells as standard cell logic or to achieve bulk synthesis (e.g., mapping large logic blocks into local wiring of the cell array).

[0057] In the foregoing description, specific details, such as particular geometries and descriptions of various components and the processes used to construct such components, have been set forth. However, it should be understood that the techniques described herein may be practiced in other embodiments departing from these specific details, and such details are for illustrative purposes rather than limiting. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, specific figures, materials, and configurations have been set forth for illustrative purposes to provide a thorough understanding. However, embodiments may be practiced without such specific details. Components having substantially the same functional construction are indicated by similar reference numerals, and therefore any redundant description may be omitted.

[0058] Various techniques have been described as multiple discrete operations to aid in understanding the various embodiments. The order of description should not be construed as meaning that these operations are necessarily order-dependent. In fact, these operations do not need to be performed in the order presented. The described operations may be performed in a different order than the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0059] Of course, for clarity, the order of discussion of the different steps described herein has been presented. Generally, these steps can be performed in any suitable order. Furthermore, although each different feature, technique, configuration, etc., may be discussed in different places within this disclosure, it is intended that each concept can be implemented independently of or in combination with each other. Therefore, the invention can be practiced and viewed in many different ways.

[0060] As used herein, "substrate" or "target substrate" generally refers to the object being processed according to the present invention. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device) and may be, for example, a base substrate structure (such as a semiconductor wafer, a photomask) or a layer (such as a thin film) on or overlaid on a base substrate structure. Therefore, a substrate is not limited to any particular base structure, underlayer, or overlayer, whether patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. This description may refer to specific types of substrates, but this is for illustrative purposes only.

[0061] The foregoing description is intended to illustrate possible embodiments of the inventive concept and is not intended to be limiting. Many variations, modifications, and alternatives will become apparent to those skilled in the art upon review of this disclosure. For example, the shown and described components may be replaced with equivalent components, the described elements and methods may be combined individually, and the described discrete elements may be distributed across many components. Therefore, the scope of the invention should not be determined by reference to the foregoing description but rather by reference to the appended claims and their equivalents.

Claims

1. An integrated circuit, comprising: Unit cells, which are arranged in an array, each unit cell comprising: Field-effect transistors, which are arranged in a stack; Local interconnect structures, including selected conductive paths between the select terminals of these field-effect transistors, to define a cell circuit system confined within the unit cell; and A contact array is disposed on the accessible surface of the unit cell, each contact being electrically coupled to a corresponding electrical node of the unit cell's circuitry, wherein: These unit cells share a common occupancy space and are positioned in the array such that the diffusion interruption of the unit circuitry surrounding each unit cell is aligned with the diffusion interruption in the adjacent unit cell, thereby forming a continuous space extending across all unit cells in the corresponding columns of the array; and The integrated circuit further includes power walls disposed in these continuous spaces, extending vertically from the substrate to the accessible surface of the unit cells, the power walls providing power to at least the unit cells in the respective columns of the array.

2. The integrated circuit according to claim 1, further comprising: Power rails, which are arranged in a continuous space, provide power to at least the unit cells in the corresponding columns of the array.

3. The integrated circuit according to claim 1, further comprising: Embedded power rails, positioned below the unit cells and aligned with the continuous space of the diffusion interruption, provide power to at least the unit cells in the corresponding columns of the array.

4. The integrated circuit of any one of claims 1, 2 and 3, further comprising a functionalized layer including conductive wiring segments formed between selected contacts on respective accessible surfaces of one or more unit cells in the array.

5. The integrated circuit as claimed in claim 1, wherein, The upper surfaces of these power walls are exposed on the accessible surfaces of each unit cell in the corresponding column of the array.

6. The integrated circuit as claimed in claim 1, wherein, The lower surfaces of these corresponding power walls are connected to embedded power rails.

7. The integrated circuit according to any one of claims 1, 2, and 3, wherein, The unit circuit system of all units in this array is identical.

8. The integrated circuit as claimed in claim 7, wherein, The unit circuit system is constructed from front-end process structures and intermediate process structures that extend from these unit units.

9. The integrated circuit as claimed in claim 8, wherein, These front-end and intermediate processes include multiplication patterning.

10. The integrated circuit as claimed in claim 9, wherein, These multiplication patterning processes include directional self-assembly and / or self-alignment dual patterning techniques.

11. The integrated circuit according to any one of claims 1, 2, and 3, wherein, These field-effect transistors are stacked in complementary pairs.

12. The integrated circuit of claim 11, wherein, The gates of each of these complementary field-effect transistor pairs are electrically connected to each other.

13. The integrated circuit of claim 12, wherein, The number of complementary pairs in this field-effect transistor stack is greater than one.

14. The integrated circuit according to any one of claims 1, 2, and 3, wherein, These field-effect transistors are stacked in a plane parallel to the accessible surface.

15. The integrated circuit according to any one of claims 1, 2, and 3, wherein, This integrated circuit is a monolithic integrated circuit.

16. The integrated circuit of any one of claims 1, 2 and 3, further comprising a set of unidirectional metal shapes for forming the unit cell into standard cell logic.

17. The integrated circuit of any one of claims 1, 2 and 3, further comprising a set of unidirectional metal shapes that map logic blocks to local wiring in a unit cell array.

18. The integrated circuit of any one of claims 1, 2 and 3, further comprising two or more layers of unidirectional metal interconnects forming a unit cell array.

19. The integrated circuit according to any one of claims 1, 2, and 3, wherein, The contact array has a fixed spacing.

20. An integrated circuit, comprising: Electrical contacts, which are disposed on a surface, beneath which identical unit cells are constructed, each unit cell comprising: Transistors, these transistors are arranged in a stack; and Local interconnect structures, which include selected conductive paths between the select terminals of these transistors, define a cell circuit system confined within the unit cell. The selection node of this unit circuit system is connected to an electrical contact located above the transistor stack of each unit cell; and Power walls, which are disposed in a continuous space between groups of these unit cells, extend vertically from the substrate to the surface of these unit cells, and provide power to at least the unit cells in the corresponding group.

21. The integrated circuit of claim 20, further comprising a functionalized layer including conductive wiring segments formed between selected electrical contacts among the electrical contacts.

22. The integrated circuit of claim 20, wherein, Selected local interconnect structures in these local interconnect structures are connected to at least one of these power walls.

23. The integrated circuit of claim 20, wherein, These transistors are stacked in a plane parallel to the surface on which these electrical contacts are located.

24. The integrated circuit of claim 20, further comprising: Power rails are arranged in a continuous space between groups of these unit cells, and these power rails provide power to at least the unit cells in the corresponding groups.

25. The integrated circuit of claim 20, further comprising: Embedded power rails, which are positioned below the unit cells and aligned with the continuous space between groups of these unit cells, provide power to at least the unit cells in the corresponding group.

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