MoS2 back gate field effect transistor based on wet transfer process and preparation method thereof

Abstract

The invention relates to the technical field of kits, in particular to a MoS2 back gate field effect transistor based on a wet transfer process and a preparation method of the MoS2 back gate field effect transistor. The MoS2 back gate field effect transistor is formed by sequentially arranging a silicon-based substrate, a SiO2 insulating layer, a MoS2 conducting channel layer and an Ag source drain electrode from bottom to top; a high-quality single-layer MoS2 thin film is prepared through a chemical vapor deposition (CVD) method, PMMA is adopted as a supporting layer, clean Van der Waals contact of the MoS2 thin film and a SiO2 / Si substrate is achieved through a wet transfer process of NaOH solution etching, deionized water cleaning and acetone stripping of the supporting layer, and finally a source electrode and a drain electrode are prepared by combining photoetching and thermal evaporation processes. According to the method, the problems of pollutant residues and traps of an interface between MoS2 and the substrate in the traditional process are effectively solved, the carrier mobility, transconductance and on-state current of the device are remarkably improved, the sub-threshold swing is reduced, and the method is suitable for manufacturing a two-dimensional material integrated circuit device with low power consumption and high performance.

Description

Technical Field

[0001] This invention relates to the field of field-effect transistor technology, specifically to a MoS2 back-gate field-effect transistor based on a wet transfer process and its fabrication method. Background Technology

[0002] As the feature size of integrated circuits continues to approach physical limits, traditional silicon-based semiconductor technology faces severe challenges such as short-channel effects and soaring power consumption. Finding new atomically thin channel materials has become crucial for continuing Moore's Law. Molybdenum disulfide (MoS2) among transition metal dichalcogenides (TMDs) possesses an atomically ultrathin structure, a suitable bandgap, and excellent mechanical flexibility. Compared to graphene, it is more suitable for constructing low-power, high-on-response field-effect transistors, making it an ideal channel material for next-generation semiconductor devices.

[0003] However, in conventional fabrication processes, when MoS2 films are in direct contact with SiO2 substrates, contaminants such as polymers and adsorbates easily remain at the interface, and inherent interface traps exist. These problems severely scatter charge carriers, causing key device performance such as carrier mobility and subthreshold swing to fall far short of theoretical values. Existing improvement schemes mostly focus on electrode work function matching or upper surface passivation layer modification, failing to fundamentally solve the interface quality problem between the channel and the substrate, thus limiting the performance improvement and practical application of MoS2 devices.

[0004] The wet transfer process, through solution cleaning and interface reconstruction, can effectively remove contaminants and form clean van der Waals contacts, providing a new approach to optimizing the interface properties between MoS2 and the substrate. However, how to efficiently integrate this process with CVD fabrication, device packaging, and other processes to achieve stable and repeatable device fabrication still requires the establishment of a standardized process system. Summary of the Invention

[0005] The purpose of this invention is to provide a MoS2 back-gate field-effect transistor based on a wet transfer process and its fabrication method, aiming to solve the problems of interface contamination and traps in traditional processes. High-quality monolayer MoS2 thin films are prepared by CVD and clean contact with the substrate is achieved by combining a wet transfer process.

[0006] To achieve the above objectives, the present invention provides a MoS2 back-gate field-effect transistor based on a wet transfer process, which is composed of a silicon substrate, a SiO2 insulating layer, a MoS2 conductive channel layer, and Ag source / drain electrodes arranged sequentially from bottom to top.

[0007] The thickness of the SiO2 insulating layer is 300 nm.

[0008] The MoS2 conductive channel layer is a single-layer structure with a thickness corresponding to the atomic scale, and its Raman spectrum shows E0... 12The shift difference between the characteristic peaks of g and A1g is 18-20 cm. - ¹.

[0009] The Ag source and drain electrodes are 100 nm thick, and the channel length and width are set according to application requirements. The channel dimensions of the devices in the same batch are kept consistent.

[0010] This invention also provides a method for fabricating a MoS2 back-gate field-effect transistor based on a wet transfer process, which includes the following steps:

[0011] Step 1: Substrate pretreatment. The SiO2 / Si substrate is cleaned sequentially in an ultrasonic bath for 15 minutes each with acetone, anhydrous ethanol, and deionized water to remove surface impurities.

[0012] Step 2: A monolayer MoS2 thin film was prepared by CVD using a dual-temperature zone tube furnace. 20.0 mg of sulfur powder was placed in the 200°C zone, and a mixture of 2.0 mg MoO3 and 0.4 mg NaCl powder was placed in the 800°C zone. High-purity argon gas was introduced at 100 sccm, maintaining a pressure of 4 × 10⁻⁶ ppm. - ³Torr, react for 15 min, then allow to cool naturally to room temperature;

[0013] Step 3: PMMA support layer preparation. PMMA is spin-coated onto the surface of the MoS2 film obtained in Step 2. The initial rotation speed is 600 r / min for 6 s, and the subsequent rotation speed is 4000 r / min for 60 s. Then, it is heated on a hot plate at 100℃ for 10 min to cure.

[0014] Step 4: Wet transfer separation. The sacrificial substrate with the PMMA / MoS2 composite layer is placed in a 2 mol / L NaOH solution and the SiO2 sacrificial layer is etched at 100°C to remove the PMMA / MoS2 composite layer.

[0015] Step 5: Cleaning and bonding. The separated PMMA / MoS2 composite layer is cleaned at least twice in deionized water at 50°C to remove ionic impurities, and then transferred to the pretreated target SiO2 / Si substrate to achieve clean bonding.

[0016] Step 6: Peel off the support layer. Place the bonded sample on a hot plate to remove excess moisture, and then dissolve the PMMA support layer with acetone to obtain a MoS2 film that forms a van der Waals contact with the target substrate.

[0017] Step 7: Source and drain electrode fabrication. Photoresist is spin-coated onto the surface of the MoS2 thin film at a spin speed of 600 r / min for 6 s, followed by a spin speed of 4000 r / min for 60 s. The film is then baked at 85°C for 90 s to solidify. After photolithography positioning, a 100 nm thick Ag layer is deposited using a thermal evaporation vacuum deposition machine. Finally, the photoresist is removed with acetone to complete the electrode patterning.

[0018] Optionally, in step 2, NaCl is used as a catalyst to react with MoO3 to generate an intermediate product, which is then reacted with sulfur powder to generate MoS2.

[0019] Optionally, the reaction between NaOH solution and SiO2 in step 4 is used to break the bond between the sacrificial substrate and the MoS2 film, thereby achieving composite layer separation.

[0020] Optionally, in step 6, the heating temperature of the hot plate is limited to remove moisture without damaging the MoS2 film, and the bonding process ensures that the MoS2 film is wrinkle-free and undamaged.

[0021] Optionally, in step 7, the photolithography positioning selects a triangular or approximately triangular MoS2 crystal region with distinct boundaries and regular shape under an optical microscope.

[0022] This invention provides a MoS2 back-gate field-effect transistor based on a wet transfer process and its fabrication method. The transistor is composed of a silicon substrate, a SiO2 insulating layer, a MoS2 conductive channel layer, and Ag source / drain electrodes arranged sequentially from bottom to top. A high-quality monolayer MoS2 thin film is prepared by chemical vapor deposition (CVD) using PMMA as a support layer. A wet transfer process is performed, including etching with NaOH solution, cleaning with deionized water, and peeling off the support layer with acetone, to achieve clean van der Waals contact between the MoS2 thin film and the SiO2 / Si substrate. Finally, the source / drain electrodes are fabricated using photolithography and thermal evaporation processes.

[0023] Specifically, the SiO2 insulating layer thickness was set to 300 nm to ensure insulation performance and MoS2 morphology identification under optical interference effects; the MoS2 conductive channel layer was characterized by Raman spectroscopy to ensure it was a single-layer structure; the Ag source / drain electrodes were 100 nm thick to balance conductivity and process compatibility. During the fabrication process, CVD process parameters were precisely controlled to ensure MoS2 crystal quality, and the cleaning, separation, and bonding steps of the wet transfer were strictly controlled in terms of temperature and time to avoid damage to the MoS2 film. Finally, the electrodes were fabricated using photolithography and thermal evaporation processes.

[0024] This invention effectively solves the problems of contaminant residue and traps at the interface between MoS2 and the substrate in traditional processes, significantly improves the carrier mobility, transconductance and on-state current of the device, and reduces the subthreshold swing, making it suitable for manufacturing low-power, high-performance two-dimensional material integrated circuit devices. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of a MoS2 back-gate field-effect transistor based on a wet transfer process according to the present invention.

[0027] Figure 2 This is a flow chart of the wet transfer process of the present invention.

[0028] Figure 3 These are optical microscope images of MoS2 thin films according to a specific embodiment of the present invention.

[0029] Figure 4 This is a Raman spectrum of a single-layer MoS2 according to a specific embodiment of the present invention.

[0030] Figure 5 This is an optical image of the device after the source and drain electrodes are patterned according to a specific embodiment of the present invention.

[0031] Figure 6 This is a comparison chart of device transfer characteristic curves in a specific embodiment of the present invention.

[0032] Figure 7 This is a comparison chart of the device output characteristic curves of a specific embodiment of the present invention. Detailed Implementation

[0033] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0034] Please see Figure 1 The present invention provides a MoS2 back-gate field-effect transistor based on a wet transfer process, which is composed of a silicon substrate, a SiO2 insulating layer, a MoS2 conductive channel layer and Ag source and drain electrodes arranged from bottom to top.

[0035] The thickness of the SiO2 insulating layer is 300 nm.

[0036] The MoS2 conductive channel layer is a monolayer structure with a thickness corresponding to the atomic scale, and its Raman spectrum contains E 12 The shift difference between the characteristic peaks of g and A1g is 18-20 cm. - ¹.

[0037] The Ag source and drain electrodes are 100 nm thick. The device channel length and width are set according to application requirements, and the channel dimensions of the same batch of comparative devices are kept consistent.

[0038] This invention also provides a method for fabricating a MoS2 back-gate field-effect transistor based on a wet transfer process, which includes the following steps:

[0039] Step 1: Substrate pretreatment. The SiO2 / Si substrate is cleaned sequentially in an ultrasonic bath for 15 minutes each with acetone, anhydrous ethanol, and deionized water to remove surface impurities.

[0040] Step 2: A monolayer MoS2 thin film was prepared by CVD using a dual-temperature zone tube furnace. 20.0 mg of sulfur powder was placed in the 200°C zone, and a mixture of 2.0 mg MoO3 and 0.4 mg NaCl powder was placed in the 800°C zone. High-purity argon gas was introduced at 100 sccm, maintaining a pressure of 4 × 10⁻⁶ ppm. - ³Torr, react for 15 min, then allow to cool naturally to room temperature;

[0041] Step 3: PMMA support layer preparation. PMMA is spin-coated onto the surface of the MoS2 film obtained in Step 2. The initial rotation speed is 600 r / min for 6 s, and the subsequent rotation speed is 4000 r / min for 60 s. Then, it is heated on a hot plate at 100℃ for 10 min to cure.

[0042] Step 4: Wet transfer separation. The sacrificial substrate with the PMMA / MoS2 composite layer is placed in a 2 mol / L NaOH solution and the SiO2 sacrificial layer is etched at 100°C to remove the PMMA / MoS2 composite layer.

[0043] Step 5: Cleaning and bonding. The separated PMMA / MoS2 composite layer is cleaned at least twice in deionized water at 50°C to remove ionic impurities, and then transferred to the pretreated target SiO2 / Si substrate to achieve clean bonding.

[0044] Step 6: Peel off the support layer. Place the bonded sample on a hot plate to remove excess moisture, and then dissolve the PMMA support layer with acetone to obtain a MoS2 film that forms a van der Waals contact with the target substrate.

[0045] Step 7: Source and drain electrode fabrication. Photoresist is spin-coated onto the surface of the MoS2 thin film at a spin speed of 600 r / min for 6 s, followed by a spin speed of 4000 r / min for 60 s. The film is then baked at 85°C for 90 s to solidify. After photolithography positioning, a 100 nm thick Ag layer is deposited using a thermal evaporation vacuum deposition machine. Finally, the photoresist is removed with acetone to complete the electrode patterning.

[0046] In step 2, NaCl acts as a catalyst, reacting with MoO3 to generate an intermediate product, which then reacts with sulfur powder to generate MoS2.

[0047] In step 4, the reaction between NaOH solution and SiO2 is used to break the bond between the sacrificial substrate and the MoS2 film, thereby achieving the separation of the composite layer.

[0048] In step 6, the heating temperature of the hot plate is limited to remove moisture without damaging the MoS2 film, and the bonding process ensures that the MoS2 film is wrinkle-free and undamaged.

[0049] In step 7, the photolithography positioning selects a triangular or approximately triangular MoS2 crystal region with distinct boundaries and regular shape under an optical microscope.

[0050] All device fabrication processes are carried out in a clean environment to avoid contaminants affecting interface quality.

[0051] Please see Figures 2 to 7 The following detailed description, along with specific embodiments and the preparation process, will further illustrate the process:

[0052] In this embodiment, the structural parameters of each layer of the transistor are as follows: the silicon substrate is a conventional P-type silicon substrate, the SiO2 insulating layer is 300nm thick, the MoS2 conductive channel layer is a single layer, the Ag source and drain electrode is 100nm thick, the channel length and width are set according to the test requirements, and the size of the comparison device is kept consistent.

[0053] The specific implementation steps of the preparation method are as follows:

[0054] Step 1: Substrate pretreatment. Select two 300nm SiO2 / Si substrates and place them in an ultrasonic bath. Clean them sequentially with acetone, anhydrous ethanol, and deionized water for 15 minutes each to remove surface oil, dust, and other impurities. After cleaning, dry them with nitrogen gas for later use.

[0055] Step 2: CVD preparation of MoS2 thin films: In a dual-temperature zone tube furnace, 20.0 mg of sulfur powder was placed in one quartz boat and positioned in the low-temperature zone (200°C). A mixture of 2.0 mg MoO3 and 0.4 mg NaCl powder was placed in the other quartz boat and positioned in the high-temperature zone (800°C). A pre-treated substrate was placed above the high-temperature quartz boat. The furnace tube was closed and a vacuum was drawn. 100 sccm of high-purity argon gas was introduced, maintaining a pressure of 4 × 10⁻⁶. - ³Torr, after heating to the set temperature, react for 15 minutes. After the reaction is complete, turn off the heating and allow the furnace to cool naturally to room temperature to obtain a sacrificial substrate with a MoS2 thin film grown on it.

[0056] Step 3: Spin-coating the PMMA support layer. Place the MoS2 film area on the sacrificial substrate facing upwards on the spin coater and drop-coat the PMMA solution. Set the spin coating parameters as follows: initial rotation speed 600 r / min, hold for 6 s, subsequent rotation speed 4000 r / min, hold for 60 s. After spin coating, place the substrate on a 100℃ hot plate and heat for 10 min to allow the PMMA to solidify and form a support layer.

[0057] Step 4: Wet separation. Prepare a 2 mol / L NaOH solution, pour it into a container and heat it to 100°C. Slowly place the sacrificial substrate with the PMMA / MoS2 composite layer into the solution to allow the SiO2 layer to react with the NaOH solution. During the reaction, the substrate can be seen to gradually dissolve, and the PMMA / MoS2 composite layer detaches from the substrate and floats on the surface of the solution.

[0058] Step 5: Cleaning and bonding. Carefully remove the floating PMMA / MoS2 composite layer with tweezers and clean it in deionized water at 50°C. Repeat the cleaning twice to remove residual NaOH and ionic impurities. Then, tilt another pretreated target substrate into the deionized water, slowly lift the composite layer and bond it to the SiO2 surface of the target substrate, ensuring that the composite layer is free of wrinkles and bubbles.

[0059] Step 6: PMMA peeling. Place the bonded target substrate on a hot plate (temperature set to 50℃) and heat for 5 minutes to remove surface moisture. Then, immerse the substrate in acetone solution for 10 minutes to dissolve the PMMA support layer. After removal, rinse with deionized water and dry with nitrogen to obtain a clean MoS2 / SiO2 / Si structure.

[0060] Step 7: Source and drain electrode fabrication. Photoresist is spin-coated onto the MoS2 thin film surface with the following parameters: 600 r / min for 6 s at the beginning and 4000 r / min for 60 s at the end. The film is then baked at 85°C for 90 s to solidify. The high-quality MoS2 region is located using an optical microscope for photolithography exposure and development. Subsequently, the substrate is placed in a thermal evaporation vacuum deposition machine to deposit a 100 nm thick Ag layer. Finally, the substrate is immersed in an acetone solution to remove the photoresist and the Ag layer on top, completing the source and drain electrode patterning and obtaining the final MoS2 back gate field-effect transistor.

[0061] like Figure 2 The wet transfer process flow is shown in the following order: substrate cleaning → CVD growth of MoS2 → spin coating of PMMA → NaOH etching and separation → deionized water cleaning → bonding to target substrate → acetone stripping of PMMA.

[0062] Figure 3 This is an optical microscope image of a MoS2 thin film, showing a well-defined triangular monolayer crystal region.

[0063] Furthermore, the present invention has undergone performance testing and verification (see details). Figures 4 to 7 ):

[0064] The electrical performance of the device was tested in a cleanroom at room temperature using a 2636b source probe station. The transfer characteristic curve (Vgs range -30V to 70V, Vds step size 1V) and output characteristic curve (Vds range 0V to 5V, Vgs step size 10V) were tested and compared with the device fabricated directly on the substrate without wet transfer.

[0065] Figure 4 This is the Raman spectrum of a single-layer MoS2, labeled E. 12 The shift difference between the characteristic peaks of g and A1g is 18.2 cm. - ¹;

[0066] Figure 5 The image shows the optical image of the device after the source and drain electrodes are patterned, illustrating the positional relationship between the Ag electrode and the MoS2 channel;

[0067] Figure 6 The graph shows a comparison of device transfer characteristic curves. Solid lines represent wet-transfer devices, and dotted lines represent untransfer devices. The vertical axis represents drain current (logarithmic scale), and the horizontal axis represents gate-source voltage.

[0068] Figure 7 This is a comparison chart of the output characteristic curves of the devices. The solid line represents the wet transfer device, and the dotted line represents the untransferred device. The vertical axis represents the drain current, and the horizontal axis represents the drain-source voltage.

[0069] The test results show that:

[0070] The on / off ratio of the wet transfer device is maintained at 10. 4 The order of magnitude is consistent with that of the untransferred device;

[0071] The subthreshold swing decreased from 4650mV / dec to 3220mV / dec, a reduction of about 1 / 3;

[0072] Electron mobility from 7.2 cm² / V s increased to 26.1cm² / V s, increased by 3.6 times;

[0073] The maximum on-state current is 4.2 × 10⁻⁶. -6 A increased to 1.2 × 10 -5 A, increase by 2 times;

[0074] The transconductance increased from 0.14 μS to 0.28 μS, a twofold increase;

[0075] The threshold voltage was changed from -15V to -12V, resulting in improved performance stability.

[0076] Raman spectroscopy confirmed that the transferred MoS2 film remained a monolayer, E 12 The shift difference between the characteristic peaks of g and A1g is 18.2 cm. - ¹, conforming to the single-layer structure standard; optical microscopy and electrical tests show that the wet transfer process effectively removes interface contaminants, forming a clean van der Waals contact, reducing the impact of Coulomb scattering and interface traps on charge carriers, thereby significantly optimizing device performance.

[0077] In summary, the beneficial effects of this invention are:

[0078] 1. The transistor of the present invention uses a wet transfer process to prepare the MoS2 conductive channel layer, which fundamentally solves the problems of interface contaminant residue and traps in traditional processes, forms a clean van der Waals contact, significantly improves carrier mobility, transconductance and on-state current, reduces subthreshold swing, and results in lower device power consumption and faster response speed.

[0079] 2. MoS2 films are prepared by CVD method, and the growth process is optimized by combining NaCl catalyst, which can realize the controllable preparation of high-quality monolayer films. Moreover, the Raman spectroscopy characterization method is simple and efficient, which facilitates the batch screening of qualified samples.

[0080] 3. The preparation method has a clear process and standardized steps. The wet transfer process does not require complex equipment and high costs. It has strong compatibility and can be seamlessly integrated with existing photolithography and evaporation processes, making it suitable for industrial production.

[0081] 4. The device structure adopts a back-gate design, the SiO2 insulating layer thickness is standardized, the Ag source and drain electrode process is mature, the performance is stable and repeatable, providing a reliable technical solution for the practical application of two-dimensional material field-effect transistors.

[0082] The method provided by this invention can not only realize the fabrication of MoS2 back-gate field-effect transistors based on wet transfer process, but also has good reproducibility.

[0083] The above description discloses only one or more preferred embodiments of the present invention, and should not be construed as limiting the scope of the present invention. Those skilled in the art will understand that all or part of the processes of the above embodiments can be implemented, and equivalent changes made in accordance with the claims of the present invention are still within the scope of the invention.

Claims

1. A MoS2 back-gate field-effect transistor based on a wet transfer process, characterized in that, It is composed of a silicon substrate, a SiO2 insulating layer, a MoS2 conductive channel layer, and Ag source / drain electrodes arranged sequentially from bottom to top.

2. The MoS2 back-gate field-effect transistor based on wet transfer process as described in claim 1, characterized in that, The thickness of the SiO2 insulating layer is 300 nm.

3. The MoS2 back-gate field-effect transistor based on wet transfer process as described in claim 2, characterized in that, The MoS2 conductive channel layer is a monolayer structure with a thickness corresponding to the atomic scale, and its Raman spectrum contains E 12 The shift difference between the characteristic peaks of g and A1g is 18-20 cm. - ¹.

4. The MoS2 back-gate field-effect transistor based on wet transfer process as described in claim 3, characterized in that, The Ag source and drain electrodes are 100 nm thick. The device channel length and width are set according to application requirements, and the channel dimensions of the same batch of comparative devices are kept consistent.

5. A method for fabricating a MoS2 back-gate field-effect transistor based on a wet transfer process, used to fabricate a MoS2 back-gate field-effect transistor based on a wet transfer process as described in any one of claims 1 to 4, characterized in that, Includes the following steps: Step 1: Substrate pretreatment. The SiO2 / Si substrate is cleaned sequentially in an ultrasonic bath for 15 minutes each with acetone, anhydrous ethanol, and deionized water to remove surface impurities. Step 2: A monolayer MoS2 thin film was prepared by CVD using a dual-temperature zone tube furnace. 20.0 mg of sulfur powder was placed in the 200°C zone, and a mixture of 2.0 mg MoO3 and 0.4 mg NaCl powder was placed in the 800°C zone. High-purity argon gas was introduced at 100 sccm, maintaining a pressure of 4 × 10⁻⁶ ppm. - ³Torr, react for 15 min, then allow to cool naturally to room temperature; Step 3: PMMA support layer preparation. PMMA is spin-coated onto the surface of the MoS2 film obtained in Step 2. The initial rotation speed is 600 r / min for 6 s, and the subsequent rotation speed is 4000 r / min for 60 s. Then, it is heated on a hot plate at 100℃ for 10 min to cure. Step 4: Wet transfer separation. The sacrificial substrate with the PMMA / MoS2 composite layer is placed in a 2 mol / L NaOH solution and the SiO2 sacrificial layer is etched at 100°C to remove the PMMA / MoS2 composite layer. Step 5: Cleaning and bonding. The separated PMMA / MoS2 composite layer is cleaned at least twice in deionized water at 50°C to remove ionic impurities, and then transferred to the pretreated target SiO2 / Si substrate to achieve clean bonding. Step 6: Peel off the support layer. Place the bonded sample on a hot plate to remove excess moisture, and then dissolve the PMMA support layer with acetone to obtain a MoS2 film that forms a van der Waals contact with the target substrate. Step 7: Source and drain electrode fabrication. Photoresist is spin-coated onto the surface of the MoS2 thin film at a spin speed of 600 r / min for 6 s, followed by a spin speed of 4000 r / min for 60 s. The film is then baked at 85°C for 90 s to solidify. After photolithography positioning, a 100 nm thick Ag layer is deposited using a thermal evaporation vacuum deposition machine. Finally, the photoresist is removed with acetone to complete the electrode patterning.

6. The method for fabricating a MoS2 back-gate field-effect transistor based on a wet transfer process as described in claim 5, characterized in that, In step 2, NaCl acts as a catalyst, reacting with MoO3 to generate an intermediate product, which then reacts with sulfur powder to generate MoS2.

7. The method for fabricating a MoS2 back-gate field-effect transistor based on a wet transfer process as described in claim 5, characterized in that, In step 4, the reaction between NaOH solution and SiO2 is used to break the bond between the sacrificial substrate and the MoS2 film, thereby achieving the separation of the composite layer.

8. The method for fabricating a MoS2 back-gate field-effect transistor based on a wet transfer process as described in claim 5, characterized in that, In step 6, the heating temperature of the hot plate is limited to remove moisture without damaging the MoS2 film, and the bonding process ensures that the MoS2 film is wrinkle-free and undamaged.

9. The method for fabricating a MoS2 back-gate field-effect transistor based on a wet transfer process as described in claim 5, characterized in that, In step 7, the photolithography positioning selects a triangular or approximately triangular MoS2 crystal region with distinct boundaries and regular shape under an optical microscope.

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