Solid-state image pickup device and image pickup apparatus

Abstract

The present invention aims at improving the speed of AD conversion in a solid-state imaging device that performs time delay integration. The solid-state imaging device includes a pair of photoelectric conversion elements, a pair of floating diffusion layers, and a transfer unit that switches a transfer destination of each of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers and transfers charges to the transfer destination. In the solid-state imaging device including the pair of photoelectric conversion elements, the pair of floating diffusion layers, and the transfer unit, the transfer unit switches the transfer destination of each of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers and transfers charges to the transfer destination.

Description

TECHNICAL FIELD

[0001] The present technology relates to a solid-state imaging device. More specifically, the present technology relates to a solid-state imaging device that performs analog-digital conversion for each pixel and an imaging apparatus. BACKGROUND

[0002] Conventionally, a time delay integration (TDI) sensor has been used in the fields of factory automation (FA) and aerial photography. Such a TDI sensor is a sensor that performs TDI processing while changing the time in accordance with the moving speed of a subject and integrates the amount of charge. For example, Patent Literature proposes a solid-state imaging device in which two adjacent rows share a floating diffusion layer of one row (or row), and the charges of the two rows are transferred to the floating diffusion layer at different times (see, for example, Patent Literature ). The TDI processing is achieved by such charge transfer.

[0003] LIST OF CITATIONS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: JP 2014-510447 W SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In the above-described conventional technology, TDI processing is performed to increase the brightness and reduce noise. However, the above-described solid-state imaging device transfers the charges of two rows to a floating diffusion layer, performs analog-digital (AD) conversion, and requires initialization of the floating diffusion layer before starting the next charge transfer. Therefore, the speed of AD conversion is reduced due to the amount of time required for initialization of the floating diffusion layer.

[0008] The present technology is made in view of such a situation, and an object of the present technology is to improve the speed of AD conversion in a solid-state imaging device that performs time delay integration.

[0009] SOLUTION TO PROBLEM

[0010] The present technology is made in view of such a situation, and an object of the present technology is to improve the speed of AD conversion in a solid-state imaging device that performs time delay integration.

[0011] Further, in the first aspect, the transfer unit can simultaneously perform the process of transferring the electric charge from one of the pair of photoelectric conversion elements to the other of the pair of floating diffusion layers and the process of transferring the electric charge from the other of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers. With this configuration, the speed of AD conversion is improved compared to the case where these transfers are performed sequentially.

[0012] Further, in the first aspect, the transfer unit can include: a first transfer transistor that transfers the electric charge from one of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers; a second transfer transistor that transfers the electric charge from the one of the pair of photoelectric conversion elements to the other of the pair of floating diffusion layers; a third transfer transistor that transfers the electric charge from the other of the pair of photoelectric conversion elements to the one of the pair of floating diffusion layers; and a fourth transfer transistor that transfers the electric charge from the other of the pair of photoelectric conversion elements to the other of the pair of floating diffusion layers. With this configuration, the transfer destination of each of the pair of photoelectric conversion elements can be switched to one of the pair of floating diffusion layers.

[0013] Further, in the first aspect, a pair of charge drain transistors that drain the electric charge from each of the pair of photoelectric conversion elements can be further included. With this configuration, the photoelectric conversion elements are initialized.

[0014] Further, in the first aspect, a pair of reset transistors that initialize each of the pair of floating diffusion layers can be further included. With this configuration, the floating diffusion layers are initialized.

[0015] Further, in the first aspect, a pair of conversion efficiency control transistors that control the charge-voltage conversion efficiency of the pair of floating diffusion layers can be further included. With this configuration, the charge-voltage conversion efficiency can be changed.

[0016] Further, in the first aspect, a pair of amplification transistors that amplify the voltage of each of the pair of floating diffusion layers and generate a pair of pixel signals and a pair of selection transistors that select one of the pair of pixel signals can be further included. With this configuration, the selected pixel signal is output.

[0017] Further, in the first aspect, an analog-digital converter that sequentially converts each of the pair of pixel signals into a digital signal can be further included. With this configuration, a plurality of digital signals are generated.

[0018] Further, in the first aspect, an arithmetic circuit that integrates (or accumulates) the digital signal can be further included. With this configuration, digital TDI processing is performed.

[0019] Further, a second aspect of the present technology is an imaging device including a pair of photoelectric conversion elements, a pair of floating diffusion layers, a transfer unit that switches a transfer destination of each of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers and transfers a charge to the transfer destination, and a signal processing unit that converts a pixel signal corresponding to an amount of the charge into a digital signal and processes the digital signal. With this configuration, the digital signal is processed, and the speed of AD conversion is improved. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a block diagram illustrating an example configuration of an imaging device according to a first embodiment of the present technology.

[0021] Figure 2 is a diagram for explaining a use example of an imaging device according to the first embodiment of the present technology.

[0022] Figure 3 is a diagram illustrating an example layer stack of a solid-state imaging device apparatus according to the first embodiment of the present technology.

[0023] Figure 4 is a block diagram illustrating an example configuration of a light-receiving chip according to the first embodiment of the present technology.

[0024] Figure 5 is a block diagram illustrating an example configuration of a circuit chip according to the first embodiment of the present technology.

[0025] Figure 6 is a diagram illustrating an example configuration of a pixel AD conversion unit according to the first embodiment of the present technology.

[0026] Figure 7 is a block diagram illustrating an example configuration of an analog-to-digital converter (ADC) according to the first embodiment of the present technology.

[0027] Figure 8 is a circuit diagram illustrating an example configuration of an analog TDI circuit according to the first embodiment of the present technology.

[0028] Figure 9 is a circuit diagram illustrating an example configuration of a differential input circuit and a positive feedback circuit according to the first embodiment of the present technology.

[0029] Figure 10 is a block diagram illustrating an example configuration of a signal processing circuit according to the first embodiment of the present technology.

[0030] Figure 11 is a diagram illustrating an example layout of elements in an analog TDI circuit according to the first embodiment of the present technology.

[0031] Figure 12 is a diagram showing another example layout of elements in an analog TDI circuit according to the first embodiment of the present technology.

[0032] Figure 13 is a timing chart showing an example of transistor control according to the first embodiment of the present technology.

[0033] Figure 14 is a timing chart showing an example operation of a solid-state imaging device until the end of exposure of the second frame according to the first embodiment of the present technology.

[0034] Figure 15 is a timing chart showing an example operation of a solid-state imaging device until initialization of the floating diffusion layer of the fourth frame according to the first embodiment of the present technology.

[0035] Figure 16 is a timing chart showing an example operation of a solid-state imaging device until the end of exposure of the fifth frame according to the first embodiment of the present technology.

[0036] Figure 17 is a diagram showing an example of the state of an analog TDI circuit until the end of exposure of the first frame according to the first embodiment of the present technology.

[0037] Figure 18 is a diagram showing an example of the state of an analog TDI circuit until the end of exposure of the second frame according to the first embodiment of the present technology.

[0038] Figure 19 is a diagram showing an example of the state of an analog TDI circuit until the end of exposure of the third frame according to the first embodiment of the present technology.

[0039] Figure 20 is a diagram showing an example of the state of an analog TDI circuit until the end of exposure of the fourth frame according to the first embodiment of the present technology.

[0040] Figure 21 is a diagram showing an example of the state of an analog TDI circuit until the end of exposure of the fifth frame according to the first embodiment of the present technology.

[0041] Figure 22 is a diagram showing an example of the state of an analog TDI circuit until the end of exposure of the second frame in a comparative example.

[0042] Figure 23 is a diagram showing an example of TDI processing according to the first embodiment of the present technology.

[0043] Figure 24is a flowchart showing an example operation of a solid-state imaging device according to the first embodiment of the present technology.

[0044] Figure 25 is a circuit diagram showing an example configuration of an analog TDI circuit according to a modification example of the first embodiment of the present technology.

[0045] Figure 26 is a circuit diagram showing an example configuration of an analog TDI circuit according to the second embodiment of the present technology.

[0046] Figure 27 is a timing chart showing an example of transistor control according to the second embodiment of the present technology.

[0047] Figure 28 is a circuit diagram showing an example configuration of an analog TDI circuit according to a modification example of the second embodiment of the present technology. DETAILED DESCRIPTION

[0048] The following is a description of modes for carrying out the present technology (these modes will be referred to as embodiments hereinafter). The description will be made in the following order.

[0049] 1. First embodiment (example of switching each charge transport destination of a pair of photoelectric conversion elements)

[0050] 2. Second embodiment (example of reducing transistors and switching each charge transport destination of a pair of photoelectric conversion elements)

[0051] <1. First Embodiment>

[0052] [Example Configuration of Imaging Device]

[0053] Figure 1 is a block diagram showing an example configuration of an imaging device 100 according to an embodiment of the present technology. The imaging device 100 is a device that acquires image data, and includes an optical unit 110, a solid-state imaging device 200, a storage unit 120, a control unit 130, and a communication unit 140.

[0054] The optical unit 110 collects incident light and guides the incident light to the solid-state imaging device 200. The solid-state imaging device 200 acquires image data. The solid-state imaging device 200 provides the image data to the storage unit 120 via a signal line 209.

[0055] The storage unit 120 stores the image data. The control unit 130 controls the solid-state imaging device 200 to acquire the image data. The control unit 130 provides a synchronization signal XHS representing an imaging timing to the solid-state imaging device 200, for example, via a signal line 208.

[0056] The communication unit 140 reads the image data from the storage unit 120, and transmits the image data to the outside.

[0057] Figure 2 is a view for explaining a use example of the imaging device 100 according to the first embodiment of the present technology. As illustrated, the imaging device 100 is used in a factory or the like in which a conveyer belt 510 is installed.

[0058] The conveyer belt 510 moves objects 511 in a predetermined direction at a constant speed. The imaging device 100 is fixed near the conveyer belt 510, and images the objects 511 and generates image data. The image data is used for, for example, checking for defects. With this arrangement, FA is realized.

[0059] Note that the imaging device 100 images the objects 511 moving at a constant speed, but is not limited to this configuration. The imaging device 100 can be designed to move at a constant speed with respect to the objects and perform imaging such as aerial photography.

[0060] [Example Configuration of Solid-state Imaging Device]

[0061] Figure 3 is a view showing an example layer structure of the solid-state imaging device 200 according to the first embodiment of the present technology. The solid-state imaging device 200 includes a circuit chip 202 and a light-receiving chip 201 layered on the circuit chip 202. These chips are electrically connected via a connection portion such as a via.

[0062] Figure 4 is a block diagram showing an example configuration of the light-receiving chip 201 according to the first embodiment of the present technology. A pixel array unit 210 and a peripheral circuit 212 are provided in the light-receiving chip 201.

[0063] In the pixel array unit 210, a plurality of pixels are arranged in a two-dimensional lattice pattern. In the pixel array unit 210, a group of pixels arranged in the horizontal direction is referred to as a "row" or a "line", and a group of pixels arranged in the vertical direction is referred to as a "column".

[0064] Further, the pixel array unit 210 is divided into a plurality of pixel blocks 211. In each pixel block 211, for example, 8 rows x 2 columns of pixels are arranged. Further, two pixels adjacent to each other in the column direction constitute one analog TDI circuit 220. In the case where 8 rows x 2 columns of pixels are arranged in the pixel block 211, the number of the analog TDI circuits 220 in the pixel block 211 is 8 (4 rows x 2 columns). The circuit configuration of the analog TDI circuit 220 will be described later.

[0065] The peripheral circuit 212 includes, for example, a circuit that supplies a direct current (DC) voltage or the like.

[0066] Figure 5 is a block diagram showing an example configuration of the circuit chip 202 according to the first embodiment of the present technology. In the circuit chip 202, a digital-to-analog converter (DAC) 251, a pixel drive circuit 252, a time code generation unit 253, a pixel AD conversion unit 254, and a vertical scanning circuit 255 are provided. Further, in the circuit chip 202, a control circuit 256, a signal processing circuit 400, an image processing circuit 260, and an output circuit 257 are provided.

[0067] The DAC 251 generates a reference signal by digital-to-analog (DA) conversion within a predetermined AD conversion period. For example, a sawtooth ramp signal is used as the reference signal. The DAC 251 supplies the reference signal to the pixel AD conversion unit 254.

[0068] The time code generation unit 253 generates a time code indicating time within the AD conversion period. For example, the time code generation unit 253 is constituted by a counter. As the counter, for example, a Gray code counter is used. The time code generation unit 253 supplies the time code to the pixel AD conversion unit 254.

[0069] The pixel drive circuit 252 drives each analog TDI circuit 220 and generates an analog pixel signal.

[0070] The pixel AD conversion unit 254 performs AD conversion for converting the analog signal of each analog TDI circuit 220, which is a pixel signal, into a digital signal. The pixel AD conversion unit 254 is divided into a plurality of clusters 300. The cluster 300 is provided for each pixel block 211, and converts the analog signal in the corresponding pixel block 211 into a digital signal.

[0071] As a result of the AD conversion, the pixel AD conversion unit 254 generates a frame which is image data in which the digital signal is arranged, and supplies the frame to the signal processing circuit 400.

[0072] The vertical scanning circuit 255 drives the pixel AD conversion unit 254 to perform the AD conversion.

[0073] The signal processing circuit 400 performs predetermined signal processing on the frame. As the signal processing, various processing including correlated double sampling (CDS) processing and digital TDI processing are performed. The signal processing circuit 400 supplies the processed frame to the image processing circuit 260.

[0074] The image processing circuit 260 performs predetermined image processing on the frame supplied from the signal processing circuit 400. As the image processing, image recognition processing, black level correction processing, image correction processing, and demosaicing processing, and the like are performed. The image processing circuit 260 supplies the processed frame to the output circuit 257.

[0075] The output circuit 257 outputs the frame that has undergone image processing to the outside.

[0076] The control circuit 256 controls the operation timing of the DAC 251, the pixel drive circuit 252, the vertical scanning circuit 255, the signal processing circuit 400, the image processing circuit 260, and the output circuit 257 in synchronization with the synchronization signal XHS.

[0077] Figure 6 is a diagram showing an example configuration of the pixel AD conversion unit 254 according to the first embodiment of the present technology. In the pixel AD conversion unit 254, a plurality of ADCs 310 are arranged in a two-dimensional lattice pattern. The ADC 310 is provided for each analog TDI circuit 220. In a case where the number of rows and the number of columns of pixels are N (N is an integer) and M (M is an integer), respectively, the number of analog TDI circuits 220 is N x M / 2, and therefore, N x M / 2 ADCs 310 are provided.

[0078] In each cluster 300, the same number of ADCs 310 as the number of analog TDI circuits 220 in the pixel block 211 is provided. In a case where 4 rows x 2 columns of analog TDI circuits 220 are provided in the pixel block 211, 4 rows x 2 columns of ADCs 310 are also provided in the cluster 300.

[0079] The ADC 310 performs AD conversion on the analog pixel signal generated by the corresponding analog TDI circuit 220. In the AD conversion, the ADC 310 compares the pixel signal with a reference signal, and holds the time code at which the comparison result is inverted. Then, the ADC 310 outputs the held time code as a digital signal after AD conversion.

[0080] Further, a repeater unit 360 is provided for each column of the cluster 300. In a case where the number of columns of the cluster 300 is M / 2, M / 2 repeater units 360 are provided. The repeater unit 360 transfers the time code. The repeater unit 360 transfers the time code from the time code generation unit 253 to the ADC 310. The repeater unit 360 also transfers the digital signal from the ADC 310 to the signal processing circuit 400. This transfer of the digital signal is also referred to as "reading" of the digital signal.

[0081] Further, in the drawings, the numbers shown in the parentheses indicate an example of the reading order of the digital signal of the ADC 310. For example, the digital signal in the odd-numbered column of the first row is read first, and the digital signal in the even-numbered column of the first row is read second. The digital signal in the odd-numbered column of the second row is read third, and the digital signal in the even-numbered column of the second row is read fourth. Likewise, the digital signal in the odd-numbered column and the even-numbered column of each row is sequentially read thereafter.

[0082] Note that the ADC 310 is provided for each analog TDI circuit 220, but the present application is not limited to this configuration. A configuration in which a plurality of analog TDI circuits 220 share one ADC 310 can also be employed.

[0083] [Configuration example of ADC]

[0084] Figure 7 is a block diagram showing an example configuration of the ADC 310 according to the first embodiment of the present technology. The ADC 310 includes a differential input circuit 320, a positive feedback circuit 330, a latch control circuit 340, and a plurality of latch circuits 350.

[0085] Furthermore, a part of the differential input circuit 320 and the analog TDI circuit 220 are provided in the optical-reception chip 201, and the remaining part of the differential input circuit 320 and the subsequent circuit are provided in the circuit chip 202.

[0086] The differential input circuit 320 compares the pixel signal from the analog TDI circuit 220 with the reference signal from the DAC 251. The differential input circuit 320 provides a comparison result signal representing the comparison result to the positive feedback circuit 330.

[0087] The positive feedback circuit 330 adds a part of the output to the input (comparison result signal), and provides the result as an output signal VCO to the latch control circuit 340.

[0088] The latch control circuit 340 causes the plurality of latch circuits 350 to hold the time code at the time when the output signal VCO is inverted, in accordance with a control signal xWORD from the vertical scanning circuit 255.

[0089] The latch circuit 350 holds the time code from the repeater unit 360 under the control of the latch control circuit 340. The number of the latch circuits 350 is the same as the number of bits of the time code. For example, in the case where the time code is constituted by 15 bits, 15 latch circuits 350 are provided in the ADC 310. Furthermore, the held time code is read by the repeater unit 360 as a digital signal after AD conversion.

[0090] With the configuration shown in the diagram, the ADC 310 converts the pixel signal from the analog TDI circuit 220 into a digital signal.

[0091] [Example configuration of analog TDI circuit]

[0092] Figure 8is a circuit diagram showing an example configuration of an analog TDI circuit 220 according to the first embodiment of the present technology. The analog TDI circuit 220 includes reset transistors 221 and 222, floating diffusion layers 223 and 224, a transfer unit 230, charge drain transistors 225 and 226, and photoelectric conversion elements 227 and 228. Further, the analog TDI circuit 220 also includes a source follower (SF) readout circuit 240. For example, the transistors in the analog TDI circuit 220 (e.g., the reset transistor 221) can be n-channel metal-oxide-semiconductor (nMOS) transistors.

[0093] The reset transistor 221 initializes the amount of charge in the floating diffusion layer 223 in accordance with a reset signal RST1 from a pixel drive circuit 252. The reset transistor 222 initializes the amount of charge in the floating diffusion layer 224 in accordance with a reset signal RST2 from the pixel drive circuit 252.

[0094] The floating diffusion layers 223 and 224 accumulate charges, and generate voltages corresponding to the amounts of charge. Note that the floating diffusion layers 223 and 224 are examples of the pair of floating diffusion layers recited in the claims.

[0095] The transfer unit 230 switches the transfer destinations of the photoelectric conversion elements 227 and 228 to one of the floating diffusion layers 223 and 224, and transfers charges to the transfer destination. The transfer unit 230 includes transfer transistors 231 to 234.

[0096] The transfer transistor 231 transfers charges from the photoelectric conversion element 227 to the floating diffusion layer 223 in accordance with a transfer signal TX1-1 from the pixel drive circuit 252. The transfer transistor 232 transfers charges from the photoelectric conversion element 227 to the floating diffusion layer 224 in accordance with a transfer signal TX1-2 from the pixel drive circuit 252. Note that the transfer transistor 231 is an example of the first transfer transistor recited in the claims, and the transfer transistor 232 is an example of the second transfer transistor recited in the claims.

[0097] The transfer transistor 233 transfers charges from the photoelectric conversion element 228 to the floating diffusion layer 223 in accordance with a transfer signal TX2-1 from the pixel drive circuit 252. The transfer transistor 234 transfers charges from the photoelectric conversion element 228 to the floating diffusion layer 224 in accordance with a transfer signal TX2-2 from the pixel drive circuit 252. Note that the transfer transistor 233 is an example of the third transfer transistor recited in the claims, and the transfer transistor 234 is an example of the fourth transfer transistor recited in the claims.

[0098] The charge extraction transistor 225 extracts the electric charge from the photoelectric conversion element 227 and performs initialization according to an emission signal OFG1 from the pixel drive circuit 252. The charge extraction transistor 226 extracts the electric charge from the photoelectric conversion element 228 and performs initialization according to an emission signal OFG2 from the pixel drive circuit 252.

[0099] The photoelectric conversion elements 227 and 228 convert light into electric charge. The photoelectric conversion elements 227 and 228 are disposed in different rows from each other. For example, the photoelectric conversion elements 227 are disposed in odd-numbered rows (for example, the first row), and the photoelectric conversion elements 228 are disposed in even-numbered rows (for example, the second row) adjacent to the photoelectric conversion elements 227. Note that the photoelectric conversion elements 227 and 228 are examples of a pair of photoelectric conversion elements recited in the claims.

[0100] The SF readout circuit 240 outputs a pixel signal corresponding to the voltage of any one of the floating diffusion layers 223 and 224. The SF readout circuit 240 includes amplification transistors 241 and 242, selection transistors 243 and 244, and a current source transistor 245.

[0101] The amplification transistor 241 amplifies the voltage of the floating diffusion layer 223. The amplification transistor 242 amplifies the voltage of the floating diffusion layer 224.

[0102] The selection transistor 243 outputs, to the ADC 310, a pixel signal SIG that is a signal of the voltage amplified by the amplification transistor 241, according to a selection signal SEL1 from the pixel drive circuit 252. The selection transistor 244 outputs, to the ADC 310, a pixel signal SIG that is a signal of the voltage amplified by the amplification transistor 242, according to a selection signal SEL2 from the pixel drive circuit 252.

[0103] The current source transistor 245 supplies a constant current to the amplification transistors 241 and 242 and the selection transistors 243 and 244.

[0104] In the drawing, the analog TDI circuit 220 is disposed in the first row and the second row. The reset signal RSTn, the transfer signal TXn-1, the transfer signal TXn-2, the emission signal OFGn, and the selection signal SELn are transferred to every nth (n is an integer) row after the second row.

[0105] Figure 9 is a circuit diagram showing an example configuration of the differential input circuit 320 and the positive feedback circuit 330 according to the first embodiment of the present technology.

[0106] The differential input circuit 320 includes p-channel MOS (pMOS) transistors 321, 324, and 326, nMOS transistors 322, 323, 325, 327, and 328, and a capacitor 329. Among these components, the nMOS transistors 322, 323, 325, and 328 and the capacitor 329 are provided in the light-receiving chip 201, and the remaining components are provided in the circuit chip 202.

[0107] The nMOS transistors 322 and 325 form a differential pair, and the sources of these transistors are both connected to the drain of the nMOS transistor 323. In addition, the drain of the nMOS transistor 322 is connected to the drain of the pMOS transistor 321 and the gates of the pMOS transistors 321 and 324. The drain of the nMOS transistor 325 is connected to the drain of the pMOS transistor 324 and the gate of the pMOS transistor 326. In addition, a reference signal REF from the DAC 251 is input to the gate of the nMOS transistor 322.

[0108] A pixel signal SIG from the analog TDI circuit 220 is input to the gate of the nMOS transistor 325 via the capacitor 329. In addition, the source and drain of the nMOS transistor 328 are connected to the gate and drain of the nMOS transistor 325. An auto-zero signal AZ from the vertical scanning circuit 255 is input to the gate of the nMOS transistor 328.

[0109] A predetermined bias voltage VB1 is applied to the gate of the nMOS transistor 323, and a predetermined ground voltage is applied to the source of the nMOS transistor 323.

[0110] The pMOS transistors 321, 324, and 326 constitute a current mirror circuit. A power supply voltage VDDH is applied to the sources of the pMOS transistors 321, 324, and 326. The power supply voltage VDDH is higher than a power supply voltage VDDL described later.

[0111] The power supply voltage VDDL is applied to the gate of the nMOS transistor 327. In addition, the drain of the nMOS transistor 327 is connected to the drain of the pMOS transistor 326, and the source is connected to a positive feedback circuit 330.

[0112] The positive feedback circuit 330 includes pMOS transistors 331, 332, 334, and 335, and nMOS transistors 333, 336, and 337. The pMOS transistors 331 and 332 and the nMOS transistor 333 are connected in series to the power supply voltage VDDL. In addition, a drive signal INI2 from the vertical scanning circuit 255 is input to the gate of the pMOS transistor 331. A connection point between the pMOS transistor 332 and the nMOS transistor 333 is connected to the source of the nMOS transistor 327.

[0113] A ground voltage is applied to the source of the nMOS transistor 333, and a drive signal INI1 from the vertical scanning circuit 255 is input to the gate of the nMOS transistor 333.

[0114] The pMOS transistors 334 and 335 are connected in series to the power supply voltage VDDL. In addition, the drain of the pMOS transistor 335 is connected to the gate of the pMOS transistor 332 and the drains of the nMOS transistors 336 and 337. A control signal TESTVCO from the vertical scanning circuit 255 is input to the gates of the pMOS transistor 335 and the nMOS transistor 337. In addition, the gates of the pMOS transistor 334 and the nMOS transistor 336 are connected to a connection point between the pMOS transistor 332 and the nMOS transistor 333.

[0115] An output signal VCO is output from a connection point between the pMOS transistor 335 and the nMOS transistor 337. In addition, a ground voltage is applied to the sources of the nMOS transistors 336 and 337.

[0116] Note that the differential input circuit 320 and the positive feedback circuit 330 are not limited to Figure 9 the respective circuits shown, as long as they have the functions described Figure 7 above.

[0117] [Example Configuration of Signal Processing Circuit]

[0118] Figure 10 is a block diagram showing an example configuration of a signal processing circuit 400 according to the first embodiment of the present technology. The signal processing circuit 400 includes a plurality of selectors 405, a plurality of arithmetic circuits 410, a P-phase frame memory 440, and a past frame memory 450.

[0119] The selectors 405 are provided for each column of clusters 300, or for each repeater unit 360. In a case where two columns of ADCs 310 are provided in a cluster 300, a selector 405 is provided for each two columns. Meanwhile, an arithmetic circuit 410 is provided for each column of ADCs 310. In a case where the ADCs 310 are provided in M columns, M / 2 selectors 405 and M arithmetic circuits 410 are provided.

[0120] As described above, the repeater unit 360 sequentially outputs the digital signals of odd-numbered columns and the digital signals of even-numbered columns.

[0121] The selector 405 selects an output destination of the digital signal under the control of the control circuit 256. In a case where the odd-numbered column is output from the repeater unit 360, the selector 405 outputs the digital signal to the arithmetic circuit 410 corresponding to the odd-numbered column. On the other hand, in a case where the even-numbered column is output, the selector 405 outputs the digital signal to the arithmetic circuit 410 corresponding to the even-numbered column.

[0122] The arithmetic circuit 410 performs CDS processing and digital TDI processing on the digital signal from the selector 405.

[0123] Here, the digital signal includes a P-phase level and a D-phase level. The P-phase level indicates a level when the pixel is initialized by the reset signal RST. On the other hand, the D-phase level indicates a level corresponding to an exposure amount when the charge is transferred by the transfer signal. The P-phase level is also referred to as a reset level, and the D-phase level is also referred to as a signal level.

[0124] In the CDS processing, the M arithmetic circuits 410 cause the P-phase frame memory 440 to hold a P-phase frame in which the P-phase level is arranged. Then, the M arithmetic circuits 410 calculate a difference between the P-phase level and the D-phase level for each pixel and generate a current frame that is a CDS frame in which the difference data is set.

[0125] In the digital TDI processing, the M arithmetic circuits 410 then cause the past frame memory 450 to hold the CDS as a past frame. Next, the M arithmetic circuits 410 add a row of a predetermined address in the CDS frame that has undergone the CDS processing to rows of addresses adjacent to the predetermined address in the past frames of the previous two frames.

[0126] The M arithmetic circuits 410 also supply the CDS frame and the TDI frame that has undergone the digital TDI processing to the image processing circuit 260.

[0127] Figure 11 is a diagram illustrating an example layout of elements in the analog TDI circuit 220 according to the first embodiment of the present technology. The photoelectric conversion elements 227 and 228 are arranged in the vertical direction, and the floating diffusion layers 223 and 224 are arranged in the horizontal direction. The transfer transistors 232 and 234 are provided between the floating diffusion layer 224 and the photoelectric conversion elements 227 and 228. Meanwhile, the transfer transistors 231 and 233 are provided between the floating diffusion layer 223 and the photoelectric conversion elements 227 and 228. The arrows in the drawing indicate the direction of charge transfer.

[0128] Here, for example, the photoelectric conversion element 227 is provided in the kth (k is an odd number) row of the odd-numbered rows, and the photoelectric conversion element 228 is provided in the (k+1)th row of the even-numbered rows. Further, the photoelectric conversion element 227 of the kth row is denoted by "PDk", and the photoelectric conversion element 228 of the (k+1)th row is denoted by "PD(k+1)". One of the floating diffusion layers 223 and 224 corresponding to the kth row and the (k+1)th row is "FDk", and the other is "FD(k+1)". In the case where k is "1", "PD1" is provided in the first row, and "PD2" is provided in the second row. Further, "FD1" and "FD2" are provided in the first row and the second row, respectively.

[0129] Further, a rectangular transistor placement unit 247 is provided on the left side of the floating diffusion layer 224, and a rectangular transistor placement unit 246 is provided on the right side of the floating diffusion layer 223. In the transistor placement unit 246, for example, the reset transistor 221, the charge discharge transistor 225, the amplification transistor 241, and the selection transistor 243 in the circuit illustrated in FIG. 2 are provided. Figure 8 Further, a rectangular transistor placement unit 247 is provided on the left side of the floating diffusion layer 224, and a rectangular transistor placement unit 246 is provided on the right side of the floating diffusion layer 223. In the transistor placement unit 246, for example, the reset transistor 221, the charge discharge transistor 225, the amplification transistor 241, and the selection transistor 243 in the circuit illustrated in FIG. 2 are provided. Figure 8 Further, a rectangular transistor placement unit 247 is provided on the left side of the floating diffusion layer 224, and a rectangular transistor placement unit 246 is provided on the right side of the floating diffusion layer 223. In the transistor placement unit 246, for example, the reset transistor 221, the charge discharge transistor 225, the amplification transistor 241, and the selection transistor 243 in the circuit illustrated in FIG. 2 are provided.

[0130] Figure 12 is a diagram illustrating another example layout of elements in the analog TDI circuit 220 according to the first embodiment of the present technology. As illustrated in the diagram, the transistor placement units 246 and 247 can be an L-shaped structure. In the diagram, "a" illustrates an example layout in which the transistor placement unit 246 is provided on the upper side and the transistor placement unit 247 is provided on the lower side. In the diagram, "b" illustrates an example layout in which the transistor placement unit 246 is provided on the lower side and the transistor placement unit 247 is provided on the upper side.

[0131] [Example operation of solid-state imaging device]

[0132] Figure 13 is a timing chart illustrating an example of transistor control according to the first embodiment of the present technology. The pixel driving circuit 252 starts exposure of all the pixels with the emission signal OFG at a timing synchronized with the synchronization signal XHS. The timing at which the exposure of all the pixels ends is immediately before the start of the next exposure. For example, the first exposure ends at a timing between the timing T1 and the timing T2, and the first frame F1 is generated. Further, the second exposure starts after the end of the first exposure. Then, the second exposure ends at a timing after the timing T22, and the second frame F2 is generated. Further, the third exposure will start immediately after the end of the second exposure.

[0133] Meanwhile, at time T1, the pixel drive circuit 252 initializes the FD1 of the first row with the reset signal RST1. Further, at time T12 immediately before the end of exposure, the pixel drive circuit 252 transfers the charge from the PD1 to the FD1 with the transfer signal TX1-1.

[0134] Next, at time T2 after the end of exposure of the frame F1, the pixel drive circuit 252 initializes the FD1 of the second row with the reset signal RST2. Further, at time T22 before the end of exposure, the pixel drive circuit 252 transfers the charge from the PD1 to the FD2 and transfers the charge from the PD2 to the FD1 with the transfer signals TX1-2 and TX2-1.

[0135] As shown in the figure, exposure is started with the emission signal OFG, and the floating diffusion layers (FD1 and FD2) are initialized with the reset signal RST.

[0136] Figure 14 is a timing chart showing an example operation of the solid-state imaging device 200 up to the end of exposure of the second frame according to the first embodiment of the present technology.

[0137] At time T1 at which the synchronization signal XHS falls after the start of exposure of the frame F1, the pixel drive circuit 252 initializes the FD1 with the reset signal RST1. Further, the auto-zero signal AZ is input to the differential input circuit 320. At time T11 immediately after the initialization, then the transfer selection signal SEL1 is input, and the ADC 310 converts the P-phase level of the FD1 into a digital signal. Next, at time T12 immediately before the end of exposure, the pixel drive circuit 252 transfers the charge from the PD1 to the FD1 with the transfer signal TX1-1. As a result of the charge transfer, the FD1 transitions from the initial state to a state in which the charge corresponding to the exposure amount in the row L1 is held. Here, the row L1 is the row of the first row of the odd-numbered rows.

[0138] At time T2 at which the synchronization signal XHS falls after the start of exposure of the frame F2, the pixel drive circuit 252 initializes the FD2 with the reset signal RST1. Further, the auto-zero signal AZ is input to the differential input circuit 320. At time T21 immediately after the initialization, then the transfer selection signal SEL2 is input, and the ADC 310 converts the P-phase level of the FD2 of the frame F2 into a digital signal.

[0139] Next, at a timing T22 immediately before the end of exposure, the pixel drive circuit 252 transfers the charges from the PD1 to the FD2 and the charges from the PD2 to the FD1 using the transfer signals TX1-2 and TX2-1. As a result of these transfers, the FD1 transitions to a state of holding charges corresponding to the respective exposure amounts in the row L1 of the frame F1 and the row L2 of the frame F2. Here, the row L2 is the second row of the even rows. On the other hand, the FD2 transitions from the initial state to a state of holding charges corresponding to the exposure amount in the row L2. As shown in the example in the figure, in the FD1, the amounts of charges in the row L1 of the frame F1 and the row L2 of the frame F2 are integrated, and thus the analog TDI processing is successfully performed.

[0140] Figure 15 is a timing chart showing an example operation of the solid-state imaging device according to the first embodiment of the present technology up to the initialization of the floating diffusion layer of the fourth frame.

[0141] At a timing T23 at which the exposure of the frame F3 starts, the selection signal SEL1 is sent, and the ADC 310 AD-converts the D-phase level in the row obtained by integrating the row L1 of the frame F1 and the row L2 of the frame F2. At the same time, the arithmetic circuit 410 performs the CDS processing to calculate the difference between the D-phase level and the P-phase level of the FD1 of the frame F1.

[0142] At a timing T3 at which the synchronization signal XHS falls after the start of the exposure of the frame F3, the pixel drive circuit 252 initializes the FD1 using the reset signal RST1. Further, the auto-zero signal AZ is input to the difference input circuit 320. Immediately after the initialization, at a timing T31, the selection signal SEL1 is then sent, and the ADC 310 converts the P-phase level of the FD1 of the frame F3 to a digital signal.

[0143] Next, at a timing T32 immediately before the end of exposure, the pixel drive circuit 252 transfers the charges from the PD1 to the FD1 and the charges from the PD2 to the FD2 using the transfer signals TX1-1 and TX2-2. As a result of these transfers, the FD1 transitions from the initial state to a state of holding charges corresponding to the exposure amount in the row L1 of the frame F3, and the FD2 transitions to a state of holding charges corresponding to the respective exposure amounts in the row L1 of the frame F2 and the row L2 of the frame F3.

[0144] At a timing T33 at which the exposure of the frame F4 starts, the selection signal SEL2 is sent, and the ADC 310 AD-converts the D-phase level in the row obtained by integrating the row L1 of the frame F2 and the row L2 of the frame F3. At the same time, the arithmetic circuit 410 performs the CDS processing to calculate the difference between the D-phase level and the P-phase level of the FD2 of the frame F2.

[0145] The pixel drive circuit 252 initializes the FD2 at the timing T4 at which the synchronization signal XHS falls after the start of exposure of the frame F4. Further, the auto-zero signal AZ is input to the differential input circuit 320.

[0146] Note that, after the exposure of the frame F3, the transfer of charges is also performed in parallel for the third and subsequent rows, but the control for the third and subsequent rows is not shown.

[0147] Figure 16 is a timing chart showing an example operation of the solid-state imaging device 200 up to the end of exposure of the fifth frame according to the first embodiment of the present technology.

[0148] The selection signal SEL2 is sent at the timing T41 immediately after the initialization, and the ADC 310 converts the P-phase level of the FD2 of the frame F4 into a digital signal.

[0149] Next, at the timing T42 immediately before the end of exposure, the pixel drive circuit 252 transfers charges from the PD1 to the FD2 and charges from the PD2 to the FD1 with the transfer signals TX1-2 and TX2-1. As a result of these transfers, the FD1 transitions to a state of holding charges corresponding to the respective exposure amounts in the row L1 of the frame F3 and the row L2 of the frame F4. On the other hand, the FD2 transitions from the initial state to a state of holding charges corresponding to the exposure amount in the row L1 of the frame F4.

[0150] The selection signal SEL1 is sent at the timing T43 at which the exposure of the frame F5 starts, and the ADC 310 AD-converts the D-phase level in the row obtained by integrating the row L1 of the frame F3 and the row L2 of the frame F4. At the same time, the arithmetic circuit 410 performs the CDS processing to calculate the difference between the D-phase level and the P-phase level of the FD1 of the frame F3.

[0151] The pixel drive circuit 252 initializes the FD1 at the timing T5 at which the synchronization signal XHS falls after the start of exposure of the frame F5. Further, the auto-zero signal AZ is input to the differential input circuit 320. The selection signal SEL1 is then sent at the timing T51 immediately after the initialization, and the ADC 310 converts the P-phase level of the FD1 of the frame F5 into a digital signal. At the same time, the arithmetic circuit 410 performs the digital TDI processing to integrate the row L1 of the frame F1, the row L2 of the frame F2, the row L3 of the frame F3, and the row L4 of the frame F4.

[0152] Next, at the time T52 immediately after the end of exposure, the pixel drive circuit 252 transfers the charge from the PD1 to the FD1 and the charge from the PD2 to the FD2 using the transfer signals TX1-1 and TX2-2. As a result of these transfers, the FD1 is transitioned from the initial state to a state in which the charge corresponding to the exposure amount in the row L1 of the frame F5 is held, and the FD2 is transitioned to a state in which the charges corresponding to the respective exposure amounts in the row L1 of the frame F4 and the row L2 of the frame F5 are held.

[0153] At the time T53 at which the exposure of the frame F5 is completed, the selection signal SEL2 is sent, and the ADC 310 AD-converts the D-phase level in the row obtained by integrating the row L1 of the frame F4 and the row L2 of the frame F5. At the same time, the arithmetic circuit 410 performs the CDS processing to calculate the difference between the D-phase level and the P-phase level of the FD2 of the frame F4.

[0154] Next, the state of the analog TDI circuit 220 at Figure 14 to Figure 16 each point in time in the timing chart shown in Fig. 12 will be described.

[0155] Figure 17 is a diagram showing an example of the state of the analog TDI circuit 220 up to the end of exposure of the first frame according to the first embodiment of the present technology. In the diagram, "a" shows an example of the state of the analog TDI circuit 220 at the time T1, and "b" shows an example of the state of the analog TDI circuit 220 at the end of exposure of the frame F1.

[0156] As shown in "a" in the diagram, the pixel drive circuit 252 initializes the FD1 at the time T1. As shown in "b" in the diagram, the pixel drive circuit 252 then transfers the charge from the PD1 to the FD1 at the end of exposure of the frame F1. As a result, the charge corresponding to the exposure amount in the row L1 of the frame F1 is held in the FD1.

[0157] Figure 18 is a diagram showing an example of the state of the analog TDI circuit 220 up to the end of exposure of the second frame according to the first embodiment of the present technology. In the diagram, "a" shows an example of the state of the analog TDI circuit 220 at the time T2, and "b" shows an example of the state of the analog TDI circuit 220 at the end of exposure of the frame F2.

[0158] As shown in "a" in the diagram, the pixel drive circuit 252 initializes the FD2 at the time T2. As shown in "b" in the diagram, the pixel drive circuit 252 transfers the charge from the PD1 to the FD2 and the charge from the PD2 to the FD1 at the end of exposure of the frame F2. As a result, the charges corresponding to the respective exposure amounts in the row L1 of the frame F1 and the row L2 of the frame F2 are held in the FD1. At the same time, the charge corresponding to the exposure amount in the row L1 of the frame F2 is held in the FD2.

[0159] Figure 19 is a diagram showing an example of the state of the analog TDI circuit 220 up to the end of exposure of the third frame according to the first embodiment of the present technology. In the diagram, "a" indicates an example of the state of the analog TDI circuit 220 at the time T3, and "b" indicates an example of the state of the analog TDI circuit 220 at the end of exposure of the frame F3.

[0160] As shown in "a" in the diagram, the pixel drive circuit 252 initializes the FD1 at the time T3. As shown in "b" in the diagram, at the end of exposure of the frame F3, the pixel drive circuit 252 transfers the charge from the PD1 to the FD1 and transfers the charge from the PD2 to the FD2. As a result, the charge corresponding to the exposure amount in the row L1 of the frame F3 is held in the FD1. Meanwhile, in the FD2, the charge corresponding to the respective exposure amounts in the row L1 of the frame F2 and the row L2 of the frame F3 is held.

[0161] Figure 20 is a diagram showing an example of the state of the analog TDI circuit 220 up to the end of exposure of the fourth frame according to the first embodiment of the present technology. In the diagram, "a" indicates an example of the state of the analog TDI circuit 220 at the time T4, and "b" indicates an example of the state of the analog TDI circuit 220 at the end of exposure of the frame F4.

[0162] As shown in "a" in the diagram, the pixel drive circuit 252 initializes the FD2 at the time T4. As shown in "b" in the diagram, at the end of exposure of the frame F4, the pixel drive circuit 252 transfers the charge from the PD1 to the FD2 and transfers the charge from the PD2 to the FD1. As a result, the charge corresponding to the respective exposure amounts in the row L1 of the frame F3 and the row L2 of the frame F4 is held in the FD1. Meanwhile, the charge corresponding to the exposure amount in the row L1 of the frame F4 is held in the FD2.

[0163] Figure 21 is a diagram showing an example of the state of the analog TDI circuit 220 up to the end of exposure of the fifth frame according to the first embodiment of the present technology. In the diagram, "a" indicates an example of the state of the analog TDI circuit 220 at the time T5, and "b" indicates an example of the state of the analog TDI circuit 220 at the end of exposure of the frame F5.

[0164] As shown in "a" in the drawing, the pixel drive circuit 252 initializes the FD 1 at time T5. As shown in "b" in the drawing, at the end of the exposure of the frame F5, the pixel drive circuit 252 transfers the charge from the PD 1 to the FD 1 and transfers the charge from the PD 2 to the FD 2. As a result, the charge corresponding to the exposure amount in the row Ll of the frame F5 is held in the FD 1. Meanwhile, in the FD 2, the charge corresponding to the respective exposure amounts in the row Ll of the frame F4 and the row L2 of the frame F5 is held.

[0165] Here, as a comparative example, a configuration in which one of the FD 1 and the FD 2 is removed from the analog TDI circuit and two transfer transistors that transfer the charge to the one FD are explained.

[0166] Figure 22 is a drawing showing an example of the state of the analog TDI circuit until the end of the exposure of the second frame in the comparative example. In the drawing, "a" shows an example of the state of the analog TDI circuit 220 at time T2, and "b" shows the state of the analog TDI circuit in which the FD is initialized. In the drawing, "c" shows an example of the state of the analog TDI circuit at the end of the exposure of the frame F2.

[0167] As shown in the example of "a" in the drawing, in the comparative example in which the PD 1 and the PD 2 share one FD, the pixel drive circuit 252 of the comparative example transfers the charge from the PD 2 to the FD. As a result, the charge corresponding to the respective exposure amounts in the row Ll of the frame F 1 and the row L2 of the frame F2 is held in the FD. Then, the D-phase level of the row obtained by integrating these rows is converted into a digital signal.

[0168] Then, as shown in "b" in the drawing, the pixel drive circuit 252 of the comparative example initializes the FD. As shown in "c" in the drawing, when the P-phase level is converted into a digital signal, the charge is transferred from the PD 1 to the FD. As a result, the charge corresponding to the exposure amount in the row Ll of the frame F2 is held in the FD.

[0169] As shown in the drawing, in the comparative example in which the PD 1 and the PD 2 share one FD, the charge transfer of the row L2 of the frame F2 and the charge transfer of the row Ll of the frame F2 cannot be performed at the same time. These charge transfers are sequentially performed by the reset of the FD interposed therebetween.

[0170] On the other hand, as Figure 18In the "b" shown in the above, in the analog TDI circuit 220 provided with the FD1 and the FD2, the charge transfer from the row L2 of the frame F2 and the charge transfer from the row L1 of the frame F2 can be performed simultaneously. Therefore, the next charge transfer can be started without waiting for the initialization of the FD. Therefore, it is possible to make the interval of the synchronization signal XHS shorter than in the comparative example. Since one row of the TDI frame is scanned in synchronization with the synchronization signal XHS, it is possible to increase the scanning speed, i.e., the scan rate, of the TDI by shortening the interval of the synchronization signal XHS. Further, it is possible to increase the rate of the AD conversion performed in synchronization with the synchronization signal XHS.

[0171] Figure 23 is a diagram showing an example of TDI processing according to the first embodiment of the present technology. For example, first, the frame F1 is imaged, and then the frames F2, F3, F4, and F5 are sequentially imaged. The arrow in the diagram indicates the moving direction of the object. As shown in the example in the diagram, the object moves line by line in the vertical direction.

[0172] The analog TDI circuit 220 initializes the FD1, and transfers the charge in the row L1 of the frame F1 to the FD1. Next, the analog TDI circuit 220 transfers the charge in the row L2 of the frame F2 to the FD1, and transfers the charge in the row L1 of the frame F2 to the FD2. The charges in the rows L1+L2 are held in the FD1, and the voltage corresponding to the amount of charge is converted to a digital signal.

[0173] Next, the analog TDI circuit 220 initializes the FD1 and the FD3, transfers the charge in the row L2 of the frame F3 to the FD2, and transfers the charge in the row L1 of the frame F3 to the FD1. At the same time, the analog TDI circuit 220 transfers the charge in the row L3 of the frame F3 to the FD3. The charges in the rows L1+L2 are held in the FD2, and the voltage corresponding to the amount of charge is converted to a digital signal.

[0174] Then, the analog TDI circuit 220 initializes the FD2 and the FD4, transfers the charge in the row L2 of the frame F4 to the FD1, and transfers the charge in the row L1 of the frame F4 to the FD2. At the same time, the analog TDI circuit 220 transfers the charge in the row L4 of the frame F4 to the FD3, and transfers the charge in the row L3 of the frame F4 to the FD4. The charges in the rows L1+L2 are held in the FD1, and the voltage corresponding to the amount of charge is converted to a digital signal. Further, the charges in the rows L3+L4 are held in the FD3, and the voltage corresponding to the amount of charge is converted to a digital signal.

[0175] The arithmetic circuit 410 performs CDS processing on the digital signal output in the frame F2 and the digital signal output in the frame F4, respectively, and adds the CDS results. As a result, the row L1 of the frame F1, the row L2 of the frame F2, the row L3 of the frame F3, and the row L4 of the frame F4 are integrated. As described above, since the object moves row by row, the pattern of each row that is integrated is the same. The arithmetic circuit 410 outputs the added row as the last row of the TDI frame. The processing of integrating the exposure amount by changing the time in this way is called TDI processing.

[0176] Next, the analog TDI circuit 220 initializes the FD3 and the FD5, and transfers the charge in the row L2 of the frame F5 to the FD2. At the same time, the analog TDI circuit 220 transfers the charge in the row L3 of the frame F5 to the FD3, and transfers the charge in the row L4 of the frame F5 to the FD4. At the same time, the analog TDI circuit 220 also transfers the charge in the row L5 of the frame F5 to the FD5. The charge in the rows L1+L2 is held in the FD2, and the voltage corresponding to the amount of charge is converted to a digital signal. In addition, the charge in the rows L3+L4 is held in the FD4, and the voltage corresponding to the amount of charge is converted to a digital signal.

[0177] The arithmetic circuit 410 performs CDS processing on the digital signal output in the frame F3 and the digital signal output in the frame F5 and corresponding to the FD4, respectively, and adds the CDS results. As a result, the row L1 of the frame F2, the row L2 of the frame F3, the row L3 of the frame F4, and the row L4 of the frame F5 are integrated. The arithmetic circuit 410 outputs the added row as the penultimate row of the TDI frame.

[0178] The processing similar to the above is performed in the frame F6 and subsequent frames, and each row of the TDI frame is output in turn.

[0179] Note that the arithmetic circuit 410 performs not only the CDS processing but also the digital TDI processing, but the arithmetic circuit 410 can also be designed to perform only the CDS processing. In addition, the solid-state imaging device 200 integrates four rows by the analog and digital TDI processing, but can also integrate more rows. Furthermore, the solid-state imaging device 200 integrates the first four rows of the first four frames, but is not limited to this configuration. For example, in the case where the moving direction of the object is reversed, the solid-state imaging device 200 only needs to integrate the last four rows of the first four frames.

[0180] Figure 24 is a flowchart showing an example operation of the solid-state imaging device 200 according to the first embodiment of the present technology. The operation starts when, for example, a predetermined application program for imaging a frame is executed.

[0181] The pixel drive circuit 252 in the solid-state imaging device 200 simultaneously exposes all the pixels and initializes the floating diffusion layers (FD1 and FD2) at the end of the exposure (step S901). Then, the ADC 310 performs AD conversion on the P-phase level of the initialized FD (step S902).

[0182] Further, the analog TDI circuit 220 analog-adds the amounts of charge in the two adjacent rows by charge transfer (step S903). Further, the arithmetic circuit 410 converts the D-phase levels of the FDs holding the two rows and performs CDS processing (step S904). Further, when the two rows are digitally output, the arithmetic circuit 410 performs digital TDI processing to add the rows (step S905). After step S905, the solid-state imaging device 200 repeats the steps S901 and the subsequent steps.

[0183] As described above, in the first embodiment of the present technology, the transfer unit 230 that switches the transfer destinations of PD1 and PD2 to FD1 or FD2 is provided. Therefore, the charge transfer from PD1 to FD2 and the charge transfer from PD2 to FD1 can be performed simultaneously. Therefore, compared to the case where these charge transfers are performed sequentially, the scanning rate can be increased, and the speed of AD conversion can be improved.

[0184] [Modified Example]

[0185] In the above-described first embodiment, the analog TDI circuit 220 generates the pixel signals with a constant charge-voltage conversion efficiency. However, in order to reduce noise at low illuminance, it is preferable to generate the pixel signals with two mutually different charge-voltage conversion efficiencies. The analog TDI circuit 220 according to the modified example of the first embodiment is different from the analog TDI circuit 220 of the first embodiment in that the pixel signals are generated with two mutually different charge-voltage conversion efficiencies, respectively.

[0186] Figure 25 is a circuit diagram showing an example configuration of the analog TDI circuit 220 according to the modified example of the first embodiment of the present technology. The analog TDI circuit 220 according to the modified example of the first embodiment is different from the analog TDI circuit 220 of the first embodiment in that it further includes conversion efficiency control transistors 235 and 236 and capacitors 237 and 238. For example, nMOS transistors are used as the conversion efficiency control transistors 235 and 236.

[0187] The conversion efficiency control transistor 235 controls the charge-voltage conversion efficiency of the floating diffusion layer 223 (FD1) in accordance with the control signal FDG1. The conversion efficiency control transistor 236 controls the charge-voltage conversion efficiency of the floating diffusion layer 224 (FD2) in accordance with the control signal FDG2. The conversion efficiency control transistor 235 is connected in series to the reset transistor 221, and the capacitor 237 is inserted between the connection point of these transistors and the ground terminal. The conversion efficiency control transistor 236 is connected in series to the reset transistor 222, and the capacitor 238 is inserted between the connection point of these transistors and the ground terminal.

[0188] The pixel drive circuit 252 supplies the high-level control signal FDG1 in the pulse period immediately after the initialization of FD1, and thereafter performs control at the low level, so that the analog TDI circuit 220 can have a higher charge-voltage conversion efficiency than a predetermined value. On the other hand, the pixel drive circuit 252 always supplies the high-level control signal FDG1, so that the analog TDI circuit 220 can have a lower charge-voltage conversion efficiency than a predetermined value. The same applies to FD2. Hereinafter, the higher charge-voltage conversion efficiency will be simply referred to as "high conversion efficiency", and the lower charge-voltage conversion efficiency will be simply referred to as "low conversion efficiency".

[0189] For example, the pixel drive circuit 252 generates a pixel signal having both the high conversion efficiency and the low conversion efficiency in accordance with the control signal FDG. If the digital signal generated with the high conversion efficiency is shorter than the full code, the arithmetic circuit 410 outputs the digital signal generated with the high conversion efficiency as the signal of the pixel. On the other hand, if the digital signal generated with the high conversion efficiency is the full code signal, the arithmetic circuit 410 outputs the digital signal generated with the low conversion efficiency as the signal of the pixel. Thus, it is possible to expand the dynamic range, and it is possible to reduce the noise in the low-illuminance signal.

[0190] As described above, in the modified example of the first embodiment of the present technology, the analog TDI circuit 220 generates a pixel signal having both the high conversion efficiency and the low conversion efficiency, and selects one of the pixel signals in accordance with whether the pixel signal is the full code signal. Thus, it is possible to reduce the noise at the time of low illumination.

[0191] <2. Second Embodiment>

[0192] In the above-described first embodiment, the reset transistor is provided for each pixel. However, the circuit size can increase as the number of pixels increases. The analog TDI circuit 220 of the second embodiment is different from the analog TDI circuit 220 of the first embodiment in that the reset transistor is reduced, and the floating diffusion layers 223 and 224 are initialized by control of the charge discharge transistors 225 and 226.

[0193] Figure 26 is a circuit diagram showing an example configuration of the analog TDI circuit 220 according to the second embodiment of the present technology. The analog TDI circuit 220 of the second embodiment differs from the analog TDI circuit 220 of the first embodiment in that the reset transistors 221 and 222 are not included.

[0194] Figure 27 is a timing chart showing an example of transistor control according to the second embodiment of the present technology. At the time of the start of exposure, the pixel drive circuit 252 simultaneously transfers the transfer signals (TX1-1 and TX2-1) to all the pixels together with the emission signals (OFG1 and OFG2). As a result, the floating diffusion layers 223 and 224 are initialized together with the photoelectric conversion elements 227 and 228.

[0195] As described above, in the second embodiment of the present technology, the pixel drive circuit 252 initializes the floating diffusion layers 223 and 224 by controlling the charge discharge transistors 225 and 226. Therefore, the reset transistors 221 and 222 are not needed. Thus, it is possible to reduce the circuit size.

[0196] [Modified Example]

[0197] In the above-described second embodiment, the analog TDI circuit 220 generates the pixel signals with a constant charge-voltage conversion efficiency. However, in order to reduce noise at low illumination, it is preferable to generate the pixel signals with two mutually different charge-voltage conversion efficiencies. The analog TDI circuit 220 according to the modified example of the second embodiment differs from the analog TDI circuit 220 of the second embodiment in that the pixel signals are respectively generated with two mutually different charge-voltage conversion efficiencies.

[0198] Figure 28 is a circuit diagram showing an example configuration of the analog TDI circuit 220 according to the modified example of the second embodiment of the present technology. The analog TDI circuit 220 according to the modified example of the second embodiment differs from the analog TDI circuit 220 of the second embodiment in that the conversion efficiency control transistors 235 and 236 and the capacitors 237 and 238 are further included.

[0199] The conversion efficiency control transistor 235 is interposed between the floating diffusion layer 223 and the power supply terminal, and the capacitor 237 is interposed between the ground terminal and the connection point between the conversion efficiency control transistor 235 and the floating diffusion layer 223. The conversion efficiency control transistor 235 is interposed between the floating diffusion layer 223 and the power supply terminal, and the capacitor 237 is interposed between the ground terminal and the connection point between the conversion efficiency control transistor 235 and the floating diffusion layer 223. The conversion efficiency control transistor 236 is interposed between the floating diffusion layer 224 and the power supply terminal, and the capacitor 238 is interposed between the ground terminal and the connection point between the conversion efficiency control transistor 236 and the floating diffusion layer 224.

[0200] The transistor control method realized by the pixel drive circuit 252 according to the variation of the second embodiment is similar to that illustrated in FIG. 9. Figure 27

[0201] As described above, in the variation of the second embodiment of the present technology, the analog TDI circuit 220 generates pixel signals having both high conversion efficiency and low conversion efficiency, and one of the pixel signals is selected depending on whether the pixel signal is a full code signal. Thus, it is possible to reduce noise at low illumination.

[0202] Note that the above-described embodiments are examples for embodying the present technology, and the contents of the embodiments correspond to the subject matters of the claims. Also, the subject matters of the claims correspond to the contents in the embodiments having the same names as the subject matters of the claims. However, the present technology is not limited to the embodiments, and various changes can be made to the embodiments without departing from the scope of the present technology.

[0203] Note that the present technology can also be embodied in the following configuration.

[0204] (1) A solid-state imaging device comprising:

[0205] a pair of photoelectric conversion elements;

[0206] a pair of floating diffusion layers; and

[0207] a transfer unit that switches a transfer destination of each of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers, and transfers charges to the transfer destination.

[0208] (2) The solid-state imaging device according to (1), wherein the transfer unit simultaneously performs a process of transferring charges from one of the pair of photoelectric conversion elements to the other of the pair of floating diffusion layers and a process of transferring charges from the other of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers.

[0209] (3) The solid-state imaging device according to (2), wherein

[0210] the transfer unit includes:

[0211] a first transfer transistor that transfers charges from one of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers;

[0212] a second transfer transistor that transfers charges from one of the pair of photoelectric conversion elements to the other of the pair of floating diffusion layers;

[0213] ​a third transfer transistor that transfers charge from the other of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers; and

[0214] a fourth transfer transistor that transfers charge from the other of the pair of photoelectric conversion elements to the other of the pair of floating diffusion layers.

[0215] (4) The solid-state imaging device according to any one of (1) to (3), further comprising:

[0216] a pair of charge discharge transistors that respectively discharge charge from the pair of photoelectric conversion elements.

[0217] (5) The solid-state imaging device according to any one of (1) to (4), further comprising:

[0218] a pair of reset transistors that initialize each of the pair of floating diffusion layers.

[0219] (6) The solid-state imaging device according to any one of (1) to (5), further comprising:

[0220] a pair of conversion efficiency control transistors that control charge-voltage conversion efficiency of the pair of floating diffusion layers.

[0221] (7) The solid-state imaging device according to any one of (1) to (6), further comprising:

[0222] a pair of amplification transistors that amplify voltage of each of the pair of floating diffusion layers and generate a pair of pixel signals; and

[0223] a pair of selection transistors that select one of the pair of pixel signals.

[0224] (8) The solid-state imaging device according to (7), further comprising an analog-digital converter that sequentially converts each of the pair of pixel signals into a digital signal.

[0225] (9) The solid-state imaging device according to (8), further comprising:

[0226] an arithmetic circuit that integrates the digital signal.

[0227] (10) An imaging apparatus comprising:

[0228] a pair of photoelectric conversion elements;

[0229] a pair of floating diffusion layers;

[0230] a transfer unit that switches a transfer destination of each of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers and transfers charge to the transfer destination; and

[0231] a signal processing unit that converts a pixel signal corresponding to the amount of the electric charge into a digital signal and processes the digital signal.

[0232] List of reference signs

[0233] 100 imaging device

[0234] 110 optical unit

[0235] 120 storage unit

[0236] 130 control unit

[0237] 140 communication unit

[0238] 200 solid-state imaging device

[0239] 201 light-receiving chip

[0240] 202 circuit chip

[0241] 210 pixel array unit

[0242] 211 pixel block

[0243] 212 peripheral circuit

[0244] 220 analog TDI circuit

[0245] 221, 222 reset transistor

[0246] 223, 224 floating diffusion

[0247] 225, 226 charge-discharge transistor

[0248] 227, 228 photoelectric conversion element

[0249] 230 transfer unit

[0250] 231 to 234 transfer transistor

[0251] 235, 236 conversion efficiency control transistor

[0252] 237, 238, 329 capacitor

[0253] 240 SF readout circuit

[0254] 241, 242 amplification transistor

[0255] 243, 244 selection transistor

[0256] 245 current source transistor

[0257] 246, 247 transistor placement unit

[0258] 251 DAC

[0259] 252 pixel drive circuit

[0260] 253 time code generation unit

[0261] 254 pixel AD conversion unit

[0262] 255 vertical scanning circuit

[0263] 256 control circuit

[0264] 257 output circuit

[0265] 260 image processing circuit

[0266] 300 cluster

[0267] 310 ADC

[0268] 320 differential input circuit

[0269] 321, 324, 326, 331, 332, 334, 335 pMOS transistor

[0270] 322, 323, 325, 327, 328, 333, 336, 337 nMOS transistor

[0271] 330 positive feedback circuit

[0272] 340 latch control circuit

[0273] 350 latch circuit

[0274] 360 repeater unit

[0275] 400 signal processing circuit

[0276] 405 selector

[0277] 410 arithmetic circuit

[0278] 440 P-phase frame memory

[0279] 450 past frame memory

Claims

1. A solid-state imaging device comprising: a pair of photoelectric conversion elements; a pair of floating diffusion layers; and a transfer unit that switches a transfer destination of each of the pair of photoelectric conversion elements to any one of the pair of floating diffusion layers and transfers a charge to the transfer destination, wherein the transfer unit performs a process of transferring a charge from one of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers during a first frame, and simultaneously performs a process of transferring a charge from one of the pair of photoelectric conversion elements to the other of the pair of floating diffusion layers and a process of transferring a charge from the other of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers during a second frame after the first frame, so that one of the pair of floating diffusion layers holds a charge of one of the pair of photoelectric conversion elements in the first frame and a charge of the other of the pair of photoelectric conversion elements in the second frame.

2. The solid-state imaging device according to claim 1, wherein the transfer unit includes: a first transfer transistor that transfers a charge from one of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers; a second transfer transistor that transfers a charge from the one of the pair of photoelectric conversion elements to the other of the pair of floating diffusion layers; a third transfer transistor that transfers a charge from the other of the pair of photoelectric conversion elements to the one of the pair of floating diffusion layers; and a fourth transfer transistor that transfers a charge from the other of the pair of photoelectric conversion elements to the other of the pair of floating diffusion layers.

3. The solid-state imaging device according to claim 1 or 2, further comprising: a pair of charge drain transistors that drain a charge from each of the pair of photoelectric conversion elements.

4. The solid-state imaging device according to claim 1 or 2, further comprising: a pair of reset transistors that initialize each of the pair of floating diffusion layers.

5. The solid-state imaging device according to claim 1 or 2, further comprising: a pair of conversion efficiency control transistors that control a charge-voltage conversion efficiency of the pair of floating diffusion layers.

6. The solid-state imaging device according to claim 1 or 2, further comprising: a pair of amplification transistors that amplify a voltage of each of the pair of floating diffusion layers and generate a pair of pixel signals; and a pair of selection transistors that select one of the pair of pixel signals.

7. The solid-state imaging device according to claim 6, further comprising an analog-digital converter that sequentially converts each of the pair of pixel signals into a digital signal.

8. The solid-state imaging device according to claim 7, further comprising: an arithmetic circuit that integrates the digital signal.

9. An imaging apparatus comprising: the solid-state imaging device according to any one of claims 1 to 8; and a signal processing unit that converts a pixel signal corresponding to an amount of the charge into a digital signal and processes the digital signal. ​ ​ ​

Images