Chip simulation test method, device, equipment and system

Abstract

The embodiments of the present application provide a chip simulation test method, device, equipment and system. The chip simulation test method includes: using a hardware simulation system to simulate the first part of the chip running the design program, and performing at least one sampling to obtain at least one sampling data; loading the at least one sampling data into the software simulation system; the software simulation system simulates the chip to continue to run part of the remaining program or all of the remaining program of the design program based on the at least one sampling data, so as to simulate the chip running the design program. The embodiment of the present application executes part of the program in the hardware simulation system, and the software simulation system continues to execute the design program based on the collected data, so that there is no need to actually execute the entire process of the design program. The hardware simulation system and the software simulation system can be combined to achieve efficient analysis and debugging, thereby providing good guidance for chip design.

Description

Technical Field

[0001] The present application relates to the technical field of chip simulation testing. Specifically, the present application relates to a chip simulation testing method, device, equipment and system. Background Art

[0002] In the field of chip design, such as the processor field, the program patterns with the most typical loads in different scenarios are generally extracted, and then a better evaluation of the performance of the processor running the program can be performed through simulation testing.

[0003] Currently, the process of chip running programs is generally simulated through hardware simulation systems, but there are often problems such as poor test accuracy or only test results without data details of the intermediate links, which cannot provide good chip design guidance. Summary of the Invention

[0004] In response to the shortcomings of existing methods, this application proposes a chip simulation test method, device, equipment and system to solve the technical problems of poor test accuracy or only test results without data details of intermediate links in the existing technology.

[0005] In a first aspect, an embodiment of the present application provides a chip simulation test method, comprising:

[0006] Using a hardware simulation system to simulate the chip running the first part of the design program, and performing at least one sampling to obtain at least one sampling data; the sampling data is information indicating the running state of the hardware simulation system running the design program;

[0007] loading at least one sample data into the software simulation system;

[0008] The software simulation system simulates the chip to continue to run part of the remaining program or all of the remaining program of the design program based on at least one sampling data, so as to perform simulation test on the chip running the design program.

[0009] In one possible implementation, the software simulation system simulates the chip continuing to run part of or all of the remaining programs of the design program based on at least one sampled data, including:

[0010] The software simulation system determines the sampling position corresponding to each sampling data based on the execution information of each sampling data; the sampling data includes the execution information and the intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program;

[0011] Determine a sampling position from the sampling positions corresponding to the sampling data as the starting position for running the design program;

[0012] According to the intermediate result information of the sampling data corresponding to the determined sampling position, part of the remaining program or all of the remaining program of the design program continues to be run from the starting position of running the design program.

[0013] In one possible implementation, a hardware emulation system is used to simulate a chip running the first part of the design program, including:

[0014] Select a section of the design process as the first part;

[0015] Determine a sampling position from the sampling positions corresponding to the sampling data as a starting position for running the design program, including:

[0016] Determine the sampling order of each sampling data according to the sampling position corresponding to each sampling data;

[0017] The sampling position corresponding to the last collected data is used as the starting position for running the design program.

[0018] In one possible implementation, a hardware emulation system is used to simulate a chip running the first part of the design program, including:

[0019] If the hardware emulation system simulates a chip running the design program and a fault occurs, the portion of the design program that the hardware emulation system has already run is used as the first portion;

[0020] Determine a sampling position from the sampling positions corresponding to the sampling data as a starting position for running the design program, including:

[0021] Determine the sampling order of each sampling data according to the sampling position corresponding to each sampling data;

[0022] The sampling position corresponding to the Nth sampling data before the last sampling data is used as the starting position for running the design program, where N is a positive integer greater than or equal to 1.

[0023] In one possible implementation, performing at least one sampling includes:

[0024] Perform sampling at least once periodically according to the designed time; or,

[0025] Sampling is performed at least once according to the designed sampling position information; the designed sampling position information is information in the design program for triggering sampling.

[0026] In one possible implementation, a hardware simulation system is used to simulate a chip running the first part of the design program and perform at least one sampling to obtain at least one sample data, including:

[0027] During the process of the hardware emulation system simulating the first part of the design program running on the chip, information on the running status of the design program running on the hardware emulation system is saved in real time to each first storage module of the first storage unit; the first storage unit includes at least one first storage module; each time sampling is performed, the real-time running status information of the design program is obtained from each first storage module as sampling data;

[0028] The software simulation system simulates the chip to continue to run part of the remaining program or all of the remaining program of the design program based on at least one sampled data, including:

[0029] According to the corresponding relationship between each first storage module of the first storage unit and each second storage module of the second storage unit of the software simulation system, each sampled data is stored in the corresponding second storage module; the second storage unit includes at least one second storage module;

[0030] When the design program is run, sampling data is obtained from the second storage module.

[0031] In a second aspect, an embodiment of the present application provides a chip simulation test method, comprising:

[0032] Acquire at least one sampled data; the at least one sampled data is obtained by simulating the first part of the design program running on the chip using a hardware simulation system and sampling at least once, the sampled data being information indicating the running state of the design program running on the hardware simulation system;

[0033] The simulation chip continues to run part of the remaining program or all of the remaining program of the design program based on at least one sampling data to perform simulation test on the chip running the design program.

[0034] In a possible implementation, the simulation chip continues to run part of or all of the remaining programs of the design program based on the at least one sampled data, including:

[0035] Determine the sampling position corresponding to each sampling data based on the execution information of each sampling data; the sampling data includes the execution information and the intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program;

[0036] Determine a sampling position from the sampling positions corresponding to the sampling data as the starting position for running the design program;

[0037] According to the intermediate result information of the sampling data corresponding to the determined sampling position, part of the remaining program or all of the remaining program of the design program continues to be run from the starting position of running the design program.

[0038] In one possible implementation, determining a sampling position from the sampling positions corresponding to the sampled data as a starting position for running the design program includes:

[0039] Determine the sampling order of each sampling data according to the sampling position corresponding to each sampling data; use the sampling position corresponding to the last collected data as the starting position for running the design program;

[0040] Alternatively, the sampling order of each sampling data is determined according to the sampling position corresponding to each sampling data; the sampling position corresponding to the Nth sampling data before the last collected data is used as the starting position for running the design program, where N is a positive integer greater than or equal to 1.

[0041] In a third aspect, an embodiment of the present application provides a chip simulation test device, comprising:

[0042] an acquisition module, configured to acquire at least one piece of sampled data; the at least one piece of sampled data is obtained by simulating the first portion of the design program running on a chip using a hardware simulation system and sampling at least once, the sampled data being information indicating the running status of the design program running on the hardware simulation system;

[0043] The simulation test module is used to simulate the chip continuing to run part of the remaining program or all of the remaining program of the design program based on at least one sampling data, so as to perform simulation test on the chip running the design program.

[0044] In a fourth aspect, an embodiment of the present application provides a chip simulation test device, comprising: a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the chip simulation test method of the second aspect.

[0045] In a fifth aspect, an embodiment of the present application provides a chip simulation test system, comprising:

[0046] The hardware simulation system is configured to perform at least one sampling operation during the process of simulating the chip running the first part of the design program to obtain at least one piece of sampled data; the sampled data is information indicating the running state of the hardware simulation system running the design program;

[0047] The software simulation system is used to obtain at least one sampling data and simulate the chip to continue to run part of the remaining program or all of the remaining program of the design program based on the at least one sampling data, so as to simulate and test the chip running the design program.

[0048] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the chip simulation test method of the second aspect.

[0049] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0050] The simulation test method of the chip described in the embodiment of the present application is to first use a hardware simulation system to simulate the first part of the chip running the design program, and in the process of the hardware simulation system running the design program, perform at least one sampling to obtain sampling data, and the software simulation system simulates the chip to continue to run part of the remaining program or all of the remaining program of the design program based on at least one sampling data, thereby realizing the simulation test of the chip running the design program. The embodiment of the present application executes part of the program in the hardware simulation system, and the software simulation system continues to execute the design program based on the collected data, without actually executing the entire process of the design program; running the design program by the software simulation system can achieve accurate simulation, ensure the accuracy of the test, and can also save and analyze the data details of the intermediate links. Combining the hardware simulation system and the software simulation system can achieve efficient analysis and debugging, thereby providing good guidance for chip design.

[0051] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0053] Figure 1 A schematic diagram of the structure of a chip simulation test system provided in an embodiment of the present application;

[0054] Figure 2 A flowchart of a chip simulation test method provided in an embodiment of the present application;

[0055] Figure 3 A flowchart of another chip simulation test method provided in an embodiment of the present application;

[0056] Figure 4 A flowchart of another chip simulation test method provided in an embodiment of the present application;

[0057] Figure 5 A flowchart of another chip simulation test method provided in an embodiment of the present application;

[0058] Figure 6 A flowchart of another chip simulation test method provided in an embodiment of the present application;

[0059] Figure 7 A schematic diagram of a chip simulation test device according to an embodiment of the present application;

[0060] Figure 8 A schematic diagram of the framework of a chip simulation test device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] The present application is described in detail below. Examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components having the same or similar functions. In addition, if the detailed description of the known technology is not necessary for the features of the present application shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0062] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0063] It will be understood by those skilled in the art that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and / or" used herein includes all or any units and all combinations of one or more associated listed items.

[0064] The inventors of this application conducted research and found that in the field of chip design, a large part of the work is to understand and analyze the running program mode. It is difficult to have a design or architecture that can achieve the best running effect for all programs. However, the actual running program is complex and changeable, and trying to traverse all possible scenarios is an impossible task. Therefore, standard program test sets came into being. Based on the experience accumulated over the past few decades, the test sets extract the program patterns with the most typical loads in different scenarios, so that a better evaluation of processor performance can be made under a limited test set.

[0065] However, for software simulation systems, the most typical load programs are generally large-scale standard program test sets, which are too large and take too long to run. Therefore, software simulation systems are generally not used for simulation testing of chip running programs.

[0066] Currently, testing of ultra-large-scale standard program test suites primarily focuses on models or hardware accelerators. However, both approaches present challenges. Models operate at a high level of abstraction, ignoring execution details and leading to accuracy issues. Hardware accelerators can accurately assess scores, but only provide the results, lacking the data details of the intermediate steps, and thus offer limited design guidance.

[0067] The chip simulation test method, device, equipment and system provided in this application are intended to solve the above technical problems in the prior art.

[0068] The following describes in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments.

[0069] The present invention provides a chip simulation test system. Figure 1 As shown, the chip simulation test system 100 includes a hardware simulation system 110 and a software simulation system 120 .

[0070] The hardware simulation system 110 is used to perform at least one sampling during the process of simulating the chip running the first part of the design program to obtain at least one sampling data; the sampling data is information indicating the running status of the hardware simulation system 110 running the design program.

[0071] The software simulation system 120 is used to obtain at least one sample data, and simulate the chip to continue to run part or all of the remaining programs of the design program based on the at least one sample data, so as to simulate and test the chip running the design program.

[0072] The chip simulation test system 100 of the embodiment of the present application executes the first part of the design program in the hardware simulation system 110, and the software simulation system 120 continues to execute the design program based on the collected data, and there is no need to actually execute the entire process of the design program; running the design program through the software simulation system 120 can achieve precise simulation, ensure the accuracy of the test, and can also save and analyze the data details of the intermediate links. Combining the hardware simulation system 110 and the software simulation system 120 can achieve efficient analysis and debugging, thereby providing good guidance for chip design.

[0073] The chip simulation test system 100 of the embodiment of the present application uses the collected data of the simulation test of the first part of the design program as a stimulus, so that the software simulation system 120 continues to perform simulation testing of the design program based on the collected data, which can enable the design program to be quickly reproduced in the software simulation system 120 and speed up the testing process of the software simulation system 120.

[0074] This embodiment of the present application combines hardware emulation system 110 and software emulation system 120, providing dual functions for performance evaluation and pipeline detail optimization. This overcomes the problem of the coarse hardware acceleration methods of existing hardware emulation system 110. Furthermore, software emulation system 120 can accurately view pipeline details in the time period following the collected data, allowing for rapid identification of bottlenecks or potential faults, making it user-friendly for design verification personnel.

[0075] Alternatively, see Figure 1 As shown, the hardware simulation system 110 and the software simulation system 120 are electrically connected, and the sampled data can be directly transmitted to the software simulation system 120. Alternatively, the sampled data can be loaded from the hardware simulation system 110 to the software simulation system 120 via an external storage device.

[0076] Optionally, the sampling data is information about the running status of the hardware simulation system 110 running the design program, and each sampling data is the result of running the design program in real time. Based on the result of running the first part of the design program, the software simulation system 120 can continue to run part of the remaining programs or all of the remaining programs of the design program without having to repeat all the parts that the hardware simulation system 110 has already run.

[0077] Optionally, the sampled data is data generated by a snapshot.

[0078] Alternatively, the hardware simulation system 110 and the software simulation system 120 can be two relatively independent environments, with sampled data serving as key intermediate data. For example, Engineer A obtains sampled data in the hardware simulation system 110 in the laboratory, and Engineer B uses the sampled data in the office for simulation, waveform analysis, or bug troubleshooting.

[0079] Optionally, the hardware simulation system 110 may be a hardware accelerator or other hardware for simulating a chip running a program.

[0080] Optionally, the design program is a program to be tested as needed, and the chip can be a chip used in a processor. Since the processor will run many programs in actual applications, some mainstream program modes are generally selected when testing the processor, such as a standard program test set.

[0081] Optionally, the hardware simulation system 110 includes a sampling unit, which is used to periodically perform sampling at least once according to the design time; or, perform sampling at least once according to the design sampling position information; the design sampling position information is information in the design program for triggering sampling.

[0082] Optionally, the hardware simulation system 110 also includes a first storage unit, which includes at least one first storage module. The first storage module is used to store sampling data. The first storage module can be a general register group, a buffer memory cache, an internal register, and an internal static random access memory (SRAM). The internal static random access memory is, for example, a branch predictor table. The sampling content can be pre-designed as needed. Different degrees of sampling data will have different degrees of restoration of the original scene. The sampling data can be stored in the corresponding first storage module according to the pre-design.

[0083] Optionally, both the hardware simulation system 110 and the software simulation system 120 can simulate the chip running design program, for example, by setting parameters to form parameter setting sets, and use these parameter setting sets to simulate the hardware units, relationships and basic operating processes inside the chip.

[0084] Optionally, the software simulation system 120 may be an EDA simulation system. The software simulation system 120 may obtain data on all chip circuit states through waveform analysis and obtain chip simulation test information during the design program execution process.

[0085] Specifically, for details on how the software simulation system 120 continues to run part of the remaining program or all of the remaining program of the design program based on the sampled data, please refer to the simulation test method of the chip applied to the software simulation system 120.

[0086] Based on the same inventive concept, the present invention provides a chip simulation test method, which is applied to a chip simulation test system 100. Figure 2 As shown, the chip simulation test method includes: steps S201 to S203.

[0087] S201 , using the hardware simulation system 110 to simulate the chip running the first part of the design program, and performing at least one sampling to obtain at least one sampling data; the sampling data is information indicating the running status of the hardware simulation system 110 running the design program.

[0088] In some embodiments, performing at least one sampling in step S201 includes:

[0089] Perform sampling at least once periodically according to the designed time. Or,

[0090] Sampling is performed at least once according to the designed sampling position information; the designed sampling position information is information in the design program for triggering sampling.

[0091] Optionally, sampling is performed at least once periodically according to a designed time. Sampling may be performed every 1 second, or at intervals of different times. The periodic sampling time is designed according to actual conditions.

[0092] Optionally, sampling is performed at least once based on the design sampling location information, and data sampling can be performed at specific points specified in the design program. For example, a trigger instruction can be added as the design sampling location information at the corresponding position of the key segment to be sampled in the original design program, and sampling is triggered when the trigger instruction is executed.

[0093] S202 : Load at least one sample data into the software simulation system 120 .

[0094] Optionally, at least one sampled data may be loaded into the software simulation system 120 via an external storage device, or the hardware simulation system 110 may store the collected data and then send the collected data to the software simulation system 120 .

[0095] S203 , the software simulation system 120 simulates the chip continuing to run part of or all of the remaining programs of the design program based on the at least one sampled data, so as to perform a simulation test on the chip running the design program.

[0096] In some embodiments, in step S203, the software simulation system 120 simulates the chip continuing to run part of the remaining program or all of the remaining program of the design program based on the at least one sample data, including:

[0097] The software simulation system 120 determines the sampling position corresponding to each sampling data based on the execution information of each sampling data; the sampling data includes the execution information and the intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program.

[0098] A sampling position is determined from the sampling positions corresponding to the sampling data as a starting position for running the design program.

[0099] According to the intermediate result information of the sampling data corresponding to the determined sampling position, part of the remaining program or all of the remaining program of the design program continues to be run from the starting position of running the design program.

[0100] Optionally, the remaining procedures of the design program are procedures after running the starting position (ie, the determined sampling position) of the design program.

[0101] Optionally, the intermediate result information is the execution result of the design program, and the program following the design program can continue to run the program following the design program based on the previous intermediate result information.

[0102] Optionally, a sampling position is determined from the sampling positions corresponding to the sampling data, which may be the sampling position of any sampling data according to actual conditions.

[0103] Optionally, the software simulation system 120 executes part of or all of the remaining programs of the design program, which may be a part or all of the programs after the sampling position corresponding to the determined sampling data of the entire design program.

[0104] In some embodiments, the hardware simulation system 110 is used to simulate the chip running the first part of the design program and perform at least one sampling to obtain at least one sample data, including:

[0105] During the process of the hardware simulation system 110 simulating the first part of the chip running the design program, information on the running status of the hardware simulation system 110 running the design program is saved in real time to each first storage module of the first storage unit; the first storage unit includes at least one first storage module;

[0106] Each time sampling is performed, information on the running status of the real-time design program is obtained from each first storage module as sampling data.

[0107] In this embodiment, the software simulation system 120 simulates the chip continuing to run part of the remaining program or all of the remaining program of the design program based on at least one sample data, including:

[0108] According to the correspondence between each first storage module of the first storage unit and each second storage module of the second storage unit of the software simulation system 120, each sampled data is stored in the corresponding second storage module; the second storage unit includes at least one second storage module;

[0109] When the design program is run, sampling data is obtained from the second storage module.

[0110] Optionally, the first storage module of the first storage unit of the hardware simulation system 110 is used to store sampling data. The first storage module can be a general register group, a buffer memory cache, an internal register and an internal static random access memory (SRAM). The internal static random access memory is, for example, a branch predictor table. The sampling content can be pre-designed as needed. Different degrees of sampling data will have different degrees of restoration of the original scene. The sampling data can be stored in the corresponding first storage module according to the pre-design.

[0111] Optionally, the software simulation system 120 includes a second storage module corresponding to the first storage module of the first storage unit, and can store the collected data from the first storage module in the second storage module to reset the collected data, so as to call the collected data when the program continues to run.

[0112] In some embodiments, the hardware simulation system 110 is used to simulate the chip to run the first part of the design program, including:

[0113] Choose a section from the design process as the first part.

[0114] In this embodiment, determining a sampling position from the sampling positions corresponding to the sampled data as a starting position for running the design program includes:

[0115] Determine the sampling order of each sampling data according to the sampling position corresponding to each sampling data;

[0116] The sampling position corresponding to the last collected data is used as the starting position for running the design program.

[0117] Alternatively, as an example, see Figure 3 As shown, a chip simulation test method is provided, including the following steps S301 to S307.

[0118] S301. Select a part of the design program as the first part.

[0119] Alternatively, the design program can be divided into two parts, with the first part being the first part, executed by the hardware simulation system 110, and the second part being executed by the software simulation system 120. Alternatively, a portion in the middle can be taken as the first part, and the software simulation system 120 executes the program after the first part based on the sampled data of the first part, while the program before the first part can be executed normally by the software simulation system 120.

[0120] Optionally, as an example, the initialization part in the design program can be used as the first part, which is the part that is not of concern and is tested by the hardware simulation system 110. The part that needs attention after initialization is further simulated and tested by the software simulation system 120.

[0121] S302 , using the hardware simulation system 110 to simulate the chip running the first part of the design program, and performing at least one sampling to obtain at least one sampling data; the sampling data is information indicating the running status of the hardware simulation system 110 running the design program.

[0122] Optionally, the content in step S302 is consistent with the content in step S201 in principle and will not be repeated again.

[0123] S303 : Load at least one sample data into the software simulation system 120 .

[0124] Optionally, the content in step S303 is consistent with the content in step S202 in principle, and will not be repeated again.

[0125] S304 , the software simulation system 120 determines the sampling position corresponding to each sampling data based on the execution information of each sampling data; the sampling data includes the execution information and the intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program.

[0126] Optionally, the execution information of each sampled data can be used to locate the location of the design program and relocate the sampling location to facilitate continued execution of the design program. The intermediate result information of each sampled data can be used to run the design program to the sampling location. The intermediate result information of the subsequent sampled data is the result obtained based on the intermediate result information of the previous sampled data. Therefore, for each sampled data, the software simulation system 120 can continue to execute the subsequent program at the corresponding sampling location based on the intermediate result information.

[0127] S305 : Determine the sampling order of each sampling data according to the sampling position corresponding to each sampling data.

[0128] Optionally, the sampling order corresponds to the order in which the design program is run, and also corresponds to the order of the sampling time.

[0129] S306: Use the sampling position corresponding to the last collected data as the starting position for running the design program.

[0130] Optionally, if the first part is the initialization part, the last collected data may correspond to the end of initialization, and the position of the end of initialization is used as the starting position for running the design program. The software simulation system 120 continues to run part of the remaining programs or all of the remaining programs of the design program.

[0131] S307 : Continue running part of or all of the remaining programs of the design program from the starting position of the design program according to the intermediate result information of the sampling data corresponding to the determined sampling position.

[0132] Optionally, the intermediate result information of the sampled data is brought into the starting position of running the design program, so that the software simulation system 120 can continue to run part of the remaining programs or all of the remaining programs of the design program based on the intermediate result information of the collected data.

[0133] Optionally, if no failure occurs during the continued running of the design program, all remaining programs of the design program may be run.

[0134] The simulation test method of the chip of the embodiment of the present application can be used in the software simulation system 120 to accurately implement the key parts of the design program in the software simulation system 120, but there is no need to waste a lot of time to execute the program of irrelevant parts, thereby providing support for the software simulation system 120 to study the details of the test design program.

[0135] In some embodiments, the hardware simulation system 110 is used to simulate the chip to run the first part of the design program, including:

[0136] If the hardware simulation system 110 simulates a chip running the design program and a fault occurs, the portion of the design program that the hardware simulation system 110 has already run serves as the first portion;

[0137] and determining a sampling position from the sampling positions corresponding to the sampling data as a starting position for running the design program, including:

[0138] Determine the sampling order of each sampling data according to the sampling position corresponding to each sampling data;

[0139] The sampling position corresponding to the Nth sampling data before the last sampling data is used as the starting position for running the design program, where N is a positive integer greater than or equal to 1.

[0140] Alternatively, as an example, see Figure 4 As shown, a chip simulation test method is provided, including the following steps S401 to S407.

[0141] S401 , using the hardware simulation system 110 to simulate a chip running a design program, and performing at least one sampling to obtain at least one sampling data; if the hardware simulation system 110 simulates a chip running a design program and a fault occurs, the sampling is stopped.

[0142] Optionally, situations in which the hardware simulation system 110 simulates a failure in the design program running on the chip include: automatically exiting the design program when the hardware simulation system 110 simulates the design program running on the chip; or entering a loop and continuously repeating the operation when the hardware simulation system 110 simulates the design program running on the chip; or, when the hardware simulation system 110 simulates the design program running on the chip, the fault detection module of the hardware simulation system 110 detects a failure in the design program running and issues a prompt message.

[0143] Optionally, the hardware simulation system 110 simulates a fault in the chip running the design program, indicating that there is a fault in the chip running the design program, but the hardware simulation system 110 itself cannot find and analyze the fault, so it is necessary to simulate the chip running the design program through the software simulation system 120 to find and analyze the fault as quickly as possible.

[0144] Optionally, if the hardware simulation system 110 stops sampling, the hardware simulation system 110 exits running the design program.

[0145] S402 : Load at least one sample data into the software simulation system 120 .

[0146] Optionally, the content in step S402 is consistent with the content in steps S303 and S202 in principle, and will not be repeated again.

[0147] S403 , the software simulation system 120 determines a sampling position corresponding to each sampling data based on the execution information of each sampling data; the sampling data includes execution information and intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program.

[0148] Optionally, the content in step S403 is consistent with the content in step S304 in principle and will not be repeated again.

[0149] S404: Determine the sampling order of each sampling data according to the sampling position corresponding to each sampling data.

[0150] Optionally, the content in step S404 is consistent with the content in step S305 in principle, and will not be repeated again.

[0151] S405 , taking the sampling position corresponding to the Nth sampling data preceding the last sampling data as the starting position for running the design program, where N is a positive integer greater than or equal to 1.

[0152] Optionally, the sampling position of the last collected data is near the fault, and the sampling position corresponding to the first, second or third collected data before the last collected data can be selected as the starting position for running the design program according to actual conditions.

[0153] S406 : Continue running the remaining portion of the design program from the starting position of the design program according to the intermediate result information of the sampling data corresponding to the determined sampling position.

[0154] Optionally, the content in step S406 is consistent with the content in step S307 in principle and will not be repeated again.

[0155] Optionally, since the determined sampling position is in front of and close to the fault, the fault can be found soon after the software simulation system 120 continues to run the remaining part of the design program, so as to locate the fault and perform waveform analysis to find the cause of the vulnerability.

[0156] The chip simulation test method of the embodiment of the present application can be used for other post-simulations or when simulation failures occur, the software simulation system 120 in the pre-simulation environment can accurately view the pipeline details of the time period after the collected data, thereby quickly discovering bottlenecks or possible failures, which is friendly to design verification personnel.

[0157] Based on the same inventive concept, the present embodiment provides a chip simulation test method, which is applied to the software simulation system 120, see Figure 5 As shown, the chip simulation test method includes: step S501 to step S502.

[0158] S501, obtain at least one sampling data; the at least one sampling data is obtained by using the hardware simulation system 110 to simulate the first part of the chip running the design program and performing at least one sampling. The sampling data is information representing the running status of the hardware simulation system 110 running the design program.

[0159] Optionally, the sampled data is collected by the chip hardware simulation system 110 .

[0160] S502 : The simulation chip continues to run part of or all of the remaining programs of the design program based on at least one sampled data, so as to perform a simulation test on the chip running the design program.

[0161] In some embodiments, the simulation chip continues to run part of or all of the remaining procedures of the design program based on the at least one sample data, including:

[0162] Determine the sampling position corresponding to each sampling data based on the execution information of each sampling data; the sampling data includes the execution information and the intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program;

[0163] Determine a sampling position from the sampling positions corresponding to the sampling data as the starting position for running the design program;

[0164] According to the intermediate result information of the sampling data corresponding to the determined sampling position, part of the remaining program or all of the remaining program of the design program continues to be run from the starting position of running the design program.

[0165] In some embodiments, determining a sampling position from the sampling positions corresponding to the sampled data as a starting position for running the design program includes:

[0166] Determine the sampling order of each sampling data according to the sampling position corresponding to each sampling data; use the sampling position corresponding to the last collected data as the starting position for running the design program;

[0167] Alternatively, the sampling order of each sampling data is determined according to the sampling position corresponding to each sampling data; the sampling position corresponding to the Nth sampling data before the last collected data is used as the starting position for running the design program, where N is a positive integer greater than or equal to 1.

[0168] Alternatively, as an example, see Figure 6 As shown, a chip simulation test method is provided, which is applied to the software simulation system 120. The chip simulation test method includes the following steps S601 to S605.

[0169] S601, obtain at least one sampling data; the at least one sampling data is obtained by using the hardware simulation system 110 to simulate the first part of the chip running the design program and performing at least one sampling, and the sampling data is information representing the running status of the hardware simulation system 110 running the design program.

[0170] Optionally, the software simulation system 120 obtains at least one sampled data; the at least one sampled data is obtained by using the hardware simulation system 110 to simulate the first part of the chip running the design program and performing at least one sampling.

[0171] S602. Determine a sampling position corresponding to each sampling data based on execution information of each sampling data; the sampling data includes execution information and intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program.

[0172] Optionally, the software simulation system 120 determines a sampling position corresponding to each sample data based on the execution information of each sample data.

[0173] S603: Determine the sampling order of each sampling data according to the sampling position corresponding to each sampling data.

[0174] Optionally, the software simulation system 120 determines the sampling order of each sampled data according to the sampling position corresponding to each sampled data.

[0175] S604. Use the sampling position corresponding to the last collected data as the starting position for running the design program; or, determine the sampling order of each sampling data based on the sampling position corresponding to each sampling data; use the sampling position corresponding to the Nth sampling data before the last collected data as the starting position for running the design program, where N is a positive integer greater than or equal to 1.

[0176] Optionally, the software simulation system 120 uses the sampling position corresponding to the last collected data as the starting position for running the design program; or, determines the sampling order of each sampling data based on the sampling position corresponding to each sampling data; and uses the sampling position corresponding to the Nth sampling data before the last collected data as the starting position for running the design program, where N is a positive integer greater than or equal to 1.

[0177] S605 : Continue running part of or all of the remaining programs of the design program from the starting position of the design program according to the intermediate result information of the sampling data corresponding to the determined sampling position.

[0178] Optionally, the software simulation system 120 continues to run part of or all of the remaining programs of the design program from the starting position of running the design program according to the intermediate result information of the sampling data corresponding to the determined sampling position.

[0179] Optionally, the chip simulation test method applied to the software simulation system 120 is consistent with the content of the software simulation system 120 in the chip simulation test method applied to the chip simulation test system 100 , and is not repeated here.

[0180] Based on the same inventive concept, the present invention provides a chip simulation test device, see Figure 7 As shown, the chip simulation test device 700 includes: an acquisition module 710 and a simulation test module 720.

[0181] The acquisition module 710 is used to obtain at least one sampling data; the at least one sampling data is obtained by using the hardware simulation system 110 to simulate the first part of the chip running the design program and performing at least one sampling. The sampling data is information representing the running status of the hardware simulation system 110 running the design program.

[0182] The simulation test module 720 is used to simulate the chip continuing to run part of the remaining program or all of the remaining program of the design program based on at least one sampled data, so as to perform simulation test on the chip running the design program.

[0183] Optionally, the simulation test module 720 is used to determine the sampling position corresponding to each sampling data based on the execution information of each sampling data; the sampling data includes execution information and intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program; a sampling position is determined from the sampling positions corresponding to each sampling data as the starting position for running the design program; according to the intermediate result information of the sampling data corresponding to the determined sampling position, continue to run part of the remaining programs or all of the remaining programs of the design program from the starting position of running the design program.

[0184] Optionally, the simulation test module 720 is also used to determine the sampling order of each sampling data according to the sampling position corresponding to each sampling data; use the sampling position corresponding to the last collected data as the starting position for running the design program; or, determine the sampling order of each sampling data according to the sampling position corresponding to each sampling data; use the sampling position corresponding to the Nth sampling data before the last collected data as the starting position for running the design program, where N is a positive integer greater than or equal to 1.

[0185] Optionally, the chip simulation test device 700 of the embodiment of the present application has the same steps as the chip simulation method of the software simulation system 120 and will not be described in detail here.

[0186] Based on the same inventive concept, an embodiment of the present application provides a chip simulation test device, including: a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the steps of the chip simulation test method of the embodiment of the present application.

[0187] In an optional embodiment, the present application provides a chip simulation test device, such as Figure 8 As shown, Figure 8 The chip simulation test device 2000 shown includes a processor 2001 and a memory 2003 . The processor 2001 and the memory 2003 are communicatively connected, for example, via a bus 2002 .

[0188] Processor 2001 can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 2001 can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0189] The bus 2002 may include a path for transmitting information between the above components. The bus 2002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 2002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0190] The memory 2003 may be a ROM (Read-Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (random access memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read-Only Memory) or other optical disk storage, optical disk storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.

[0191] Optionally, chip simulation test device 2000 may further include a transceiver 2004. Transceiver 2004 may be used to receive and transmit signals. Transceiver 2004 may allow chip simulation test device 2000 to communicate with other devices wirelessly or wired to exchange data. It should be noted that in actual applications, the number of transceivers 2004 is not limited to one.

[0192] Optionally, the chip simulation test device 2000 may further include an input unit 2005. The input unit 2005 may be configured to receive input digital, character, image, and / or sound information, or to generate key signal input related to user settings and function control of the chip simulation test device 2000. The input unit 2005 may include, but is not limited to, one or more of a touch screen, a physical keyboard, function keys (such as a volume control key, a power button, etc.), a trackball, a mouse, a joystick, a camera, a microphone, and the like.

[0193] Optionally, the chip simulation test device 2000 may further include an output unit 2006. The output unit 2006 may be used to output or display information processed by the processor 2001. The output unit 2006 may include, but is not limited to, one or more of a display device, a speaker, a vibration device, and the like.

[0194] Although Figure 8 The simulation test apparatus 2000 of a chip having various devices is shown, but it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed instead.

[0195] Optionally, the memory 2003 is used to store application code for executing the solution of the present application, and the execution is controlled by the processor 2001. The processor 2001 is used to execute the application code stored in the memory 2003 to implement any chip simulation test method provided in the embodiments of the present application.

[0196] Based on the same inventive concept, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the chip simulation test method of the embodiment of the present application are implemented.

[0197] Computer-readable storage media include, but are not limited to, any type of disk (including floppy disks, hard disks, optical disks, CD-ROMs, and magneto-optical disks), ROMs, RAMs, EPROMs (Erasable Programmable Read-Only Memory), EEPROMs, flash memories, magnetic cards, or optical cards. In other words, computer-readable media include any medium that can store or transmit information in a form that can be read by a device (e.g., a computer).

[0198] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0199] (1) In the embodiment of the present application, the hardware simulation system 110 executes the first part of the design program, and the software simulation system 120 continues to execute the design program based on the collected data. It is not necessary to actually execute the entire process of the design program. By running the design program through the software simulation system 120, accurate simulation can be achieved to ensure the accuracy of the test, and the data details of the intermediate links can also be saved and analyzed. Combining the hardware simulation system 110 and the software simulation system 120 can achieve efficient analysis and debugging, thereby providing good guidance for chip design.

[0200] (2) The embodiment of the present application uses the collected data of the simulation test of the first part of the design program as a stimulus, so that the software simulation system 120 continues to perform the simulation test of the design program based on the collected data, which can enable the design program to be quickly reproduced in the software simulation system 120 and speed up the testing process of the software simulation system 120.

[0201] (3) The embodiment of the present application combines the hardware simulation system 110 with the software simulation system 120, providing dual functions of performance evaluation and pipeline detail optimization, overcoming the problem of the coarse hardware acceleration method of the existing hardware simulation system 110. At the same time, the software simulation system 120 can accurately view the pipeline details of the time period after the data is collected, thereby quickly discovering bottlenecks or potential faults, which is friendly to design verification personnel.

[0202] (4) The embodiments of the present application can accurately implement the key parts of the design program in the software simulation system 120, but there is no need to waste a lot of time to execute the program of irrelevant parts, thereby providing support for the software simulation system 120 to study the details of the test design program.

[0203] (5) The embodiment of the present application can be used when other post-simulation or hardware simulation fails. The software simulation system 120 in the pre-simulation environment can accurately view the pipeline details of the time period after the collected data, thereby quickly discovering the bottleneck or possible failure, which is convenient for design verification personnel to perform chip simulation testing.

[0204] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0205] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0206] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0207] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0208] The above description is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A chip simulation test method, characterized in that: include: Using a hardware simulation system to simulate the chip running the first part of the design program, and performing at least one sampling to obtain at least one sampling data; The simulating the first part of the design program executed by the chip using the hardware emulation system includes: if a fault occurs when the hardware emulation system simulates the chip executing the design program, the portion of the design program executed by the hardware emulation system is used as the first part, and the sampled data is information indicating an operating status of the design program executed by the hardware emulation system; loading the at least one sample data into a software simulation system; The software simulation system determines a sampling position corresponding to each of the sampled data based on execution information of each of the sampled data; the sampled data includes execution information and intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program; Determine the sampling order of each sampled data according to the sampling position corresponding to each sampled data; use the sampling position corresponding to the Nth sampled data before the last sampled data as the starting position for running the design program, where N is a positive integer greater than or equal to 1; According to the intermediate result information of the sampling data corresponding to the determined sampling position, part of the remaining program or all of the remaining program of the design program continues to be run from the starting position of the running design program to perform simulation test on the chip running the design program.

2. The chip simulation test method according to claim 1, characterized in that: The step of simulating the chip running the first part of the design program using a hardware simulation system includes: selecting a part of the design program as the first part; Determining a sampling position from the sampling positions corresponding to the sampling data as a starting position for running the design program includes: Determining a sampling order of each of the sampled data according to a sampling position corresponding to each of the sampled data; The sampling position corresponding to the last collected data is used as the starting position for running the design program.

3. The chip simulation test method according to claim 1, characterized in that: The performing of sampling at least once comprises: Perform sampling at least once periodically according to the designed time; or, Sampling is performed at least once according to the designed sampling position information; the designed sampling position information is information in the design program for triggering sampling.

4. The chip simulation test method according to claim 1, characterized in that: The method of using a hardware simulation system to simulate the first part of the design program executed by the chip and performing at least one sampling to obtain at least one piece of sampled data includes: during the process of simulating the first part of the design program executed by the chip by the hardware simulation system, saving information on the running status of the design program executed by the hardware simulation system in real time to each first storage module of a first storage unit; the first storage unit includes at least one first storage module; and obtaining real-time information on the running status of the design program from each first storage module as the sampled data each time sampling is performed; The software simulation system simulates that the chip continues to run part of the remaining program or all of the remaining program of the design program based on the at least one sampled data, including: According to the correspondence between each first storage module of the first storage unit and each second storage module of the second storage unit of the software simulation system, each of the sampled data is stored in a corresponding second storage module; the second storage unit includes at least one second storage module; When the design program is run, the sampling data is obtained from the second storage module.

5. A chip simulation test method, characterized in that: include: Obtain at least one sample data; The at least one sampled data is obtained by simulating a first portion of the design program executed by the chip using a hardware emulation system and performing at least one sampling operation. If a failure occurs when the hardware emulation system simulates the chip executing the design program, the portion of the design program executed by the hardware emulation system is used as the first portion. The sampled data is information indicating an operating status of the design program executed by the hardware emulation system. Determining a sampling position corresponding to each of the sampling data based on execution information of each of the sampling data; the sampling data includes execution information and intermediate result information, and the sampling position is a position corresponding to a sampling moment in the design program; Determining a sampling order of each of the sampled data according to a sampling position corresponding to each of the sampled data; The sampling position corresponding to the last collected data is used as the starting position for running the design program; or, the sampling order of each sampled data is determined according to the sampling position corresponding to each sampled data; The sampling position corresponding to the Nth sampling data before the last collected data is used as the starting position for running the design program, where N is a positive integer greater than or equal to 1; According to the intermediate result information of the sampling data corresponding to the determined sampling position, part of the remaining program or all of the remaining program of the design program continues to be run from the starting position of the running design program to perform simulation test on the chip running the design program.

6. A chip simulation test device, characterized in that: include: An acquisition module, configured to acquire at least one sample data; The at least one sampled data is obtained by simulating a first portion of the design program running on the chip using a hardware simulation system and sampling at least once, wherein the simulating the first portion of the design program running on the chip using the hardware simulation system includes: if a failure occurs when the hardware simulation system simulates the design program running on the chip, the portion of the design program that has been run by the hardware simulation system is used as the first portion, and the sampled data is information indicating an operating status of the design program running on the hardware simulation system; A simulation test module is used to simulate the chip based on the execution information of each sampling data, and determine the sampling position corresponding to each sampling data; the sampling data includes execution information and intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program; according to the sampling position corresponding to each sampling data, the sampling order of each sampling data is determined; the sampling position corresponding to the Nth sampling data before the last collected data is used as the starting position for running the design program, where N is a positive integer greater than or equal to 1; and, according to the intermediate result information of the sampling data corresponding to the determined sampling position, continue to run part of the remaining programs or all of the remaining programs of the design program from the starting position of the running design program, so as to simulate the running of the design program on the chip.

7. A chip simulation test device, characterized in that: include: A memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the chip simulation test method according to claim 5.

8. A chip simulation test system, characterized in that: include: A hardware simulation system is used to perform at least one sampling during the process of simulating the chip running the first part of the design program to obtain at least one sampling data; The sampled data is information indicating the running status of the hardware simulation system running the design program; A software simulation system is configured to obtain the at least one sampled data, simulate the chip based on execution information of each sampled data, and determine a sampling position corresponding to each sampled data; the sampled data includes execution information and intermediate result information, and the sampling position is the position of the corresponding sampling moment in the design program; determine a sampling order for each sampled data based on the sampling position corresponding to each sampled data; use the sampling position corresponding to the last acquired data as the starting position for running the design program; or determine a sampling order for each sampled data based on the sampling position corresponding to each sampled data; The sampling position corresponding to the Nth sampling data before the last collected data is used as the starting position for running the design program, where N is a positive integer greater than or equal to 1; based on the intermediate result information of the sampling data corresponding to the determined sampling position, continue to run part of the remaining programs or all of the remaining programs of the design program from the starting position of the running design program to perform simulation testing on the chip running the design program.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the chip simulation test method according to claim 5 are implemented.

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