Wafer detection data processing method and computer readable storage medium

Abstract

The present disclosure provides a method for processing wafer detection data and a computer-readable storage medium, which relate to the field of wafer manufacturing technology. Among them, the method for processing wafer detection data includes: determining the new failed bits generated in the completed wafer detection process; obtaining the repair records of the new failed bits, and the repair records of the adjacent bits of the new failed bits; parsing the repair records to determine the attribute information of the new failed bits and the adjacent bits, and the attribute information includes at least one of the position information, spare circuit information, unit graphics of the new failed bits and wafer detection process; performing classification learning according to the attribute information to obtain a failed bit prediction model; and predicting the failed bits to be subjected to wafer detection through the failed bit prediction model. Through the technical solution disclosed in the present disclosure, the reliability of predicting failed bits is improved, which is conducive to improving the yield rate of wafer products.

Description

Technical Field

[0001] The present disclosure relates to the field of wafer manufacturing technology, and in particular to a method for processing wafer detection data and a computer-readable storage medium. Background Art

[0002] During the wafer probing (circuit probing) stage, all the Fail Bits (hereinafter referred to as FBs) positions will be repaired. This disclosure refers to the repair of FBs as "general repair".

[0003] In addition, some non-FBs positions may also be patched. In the multi-pass test process after "general patching", new failed bits are likely to appear in non-FBs positions. Therefore, these non-FBs positions will be patched together after general patching, which is called "predictive patching".

[0004] The circuit wiring on the wafer is mostly at the micron or nanometer level. Determining the failed bits through manual screening or eliminating each unit with a probe will not only lead to low wafer detection efficiency and affect the output of wafer products, but may also cause new failed components to be generated due to the detection process, affecting the yield rate of wafer products. Summary of the invention

[0005] The purpose of the present disclosure is to provide a method for processing wafer detection data and a computer-readable storage medium, which at least to some extent overcome the problem of low efficiency in detecting failed bits of wafers in related technologies.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for processing wafer detection data is provided, including: determining a new failed bit generated in a completed wafer detection process; obtaining a repair record of the new failed bit, and a repair record of an adjacent bit of the new failed bit; parsing the repair record to determine attribute information of the new failed bit and the adjacent bit, the attribute information including at least one of position information, spare circuit information, a unit graphic of the new failed bit, and a wafer detection process; performing classification learning based on the attribute information to obtain a failed bit prediction model; and predicting the failed bit to be subjected to wafer detection by using the failed bit prediction model.

[0008] According to one embodiment of the present disclosure, parsing the repair record to determine the attribute information of the new failed bit and the attribute information of the adjacent bits includes: parsing the repair record to detect whether the new failed bit has been repaired, and detecting whether the adjacent bits have been repaired; if it is determined according to the repair record that the new failed bit has not been repaired, and it is determined according to the repair record that the adjacent bits have not been repaired, then obtaining the position information of the new failed bit in the attribute information and the wafer detection process.

[0009] According to one embodiment of the present disclosure, classification learning is performed based on attribute information to obtain a failed bit prediction model, including: correlation analysis of location information of new failed bits and wafer detection processes; or, mining analysis of unit graphics of new failed bits; or, wafer graph classification analysis of the wafer to which the new failed bits belong; and obtaining a failed bit prediction model based on the results of the analysis.

[0010] According to one embodiment of the present disclosure, parsing the patch record to determine the attribute information of the new failed bit and the attribute information of the adjacent bits also includes: parsing the patch record to detect whether the new failed bit has been patched; if it is determined according to the patch record that the new failed bit has been patched, then determining the position information of the new failed bit in the attribute information and the spare circuit information for patching the new failed bit.

[0011] According to an embodiment of the present disclosure, performing classification learning based on attribute information to obtain a failed bit prediction model also includes: performing backup circuit selection analysis on location information of new failed bits and backup circuit information for repairing new failed bits; and obtaining a failed bit prediction model based on the results of the analysis.

[0012] According to one embodiment of the present disclosure, parsing the patch record to determine the attribute information of the new failed bit and the attribute information of the adjacent bits also includes: parsing the patch record to detect whether the new failed bit has been patched, and detecting whether the adjacent bits have been patched; if it is determined according to the patch record that the new failed bit has not been patched, and it is determined according to the patch record that the adjacent bits have been patched, then determining the position information of the adjacent bits in the attribute information and the spare circuit information for patching the adjacent bits.

[0013] According to one embodiment of the present disclosure, classification learning is performed based on attribute information to obtain a failed bit prediction model, which also includes: analyzing the association probability between the position information of the failed bit and the repair position in the spare circuit information used to repair the adjacent bits, or performing mining analysis of the repair processing rules; and obtaining the failed bit prediction model based on the results of the analysis.

[0014] According to an embodiment of the present disclosure, the location information includes at least one of bit coordinate information, bit number information, and wafer product type.

[0015] According to an embodiment of the present disclosure, the backup circuit information includes at least one of a backup circuit version, a patch position, a patch detection item, a patch bit number, and a backup circuit information version.

[0016] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any one of the above-mentioned methods for processing wafer detection data is implemented.

[0017] The wafer detection data processing scheme provided in the embodiments of the present disclosure obtains the repair records of new failed bits and adjacent bits generated during the wafer detection process, and performs classification learning based on the above two types of repair records, so as to predict the failed bits according to the results of the classification learning, so as to improve the efficiency of failed bit detection of the wafer, the wafer output and the yield, that is, to provide an efficient and highly reliable wafer detection data processing scheme.

[0018] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0020] Figure 1A A schematic diagram showing a wafer detection process in an embodiment of the present disclosure;

[0021] Figure 1B A schematic diagram showing another wafer detection process in an embodiment of the present disclosure;

[0022] Figure 1C A schematic diagram showing another wafer detection process in an embodiment of the present disclosure;

[0023] Figure 2 A schematic flow chart showing a method for processing wafer detection data in an embodiment of the present disclosure;

[0024] Figure 3 A schematic flow chart showing another method for processing wafer detection data in an embodiment of the present disclosure;

[0025] Figure 4 A schematic flow chart showing another method for processing wafer detection data in an embodiment of the present disclosure;

[0026] Figure 5A schematic flow chart showing another method for processing wafer detection data in an embodiment of the present disclosure;

[0027] Figure 6 A schematic flow chart showing another method for processing wafer detection data in an embodiment of the present disclosure;

[0028] Figure 7 A schematic flow chart showing another method for processing wafer detection data in an embodiment of the present disclosure;

[0029] Figure 8 A schematic flow chart showing another method for processing wafer detection data in an embodiment of the present disclosure;

[0030] Fig. 9 A schematic flow chart showing another method for processing wafer detection data in an embodiment of the present disclosure;

[0031] Fig.10 A schematic block diagram showing another wafer detection data processing device in an embodiment of the present disclosure;

[0032] Fig.11 A schematic block diagram showing an electronic device in an embodiment of the present disclosure; and

[0033] Fig.12 A schematic diagram showing a computer-readable storage medium in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0035] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0036] The solution provided by the present invention obtains the repair records of new failed bits and adjacent bits generated during the wafer detection process, and performs classification learning based on the above two types of repair records, so as to predict the failed bits according to the results of the classification learning, so as to improve the efficiency of failed bit detection of the wafer, the wafer output and the yield, that is, to provide an efficient and highly reliable wafer detection data processing solution.

[0037] The processing scheme for wafer detection data provided by the embodiments of the present disclosure involves technologies such as wafer detection and classification learning, which is specifically described through the following embodiments.

[0038] Combination Figure 1A , Figure 1B and Figure 1C As shown, grooves 106 are provided between the functional areas on each wafer to partition the area into multiple sections. After some positions are repaired by the backup circuit, other valid bits will be affected, causing other valid bits to become new fail bits (NFBs). Figure 1A , Figure 1B and Figure 1C The new failed bit 102 , one of the new failed bits, is taken as an object for analysis. The new failed bit 102 may be referred to as an ONFB (Observed NFB).

[0039] The reason for NFBs may be caused by the patching, or by the invalid bits in the original patch position 108. These bits that may affect other valid bits and become new invalid bits after being patched are referred to as "related bits 104" in the present disclosure.

[0040] (1) Figure 1A , Figure 1B and Figure 1C As shown, the position of the new failed bit 102 is represented by (x, y), and the related bits 104 are mainly bits determined according to the new failed bit 102 and the repair position 108. Specifically, the related bits 104 include the following positions:

[0041] (1.1) The position (x-1,0) and the position (x-1,y max ), position (x+1,0) and position (x+1,y max )

[0042] (1.2) Location With location All bit positions, positions between With location All bit positions in between.

[0043] (1.3) Location With location All bit positions, positions between With location All bit positions in between.

[0044] The origin of the xy axis is determined by the lower left corner bit reference of the wafer, and M and N are integers greater than 1. Set the new failure bit 102 to be in Section N, y max It refers to the highest position in the y direction of the section where the new invalid bit 102 is located. It refers to the lowest position in the x direction in Section N. Refers to the highest position in the x direction in Section N.

[0045] Refer to the following Figure 2 A method for processing wafer detection data according to this embodiment of the present disclosure will be described. Figure 2 The method for processing wafer detection data shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0046] like Figure 2 As shown, the processing method of wafer detection data disclosed in the present invention includes:

[0047] Step S202, determining new failure bits generated during the completed wafer detection process.

[0048] Step S204, obtaining a repair record of the new failed bit and a repair record of the adjacent bits of the new failed bit.

[0049] In the above embodiment, the repair record includes but is not limited to the following:

[0050] (1) Version: The version of the backup circuit patch.

[0051] (2)Repaired Address: The repaired location.

[0052] (2.1)Chip location: The (x,y) location of the chip.

[0053] (2.2)Region: Bank location.

[0054] (2.3)Subdomain: The location of the data line.

[0055] (2.4)Row address: The x-axis position in the data line.

[0056] (2.5)Column address: The y-axis position in the data line.

[0057] (3)Bin: A collection of test items.

[0058] (4) Fail Bit Count: The number of failed bits repaired.

[0059] (5)Redundant ID: Redundant circuit number.

[0060] Step S206, parsing the repair record to determine attribute information of the new failed bit and attribute information of adjacent bits, wherein the attribute information includes at least one of position information, spare circuit information, unit pattern of the new failed bit and wafer detection process.

[0061] In the above embodiment, the location data includes but is not limited to the following:

[0062] (1)id: NFB number.

[0063] (2)product id: product type number.

[0064] (3) Fail Bit Address: The location of the failed bit.

[0065] (3.1) Lot ID: wafer lot number.

[0066] (3.2)Wafer No: Wafer number.

[0067] (3.3)Channel id: channel number.

[0068] (3.4)Chip location: The (x,y) location of the chip.

[0069] (3.5) Bank id: bank number. Inside the chip, the memory data is written into a large matrix in bits. The matrix contains multiple functional units (cells) and is addressed by row coordinates (x-axis) and column coordinates (y-axis). This matrix is ​​the logic bank of the chip.

[0070] (3.6)Row address: The x-axis position in the data line.

[0071] (3.7)Column address: The y-axis position in the data line.

[0072] (3.8)DQ address: data line location.

[0073] Step S208: performing classification learning according to the attribute information to obtain a failed bit prediction model.

[0074] Step S210 , predicting the failed bits to be detected on the wafer using a failed bit prediction model.

[0075] In the above embodiment, the adjacent bits of the new failed bit, that is, the related bits, are classified through the repair records of the new time-sensitive bits and the repair records of the adjacent bits, and the model is trained based on the classified data. The trained model is used for the prediction of the new failed bits, which is beneficial to improve the detection efficiency, reliability, output and yield.

[0076] based on Figure 2 The method steps shown are as follows: Figure 3 As shown, parsing the repair record to determine the attribute information of the new invalid bit and the attribute information of the adjacent bits includes:

[0077] Step S3062, parsing the repair record to detect whether the new failed bit has been repaired, and detecting whether the adjacent bits have been repaired.

[0078] Step S3064, if it is determined according to the repair record that the new failed bit has not been repaired, and it is determined according to the repair record that the adjacent bit has not been repaired, then the position information of the new failed bit in the attribute information and the wafer detection process are obtained.

[0079] In the above embodiment, by determining that the new failed bit and the adjacent bits have not been repaired (this detection result is defined as phenomenon 1), the failure causes are classified and learned from the perspective of position information and wafer detection process, so as to predict the position of the new failed bit based on the wafer detection process, which is beneficial to improving the efficiency and reliability of wafer detection.

[0080] based on Figure 2 and Figure 3 The method steps shown are as follows: Figure 4 As shown, classification learning is performed based on attribute information to obtain a failed bit prediction model including:

[0081] Step S4082, performing correlation analysis on the location information of the new failed bit and the wafer detection process.

[0082] Step S4084, mining and analyzing the cell pattern of the new failed bit.

[0083] Step S4086, performing wafer map classification analysis on the wafer to which the new failed bit belongs.

[0084] Step S4088, obtaining a failed bit prediction model according to the analysis result.

[0085] In the above embodiment, steps S4082, S4084 and S4086 are three independent classification learning processes, that is, analysis is performed based on position information and wafer detection process, unit graphics, and wafer map classification respectively to obtain a failure bit prediction model. In the subsequent wafer detection process, new failure bit prediction can be performed based on position information, wafer detection process, unit graphics and wafer map classification to improve the reliability and accuracy of wafer detection efficiency, which is beneficial to improving the output and yield of wafer products.

[0086] based on Figure 2 The method steps shown are as follows: Figure 5 As shown, parsing the repair record to determine the attribute information of the new invalid bit and the attribute information of the adjacent bit also includes:

[0087] Step S5062, parsing the repair record to detect whether the new failed bit has been repaired.

[0088] Step S5064: if it is determined according to the repair record that the new failed bit has been repaired, then the position information of the new failed bit in the attribute information and the spare circuit information for repairing the new failed bit are determined.

[0089] In the above embodiment, after determining that the new failed bit has been repaired (this detection result is defined as phenomenon 2), the inventor analyzed that the main reason for the generation of the new failed bit may be the introduction of a spare circuit to repair the new failed bit. Therefore, the spare circuit information used to repair the new failed bit is obtained for analysis.

[0090] based on Figure 2 and Figure 5 The method steps shown are as follows: Figure 6 As shown, classification learning is performed based on attribute information to obtain a failed bit prediction model, which also includes:

[0091] Step S6082: Perform backup circuit selection analysis on the location information of the new failed bit and the backup circuit information for repairing the new failed bit.

[0092] Step S6084, obtaining a failed bit prediction model according to the analysis result.

[0093] In the above embodiment, by analyzing the selection of the spare circuit for repairing the new failed bit, on the one hand, the characteristics of the spare circuit that is more likely to cause the new failed bit to appear can be determined, so as to improve the spare circuit and improve the overall reliability of the wafer. On the other hand, when the spare circuit is used for repair processing next time, the spare circuit information is input into the prediction model to predict the location where the new failed bit may appear, thereby improving the reliability and accuracy of wafer detection, and improving the wafer production and yield.

[0094] based on Figure 2 The method steps shown are as follows: Figure 7 As shown, parsing the repair record to determine the attribute information of the new invalid bit and the attribute information of the adjacent bit also includes:

[0095] Step S7062, parsing the repair record to detect whether the new failed bit has been repaired, and detecting whether the adjacent bits have been repaired.

[0096] Step S7064, if it is determined according to the repair record that the new failed bit has not been repaired, and it is determined according to the repair record that the adjacent bit has been repaired, then determine the position information of the adjacent bit in the attribute information and the spare circuit information for repairing the adjacent bit.

[0097] In the above embodiment, after determining that the new failed bit has not been repaired and the adjacent bit has been repaired (this detection result is defined as phenomenon 3), the inventor analyzed that the main reason for the generation of the adjacent bit may be the introduction of a backup circuit to repair the adjacent bit, and therefore, the backup circuit information is obtained for analysis.

[0098] based on Figure 2 and Figure 7 The method steps shown are as follows: Figure 8 As shown, classification learning is performed based on attribute information to obtain a failed bit prediction model, which also includes:

[0099] Step S8082, analyzing the association probability between the position information of the adjacent bits and the repair position in the spare circuit information for repairing the adjacent bits, or performing a mining analysis of the repair processing rules.

[0100] Step S8084, obtaining a failed bit prediction model according to the analysis result.

[0101] In the above embodiment, by analyzing the selection of the backup circuits for adjacent bits, on the one hand, the characteristics of the backup circuits that are more likely to cause the adjacent bits to appear can be determined, so as to improve the backup circuits and thus improve the overall reliability of the wafer. On the other hand, when the backup circuits are used for repair processing next time, the backup circuit information is input into the prediction model to predict the location where the adjacent bits may appear, thereby improving the reliability and accuracy of wafer detection, and increasing the wafer output and yield.

[0102] According to an embodiment of the present disclosure, the location information includes at least one of bit coordinate information, bit number information, and wafer product type.

[0103] According to an embodiment of the present disclosure, the backup circuit information includes at least one of a backup circuit version, a patch position, a patch detection item, a patch bit number, and a backup circuit information version.

[0104] like Fig. 9 As shown, the processing scheme of wafer detection data according to the present disclosure includes but is not limited to the following data processing, writing and reading processes:

[0105] (1) Source data includes, but is not limited to, NFB Data (New Failure Bit Data) and FU Data (Full Repair Record Data).

[0106] (2) System flow is mainly used to execute data processing steps, including:

[0107] Step S902: Obtain an NFB.

[0108] Step S904, acquiring repair information.

[0109] Step S906, determine whether it meets the condition 1, if so, execute step S910, if not, execute step S908.

[0110] Step S908, determine whether it meets phenomenon 2, if so, execute step S912, if not, execute step S914.

[0111] Step S910, outputting test process phenomenon sample data.

[0112] Step S912, outputting failed bit phenomenon sample data.

[0113] Step S914: outputting repair phenomenon sample data.

[0114] Step S916, determining whether it is the last NFB on the wafer, if so, ending, if not, executing step S902.

[0115] (3) Valid sample analysis includes: test process phenomenon sample data, i.e., new failure bit data NFB Data that conforms to phenomenon 1; failure bit phenomenon sample data, i.e., new failure bit data NFB Data that conforms to phenomenon 2 and corresponding repair record data FU Data; repair phenomenon sample data, i.e., new failure bit data NFB Data that conforms to phenomenon 3 and corresponding repair record data FU Data.

[0116] (4) Machine learning system: correlation analysis between test process and failed bits; failed bit unit graph mining analysis; wafer image classification analysis.

[0117] In summary, the core processing steps of the wafer detection data processing solution disclosed in the present invention are as follows:

[0118] (1) Obtain an NFB: Obtain an NFB information from the source data FB data in sequence. The most recently obtained NFB is the ONFB.

[0119] (2) Retrieve patch information: obtain the patch bit position of ONFB and the patch information of its related bit position, and obtain the spare circuit number using the patch.

[0120] (3) Output test process phenomenon sample data: Output ONFB information to the test process phenomenon sample database.

[0121] (4) Outputting failed bit phenomenon sample data: Outputting ONFB information, ONFB repair bit position information, and spare circuit number used for backup to the failed bit phenomenon sample database.

[0122] (5) Outputting repair phenomenon sample data: Outputting ONFB information, repair information of relevant bit positions, and spare circuit numbers used for backup to the repair phenomenon sample database.

[0123] Refer to the following Fig.10 A wafer detection data processing apparatus 1000 according to the embodiment of the present disclosure will be described. Fig.10 The wafer detection data processing device 1000 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0124] like Fig.10 As shown, the wafer detection data processing device 1000 includes: an acquisition module 1002 , a parsing module 1004 and a prediction module 1006 .

[0125] The acquisition module 1002 is used to determine new failure bits generated during the completed wafer detection process.

[0126] The acquisition module 1002 is further used to acquire the repair record of the new failed bit and the repair record of the adjacent bits of the new failed bit.

[0127] The parsing module 1004 is used to parse the repair record to determine the attribute information of the new failed bit and the attribute information of the adjacent bits, wherein the attribute information includes at least one of position information, spare circuit information, unit pattern of the new failed bit and wafer detection process.

[0128] The parsing module 1004 is further used to perform classification learning according to the attribute information to obtain a failed bit prediction model.

[0129] The prediction module 1006 is used to predict the failed bits to be detected on the wafer by using the failed bit prediction model.

[0130] Refer to the following Fig.11 1100 according to this embodiment of the present disclosure is described. Fig.11The electronic device 1100 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0131] like Fig.11 As shown, the electronic device 1100 is in the form of a general computing device. The components of the electronic device 1100 may include but are not limited to: the above-mentioned processing unit 1110, the above-mentioned storage unit 1120, and a bus 1130 connecting components of the processing system of different wafer detection data (including the storage unit 1120 and the processing unit 1110).

[0132] The storage unit stores program codes, which can be executed by the processing unit 1110, so that the processing unit 1110 executes the steps according to various exemplary embodiments of the present disclosure described in the above “Exemplary Method” section of this specification. For example, the processing unit 1110 can execute the following steps: Figures 2 to 8 All the steps shown in and other steps defined in the method for processing wafer detection data of the present disclosure.

[0133] The storage unit 1120 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 11201 and / or a cache storage unit 11202 , and may further include a read-only storage unit (ROM) 11203 .

[0134] The storage unit 1120 may also include a program / utility 11204 having a set of program modules 11205, such program modules 11205 including but not limited to: a processing system for operating wafer detection data, one or more application programs, other program modules and program data, each of which or some combination may include the implementation of a network environment.

[0135] Bus 1130 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0136] The electronic device 1100 may also communicate with one or more external devices 1140 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), one or more devices that enable a user to interact with the electronic device, and / or any device that enables the electronic device 1100 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed through an input / output (I / O) interface 1150.

[0137] Furthermore, the electronic device 1100 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 1160. As shown, the network adapter 1160 communicates with other modules of the electronic device 1100 via a bus 1130. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID wafer detection data processing systems, tape drives, and data backup storage wafer detection data processing systems, etc.

[0138] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0139] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the above method of the present specification is stored. In some possible implementations, various aspects of the present disclosure may also be implemented in the form of a program product, which includes a program code, and when the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps according to various exemplary implementations of the present disclosure described in the above "Exemplary Method" section of the present specification.

[0140] refer to Fig.12 As shown, a computer program 1200 for implementing the above method according to an embodiment of the present disclosure is described, which can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto. In this document, a readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with a processing system, apparatus or device that instructs execution of wafer detection data.

[0141] Computer readable signal media may include data signals propagated in baseband or as part of a carrier wave, in which readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Readable signal media may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with a processing system, apparatus, or device that executes wafer detection data by instructions.

[0142] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

[0143] Program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0144] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0145] In addition, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0146] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0147] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the disclosure disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for processing wafer detection data, characterized in that: include: Identify new failed bits generated during completed wafer probing; Acquire a repair record of the new failed bit and a repair record of adjacent bits of the new failed bit; Parsing the repair record to determine attribute information of the new failed bit and the adjacent bits, the attribute information including at least one of position information, spare circuit information, a unit pattern of the new failed bit, and a wafer detection process; Perform classification learning according to the attribute information to obtain a failed bit prediction model; The failed bit prediction model is used to predict the failed bits of the wafer to be detected.

2. The method for processing wafer detection data according to claim 1, characterized in that: Parsing the repair record to determine the attribute information of the new failed bit and the attribute information of the adjacent bit includes: Parsing the repair record to detect whether the new failed bit has been repaired, and detecting whether the adjacent bit has been repaired; If it is determined according to the repair record that the new failed bit has not been repaired, and it is determined according to the repair record that the adjacent bit has not been repaired, then the position information of the new failed bit in the attribute information and the wafer detection process are obtained.

3. The method for processing wafer detection data according to claim 2, characterized in that: Classification learning is performed according to the attribute information to obtain a failed bit prediction model including: Performing correlation analysis on the location information of the new failed bit and the wafer detection process; or, performing mining analysis on the cell graph of the new failed bit; Or, performing wafer map classification analysis on the wafer to which the new failed bit belongs; The failed bit prediction model is obtained according to the analysis result.

4. The method for processing wafer detection data according to claim 1, characterized in that: Parsing the repair record to determine the attribute information of the new failed bit and the attribute information of the adjacent bit also includes: parsing the repair record to detect whether the new failed bit has been repaired; If it is determined according to the repair record that the new failed bit has been repaired, the position information of the new failed bit in the attribute information and the spare circuit information for repairing the new failed bit are determined.

5. The method for processing wafer detection data according to claim 4, characterized in that: Performing classification learning according to the attribute information to obtain a failed bit prediction model also includes: Performing a backup circuit selection analysis on the location information of the new failed bit and the backup circuit information for repairing the new failed bit; The failed bit prediction model is obtained according to the analysis result.

6. The method for processing wafer detection data according to claim 1, characterized in that: Parsing the repair record to determine the attribute information of the new failed bit and the attribute information of the adjacent bit also includes: Parsing the repair record to detect whether the new failed bit has been repaired, and detecting whether the adjacent bit has been repaired; If it is determined according to the repair record that the new failed bit has not been repaired, and it is determined according to the repair record that the adjacent bit has been repaired, then the position information of the adjacent bit in the attribute information and the spare circuit information for repairing the adjacent bit are determined.

7. The method for processing wafer detection data according to claim 6, characterized in that: Performing classification learning according to the attribute information to obtain a failed bit prediction model also includes: Analyzing the association probability between the position information of the adjacent bits and the repair position in the spare circuit information for repairing the adjacent bits, or performing mining analysis of repair processing rules; The failed bit prediction model is obtained according to the analysis result.

8. The method for processing wafer detection data according to any one of claims 1 to 7, characterized in that: The location information includes at least one of bit coordinate information, bit number information, and wafer product type.

9. The method for processing wafer detection data according to any one of claims 1 to 7, characterized in that: The backup circuit information includes at least one of a backup circuit version, a patch position, a patch detection item, a patch bit quantity, and a backup circuit information version.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for processing wafer detection data according to any one of claims 1 to 9 is implemented.

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