Memory device and method of operating a memory device

Abstract

The present technology relates to electronic devices. For example, the present technology relates to a memory device and a method for operating the memory device. According to an embodiment, the memory device includes: a memory cell, a page buffer, and a test executor, the test executor controls the page buffer to sequentially apply a first test voltage and a second test voltage whose level is lower than the first test voltage to a sensing node of the page buffer through a bit line, and detects a defect of the sensing node according to whether the potential level of the sensing node changes.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to memory devices and methods of operating memory devices. Background Art

[0002] A storage device is a device that stores data under the control of a host device. The storage device may include a memory device that stores data and a memory controller that controls the memory device. The memory device may be classified into a volatile memory device and a non-volatile memory device.

[0003] A volatile memory device may store data only while receiving power from a power source. When the power supply is cut off, the data stored in the volatile memory device may be lost. A volatile memory device may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and the like.

[0004] A nonvolatile memory device may be a device that does not lose data even if power is cut off. Nonvolatile memory devices may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the invention

[0005] A memory device according to an embodiment of the present disclosure may include: a memory cell connected to a bit line; a page buffer storing data to be stored in the memory cell; and a test executor controlling the page buffer to sequentially apply a first test voltage and a second test voltage having a level lower than the first test voltage to a sensing node of the page buffer through the bit line, and detecting a defect of the sensing node according to whether the potential level of the sensing node changes; and the page buffer may include: a test voltage transmission component sending the first test voltage or the second test voltage to the sensing node; a sensing node connector electrically connecting the bit line and the sensing node; and a sensing latch latching a sensing value corresponding to the potential level of the sensing node and providing the sensing value to the test executor.

[0006] A method for operating a memory device according to an embodiment of the present disclosure may include: sequentially applying a first test voltage and a second test voltage having a level lower than the first test voltage to a sensing node of a page buffer through a bit line; and detecting a defect of the sensing node based on whether a potential level of the sensing node is changed to be less than a preset reference level. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram illustrating a storage system according to an embodiment of the present disclosure.

[0008] Figure 2is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0009] Figure 3 is an example Figure 2 A diagram of the structure of any one of the multiple storage blocks shown.

[0010] Figure 4 is a diagram illustrating a page buffer according to an embodiment of the present disclosure.

[0011] Figure 5 It is an example Figure 4 FIG. 1 is a diagram of an embodiment in which a first test voltage is applied to a sensing node of a page buffer.

[0012] Figure 6 It is an example Figure 4 FIG. 1 is a diagram of an embodiment in which a second test voltage is applied to a sensing node of a page buffer.

[0013] Figure 7 is a diagram schematically illustrating signal waveforms of control signals for applying a first test voltage and a second test voltage to a sensing node.

[0014] Figure 8 This is an example detection Figure 4 FIG. 1 is a diagram of an embodiment of a defect in a sensing node of a page buffer.

[0015] Fig. 9 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0016] Fig.10 is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0017] Fig.11 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0018] Fig.12 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0019] Fig.13 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0020] The specific structural or functional description of the embodiments according to the concepts disclosed in this specification or application is only exemplified to describe the embodiments according to the concepts of the present disclosure. The embodiments according to the concepts of the present disclosure can be performed in various forms, and the description is not limited to the embodiments described in this specification or application.

[0021] Embodiments of the present disclosure provide a memory device that prevents performance degradation by sensing a defect of a sensing node and a method of operating the memory device.

[0022] According to the present technology, a memory device that prevents performance degradation by sensing a defect of a sensing node and a method of operating the memory device are provided.

[0023] Figure 1 is a diagram illustrating a storage system according to an embodiment of the present disclosure.

[0024] Reference Figure 1 The storage system can be implemented as a personal computer (PC), a data center, an enterprise data storage system, a data processing system including a direct-attached storage (DAS), a data processing system including a storage area network (SAN), and a data processing system including a network-attached storage (NAS).

[0025] The storage system may include a storage device 1000 and a host 400 .

[0026] The storage device 1000 may be a device that stores data according to a request of a host 400 such as a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system.

[0027] The storage device 1000 may be manufactured as one of various types of storage devices according to a host interface as a communication method with the host 400. For example, the storage device 1000 may be configured as any of various types of storage devices such as SSD, multimedia cards in the form of MMC, eMMC, RS-MMC, and micro MMC, secure digital cards in the form of SD, mini SD, and micro SD, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a PCI-Express (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0028] The storage device 1000 may be manufactured as any of various types of packages. For example, the storage device 1000 may be manufactured as any of various types of packages such as package-on-package (PoP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0029] The storage device 1000 may include a memory device 100 and a memory controller 200 .

[0030] The memory device 100 may operate in response to the control of the memory controller 200. For example, the memory device 100 may receive a command and an address from the memory controller 200 and access a memory cell selected by the address among memory cells (not shown). The memory device 100 may perform an operation indicated by the command on the memory cell selected by the address.

[0031] The command may be, for example, a program command, a read command, or an erase command, and the operation indicated by the command may be, for example, a program operation (or a write operation), a read operation, or an erase operation.

[0032] For example, the memory device 100 may receive a program command, an address, and data, and program the data in a memory cell selected by the address. Here, the data to be programmed in the selected memory cell may be defined as write data.

[0033] For example, the memory device 100 may receive a read command and an address and read data from a region selected by the address in the memory cell array 101. Data to be read from the selected region among data stored in the memory device 100 may be defined as read data.

[0034] For example, the memory device 100 may receive an erase command and an address, and erase data stored in a region selected by the address.

[0035] For example, the memory device 100 may be implemented using double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4 (LPDDR4) SDRAM, graphic double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory (vertical NAND), NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory, spin transfer torque random access memory (STT-RAM), etc.

[0036] In this specification, for convenience of description, it is assumed that the memory device 100 is a NAND flash memory.

[0037] The memory device 100 may store write data under the control of the memory controller 200 , or read stored read data and provide the read data to the memory controller 200 .

[0038] The memory device 100 may include at least one plane. One plane may include a memory cell array 101 including memory cells storing data.

[0039] The memory cell array 101 may include a plurality of memory blocks (not shown). A memory block may be a unit for performing an erase operation of erasing data.

[0040] The memory block may include a plurality of pages (not shown). A page may be a unit for performing a program operation for storing write data or a read operation for reading stored read data.

[0041] The memory device 100 may perform a test operation of detecting a defect of a sensing node (not shown) of the page buffer 102 in response to a test command TCMD provided from an external controller. To this end, the memory device 100 may include a test executor 103.

[0042] As an embodiment, in response to a test command TCMD input from an external controller, the test executor 103 can control the page buffer 102 to sequentially apply a first test voltage and a second test voltage to a sensing node of the page buffer 102, and detect a defect of the sensing node according to whether the potential level of the sensing node changes.

[0043] In an implementation, the second test voltage may be a voltage having a level lower than that of the first test voltage.

[0044] In an embodiment, when the potential level of the sensing node changes, the test executor 103 may detect that the sensing node is defective. For example, when the potential level of the sensing node decreases from a first level to a second level lower than the first level, the test executor 103 may detect that the sensing node is defective.

[0045] In an embodiment, when the potential level of the sensing node does not change, the test executor 103 may detect that the sensing node is normal.

[0046] After performing the test operation, the memory device 100 may provide the test data TDATA to the external controller as a response to the test command TCMD.

[0047] The test data TDATA may be data indicating completion of a test operation, data related to the state of a sensing node of the page buffer 102, or data indicating information about a sensing node detected as a defective sensing node. Here, the state of the sensing node may be, for example, a normal state or a defective state.

[0048] In an implementation, when a defect of a sensing node is detected, the memory device 100 may store data related to the defective sensing node and, in response to control of an external controller, may provide the data related to the defective sensing node to the external controller as test data TDATA.

[0049] In an implementation, the number of page buffers 102 may be plural. Therefore, the memory device 100 may output test data TDATA for the state of each sensing node to an external controller. Alternatively, the memory device 100 may selectively output test data TDATA for the state of each sensing node to an external controller.

[0050] As an embodiment, the external controller may be a test controller that tests the memory device 100 in a manufacturing step of the memory device 100 .

[0051] As an implementation, the external controller may be the memory controller 200 .

[0052] The memory controller 200 may control overall operations of the memory device 1000 .

[0053] The memory controller 200 may execute firmware when power is applied to the storage device 1000. When the memory device 100 is a flash memory device, the firmware may include a host interface layer, a flash translation layer, and a flash interface layer.

[0054] The host interface layer may control operations between the host 400 and the memory controller 200 .

[0055] The flash translation layer may convert a logical address provided from the host 400 into a physical address. To this end, the memory controller 200 may store mapping data, which is a correspondence relationship between a logical address and a physical address.

[0056] The flash interface layer may control communication between the memory controller 200 and the memory device 100 .

[0057] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, and an erase operation, respectively, in response to a write request, a read request, and an erase request of the host 400 .

[0058] During a program operation, the memory controller 200 may provide a program command, a physical address, and write data to the memory device 100 .

[0059] During a read operation, the memory controller 200 may provide a read command and a physical address to the memory device 100 .

[0060] In an erase operation, the memory controller 200 may provide an erase command and a physical address to the memory device 100 .

[0061] The memory controller 200 may autonomously generate a command, an address, and data regardless of a request provided from the host 400. The memory controller 200 may transmit the autonomously generated command, address, and data to the memory device 100.

[0062] For example, the memory controller 200 may generate commands, addresses, and data for performing background operations. In addition, the memory controller 200 may provide commands, addresses, and data to the memory device 100.

[0063] The background operation may be at least one of wear leveling, read reclamation, or garbage collection.

[0064] Wear leveling may refer to an operation of storing the number of erase times of memory blocks and programming data into a memory block having the least number of erase times.

[0065] Read reclamation may refer to an operation of moving data stored in a memory block to another memory block before an uncorrectable error occurs in the data stored in the memory block.

[0066] Garbage collection may refer to an operation of copying valid data included in a bad block among storage blocks to a free block and erasing invalid data included in the bad block.

[0067] The memory controller 200 may control two or more memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operation performance.

[0068] The interleaving method may be a method of controlling operations of two or more memory devices 100 to overlap.

[0069] In an embodiment, in response to a test request of the host 400 , the memory controller 200 may provide a test command TCMD instructing to perform a test operation to the memory device 100 .

[0070] In an embodiment, in response to the memory device 1000 corresponding to end of life (EOL), the memory controller 200 may provide a test command TCMD to the memory device 100. Here, EOL may refer to a stage where the life of the memory device 1000 is close to end.

[0071] Based on the test data TDATA provided from the memory device 100 , the memory controller 200 may provide a control command (not shown) to the memory device 100 , the control command instructing to limit the operation of the page buffer 102 having the sense node detected as a defective sense node.

[0072] Although not shown, the storage device 1000 may further include a buffer memory. For example, the buffer memory may be implemented using any one of a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphic double data rate (GDDR) SDRAM, a low power DDR (LPDDR), and a Rambus dynamic random access memory (RDRAM).

[0073] The host 400 may communicate with the storage device 1000 through an interface (not shown).

[0074] The interface may be implemented with a Serial Advanced Technology Attachment (SATA) interface, a SATA express interface, a Serial Attached Small Computer System Interface (SAS) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Non-Volatile Memory Express (NVMe) interface, an Advanced Host Controller Interface (AHCI) or a Multimedia Card interface. However, the interface is not limited thereto.

[0075] The host 400 may communicate with the storage device 1000 to store write data in the storage device 1000 or obtain read data stored in the storage device 1000 .

[0076] In an embodiment, the host 400 may provide a write request to the storage device 1000 for requesting to store write data in the storage device 1000. In addition, the host 400 may provide the storage device 1000 with a write request, write data, and a logical address for identifying the write data.

[0077] The storage device 1000 may store write data provided by the host 400 in the memory device 100 in response to a write request provided from the host 400 , and provide a storage completion response to the host 400 .

[0078] In an embodiment, the host 400 may provide a read request to the storage device 1000 to request that the data stored in the storage device 1000 be provided to the host 400. In addition, the host 400 may provide the storage device 1000 with a read request and a read address.

[0079] The storage device 1000 may read read data corresponding to a read address provided by the host 400 from the memory device 100 in response to a read request provided from the host 400 , and provide the read data to the host 400 as a response to the read request.

[0080] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0081] Reference Figure 2 , the memory device 100 may include a memory cell array 110, a peripheral circuit 120, and a control logic 130. The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be a control logic circuit that operates according to an algorithm and / or a processor that executes control logic code.

[0082] Figure 2 The memory cell array 110 shown may be Figure 1 A memory cell array 101 is shown.

[0083] Figure 2 The illustrated memory cell array 110 may include a plurality of memory blocks MB1 to MBk (k is a positive integer). Here, the number of the plurality of memory blocks MB1 to MBk is merely an example for describing an embodiment of the present disclosure and is not limited thereto.

[0084] Each of the memory blocks MB1 to MBk may be connected to a local line LL and bit lines BL1 to BLn (n is a positive integer).

[0085] The local line LL may be connected to the row decoder 122 .

[0086] A local line LL may be connected to each of the memory blocks MB1 to MBk.

[0087] Although not shown, the local line LL may include a first selection line, a second selection line, and a plurality of word lines disposed between the first selection line and the second selection line.

[0088] Although not shown, the local line LL may further include a dummy line disposed between the first selection line and the word line, a dummy line disposed between the second selection line and the word line, and a pipe line.

[0089] The bit lines BL1 to BLn may be commonly connected to the memory blocks MB1 to MBk.

[0090] The memory blocks MB1 to MBk may be implemented as a two-dimensional or three-dimensional structure.

[0091] For example, in the memory blocks MB1 to MBk of a two-dimensional structure, memory cells may be arranged in a direction parallel to a substrate.

[0092] For example, in the memory blocks MB1 to MBk of a three-dimensional structure, memory cells may be stacked on a substrate in a vertical direction.

[0093] The peripheral circuit 120 may include a voltage generator 121 , a row decoder 122 , a page buffer group 123 , a column decoder 124 , an input / output circuit (I / O circuit) 125 , and a sensing circuit 126 .

[0094] The voltage generator 121 may generate various operation voltages Vop for programming, reading, and erasing operations in response to the operation command OP_CMD. In addition, the voltage generator 121 may selectively discharge the local line LL in response to the operation command OP_CMD. For example, the voltage generator 121 may generate a program voltage, a verification voltage, a pass voltage, a turn-on voltage, a read voltage, an erase voltage, a source line voltage, etc. under the control of the control logic 130.

[0095] As an embodiment, the voltage generator 121 may adjust an external power supply voltage to generate an internal power supply voltage. The internal power supply voltage generated by the voltage generator 121 is used as an operating voltage of the memory device 100.

[0096] As an embodiment, the voltage generator 121 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 121 may include a plurality of pumping capacitors receiving the internal power supply voltage, and may generate a plurality of voltages by selectively activating the plurality of pumping capacitors in response to the control of the control logic 130. The plurality of generated voltages may be provided to the memory cell array 110 by the row decoder 122.

[0097] As an embodiment, the voltage generator 121 may generate the first test voltage using an external power supply voltage in response to the control of the control logic 130 .

[0098] As an implementation, the level of the first test voltage may be higher than the voltage level of the internal power supply voltage.

[0099] As an embodiment, the voltage generator 121 may generate the second test voltage using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 121 may generate the test voltage based on the internal power supply voltage in response to the control of the control logic 130.

[0100] As an embodiment, the level of the second test voltage may be lower than the level of the first test voltage. For example, the level of the second test voltage may be ground. However, the present disclosure is not limited thereto.

[0101] Although not shown, the first test voltage or the second test voltage generated by the voltage generator 121 may be supplied to the page buffer group 123 .

[0102] The row decoder 122 may transmit the operating voltage Vop to the local line LL in response to the row address RADD. The operating voltage Vop may be transmitted to the selected memory blocks MB1 to MBk through the local line LL.

[0103] For example, during a program operation, the row decoder 122 may apply a program voltage to a selected word line and a program pass voltage having a level less than the program voltage to unselected word lines. During a program verification operation, the row decoder 122 may apply a verification voltage to a selected word line and a verification pass voltage greater than the verification voltage to unselected word lines.

[0104] During a read operation, the row decoder 122 may apply a read voltage to a selected word line and apply a read pass voltage greater than the read voltage to unselected word lines.

[0105] During an erase operation, the row decoder 122 may select a memory block according to a decoded address. During an erase operation, the row decoder 122 may apply a ground voltage to a word line connected to the selected memory block.

[0106] The page buffer group 123 may include first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn may be connected to the memory cell array 110 through first to nth bit lines BL1 to BLn, respectively. The first to nth page buffers PB1 to PBn may operate in response to the control of the control logic 130.

[0107] For example, the first to n-th page buffers PB1 to PBn may operate in response to the page buffer control signal PBSIGNALS. For example, the first to n-th page buffers PB1 to PBn may temporarily store data received through the first to n-th bit lines BL1 to BLn, or may sense voltages or currents of the bit lines BL1 to BLn during a read operation or a verification operation.

[0108] During a programming operation, when a programming voltage is applied to a selected word line, the first page buffer PB1 to the nth page buffer PBn may temporarily store data DATA received through the column decoder 124 and the input / output circuit 125 and transmit the data DATA to the selected memory cell through the first bit line BL1 to the nth bit line BLn. The memory cells of the selected page are programmed according to the transmitted data DATA. The memory cells connected to the bit lines to which a programming enable voltage (e.g., a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit lines to which a programming inhibit voltage (e.g., a power supply voltage) is applied may be maintained.

[0109] During a verification operation, the first to nth page buffers PB1 to PBn may sense data stored in selected memory cells through the first to nth bit lines BL1 to BLn and may temporarily store the data stored in the selected memory cells.

[0110] During a read operation, the first to nth page buffers PB1 to PBn may sense data DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn, temporarily store the sensed data DATA, and output the temporarily stored data DATA to the input / output circuit 125 under the control of the column decoder 124 .

[0111] During an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn.

[0112] As an embodiment, the first to nth page buffers PB1 to PBn may sequentially transmit the first and second test voltages output from the voltage generator 121 to the sensing nodes.

[0113] For example, the first to nth page buffers PB1 to PBn may transmit a first test voltage to the sensing node during a first period, and transmit a second test voltage to the sensing node during a second period after the first period.

[0114] As another example, the first to nth page buffers PB1 to PBn may transmit the second test voltage to the sensing node during a first period, and transmit the first test voltage to the sensing node during a second period after the first period.

[0115] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may exchange data with the page buffers PB1 to PBn through the data lines DL or may exchange data with the input / output circuit 125 through the column lines CL.

[0116] The input / output circuit 125 may transfer a command CMD and an address ADD received from the memory controller 200 to the control logic 130 , or may exchange data DATA with the column decoder 124 .

[0117] Reference Figure 1 and Figure 2 In an implementation, the input / output circuit 125 may transmit the test command TCMD output from the memory controller 200 to the control logic 130 .

[0118] During a read operation or a verification operation, the sensing circuit 126 may generate a reference current in response to an enable bit VRY_BIT<#> signal and compare a sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0119] The control logic 130 may output an operation command OP_CMD, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRY_BIT<#> in response to a command CMD and an address ADD to control the peripheral circuit 120 .

[0120] As an implementation, the control logic 130 may include Figure 1 The test executor 103 is shown.

[0121] Reference Figure 1 and Figure 2 As an embodiment, in response to a test command TCMD input from an external controller (e.g., the memory controller 200), the test executor 103 may control the voltage generator 121 to generate a first test voltage and a second test voltage. In addition, in response to the test command TCMD, the test executor 103 may control the page buffer to sequentially apply the first test voltage and the second test voltage to the sensing node of the page buffer (e.g., any one of the first to nth bit lines BL1 to BLn) through the bit line (e.g., any one of the first to nth bit lines BLn). In addition, the test executor 103 may detect a defect of the sensing node of the page buffer according to whether the potential level of the sensing node of the page buffer changes.

[0122] In an embodiment, each page buffer control signal PBSIGNALS for controlling the page buffer by the test executor 103 may include a bit line bias signal, a bit line selection signal, a bit line discharge signal, a sense node sense signal, a page buffer sense signal, a first control signal, a second control signal, a reset signal, a first set signal, a second set signal, etc., as will be described later with reference to Figure 4 As described.

[0123] Figure 3 is an example Figure 2 A diagram of the structure of any one of the multiple storage blocks shown.

[0124] Reference Figure 3 , Figure 3 The memory blocks MBi shown may be Figure 2 Any one of the storage blocks MB1 to MBk.

[0125] The memory block MBi may include a first selection line, a second selection line, a plurality of word lines WL1 to WL16 , a source line SL, a plurality of bit lines BL1 to BLn, and a plurality of strings ST.

[0126] The first selection line may be, for example, a source selection line SSL. Hereinafter, it is assumed that the first selection line is the source selection line SSL.

[0127] The second selection line may be, for example, a drain selection line DSL. Hereinafter, it is assumed that the second selection line is the drain selection line DSL.

[0128] A plurality of word lines WL1 to WL16 may be arranged in parallel between the source select line SSL and the drain select line DSL.

[0129] Figure 3 The number of word lines WL1 to WL16 shown is an example and is not limited to the number shown in the drawings.

[0130] The source lines SL may be commonly connected to the plurality of strings ST.

[0131] A plurality of bit lines BL1 to BLn may be connected to the strings ST, respectively.

[0132] A plurality of strings ST may be connected to bit lines BL1 to BLn and a source line SL.

[0133] Since the strings ST may be configured identically to each other, the string ST connected to the first bit line BL1 is described as an example.

[0134] The string ST may include a plurality of memory cells MC1 to MC16 , at least one first selection transistor, and at least one second selection transistor.

[0135] The plurality of memory cells MC1 to MC16 may be connected in series between the source select transistor SST and the drain select transistor DST.

[0136] Gate electrodes of the memory cells MC1 to MC16 may be connected to the plurality of word lines WL1 to WL16 , respectively. Therefore, the number of memory cells MC1 to MC16 included in one string ST may be the same as the number of word lines WL1 to WL16 .

[0137] Any one of the plurality of memory cells MC1 to MC16 may be configured by any one of SLC, MLC, TLC, and QLC.

[0138] A group of memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a physical page PG. Therefore, the memory block MBi may include a physical page PG corresponding to the number of word lines WL1 to WL16. Hereinafter, it is assumed that the memory cell (e.g., MC3) included in the physical page PG is a selected memory cell.

[0139] The first selection transistor may be, for example, a source selection transistor SST. Hereinafter, it is assumed that the first selection transistor is a source selection transistor SST.

[0140] A first electrode of the source select transistor SST may be connected to a source line SL. A second electrode of the source select transistor SST may be connected to a first memory cell MC1 among a plurality of memory cells MC1 to MC16. A gate electrode of the source select transistor SST may be connected to a source select line SSL.

[0141] The second selection transistor may be, for example, a drain selection transistor DST. Hereinafter, it is assumed that the second selection transistor is the drain selection transistor DST.

[0142] A first electrode of the drain select transistor DST may be connected to a sixteenth memory cell MC16 among the plurality of memory cells MC1 to MC16. A second electrode of the drain select transistor DST may be connected to a first bit line BL1. A gate electrode of the drain select transistor DST may be connected to a drain select line DSL.

[0143] Figure 4 is a diagram illustrating a page buffer according to an embodiment of the present disclosure.

[0144] Reference Figure 4 , the page buffer 300 may be Figure 1 The page buffer 102 shown, or Figure 2 Any one of the first to nth page buffers PB1 to PBn shown.

[0145] Figure 4 The illustrated page buffer 300 may include a test voltage transfer component 310 , a sense node connector 320 , and a sense latch 330 .

[0146] The test voltage transfer component 310 may transfer the first test voltage VEXT or the second test voltage to the sensing node SO.

[0147] Here, the level of the second test voltage may be lower than the level of the first test voltage VEXT. For example, the second test voltage may be ground. However, the present disclosure is not limited thereto. In the following, for ease of description, it is assumed that the second test voltage is ground.

[0148] For example, the test executor 103 provides the bit line selection signal SEL_BL to the test voltage transfer component 310. Here, the bit line selection signal SEL_BL may be a signal that electrically connects the page buffer 300 to be tested among the plurality of page buffers and the bit line BL.

[0149] The test executor 103 may sequentially provide a bit line bias signal BL_BIAS and a bit line discharge signal BLDIS to the test voltage transfer component 310. Here, the bit line bias signal BL_BIAS may be a signal indicating that a first test voltage VEXT is applied to the sensing node SO, and the bit line discharge signal BLDIS may be a signal indicating that a second test voltage is applied to the sensing node SO.

[0150] The test voltage transfer component 310 may provide a first test voltage VEXT to the bit line BL in response to the bit line bias signal BL_BIAS. The test voltage transfer component 310 may provide a second test voltage to the bit line BL in response to the bit line discharge signal BLDIS.

[0151] In an implementation, the test voltage transfer component 310 may include first to third transistors N1 to N3 .

[0152] The first transistor N1 may be turned on in response to a bit line bias signal BL_BIAS. The bit line bias signal BL_BIAS may be applied to a gate electrode of the first transistor N1, a first test voltage VEXT may be applied to a first electrode of the first transistor N1, and a second electrode of the first transistor N1 may be connected to the bit line BL. The first transistor N1 may be referred to as a bias transistor.

[0153] The second transistor N2 may be turned on in response to a bit line selection signal SEL_BL. The bit line selection signal SEL_BL may be applied to a gate electrode of the second transistor N2, a first electrode of the second transistor N2 may be connected to the bit line BL, and a second electrode of the second transistor N2 may be connected to a first electrode of the third transistor N3.

[0154] The third transistor N3 may be turned on in response to a bit line discharge signal BLDIS. The bit line discharge signal BLDIS may be applied to a gate electrode of the third transistor N3, a first electrode of the third transistor N3 may be connected to a second electrode of the second transistor N2, and a second test voltage may be applied to a second electrode of the third transistor N3. In an embodiment, a second electrode of the third transistor N3 may be connected to ground. The third transistor N3 may be referred to as a discharge transistor.

[0155] Although not shown, the signal line through which the bit line bias signal BL_BIAS flows and the signal line through which the bit line discharge signal BLDIS flows may be provided on different layers. Since the signal line through which the bit line bias signal BL_BIAS flows and the signal line through which the bit line discharge signal BLDIS flows are stacked on different layers, it is possible to check whether the sensing node SO is defective by changing the potential of the sensing node SO without providing data to the page buffer 300.

[0156] In an implementation, the test executor 103 may provide a connection signal indicating to connect the bit line BL and the sense node SO to the sense node connector 320. Here, the connection signal may include, for example, a page buffer sense signal PBSENSE and a sense node sense signal SA_SENSE.

[0157] The sense node connector 320 may electrically connect the bit line BL and the sense node SO. For example, the sense node connector 320 may electrically connect the bit line BL, the common sense node CSO, and the sense node SO in response to the page buffer sense signal PBSENSE and the sense node sense signal SA_SENSE.

[0158] The sensing node connector 320 may include fourth to ninth transistors N4 to N9 .

[0159] The fourth transistor N4 may be turned on in response to the page buffer sensing signal PBSENSE. The page buffer sensing signal PBSENSE may be applied to a gate electrode of the fourth transistor N4, a first electrode of the fourth transistor N4 may be connected to the test voltage transfer component 310, and a second electrode of the fourth transistor N4 may be connected to the common sensing node CSO.

[0160] As an embodiment, a first electrode of the fourth transistor N4 may be connected to a node electrically connected to the second electrode of the second transistor N2 and the first electrode of the third transistor N3 .

[0161] The fifth transistor N5 may be turned on in response to a sense node sense signal SA_SENSE applied to a gate electrode of the fifth transistor N5, a first electrode of the fifth transistor N5 may be connected to the sense node SO, and a second electrode of the fifth transistor N5 may be connected to the common sense node CSO.

[0162] The sixth transistor N6 may be turned on in response to a sense node precharge signal SA_PRECH_N. The sense node precharge signal SA_PRECH_N may be applied to a gate electrode of the sixth transistor N6, a first electrode of the sixth transistor N6 may be connected to a common sense node CSO, and a second electrode of the sixth transistor N6 may be connected to a first electrode of the seventh transistor N7, a second electrode of the eighth transistor N8, and a first electrode of the ninth transistor N9.

[0163] The seventh transistor N7 may be turned on according to the potential level of the first latch node QS of the sensing latch 330. The gate electrode of the seventh transistor N7 may be connected to the first latch node QS, the first electrode of the seventh transistor N7 may be connected to the second electrode of the sixth transistor N6 and the second electrode of the eighth transistor N8, and the core voltage VCORE may be applied to the second electrode of the seventh transistor N7. The core voltage VCORE may be the above reference Figure 2 Describes the internal supply voltage.

[0164] The eighth transistor N8 may be turned on in response to a first control signal SA_PRE_N. The first control signal SA_PRE_N may be input to a gate electrode of the eighth transistor N8, a core voltage VCORE may be applied to a first electrode of the eighth transistor N8, and a second electrode of the eighth transistor N8 may be connected to a second electrode of the sixth transistor N6, a first electrode of the seventh transistor N7, and a first electrode of the ninth transistor N9.

[0165] The ninth transistor N9 may be turned on in response to the second control signal SA_CSOC. The second control signal SA_CSOC may be input to the gate electrode of the ninth transistor N9, a first electrode of the ninth transistor N9 may be connected to the second electrode of the sixth transistor N6, the first electrode of the seventh transistor N7, and the second electrode of the eighth transistor N8, and a second electrode of the ninth transistor N9 may be connected to the common sensing node CSO.

[0166] The sense latch 330 may latch a sense value corresponding to a potential level of the sense node SO and provide the sense value to the test executor 103 .

[0167] The sensing latch may include inverters IV1 and IV2 and tenth to thirteenth transistors N10 to N13 .

[0168] Inverters IV1 and IV2 may be connected in anti-parallel between the first latch node QS and the second latch node QS_N.

[0169] The tenth transistor N10 and the eleventh transistor N11 may be connected in series between the first latch node QS and the ground. The tenth transistor N10 may be turned on in response to the reset signal SRST, and the eleventh transistor N11 may be turned on in response to the first set signal PBSET. When the tenth transistor N10 and the eleventh transistor N11 are turned on, the first latch node QS and the ground may be electrically connected.

[0170] For example, in a state where the sensing node SO is precharged to a first level (e.g., a high level), when the reset signal SRST is input to the tenth transistor N10 and the first set signal PBSET is input to the eleventh transistor N11, the first latch node QS may be initialized to a second level (e.g., a low level) lower than the first level, and the second latch node QS_N may be initialized to the first level.

[0171] The twelfth transistor N12 and the thirteenth transistor N13 may be connected in series between the second latch node QS_N and the ground. The twelfth transistor N12 may be turned on according to the potential level of the sensing node SO, and the thirteenth transistor N13 may be turned on in response to the second set signal SSET. When the twelfth transistor N12 and the thirteenth transistor N13 are turned on, the second latch node QS_N and the ground may be electrically connected.

[0172] For example, in a state where the sensing node SO is precharged to a first level (e.g., a high level), when the second set signal SSET is applied to the thirteenth transistor N13, the first latch node QS may be set to a first level and the second latch node QS_N may be set to a second level (e.g., a low level) lower than the first level.

[0173] The input of the above-mentioned control signals BL_BIAS, SEL_BL, BLDIS, PBSENSE, SA_CSOC, SA_PRE_N, SA_PRECH_N, SA_SENSE, SA_DISCH, SRST, PBSET and SSET to transistors N1 to N13 may mean inputting control signals of conduction levels to transistors N1 to N13 according to preset timing. The word "preset" as used herein with respect to a parameter (such as preset timing and preset reference level) refers to determining the value of the parameter before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm starts. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0174] That the above control signals BL_BIAS, SEL_BL, BLDIS, PBSENSE, SA_CSOC, SA_PRE_N, SA_PRECH_N, SA_SENSE, SA_DISCH, SRST, PBSET, and SSET are not input to the transistors N1 to N13 may mean that control signals of a turn-off level are input to the transistors N1 to N13 according to preset timing.

[0175] Figure 5 It is an example Figure 4 FIG. 1 is a diagram showing an embodiment of applying a first test voltage to a sensing node of a page buffer, Figure 6 It is an example Figure 4 FIG. 1 is a diagram of an embodiment in which a second test voltage is applied to a sensing node of a page buffer, and Figure 7 is a diagram schematically illustrating signal waveforms of control signals for applying a first test voltage and a second test voltage to a sensing node.

[0176] Reference Figure 1 , Figure 2 and Figure 5 , the test executor 103 may input the bit line bias signal BL_BIAS, the bit line selection signal SEL_BL, the page buffer sense signal PBSENSE, and the sense node sense signal SA_SENSE to the first transistor N1, the second transistor N2, the fourth transistor N4, and the fifth transistor N5, so that the first test voltage VEXT is applied to the sense node SO. Therefore, the first transistor N1, the second transistor N2, the fourth transistor N4, and the fifth transistor N5 may be turned on, and the third transistor N3 and the sixth transistor N6 to the ninth transistor N9 may be turned off. In this case, a first path electrically connecting the first transistor N1, the bit line BL, the second transistor N2, the fourth transistor N4, the common sense node CSO, and the fifth transistor N5 may be formed, and the first path (i.e., Figure 5 A first test voltage is applied to the sensing node SO (shown by a dotted line).

[0177] In an embodiment, in response to the bias transistor (e.g., the first transistor N1) being turned on and the discharge transistor (e.g., the third transistor N3) being turned off, the potential level of the sensing node SO may be changed from the second level (e.g., the low level) to the first level (e.g., the high level).

[0178] Reference Figure 7At the first time point t1, the bit line bias signal BL_BIAS, the bit line selection signal SEL_BL, the page buffer sense signal PBSENSE, and the sense node sense signal SA_SENSE may be changed from the second level (e.g., a low level Low) to the first level (e.g., a high level High). At the first time point t1, the bit line discharge signal BLDIS may be changed from the first level to the second level.

[0179] During a first period corresponding to a period from a first time point t1 to a second time point t2, a bit line bias signal BL_BIAS, a bit line selection signal SEL_BL, a page buffer sense signal PBSENSE, and a sense node sense signal SA_SENSE may maintain a first level, and a bit line discharge signal BLDIS may maintain a second level. A first test voltage VEXT may be applied to the sense node SO during the first period.

[0180] Reference Figure 1 , Figure 2 and Figure 6 , the test executor 103 may input a bit line selection signal SEL_BL, a bit line discharge signal BLDIS, a page buffer sense signal PBSENSE, and a sense node sense signal SA_SENSE to the second transistor N2 to the fifth transistor N5, so that a second test voltage (e.g., ground) is applied to the sense node SO. Therefore, the second transistor N2 to the fifth transistor N5 may be turned on, and the first transistor N1 and the sixth transistor N6 to the ninth transistor N9 may be turned off. In this case, a second path electrically connecting the bit line BL, the second transistor N2, the third transistor N3, the fourth transistor N4, the common sense node CSO, and the fifth transistor N5 may be formed, and a second test voltage may be applied to the sense node SO through the second path.

[0181] Reference Figure 7 At the second time point t2, the bit line bias signal BL_BIAS may be changed from the first level (e.g., high level High) to the second level (e.g., low level Low). At the second time point t2, the bit line discharge signal BLDIS may be changed from the second level to the first level. The bit line selection signal SEL_BL, the page buffer sense signal PBSENSE, and the sense node sense signal SA_SENSE may be the first level.

[0182] During a second period corresponding to a period from the second time point t2 to the third time point t3, the bit line bias signal BL_BIAS may maintain a second level, and the bit line selection signal SEL_BL, the page buffer sense signal PBSENSE, the sense node sense signal SA_SENSE, and the bit line discharge signal BLDIS may maintain a first level. A second test voltage may be applied to the sense node SO during the second period.

[0183] In an embodiment, in response to the bias transistor (e.g., the first transistor N1) being turned off and the discharge transistor (e.g., the third transistor N3) being turned on, the potential level of the sensing node SO may be changed from a first level (e.g., a high level) to a second level (e.g., a low level).

[0184] like Figure 1 , Figure 2 and Figure 7 As shown, the test executor 103 may apply a first test voltage VEXT to the sensing node SO during a first period corresponding to the first time point t1 to the second time point t2, and apply a second test voltage to the sensing node SO during a second period corresponding to the second time point t2 to the third time point t3. However, the present disclosure is not limited thereto.

[0185] Although not shown, the test executor 103 may apply a second test voltage to the sensing node SO during a first period corresponding to a period from the first time point t1 to the second time point t2, and apply the first test voltage VEXT to the sensing node SO during a second period corresponding to a period from the second time point t2 to the third time point t3.

[0186] Similarly, if Figure 7 As shown, during a first period corresponding to a period from a first time point t1 to a second time point t2, a first level bit line bias signal BL_BIAS and a second level bit line discharge signal BLDIS may be input to the test voltage transfer component 310. During a second period corresponding to a period from a second time point t2 to a third time point t3, a second level bit line bias signal BL_BIAS and a first level bit line discharge signal BLDIS may be input to the test voltage transfer component 310. However, the present disclosure is not limited thereto.

[0187] For example, the test executor 103 may provide the bit line discharge signal BLDIS of the first level to the test voltage transfer component 310 after providing the bit line bias signal BL_BIAS of the first level to the test voltage transfer component 310 .

[0188] Although not shown, during the first period, the second level bit line bias signal BL_BIAS and the first level bit line discharge signal BLDIS may be input to the test voltage transfer component 310, and during the second period, the first level bit line bias signal BL_BIAS and the second level bit line discharge signal BLDIS may be input to the test voltage transfer component 310.

[0189] For example, the test executor 103 may provide the bit line bias signal BL_BIAS of the first level to the test voltage transfer component 310 after providing the bit line discharge signal BLDIS of the first level to the test voltage transfer component 310 .

[0190] Figure 8 This is an example detection Figure 4 FIG. 1 is a diagram of an embodiment of a defect in a sensing node of a page buffer.

[0191] Reference Figure 4 and Figure 8 , the test executor 103 may perform a precharge operation of changing a potential level of the sensing node SO from a second level (eg, a low level) to a first level (eg, a high level) after applying the first test voltage VEXT and the second test voltage to the sensing node SO.

[0192] Reference Figure 4 and Figure 8 For example, at the first time point t1, the bit line bias signal BL_BIAS, the bit line selection signal SEL_BL, the page buffer sense signal PBSENSE, and the sense node sense signal SA_SENSE may be changed from the second level to the first level. The bit line discharge signal BLDIS may be changed from the first level to the second level. In this case, the potential level of the sense node SO may be increased by the first test voltage VEXT.

[0193] At the second time point t2, the bit line bias signal BL_BIAS may be changed from the first level to the second level. The bit line selection signal SEL_BL, the page buffer sensing signal PBSENSE, and the sensing node sensing signal SA_SENSE may maintain the first level. The bit line discharge signal BLDIS may maintain the second level. In addition, the potential level of the sensing node SO may be changed from the second level to the first level. That is, the sensing node SO may be precharged to the first level.

[0194] During a period from the first time point t1 to the third time point t3 , the bit line selection signal SEL_BL, the page buffer sense signal PBSENSE, and the sense node sense signal SA_SENSE may maintain the first level, and the bit line discharge signal BLDIS may maintain the second level.

[0195] After the sensing node SO is precharged, the test executor 103 may detect a defect of the sensing node SO in response to a potential level of the sensing node SO being changed from the first level to be less than a preset reference level by using a sensing value of the sensing latch 330 .

[0196] At the third time point t3, the bit line selection signal SEL_BL, the page buffer sensing signal PBSENSE, and the sensing node sensing signal SA_SENSE may be changed from the first level to the second level. The bit line discharge signal BLDIS may be changed from the second level to the first level. Here, when the potential level of the sensing node SO is maintained at the first level, the state of the sensing node SO may be detected as a normal state Normal. When the potential level of the sensing node SO decreases from the first level and the potential level of the sensing node SO is less than the reference level, the state of the sensing node SO may be detected as a defective state Defect.

[0197] Fig. 9 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0198] Reference Figure 1 and Fig. 9 , the memory device 100 sequentially applies a first test voltage and a second test voltage ( S110 ).

[0199] For example, the test executor 103 may sequentially apply a first test voltage and a second test voltage to the sensing node of the page buffer 102 through the bit line.

[0200] For example, the test executor 103 may provide the page buffer 102 with a bit line bias signal indicating application of a first test voltage to the sense node, and may apply a bit line discharge signal indicating application of a second test voltage to the sense node to the page buffer 102 after providing the bit line bias signal.

[0201] As another example, the test executor 103 may provide the page buffer 102 with a bit line discharge signal indicating application of the second test voltage to the sense node, and may apply a bit line bias signal indicating application of the first test voltage to the sense node to the page buffer 102 after providing the bit line discharge signal.

[0202] In an implementation, as the first test voltage is applied, the potential level of the sensing node may be changed from the second level to the first level.

[0203] In an implementation, as the second test voltage is applied, the potential level of the sensing node may be changed to a second level lower than the first level.

[0204] The memory device 100 performs a precharge operation so that the potential of the sensing node becomes logic high ( S120 ).

[0205] For example, after applying the first test voltage and the second test voltage to the sensing node, the test executor 103 may perform a precharge operation of changing the potential level of the sensing node from the second level to a first level higher than the second level.

[0206] The memory device 100 senses a potential level of the sensing node ( S130 ), and determines whether the potential level of the sensing node is less than a preset reference level ( S140 ).

[0207] For example, the test executor 103 may change the bit line selection signal, the page buffer sensing signal, and the sensing node sensing signal from the first level to the second level at a specific time point, and may change the bit line discharge signal from the first level to the second level. In this case, the potential level of the sensing node may be maintained at the first level or decreased from the first level.

[0208] When the potential level of the sensing node is less than the reference level ( S140 , Yes), the memory device 100 determines that the sensing node is defective ( S150 ).

[0209] When the potential level of the sensing node is equal to or greater than the reference level ( S140 , No), the memory device 100 determines that the sensing node is normal ( S160 ).

[0210] Fig.10 is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0211] Reference Figure 1 and Fig.10 , the memory controller 200 may include a processor 210 , a RAM 220 , an error correction circuit 230 , a ROM 260 , a host interface 270 , and a flash memory interface 280 .

[0212] The processor 210 may control the overall operation of the memory controller 200 .

[0213] The RAM 220 may be used as a buffer memory, a cache memory, an operation memory, etc. of the memory controller 200. For example, the buffer memory may be the RAM 220, and in an embodiment, the buffer memory may be an SRAM.

[0214] The ROM 260 may store various information necessary for the memory controller 200 to operate in the form of firmware.

[0215] The memory controller 200 may communicate with an external device (eg, the host 400 , an application processor, etc.) through the host interface 270 .

[0216] The memory controller 200 may communicate with the memory device 100 through the flash interface 280. The memory controller 200 may transmit a command CMD, an address ADDR, a control signal CTRL, etc. to the memory device 100 through the flash interface 280 and receive data DATA.

[0217] For example, flash memory interface 280 may include a NAND interface.

[0218] Fig.11 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0219] Reference Figure 1 and Fig.11 , the memory card system 2000 includes a memory device 2100 , a memory controller 2200 , and a connector 2300 .

[0220] For example, the memory device 2100 may be composed of various nonvolatile memory elements such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0221] The memory controller 2200 is connected to the memory device 2100. The memory controller 2200 is configured to access the memory device 2100. For example, the memory controller 2200 may be configured to control a read operation, a write operation, an erase operation, and a background operation of the memory device 2100. The memory controller 2200 is configured to provide an interface between the memory device 2100 and the host 400. The memory controller 2200 is configured to drive firmware for controlling the memory device 2100. The memory controller 2200 may be connected to the memory device 2100 with reference to Figure 1 The memory controller 200 described is implemented identically.

[0222] For example, the memory controller 2200 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error correction circuit.

[0223] The memory controller 2200 may communicate with an external device through the connector 2300. The memory controller 2200 may communicate with an external device (e.g., the host 400) according to a specific communication standard. For example, the memory controller 2200 is configured to communicate with an external device through at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 may be defined by at least one of the various communication standards described above.

[0224] The memory device 2100 and the memory controller 2200 may be integrated into one semiconductor device to construct a memory card. For example, the memory controller 2200 and the memory device 2100 may be integrated into one semiconductor device to construct a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, Micro MMC or eMMC), an SD card (SD, Mini SD, Micro SD or SDHC), and a Universal Flash Storage (UFS).

[0225] Fig.12 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0226] Reference Figure 1 and Fig.12 , the SSD system includes a host 400 and an SSD 3000 .

[0227] The SSD 3000 exchanges a signal SIG with the host 400 through a signal connector 3001 and receives power PWR through a power connector 3002. The SSD 3000 includes an SSD controller 3200, a plurality of flash memories 3100_1, 3100_2, and 3100_n, an auxiliary power device 3300, and a buffer memory 3400.

[0228] According to an embodiment of the present disclosure, the SSD controller 3200 may execute a reference Figure 1 The functions of the memory controller 200 are described.

[0229] The SSD controller 3200 may control the plurality of flash memories 3100_1, 3100_2, and 3100_n in response to a signal SIG received from the host 400. For example, the signal SIG may be a signal based on an interface between the host 400 and the SSD 3000. For example, the signal SIG may be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI-Express (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0230] The auxiliary power supply device 3300 is connected to the host 400 through the power connector 3002. The auxiliary power supply device 3300 can receive the power PWR from the host 400 and can charge the power. When the power from the host 400 is not stable, the auxiliary power supply device 3300 can provide the power of the SSD 3000. For example, the auxiliary power supply device 3300 can be located in the SSD 3000 or can be located outside the SSD 3000. For example, the auxiliary power supply device 3300 can be located on the mainboard and can provide auxiliary power to the SSD 3000.

[0231] The buffer memory 3400 may temporarily store data. For example, the buffer memory 3400 may temporarily store data received from the host 400 or data received from the plurality of flash memories 3100_1, 3100_2, and 3100_n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3100_1, 3100_2, and 3100_n. The buffer memory 3400 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0232] Fig.13 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied.

[0233] Reference Fig.13 , the user system 4000 includes an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 and a user interface 4500 .

[0234] The application processor 4100 may drive components included in the user system 4000, an operating system (OS), a user program, etc. For example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. that control components included in the application processor 4100. The application processor 4100 may be provided as a system on chip (SoC).

[0235] The memory module 4200 may be used as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a package-on-package (POP) and provided as one semiconductor package.

[0236] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 4300 may be included in the application processor 4100.

[0237] The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100. Alternatively, the storage module 4400 may send the data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 may be implemented with a non-volatile semiconductor memory element such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, and a three-dimensional NAND flash memory. For example, the storage module 4400 may be provided as an external drive of the user system 4000 and a removable storage device (removable drive) such as a memory card.

[0238] For example, the storage module 4400 may be associated with a reference Figure 1 The storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may be the same as those described in reference 1. Figure 1 The described memory device 100 operates identically.

[0239] The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 4500 may include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0240] CROSS-REFERENCE TO RELATED APPLICATIONS

[0241] This application claims the priority of Korean Patent Application No. 10-2020-0117889 filed on September 14, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, the memory device comprising: a memory cell connected to a bit line; a page buffer storing data to be stored in the memory cell; as well as a test executor that controls the page buffer to sequentially apply a first test voltage and a second test voltage having a level lower than the first test voltage to a sensing node of the page buffer through the bit line, and detects a defect of the sensing node according to whether a potential level of the sensing node changes, Wherein, the page buffer comprises: a test voltage transmitting component, the test voltage transmitting component transmitting the first test voltage or the second test voltage to the sensing node; a sensing node connector that electrically connects the bit line and the sensing node; and a sense latch that latches a sense value corresponding to the potential level of the sense node and provides the sense value to the test executor, and wherein the test executor performs a precharge operation after applying the first test voltage and the second test voltage to the sensing node, the precharge operation changes the potential level of the sensing node from the second level to a first level higher than the second level, and detects a defect of the sensing node in response to the potential level of the sensing node changing from the first level to less than a preset reference level.

2. The memory device according to claim 1, wherein: In response to a test command input from an external controller, the test executor controls the page buffer to sequentially apply the first test voltage and the second test voltage whose level is lower than the first test voltage to the sensing node of the page buffer through the bit line, and detects a defect of the sensing node based on whether the potential level of the sensing node changes.

3. The memory device according to claim 1, wherein: The test executor sequentially provides a bit line bias signal to the page buffer to apply the first test voltage to the sense node and provides a bit line discharge signal to the page buffer to apply the second test voltage to the sense node.

4. The memory device according to claim 3, wherein: The test executor provides the bit line bias signal to the test voltage transfer component and then provides the bit line discharge signal to the test voltage transfer component.

5. The memory device according to claim 3, wherein: The test executor provides the bit line discharge signal to the test voltage transfer component and then provides the bit line bias signal to the test voltage transfer component.

6. The memory device according to claim 3, wherein: The test voltage transfer component provides the first test voltage to the bit line in response to the bit line bias signal, and provides the second test voltage to the bit line in response to the bit line discharge signal.

7. The memory device according to claim 6, wherein: The test voltage transmission component comprises: a bias transistor that is turned on in response to the bit line bias signal; and A discharge transistor is turned on in response to the bit line discharge signal.

8. The memory device according to claim 7, wherein: The potential level of the sensing node changes to the first level in response to turning on the bias transistor and turning off the discharge transistor, and changes to the second level lower than the first level in response to turning off the bias transistor and turning on the discharge transistor.

9. The memory device according to claim 1, wherein: The test executor provides a connection signal to the sensing node connector to connect the bit line and the sensing node.

10. A method of operating a memory device, the method comprising the steps of: sequentially applying a first test voltage and a second test voltage having a level lower than that of the first test voltage to a sensing node of the page buffer through a bit line; as well as detecting a defect of the sensing node according to whether the potential level of the sensing node changes to be less than a preset reference level, The step of detecting defects of the sensing node comprises the following steps: After applying the first test voltage and the second test voltage to the sensing node, performing a precharge operation of changing the potential level of the sensing node from a second level to a first level higher than the second level; and A defect of the sensing node is detected in response to the potential level of the sensing node being changed from the first level to be less than the preset reference level.

11. The method according to claim 10, wherein: The step of applying the first test voltage and the second test voltage to the sensing node comprises the following steps: providing a bit line bias signal to the page buffer to apply the first test voltage to the sensing node of the page buffer; and After the bit line bias signal is provided, a bit line discharge signal is provided to the page buffer to apply the second test voltage to the sensing node of the page buffer.

12. The method according to claim 10, wherein: The step of applying the first test voltage and the second test voltage to the sensing node comprises the following steps: providing a bit line discharge signal to the page buffer to apply the second test voltage to the sensing node of the page buffer; and After the bit line discharge signal is provided, a bit line bias signal is provided to the page buffer to apply the first test voltage to the sensing node of the page buffer.

13. The method according to claim 10, wherein: The potential level of the sensing node is changed to the first level as the first test voltage is applied, and is changed to the second level lower than the first level as the second test voltage is applied.

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