Semiconductor device and method of manufacturing the same

Abstract

The present application provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a substrate, the substrate comprising a first region, a second region, a third region and a fourth region; forming a pad oxide layer on the substrate; forming a pad nitride layer on the pad oxide layer; removing the pad oxide layer and the pad nitride layer of the first region and the second region to expose the top surface of the substrate; forming a first isolation structure and a second isolation structure in the first region and the second region respectively; removing the pad oxide layer and the pad nitride layer of the third region and the fourth region to expose the top surface; and forming a third isolation structure and a fourth isolation structure in the third region and the fourth region respectively, and increasing the thickness of the first isolation structure and the second isolation structure simultaneously. The present application can control the breakdown voltage and the on-resistance of each element in the same process, so as to reduce the wafer area occupied by the circuit and reduce the production cost.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device and a manufacturing method thereof for simultaneously forming four different isolation structures. BACKGROUND

[0002] Lateral Diffused Metal Oxide Semiconductor (LDMOS) and High Voltage Metal Oxide Semiconductor (HVMOS) are two typical high voltage devices which can be integrated with CMOS process to fabricate control, logic and power switches on a single wafer. LDMOS and HVMOS must have high breakdown voltage and low on-state resistance (Ron) when operating, so that the devices have low power loss when used in high voltage applications. Moreover, lower on-state resistance can make the transistors have higher drain current in saturation state to increase the operating speed of the devices.

[0003] However, not all devices in a circuit have the same voltage value and on-state resistance. In addition, the breakdown voltage is related to the area occupied by the device. In order to effectively reduce the area occupied by the circuit, it is necessary to realize devices with different breakdown voltages and different on-state resistances in the same process. SUMMARY

[0004] Therefore, the present application provides a manufacturing method of a semiconductor device, comprising the following steps: providing a substrate, the substrate comprising a first region, a second region, a third region and a fourth region; forming a pad oxide layer on the substrate; forming a pad nitride layer on the pad oxide layer; removing the pad oxide layer and the pad nitride layer of the first region and the second region to expose a top surface of the substrate; forming a first isolation structure and a second isolation structure in the first region and the second region, respectively; after the step of forming the first isolation structure and the second isolation structure in the first region and the second region, respectively, removing the pad oxide layer and the pad nitride layer of the third region and the fourth region to expose the top surface; and forming a third isolation structure and a fourth isolation structure in the third region and the fourth region, respectively, and simultaneously increasing the thickness of the first isolation structure and the second isolation structure.

[0005] According to an embodiment of the present application, the first isolation structure has a first thickness, the second isolation structure has a second thickness, the third isolation structure has a third thickness, and the fourth isolation structure has a fourth thickness, wherein the first thickness is equal to the second thickness, the third thickness is equal to the fourth thickness, and the first thickness is greater than the third thickness.

[0006] According to an embodiment of the present application, the method for manufacturing a semiconductor device further comprises performing the removing step to remove both sides of the second isolation structure and the fourth isolation structure to achieve sufficient isolation width between elements while leaving the bottom surface of the second isolation structure and the fourth isolation structure substantially coplanar with the top surface of the substrate.

[0007] According to an embodiment of the present application, the step of performing the removing step to remove both sides of the second isolation structure and the fourth isolation structure further comprises covering the first isolation structure, the second isolation structure, the third isolation structure, and the fourth isolation structure with a plurality of photoresist layers and exposing both sides of the second isolation structure and the fourth isolation structure; removing both sides of the second isolation structure and the fourth isolation structure; and removing the photoresist layers.

[0008] According to an embodiment of the present application, the width of the second region and the fourth region is greater than the width of the first region and the third region.

[0009] According to an embodiment of the present application, the angle between the sidewall of at least one side of the second isolation structure and the fourth isolation structure and the top surface is a right angle or an obtuse angle.

[0010] According to an embodiment of the present application, the method for manufacturing a semiconductor device further comprises performing the removing step to remove the pad oxide layer and the pad nitride layer on the substrate before the step of performing the removing step to remove both sides of the second isolation structure and the fourth isolation structure.

[0011] According to an embodiment of the present application, the method for manufacturing a semiconductor device further comprises forming a plurality of high voltage elements that are different from each other. The first isolation structure, the second isolation structure, the third isolation structure, and the fourth isolation structure are each a drift oxide layer of the high voltage elements to control the breakdown voltage and the on-resistance of the high voltage elements in the same process.

[0012] The present application further provides a semiconductor device, which includes a substrate, a first isolation structure, a second isolation structure, a third isolation structure, and a fourth isolation structure. The substrate has a top surface. The first isolation structure is formed on the substrate and has a first thickness. The second isolation structure is formed on the substrate and has a second thickness, wherein at least a portion of the second isolation structure has a bottom surface substantially coplanar with the top surface. The third isolation structure is formed on the substrate and has a third thickness. The fourth isolation structure is formed on the substrate and has a fourth thickness, wherein at least a portion of the fourth isolation structure has a bottom surface substantially coplanar with the top surface. The first thickness is equal to the second thickness, the third thickness is equal to the fourth thickness, and the first thickness is greater than the third thickness.

[0013] According to an embodiment of the present application, the semiconductor device further includes a plurality of high-voltage elements. The first isolation structure, the second isolation structure, the third isolation structure, and the fourth isolation structure are each a drift oxide layer of the high-voltage elements.

[0014] The present application provides a method for manufacturing a semiconductor device, so that isolation structures with different thicknesses and shapes can be realized in the same process, which can be used as drift regions of different high-voltage elements, thereby controlling the breakdown voltage and on-resistance of each element in the same process, so as to reduce the wafer area occupied by the circuit and reduce the production cost. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figures 1A-1H is a cross-sectional schematic view showing a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0016] REFERENCE NUMERALS:

[0017] 10: substrate

[0018] 11: pad oxide layer

[0019] 12: pad nitride layer

[0020] 110: first region

[0021] 120: second region

[0022] 130: third region

[0023] 140: fourth region

[0024] 111: first isolation structure

[0025] 121: second isolation structure

[0026] 131: third isolation structure

[0027] 141: fourth isolation structure

[0028] 121A: first bottom surface

[0029] 121B: first sidewall

[0030] 121C: second sidewall

[0031] 121X: first left portion

[0032] 121Y: first right portion

[0033] 121Z: first central portion

[0034] 141A: second bottom surface

[0035] 141B: third sidewall

[0036] 141C: fourth sidewall

[0037] 141X: second left portion

[0038] 141Y: second right portion

[0039] 141Z: second central portion

[0040] 151: first photoresist layer

[0041] 152: second photoresist layer

[0042] 153: third photoresist layer

[0043] 10A-1: first top surface

[0044] 10A-2: second top surface

[0045] 10A-3: third top surface

[0046] 10A-4: fourth top surface

[0047] L1: first width

[0048] L2: second width

[0049] L3: third width

[0050] L4: fourth width

[0051] T1: first thickness

[0052] T2: second thickness

[0053] T3: third thickness

[0054] α: first included angle

[0055] β: second included angle

[0056] G: third included angle

[0057] G: fourth included angle DETAILED DESCRIPTION

[0058] Embodiments of a substrate, a semiconductor device, and a method of manufacturing a semiconductor device are described herein. It is to be understood that the following description provides many different embodiments or examples for implementing different aspects, embodiments or examples of various aspects of the embodiments. Other embodiments can be utilized, and structural, and operational (for example, component parts) changes can be made without departing from the scope of the present embodiments. The specific embodiments given herein are representative of the various aspects of the embodiments. The scope of the embodiments is indicated by the appended claims and is not limited to the specific embodiments described hereinafter. Furthermore, the described embodiments can be used in combination with each other. In the following description, numerous specific details are discussed to provide a thorough understanding of the embodiments. However, in certain instances, detailed descriptions have been omitted in order to avoid obscuring the embodiments. The embodiments described herein are not intended to be exhaustive or to be limited to the precise form disclosed. Identical reference numerals in the figures designate the same elements. The embodiments described herein are intended to cover any and all modifications within the scope of the embodiments.

[0059] Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top", can be used herein to describe one element's or feature's relationship to another element or feature as illustrated in the figures. These relative terms are intended to encompass different orientations of the device in its operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the embodiments of the devices described herein can operate in any orientation.

[0060] In the present disclosure, the terms "about", "approximately", "substantially" are used to describe a value or a range of values that is within 20% of a given value or range, preferably within 10%, more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. A value given herein as approximately a value implies that the meaning of "about", "approximately", "substantially" is implied in the absence of a specific indication of "about", "approximately", "substantially".

[0061] It is to be understood that the terms "first", "second", "third", and the like, used herein can refer to different elements, components, regions, layers, and / or portions, but do not require any particular order of these elements, components, regions, layers, and / or portions. Thus, a first element, component, region, layer, and / or portion discussed below could be termed a second element, component, region, layer, and / or portion without departing from the teachings of the embodiments.

[0062] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0063] This disclosure includes embodiments that can be understood in conjunction with the accompanying drawings, which are also considered part of the description of these embodiments. It should be understood that the drawings of this disclosure are not drawn to scale with actual devices and components. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the disclosed embodiments. Furthermore, the structures and devices in the drawings are illustrated schematically to clearly show the features of the disclosed embodiments.

[0064] In some embodiments disclosed herein, relative terms such as "down," "up," "horizontal," "vertical," "below," "above," "top," "bottom," etc., should be understood as referring to the orientation shown in the paragraph and related figures. These relative terms are for illustrative purposes only and do not imply that the described device must be manufactured or operated in a specific orientation. Terms related to joining or connecting, such as "connection" or "interconnection," unless specifically defined, may refer to two structures in direct contact, or to two structures not in direct contact, with another structure disposed between them. Furthermore, these terms related to joining or connecting may include situations where both structures are movable or both structures are fixed.

[0065] Embodiments of the present invention disclose embodiments of semiconductor devices, which can be included in integrated circuits (ICs) such as microprocessors, memory elements, and / or other components. These ICs can also include various passive and active microelectronic components, such as thin-film resistors, other types of capacitors (e.g., metal-insulator-metal capacitors, MIMCAPs), inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors, high-power MOS transistors, or other types of transistors. Those skilled in the art will understand that semiconductor devices can also be used to include other types of semiconductor elements within integrated circuits.

[0066] Figures 1A-1H A cross-sectional schematic diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Figure 1A As shown, a substrate 10 is provided, comprising a first region 110, a second region 120, a third region 130, and a fourth region 140. The relative positions of the first region 110, the second region 120, the third region 130, and the fourth region 140 are interchangeable and are used for illustrative purposes only, without any limitation thereof. The substrate 10 may be formed of at least one semiconductor material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. Alternatively, a substrate with silicon on insulator (SOI) may also be used.

[0067] Next, a pad oxide layer 11 is formed on the substrate 10. The material of the pad oxide layer 11 is, for example, silicon oxide or other suitable materials. The method for forming the pad oxide layer 11 is, for example, thermal oxidation. Then, a pad nitride layer 12 is formed on the pad oxide layer 11.

[0068] Next, please refer to Figure 1B as well as Figure 1CThe removal step involves removing the pad oxide layer 11 and the pad nitride layer 12 of the first region 110 to expose the first top surface 10A-1 of the substrate 10, and removing the pad oxide layer 11 and the pad nitride layer 12 of the second region 120 to expose the second top surface 10A-2 of the substrate 10, wherein the first top surface 10A-1 and the second top surface 10A-2 are substantially coplanar. According to an embodiment of the invention, the removal step includes a photolithography process and an etching process. According to an embodiment of the invention, the first region 110 has a first width L1, and the second region 120 has a second width L2, wherein the second width L2 is greater than the first width L1.

[0069] Then as Figure 1C As shown, a first isolation structure 111 is formed in a first region 110, and a second isolation structure 121 is formed in a second region 120. The second isolation structure 121 has a first bottom surface 121A, wherein the first bottom surface 121A and the second top surface 10A-2 are substantially coplanar. Figure 1C As shown, the first isolation structure 111 and the second isolation structure 121 have a first thickness T1.

[0070] According to one embodiment of the present invention, the material of the first isolation structure 111 and the second isolation structure 121 is, for example, silicon oxide. The thickness of the first isolation structure 111 and the second isolation structure 121 is, for example, approximately... (Angstrom) to approximately In this embodiment, the first isolation structure 111 and the second isolation structure 121 are formed by, for example, local oxidation of silicon (LOCOS). The method of forming the first isolation structure 111 and the second isolation structure 121 is not limited to the local oxidation method described in this embodiment. Shallow trench isolation method or chemical vapor deposition combined with patterning process (e.g., photolithography and etching process) can also be used.

[0071] Next, please refer to Figure 1D The removal step involves removing the pad oxide layer 11 and the pad nitride layer 12 of the third region 130 to expose the third top surface 10A-3 of the substrate 10, and removing the pad oxide layer 11 and the pad nitride layer 12 of the fourth region 140 to expose the fourth top surface 10A-4 of the substrate 10. According to an embodiment of the invention, the removal step includes a photolithography process and an etching process. According to an embodiment of the invention, the first top surface 10A-1 of the first region 110, the second top surface 10A-2 of the second region 120, the third top surface 10A-3 of the third region 130, and the fourth top surface 10A-4 of the fourth region 140 are substantially coplanar. The third region 130 has a third width L3, and the fourth region 140 has a fourth width L4, wherein the fourth width L4 is greater than the third width L3.

[0072] Next, referring to Figure 1E The third isolation structure 131 is formed in the third region 130 and the fourth isolation structure 141 is formed in the fourth region 140, such that the third isolation structure 131 and the fourth isolation structure 141 have the second thickness T2, and the first isolation structure 111 and the second isolation structure 121 have a third thickness T3, where the third thickness T3 is greater than the first thickness T1 and less than the sum of the first thickness T1 and the second thickness T2. In other words, although the thickness of the first isolation structure 111 and the second isolation structure 121 is increased simultaneously when the third isolation structure 131 and the fourth isolation structure 141 are formed, the thickness of the first isolation structure 111 and the second isolation structure 121 is not increased linearly.

[0073] According to an embodiment of the present application, the material of the third isolation structure 131 and the fourth isolation structure 141 is, for example, silicon oxide. The thickness of the third isolation structure 131 and the fourth isolation structure 141 is, for example, about (Angstrom) to about In this embodiment, the method of forming the third isolation structure 131 and the fourth isolation structure 141 is, for example, the local oxidation of silicon (LOCOS) method. The method of forming the first isolation structure 111 and the second isolation structure 121 is not limited to the LOCOS method described in this embodiment, and can also use the shallow trench isolation method, or the chemical vapor deposition method combined with a patterning process (such as photolithography and etching process).

[0074] As shown in Figure 1E , the fourth isolation structure 141 has a second bottom surface 141A, where the second bottom surface 141A is substantially coplanar with the fourth top surface 10A-4. According to an embodiment of the present application, the first top surface 10A-1 of the first region 110, the second top surface 10A-2 of the second region 120, the third top surface 10A-3 of the third region 130, the fourth top surface 10A-4, the first bottom surface 121A and the second bottom surface 141A are substantially coplanar.

[0075] Next, as shown in Figure 1F , the remaining pad oxide layer 11 and the pad nitride layer 12 on the substrate 10 are removed, and the first isolation structure 111, the second isolation structure 121, the third isolation structure 131 and the fourth isolation structure 141 are exposed. Next, as shown in Figure 1G , the first photoresist layer 151, the second photoresist layer 152 and the third photoresist layer 153 are covered on the first isolation structure 111, the second isolation structure 121, the third isolation structure 131 and the fourth isolation structure 141.

[0076] AsFigure 1G As shown, the first photoresist layer 151 is used to completely cover the first isolation structure 111 and the third isolation structure 131. The second photoresist layer 151 is used to cover the first central portion 121Z of the second isolation structure 121, while exposing the first left portion 121X and the first right portion 121Y of the second isolation structure 121. The third photoresist layer 153 is used to cover the second central portion 141Z of the fourth isolation structure 141, while exposing the second left portion 141X and the second right portion 141Y of the fourth isolation structure 141.

[0077] As shown, the first photoresist layer 151 is used to completely cover the first isolation structure 111 and the third isolation structure 131. The second photoresist layer 151 is used to cover the first central portion 121Z of the second isolation structure 121, while exposing the first left portion 121X and the first right portion 121Y of the second isolation structure 121. The third photoresist layer 153 is used to cover the second central portion 141Z of the fourth isolation structure 141, while exposing the second left portion 141X and the second right portion 141Y of the fourth isolation structure 141. Figure 1H As shown, the first photoresist layer 151 is used to completely cover the first isolation structure 111 and the third isolation structure 131. The second photoresist layer 151 is used to cover the first central portion 121Z of the second isolation structure 121, while exposing the first left portion 121X and the first right portion 121Y of the second isolation structure 121. The third photoresist layer 153 is used to cover the second central portion 141Z of the fourth isolation structure 141, while exposing the second left portion 141X and the second right portion 141Y of the fourth isolation structure 141.

[0078] According to some embodiments of the present application, the first isolation structure 111, the first central portion 121Z of the second isolation structure 121, the third isolation structure 131 and the second central portion 141Z of the fourth isolation structure 141 are used to form a plurality of high voltage elements in the first region 110, the second region 120, the third region 130 and the fourth region 140, respectively, wherein each of the high voltage elements has a different breakdown voltage and a different on-resistance. Furthermore, the first isolation structure 111, the second isolation structure 121, the third isolation structure 131 and the fourth isolation structure 141 each serve as a draft oxide of the high voltage elements to control the breakdown voltage and the on-resistance of different high voltage elements in the same process.

[0079] According to an embodiment of the present application, the purpose of removing the second isolation structure 121 and the fourth isolation structure 141 on both sides is to achieve sufficient isolation width between the plurality of high voltage elements, and to make the first bottom surface 121A of the second isolation structure 121 and the second bottom surface 141A of the fourth isolation structure 141 substantially coplanar with the second top surface 10A-2 and the fourth top surface 10A-4, respectively.

[0080] As shown, the first photoresist layer 151 is used to completely cover the first isolation structure 111 and the third isolation structure 131. The second photoresist layer 151 is used to cover the first central portion 121Z of the second isolation structure 121, while exposing the first left portion 121X and the first right portion 121Y of the second isolation structure 121. The third photoresist layer 153 is used to cover the second central portion 141Z of the fourth isolation structure 141, while exposing the second left portion 141X and the second right portion 141Y of the fourth isolation structure 141. Figure 1HAs shown, the first angle a between the first side wall 121B of the first central portion 121Z of the second isolation structure 121 and the second top surface 10A-2 can be a right angle or adjusted to be an obtuse angle, for example, by controlling the etching process according to actual needs; the second angle β between the second side wall 121C of the first central portion 121Z and the second top surface 10A-2 can be a right angle or adjusted to be an obtuse angle, for example, by controlling the etching process according to actual needs. The third angle γ between the third side wall 141B of the second central portion 141Z of the fourth isolation structure 141 and the fourth top surface 10A-4 can be a right angle or adjusted to be an obtuse angle, for example, by controlling the etching process according to actual needs; the fourth angle θ between the fourth side wall 141C of the second central portion 141Z and the fourth top surface 10A-4 can be a right angle or adjusted to be an obtuse angle, for example, by controlling the etching process according to actual needs.

[0081] The present application provides a method for manufacturing semiconductor devices, so that isolation structures with different thicknesses and shapes can be realized in the same process, which can be used as drift regions of different high-voltage elements, thereby controlling the breakdown voltage and on-resistance of each element in the same process, so as to reduce the wafer area occupied by the circuit and reduce production costs.

[0082] Although the embodiments of the present disclosure and their advantages have been disclosed, it should be understood that any person skilled in the art can make modifications, substitutions and refinements without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacture, material composition, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufacture, material composition, devices, methods and steps from the disclosure of some embodiments of the present disclosure, as long as they can substantially perform the same function or achieve substantially the same result as in the embodiments described herein. Therefore, the scope of protection of the present disclosure includes the above processes, machines, manufacture, material composition, devices, methods and steps. In addition, each application patent range constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of each claim and embodiment.

Claims

1. A method of manufacturing a semiconductor device, characterized by, Comprising: providing a substrate, the substrate comprising a first region, a second region, a third region, and a fourth region; forming a pad oxide layer on the substrate; forming a pad nitride layer on the pad oxide layer; performing a first removing step to remove the pad oxide layer and the pad nitride layer of the first region and the second region to expose a top surface of the substrate; forming a first isolation structure and a second isolation structure in the first region and the second region, respectively; after the step of forming the first isolation structure and the second isolation structure in the first region and the second region, respectively, performing a second removing step to remove the pad oxide layer and the pad nitride layer of the third region and the fourth region to expose the top surface; forming a third isolation structure and a fourth isolation structure in the third region and the fourth region, respectively, and simultaneously increasing the thickness of the first isolation structure and the second isolation structure; and performing a third removing step to remove the left and right portions of the second isolation structure and the left and right portions of the fourth isolation structure such that the bottom surface of the second isolation structure and the fourth isolation structure is substantially coplanar with the top surface of the substrate. The step of performing the third removing step to remove the left and right portions of the second isolation structure and the fourth isolation structure further comprises: covering the first isolation structure, the second isolation structure, the third isolation structure, and the fourth isolation structure with photoresist layers and exposing the left and right portions of the second isolation structure and the fourth isolation structure; 2. The method for manufacturing a semiconductor device according to Claim 1, wherein removing the left and right portions of the second isolation structure and the fourth isolation structure; and 3. The method for manufacturing a semiconductor device according to Claim 1, wherein removing the photoresist layers. The width of the second region and the fourth region is greater than the width of the first region and the third region. The angle between the sidewall of at least one side of the second isolation structure and the fourth isolation structure and the top surface is a right angle or an obtuse angle. The step of performing the third removing step to remove the left and right portions of the second isolation structure and the fourth isolation structure further comprises:

4. The method for manufacturing a semiconductor device according to Claim 1, wherein performing a fourth removing step to remove the pad oxide layer and the pad nitride layer on the substrate before the step of performing the third removing step to remove the left and right portions of the second isolation structure and the fourth isolation structure.

5. The method for manufacturing a semiconductor device according to Claim 1, wherein The step of performing the third removing step to remove the left and right portions of the second isolation structure and the fourth isolation structure further comprises:

6. The method for manufacturing a semiconductor device according to Claim 1, wherein performing a fifth removing step to remove the pad oxide layer and the pad nitride layer on the substrate after the step of performing the third removing step to remove the left and right portions of the second isolation structure and the fourth isolation structure. ​ 7. The method for manufacturing a semiconductor device according to Claim 6, wherein ​ A plurality of high voltage devices are formed with different isolation structures, wherein the first, second, third and fourth isolation structures are each a drift oxide layer of the high voltage devices to control the breakdown voltage and on-resistance of the high voltage devices in the same process.

8. A semiconductor device, characterized by comprising: Further comprising: a substrate having a top surface; a first isolation structure formed on the substrate and having a first thickness; a second isolation structure formed on the substrate and having a second thickness, wherein at least a portion of a bottom surface of the second isolation structure is substantially coplanar with the top surface; a third isolation structure formed on the substrate and having a third thickness; and a fourth isolation structure formed on the substrate and having a fourth thickness, wherein at least a portion of a bottom surface of the fourth isolation structure is substantially coplanar with the top surface, wherein the first thickness is equal to the second thickness, the third thickness is equal to the fourth thickness, and the first thickness is greater than the third thickness.

9. The semiconductor device according to claim 8, wherein Further comprising: a plurality of high voltage devices with different isolation structures, wherein the first, second, third and fourth isolation structures are each a drift oxide layer of the high voltage devices.

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