A semiconductor structure and a method for forming the same

Abstract

A semiconductor structure and a method for forming the same. The method includes: using the sidewall structure as a mask to etch the composite layer and the initial first region, forming a first region and two discrete first fin portions located on the first region. There is a first opening between the two first fin portions. The first fin portion includes a first bottom structure located on the first region, a plurality of overlapping first sacrificial layers located on the first bottom structure, and a first channel layer located between adjacent two first sacrificial layers. A first isolation structure is formed in the first opening. The first fin portion and the first opening are synchronously formed by a single etching using the sidewall structure as a mask, without relying on a patterned layer. The widths and positions of the first fin portion and the first opening are not limited by the lithography technology of pattern transfer. Therefore, self-aligned formation of the first isolation structure can be achieved, reducing the requirements for the lithography process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] In the existing semiconductor field, the fin field-effect transistor (FinFET) is an emerging multi-gate device. Compared with the planar metal-oxide-semiconductor field-effect transistor (MOSFET), the fin field-effect transistor has stronger short-channel suppression ability and stronger working current, and has now been widely used in various semiconductor devices. However, with the further development of semiconductor technology, when the transistor size is reduced to less than a few nanometers and the size of the FinFET itself has reached the limit, problems such as fin pitch, short-channel effect, leakage, and material limitations have made transistor manufacturing precarious, and even the physical structure cannot be completed.

[0003] The gate-all-around (GAA) device has become a new direction of research and development in the industry. The characteristic of this technology is that the gate wraps around the channel on all four sides. The source and drain no longer contact the substrate, but after multiple source and drain electrodes in the form of lines (which can be understood as rods), plates, or sheets are distributed horizontally and perpendicularly to the gate, the basic structure and function of the MOSFET are realized. Such a design largely solves various problems brought about by the reduction of the gate pitch size, including capacitance effects, etc. In addition, since the channel is wrapped by the gate on all four sides, the channel current is also smoother than the three-sided wrapping of the FinFET.

[0004] However, as an important direction of development in the industry, the gate-all-around device is still in the stage of continuous research and improvement. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a semiconductor structure and a method for forming the same to improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes an initial first region, forming a composite layer on the substrate, the composite layer includes several overlapping initial sacrificial layers and an initial channel layer located between two adjacent initial sacrificial layers, forming a plurality of sidewall structures on the surface of the composite layer in the initial first region, the sidewall structures include two separate first sidewalls, using the sidewall structures as a mask, etching the composite layer and the initial first region to form a first region and two separate first fin portions located on the first region, there is a first opening between the two first fin portions, the first fin portions include a first bottom structure located on the first region, several overlapping first sacrificial layers located on the first bottom structure, and a first channel layer located between two adjacent first sacrificial layers, forming a first isolation structure in the first opening.

[0007] Optionally, the method for forming the sidewall structures includes: forming a plurality of first axis layers on a part of the composite layer; forming a first sidewall material layer on the sidewalls of the first axis layers and the composite layer; back-etching the first sidewall material layer to expose the surface of the composite layer and the surface of the first axis layers, forming a first axis layer structure, the first axis layer structure includes the first axis layers and two first sidewalls on the sidewalls of the first axis layers; removing the first axis layers on the surface of the composite layer in the initial first region.

[0008] Optionally, the process of removing the first axis layers on the surface of the composite layer in the initial first region includes one or a combination of wet etching and dry etching.

[0009] Optionally, it includes: the material of the first axis layers is different from the material of the first sidewalls; the material of the first axis layers is different from the material on the surface of the composite layer; the material of the first axis layers includes amorphous silicon.

[0010] Optionally, the substrate further includes a second region; the method for forming the semiconductor structure further includes: forming a plurality of second fin portions on the second region, the second fin portions include a second bottom structure located on the second region, several overlapping second sacrificial layers located on the second bottom structure, and a second channel layer located between two adjacent second sacrificial layers.

[0011] Optionally, it further includes: forming a second isolation structure on the substrate, the second isolation structure covers the sidewalls of the first bottom structure of the first fin portions.

[0012] Optionally, the second isolation structure also covers the sidewalls of the second bottom structure of the second fin portions.

[0013] Optionally, it includes: the material of the second isolation structure is an insulating dielectric material; the material of the second isolation structure includes silicon oxide.

[0014] Optionally, the substrate further includes an initial second region, and the composite layer is also located on the initial second region; the method for forming the second fin portion and the second region includes: forming a plurality of second sidewalls on the surface of the composite layer on the initial second region; using the second sidewalls as a mask to etch the composite layer and the initial second region to form the second region and a plurality of mutually separated second fin portions located on the second region.

[0015] Optionally, the method for forming the second sidewalls includes: forming a second core layer on the surface of the composite layer on the initial second region; covering the second core layer and forming a second sidewall material layer on the surface of the composite layer; back-etching the second sidewall material layer to expose the surface of the composite layer and the surface of the second core layer; removing the second core layer to form the second sidewalls.

[0016] Optionally, the process for removing the second core layer includes one or a combination of wet etching and dry etching.

[0017] Optionally, the second sidewalls are formed simultaneously with the first sidewalls, and the method for forming the first sidewalls and the second sidewalls includes: the first core layer structure is also located on a partial surface of the composite layer on the initial second region; removing the first core layer on the initial first region and forming the first sidewalls on the surface of the composite layer on the initial first region; removing the first core layer on the initial second region and forming the second sidewalls on the surface of the composite layer on the initial second region.

[0018] Optionally, it includes: the material of the second sidewalls is an insulating dielectric material; the material of the second sidewalls includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon silicon nitride, or carbon oxynitride silicon.

[0019] Optionally, the sidewall structure further includes a third sidewall located on the sidewall of the first sidewall; the method for forming the third sidewall includes: after forming the first core layer structure, forming a first auxiliary layer on the surface of the composite layer, and the first auxiliary layer is also located on the sidewall of the first core layer structure; removing the first core layer on the surface of the composite layer on the initial first region and forming a groove in the first sidewall; forming the third sidewall on the sidewall of the groove.

[0020] Optionally, it includes: the material of the third sidewalls is an insulating dielectric material; the material of the third sidewalls includes one or more of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon silicon nitride, or carbon oxynitride silicon.

[0021] Optionally, it includes: the material of the first auxiliary layer is different from the material on the surface of the composite layer; the material of the first auxiliary layer is different from the material of the third axis layer structure; the material of the first auxiliary layer is different from the material of the second sidewall; the material of the first auxiliary layer includes amorphous carbon or photoresist.

[0022] Optionally, before forming the first fin, the second fin is formed; the method for forming the second fin further includes: forming a third axis layer in the trench, and forming a third axis layer structure with the third axis layer and the sidewall structure; after forming the third axis layer structure, removing the first auxiliary layer; using the second sidewall as a mask to etch the composite layer and the initial second region to form the second region and the second fin on the second region.

[0023] Optionally, the process for removing the first auxiliary layer includes one or a combination of wet etching and dry etching.

[0024] Optionally, it includes: the material of the third axis layer is different from the material on the surface of the composite layer; the material of the third axis layer is different from the material of the sidewall structure; the material of the third axis layer includes silicon carbide.

[0025] Optionally, it further includes: using the third axis layer structure as a mask to etch the composite layer and the initial first region to form an initial first fin; forming a second auxiliary layer on the surface of the substrate, and the second auxiliary layer is also located on the sidewalls of the second fin and the initial first fin; removing the third axis layer, and using the sidewall structure as a mask to etch the initial first fin to form the first opening in the initial first fin to form the first fin.

[0026] Optionally, it further includes: after forming the first isolation structure, removing the second auxiliary layer; after removing the second auxiliary layer, forming the second isolation structure.

[0027] Optionally, the process for removing the second auxiliary layer includes one or a combination of wet etching and dry etching.

[0028] Optionally, it includes: the material of the second auxiliary layer is different from the material of the substrate; the material of the second auxiliary layer is different from the material of the composite layer; the material of the second auxiliary layer includes amorphous carbon or photoresist.

[0029] Optionally, it further includes: forming a first dummy gate spanning the first fin, the first dummy gate being located on a partial top surface and a partial sidewall surface of the first fin; forming first source / drain regions in one of the first fins on both sides of the first dummy gate; forming second source / drain regions in the other first fin on both sides of the first dummy gate; forming an interlayer dielectric layer on the substrate surface and the first fin surface, the interlayer dielectric layer also being located on the sidewalls of the first dummy gate and exposing the top surface of the first dummy gate; removing the first dummy gate to form a first gate opening in the interlayer dielectric layer; removing a first sacrificial layer exposed at the bottom of the first gate opening to form a first groove between the first channel layers exposed in the first gate opening; forming a first gate electrode in the first gate opening and the first groove on the first region.

[0030] Optionally, the doping ions of the first source / drain regions are N-type, and the doping ions of the second source / drain regions are P-type.

[0031] Optionally, it further includes: forming a second dummy gate spanning the second fin, the second dummy gate being located on a partial top surface and a partial sidewall surface of the second fin; forming third source / drain regions in the second fin on both sides of the second dummy gate; the interlayer dielectric layer also being located on the second fin surface and the sidewalls of the second dummy gate and exposing the top surface of the second dummy gate; removing the second dummy gate to form a second gate opening in the interlayer dielectric layer; removing a second sacrificial layer exposed at the bottom of the second gate opening to form a second groove between the second channel layers exposed in the second gate opening; forming a second gate electrode in the second gate opening and the second groove on the second region.

[0032] Optionally, the material of the initial sacrificial layer is different from the material of the initial channel layer.

[0033] Optionally, the material of the initial sacrificial layer includes silicon; the material of the initial channel layer includes germanium silicon.

[0034] Optionally, it includes: the material of the first sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride or silicon carbon oxynitride.

[0035] Optionally, it includes: the material of the first isolation structure is an insulating dielectric material; the material of the first isolation structure includes silicon oxide.

[0036] Optionally, it further includes: forming a hard mask layer on the surface of the composite layer before forming the sidewall structure.

[0037] Optionally, it includes: the material of the hard mask layer is different from the material of the first sidewall; the material of the hard mask layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride or silicon carbon oxynitride.

[0038] Correspondingly, the technical solution of the present invention further provides a semiconductor structure, including: a substrate, the substrate includes a first region, a plurality of mutually discrete first fin portions on the first region, the first fin portions include a plurality of overlapping first sacrificial layers, a first channel layer located between adjacent two layers of the first sacrificial layers, and a first bottom structure located on the first region, and a first isolation structure in adjacent first fin portions.

[0039] Optionally, the substrate further includes a second region, and a plurality of second fin portions are provided on the second region, the second fin portions include a plurality of overlapping second sacrificial layers, a second channel layer located between adjacent two layers of the second sacrificial layers, and a second bottom structure located on the second region.

[0040] Optionally, the widths of the second fin portions and the first fin portions are different.

[0041] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0042] In the method for forming a semiconductor structure provided by the technical solution of the present invention, using the sidewall structure as a mask, etching the composite layer and the initial first region to form a first region and two mutually discrete first fin portions on the first region, there is a first opening between the two first fin portions, the first fin portions include a first bottom structure located on the first region, a plurality of overlapping first sacrificial layers on the first bottom structure, and a first channel layer located between adjacent two layers of the first sacrificial layers. Forming a first isolation structure in the first opening, the first fin portions are used to form the source-drain regions and channel regions of the surround gate devices, the first fin portions and the first opening are synchronously formed by one etching using the sidewall structure as a mask, and do not rely on a patterned layer. The widths and positions of the first fin portions and the first opening are not limited by the lithography technology of pattern transfer. Therefore, self-aligned formation of the first isolation structure can be achieved, reducing the requirements for the lithography process.

[0043] Furthermore, since the first fin portions are formed using the sidewall structure as a mask and the second fin portions are formed using the second sidewall as a mask, the widths of the first fin portions and the second fin portions can be adjusted by adjusting the widths of the sidewall structure and the second sidewall, so that the widths of the first fin portions and the second fin portions are different. Therefore, fin portions with different widths can be formed on the same chip to meet different device design requirements. Description of the Drawings

[0044] Figures 1 to 2 is a schematic cross-sectional view of a semiconductor structure forming process;

[0045] Figures 3 to 13It is a schematic cross-sectional structure diagram corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present invention;

[0046] Figures 14 to 28 It is a schematic cross-sectional structure diagram corresponding to each step in the method for forming a semiconductor structure according to another embodiment of the present invention. Detailed implementation manners

[0047] As described in the background art, the performance of semiconductor devices formed in the prior art needs to be improved. Now, a semiconductor structure will be described and analyzed in combination.

[0048] Figures 1 to 2 It is a schematic cross-sectional view of a semiconductor structure forming process.

[0049] Please refer to Figure 1 , a substrate 100 is provided, and the substrate 100 includes: a base 101 and fin portions 102 located on the surface of the base; a hard mask material layer 103 is formed on the surface of the substrate 100, and a patterned photoresist layer 104 is formed on the hard mask material layer 103.

[0050] Please refer to Figure 2 , using the photoresist layer 104 to etch the hard mask material layer 103 to form a hard mask layer 105, the hard mask layer 105 exposes a part of the surface of the fin portion 102, using the hard mask layer 105 as a mask to etch the substrate 100 to form a partition trench (not marked in the figure); filling the partition trench with an insulating medium such as silicon oxide and silicon nitride to form a partition structure 106.

[0051] The above method is used in the fin isolation structure of a GAA device. The fin portion 102 includes several overlapping sacrificial layers and channel layers located between adjacent sacrificial layers. After the fin portion 102 of the GAA device is formed, the isolation trench of the GAA device is formed by etching the substrate using the patterned hard mask layer 105 as a mask, and the partition trench is located in the base 101 and the fin portion 102. As the device size continues to shrink, the accuracy requirements for the lithography process are getting higher and higher. Due to the influence of lithography technology, when the pattern of the photoresist layer 105 is transferred to the substrate 100, the size of the pattern will change, thereby affecting the size of the partition trench and the fin portion 102, and also making the position of the partition trench inaccurate. At the same time, the fin portion 102 and the isolation trench are formed by a two-step etching process, and the process is complex, increasing the production cost.

[0052] To solve the above problems, the present invention provides a method for forming a semiconductor structure. Using the sidewall structure as a mask, the composite layer and the initial first region are etched to form a first region and two separate first fin portions located on the first region. There is a first opening between the two first fin portions. The first fin portion includes a first bottom structure located on the first region, several overlapping first sacrificial layers located on the first bottom structure, and a first channel layer located between adjacent two first sacrificial layers. A first isolation structure is formed in the first opening. The first fin portion is used to form the channel region of the surround gate device. The first fin portion and the first opening are synchronously formed by one etching using the sidewall structure as a mask, which simplifies the production process and does not rely on a patterning layer. The width and position of the first fin portion and the first opening are not limited by the lithography technology of pattern transfer. Therefore, self-aligned formation of the first isolation structure can be achieved, reducing the requirements for the lithography process.

[0053] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0054] Figures 3 to 13 It is a schematic cross-sectional structure diagram corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0055] Please refer to Figure 3 , a substrate 200 is provided, and the substrate 200 includes an initial first region 201; a composite layer 203 is formed on the substrate 200, and the composite layer 203 includes several overlapping initial sacrificial layers 204 and an initial channel layer 205 located between adjacent two initial sacrificial layers.

[0056] The substrate 200 further includes a base 202. The material of the substrate 200 includes single crystal silicon.

[0057] The initial first region 201 is used to form a first region and the first bottom structure of the first fin portion located on the first region.

[0058] The composite layer 203 is used to form the first fin portion.

[0059] The material of the initial sacrificial layer 204 is different from that of the initial channel layer 205. The initial channel layer 205 is used to form the channel layer for forming the source and drain regions and the channel region of the device. The initial sacrificial layer 204 is used to form the first sacrificial layer subsequently, and the first sacrificial layer will be removed later. The material of the initial sacrificial layer 204 has a higher etching selectivity relative to the material of the initial channel layer 205, so that the influence on the first channel layer is smaller when the first sacrificial layer is removed later; the material of the initial sacrificial layer 204 has a better lattice match relative to the material of the initial channel layer 205 to obtain a smooth interface between the initial sacrificial layer 204 and the initial channel layer 205, making the surface of the first channel layer formed later flat, which is conducive to obtaining a device with good performance.

[0060] The material of the initial sacrificial layer 204 includes silicon; the material of the initial channel layer 205 includes silicon germanium. In this embodiment, the material of the initial sacrificial layer 204 is silicon; the material of the initial channel layer 205 is silicon germanium. In other embodiments, the initial channel layer 205 is Ge or GeSi. In other embodiments, the material of the initial sacrificial layer 2 can be ZnS, ZnSe, BeS, GaP, etc.

[0061] In this embodiment, it further includes: forming a hard mask layer 206 on the surface of the composite layer 203, and the material of the hard mask layer 206 is silicon oxide. In other embodiments, the material of the hard mask layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon silicon oxide, carbon silicon nitride, or carbon oxynitride. The hard mask layer 206 is used to protect the composite layer 203 to prevent the composite layer 203 from being damaged when etching and other processes are performed on the surface of the composite layer 203 later. The material of the hard mask layer is different from the material of the first sidewall formed later, and the material of the first sidewall has a larger etching selectivity than the hard mask material to prevent the hard mask layer from being etched away during the etching process of forming the first sidewall later.

[0062] In this embodiment, the uppermost layer of the composite layer 203 is the initial channel layer 205. In other embodiments, the uppermost layer of the composite layer 203 is the initial sacrificial layer.

[0063] Subsequently, a plurality of sidewall structures are formed on the surface of the composite layer 203, and the sidewall structures include two separate first sidewalls. The formation method of the sidewall structures is as Figures 4 to 6 shown.

[0064] Please refer to Figure 4 and form a plurality of first core layers 207 on a part of the composite layer 203.

[0065] The material of the first core layer 207 includes amorphous silicon.

[0066] The material of the first central axis layer 207 is different from the material of the first sidewall formed subsequently.

[0067] The material of the first central axis layer 207 is different from the material on the surface of the composite layer 203.

[0068] In this embodiment, the surface of the composite layer 203 is a hard mask layer 206, the material on the surface of the composite layer 203 is silicon oxide, and the material of the first central axis layer 207 is amorphous silicon. Subsequently, a first sidewall will be formed on the sidewall of the first central axis layer 207. After forming the first sidewall, the first central axis layer 207 is removed. Therefore, during the etching process of removing the first central axis layer 207, in order to avoid damage to the materials of the first sidewall and the surface of the composite layer 203, the material of the first central axis layer 207 needs to have a larger etching selectivity ratio compared to the material on the surface of the composite layer 203; the material of the first central axis layer 207 has a larger etching selectivity ratio compared to the first sidewall.

[0069] Please refer to Figure 5 , a first sidewall material layer (not marked in the figure) is formed on the sidewall of the first central axis layer 207 and on the composite layer 203; the first sidewall material layer is etched back to expose the surface of the composite layer 203 and the surface of the first central axis layer 207, forming a first central axis layer structure 209, and the first central axis layer structure 209 includes the first central axis layer 207 and two first sidewalls on the sidewall of the first central axis layer 207.

[0070] In this embodiment, it further includes: removing the first central axis layer 207 on the surface of the composite layer 203 of the initial first region 201. The sidewall structure 208 includes two separate first sidewalls.

[0071] The material of the first sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon silicon nitride, or carbon oxynitride silicon. In this embodiment, the material of the first sidewall is silicon nitride. Each subsequent sidewall structure 209 is used to form two separate first fins, and there is a first opening between the two first fins, and a first isolation structure is formed in the first opening. Therefore, the sidewall structure 209 requires two separate first sidewalls to form the first fins with the first sidewalls as masks.

[0072] Please refer to Figure 6, using the sidewall structure 209 as a mask, etching the composite layer 203 and the initial first region 201 to form a first region 210 and two separate first fin portions 212 located on the first region 210. There is a first opening 213 between the two first fin portions 212. The first fin portion 212 includes a first bottom structure 214 located on the first region 210, several overlapping first sacrificial layers 215 located on the first bottom structure 214, and a first channel layer 216 located between two adjacent first sacrificial layers 215.

[0073] The process of etching the composite layer 203 and the initial first region 201 is a dry etching process.

[0074] In this embodiment, the hard mask layer 206 is etched to form a first hard mask layer 217. The topmost layer of the first fin portion 212 is the first channel layer 216, and the first hard mask layer 217 is on the surface of the first fin portion 212. In another embodiment, the topmost layer of the first fin is the first sacrificial layer, and the first hard mask layer is on the surface of the first fin. In another embodiment, the topmost layer of the first fin is the first sacrificial layer, and there is no first hard mask layer on the surface of the first fin.

[0075] Please refer to Figure 7 , forming a first isolation structure 218 in the first opening 213; forming a second isolation structure 219 on the substrate 200, and the second isolation structure 219 covers the sidewalls of the first bottom structure 214 of the first fin portion 212.

[0076] The material of the first isolation structure 218 is an insulating dielectric material. In this embodiment, the material of the first isolation structure 218 is silicon oxide. In other embodiments, the material of the first isolation structure is an insulating dielectric material such as silicon nitride.

[0077] The material of the second isolation structure 219 is an insulating dielectric material. In this embodiment, the material of the second isolation structure 219 is silicon oxide. In other embodiments, the material of the second isolation structure is an insulating dielectric material such as silicon nitride.

[0078] The first isolation structure 218 and the second isolation structure 219 are used for electrical isolation of different devices.

[0079] The forming process of the first isolation structure 218 includes an HDP CVD (high density plasma chemical vapor deposition) process. The HDP CVD process bombards and sputter etches with a high-density ion plasma to prevent premature closing of the first opening 213 during chemical vapor deposition, and to avoid void formation in the first opening 213. The HDP CVD process has very good step coverage and can effectively fill the voids in the first opening 213.

[0080] The forming process of the second isolation structure 219 includes an HDP CVD process. The advantages of the HDP CVD process are as described above and will not be elaborated here.

[0081] Please refer to Figure 8 and Figure 9 , Figure 9 is Figure 8 a top view along the Y direction, forming a first dummy gate 220 across the first fin 212, and the first dummy gate 220 is located on a partial top surface and a partial sidewall surface of the first fin 212.

[0082] In this embodiment, before forming the first dummy gate 220, it further includes: removing the sidewall structure 209; removing the first hard mask layer 217. In other embodiments, the first hard mask layer is retained and only the sidewall structure is removed; or both the sidewall structure and the first hard mask layer are retained.

[0083] The method of forming the first dummy gate 220 includes: forming a first dummy gate material layer on the substrate 200, forming a patterned layer on the first dummy gate material layer, and using the patterned layer as a mask to etch the first dummy gate material layer until the surface of the substrate 200 is exposed, thereby forming the first dummy gate 220.

[0084] In this embodiment, the surface of the first dummy gate 220 is flush with the first isolation structure 218. In other embodiments, the first dummy gate straddles two adjacent first fins and covers a partial surface of the first isolation structure 218.

[0085] The process of etching the first dummy gate material layer includes a dry etching process.

[0086] Please refer to Figure 8 and Figure 10 , Figure 10 is Figure 8 a top view along the Y direction, forming a first source / drain region 221 in one of the first fins 212 on both sides of the first dummy gate 220; forming a second source / drain region 222 in the other first fin 212 on both sides of the dummy gate.

[0087] In this embodiment, the first isolation structure 218 isolates PMOS and NMOS devices. The doping ions of the first source / drain region are N-type, and the doping ions of the second source / drain region are P-type. In this embodiment, the second source / drain region 222 is formed after the first source / drain region 221. In another embodiment, the second source / drain region 222 is formed first, and then the first source / drain region 221 is formed. In other embodiments, the conduction types of the first source / drain region 221 and the second source / drain region 222 are the same.

[0088] Please refer to Figure 11 , an interlayer dielectric layer 223 is formed on the surface of the substrate 200 and the surface of the first fin 212. The interlayer dielectric layer 223 also covers the sidewalls of the first dummy gate 220 and exposes the top surface of the first dummy gate 220.

[0089] The interlayer dielectric layer 223 is used to isolate metal interconnections from devices in subsequent device manufacturing processes, reduce the parasitic capacitance between the metal and the substrate, and improve the parasitic field-effect transistors formed when the metal spans different regions.

[0090] The material of the interlayer dielectric layer 208 includes silicon oxide.

[0091] In this embodiment, the method for forming the interlayer dielectric layer 223 includes: using chemical vapor deposition to form an interlayer dielectric material layer on the surface of the substrate 200, and the interlayer dielectric material layer also lies on the sidewalls and surface of the dummy gate 220, and using chemical mechanical polishing to planarize the interlayer dielectric material layer until the top surface of the dummy gate 220 is exposed.

[0092] Please refer to Figure 12 , the first dummy gate 220 is removed, and a first gate opening 224 is formed in the interlayer dielectric layer 223; the first sacrificial layer 215 exposed at the bottom of the first gate opening 224 is removed, and a first groove 225 is formed between the first channel layers 216 exposed in the first gate opening 224.

[0093] The process of removing the dummy gate 220 includes a wet etching process. In this embodiment, the process of removing the dummy gate 220 is a wet etching process. The method for removing the dummy gate 220 includes: the solution used includes tetramethylammonium hydroxide or potassium hydroxide solution, so that during the etching process of removing the dummy gate 220, the dummy gate 220 has a large etching selectivity with respect to the interlayer dielectric 223 and the first isolation structure 218.

[0094] The process of removing the first sacrificial layer 215 exposed at the bottom of the gate opening 224 includes a wet etching process.

[0095] Please refer to Figure 13, a first gate 226 is formed within the first gate opening 224 and the first groove 225 on the first region 210.

[0096] The material of the first gate 226 includes metal.

[0097] The formation process of the first gate 226 is an atomic layer deposition process. The atomic layer deposition process has good step coverage, enabling good filling of the gate opening.

[0098] Figures 14 to 28 It is a schematic cross-sectional structure diagram corresponding to each step in the method for forming a semiconductor structure according to another embodiment of the present invention.

[0099] Please refer to Figure 14 , a substrate 300 is provided. The substrate 300 includes an initial first region 301 and an initial second region 302; a composite layer 304 is formed on the substrate 300. The composite layer 304 includes several overlapping initial sacrificial layers 305 and initial channel layers 306 located between adjacent two initial sacrificial layers.

[0100] The substrate 300 further includes a substrate 303. The material of the substrate 300 includes single crystal silicon.

[0101] The initial first region 301 is used to form the first region and the first bottom structure of the first fin portion on the first region; the initial second region 302 is used to form the second region and the second bottom structure of the second fin portion on the second region.

[0102] The composite layer 304 is used to form the first fin portion and the second fin portion.

[0103] The material of the initial sacrificial layer 305 is different from that of the initial channel layer 306. The initial channel layer 306 is used to form the first channel layer and the second channel layer, and is used to form the source-drain region and the channel region of the device. The initial sacrificial layer 305 is used to form the first sacrificial layer and the second sacrificial layer subsequently, and the first sacrificial layer and the second sacrificial layer will be removed subsequently. The material of the initial sacrificial layer 305 has a higher etching selectivity ratio relative to the material of the initial channel layer 306, so that the influence on the first sacrificial layer and the second sacrificial layer is smaller when the first sacrificial layer and the second sacrificial layer are removed subsequently; the material of the initial sacrificial layer 305 has better lattice matching relative to the material of the initial channel layer 306 to obtain a smooth interface between the initial sacrificial layer 305 and the initial channel layer 306, making the surfaces of the first channel layer and the second channel layer formed subsequently flat, which is beneficial to obtaining a device with good performance.

[0104] The material of the initial sacrificial layer 305 includes silicon; the material of the initial channel layer 306 includes silicon germanium. In this embodiment, the material of the initial sacrificial layer 305 is silicon; the material of the initial channel layer 306 is silicon germanium. In other embodiments, the initial channel layer 205 is Ge or GeSi. In other embodiments, the material of the initial sacrificial layer 305 may be ZnS, ZnSe, BeS, GaP, etc.

[0105] In this embodiment, it further includes: forming a hard mask layer 307 on the surface of the composite layer 304, and the material of the hard mask layer 307 is silicon oxide. In other embodiments, the material of the hard mask layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride or silicon carbon oxynitride. The hard mask layer 307 is used to protect the composite layer 304 to avoid damage to the composite layer 304 during subsequent etching and other processes on the surface of the composite layer 304. The material of the hard mask layer 307 is different from the material of the subsequent formed first sidewall, and the material of the first sidewall has a larger etching selectivity ratio than the hard mask material, so as to avoid the hard mask layer being etched away during the subsequent etching process of forming the first sidewall.

[0106] In this embodiment, the uppermost layer of the composite layer 304 is the initial channel layer 306. In other embodiments, the uppermost layer of the composite layer is the initial sacrificial layer.

[0107] Subsequently, a plurality of sidewall structures are formed on the surface of the composite layer 304 on the initial first region 301. The sidewall structure includes two separate first sidewalls, and the sidewall structure further includes a third sidewall located on the sidewalls of the first sidewalls; a plurality of second sidewalls are formed on the surface of the composite layer 304 on the initial second region 302. In other embodiments, the sidewall structure only includes the first sidewall and does not include the third sidewall. The formation method of the second sidewall and the sidewall structure refers to Figures 15 to 18 .

[0108] Please refer to Figure 15 , forming a plurality of first core layers 308 on a part of the composite layer 304; forming a first sidewall material layer on the sidewalls of the first core layer 308 and the composite layer 304; back-etching the first sidewall material layer to expose the surface of the composite layer and the surface of the first core layer, forming a first core layer structure 310, and the first core layer structure 310 includes the first core layer 308 and two first sidewalls 309 on the sidewalls of the first core layer.

[0109] The material of the first core layer 310 includes amorphous silicon. In this embodiment, the material of the first core layer 308 is amorphous silicon.

[0110] The material of the first axial layer 310 is different from that of the first sidewall 309.

[0111] The material of the first axial layer 310 is different from the material on the surface of the composite layer 304.

[0112] In this embodiment, the surface of the composite layer 304 is a hard mask layer 307, the material on the surface of the composite layer 304 is silicon oxide, and the material of the first axial layer 308 is amorphous silicon. Subsequently, the first axial layer 308 needs to be removed, and two first sidewalls on the sidewalls of the first axial layer are retained. To avoid damage to the materials of the first sidewall and the surface of the composite layer 304, during the process of etching and removing the first axial layer 308, the material of the first axial layer 308 needs to have a larger etching selectivity ratio compared to the material on the surface of the composite layer 304; the material of the first axial layer 308 has a larger etching selectivity ratio compared to the first sidewall 309.

[0113] The material of the first sidewall 309 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, or silicon carbon oxynitride. In this embodiment, the material of the first sidewall 309 is silicon nitride.

[0114] In this embodiment, the first axial layer structure 310 is also located on a partial surface of the composite layer 304 in the initial second region 302. The first axial layer structure 310 is used to form the first sidewall and the second sidewall. Subsequently, the first axial layer 308 on the composite layer 304 in the initial second region 302 is removed, and the second sidewall is formed on the surface of the composite layer 304 in the initial second region 302. In other embodiments, a second axial layer is formed on the surface of the composite layer in the initial second region. A second sidewall material layer is formed to cover the second axial layer and the surface of the composite layer; the second sidewall material layer is etched back to expose the surface of the composite layer and the surface of the second axial layer; the second axial layer is removed to form the second sidewall.

[0115] Please refer to Figure 16 , after forming the first axial layer structure 310, a first auxiliary layer 311 is formed on the surface of the composite layer 304, and the first auxiliary layer 311 is also located on the sidewalls of the first axial layer structure 310; the first axial layer 308 on the surface of the composite layer 304 in the initial first region 301 is removed, and a trench 312 is formed in the first sidewall 309.

[0116] The material of the first auxiliary layer 311 includes amorphous carbon or photoresist. In this embodiment, the material of the first auxiliary layer 311 is amorphous carbon.

[0117] The material of the first auxiliary layer 311 is different from the material on the surface of the composite layer 304. The material of the first auxiliary layer 311 is different from the material of the first central axis layer structure 310. The material of the first auxiliary layer 311 is different from the material of the second sidewall.

[0118] Subsequently, it is necessary to remove the first auxiliary layer 311 and retain the second sidewall and the third central axis layer structure on the surface of the composite layer 304. To avoid damage to the material on the surface of the composite layer 304, the second sidewall, and the third central axis layer structure, during the process of removing the first auxiliary layer 311, the material of the first auxiliary layer 311 has a relatively large etching selectivity ratio with respect to the material of the third central axis layer structure; the first auxiliary layer 311 has a relatively large etching selectivity ratio compared to the material on the surface of the composite layer 304; the first auxiliary layer 311 has a relatively large etching selectivity ratio compared to the second sidewall.

[0119] In this embodiment, the surface of the composite layer 304 is a hard mask layer 307, the material on the surface of the composite layer 304 is silicon oxide, and the material of the first auxiliary layer 311 is amorphous carbon.

[0120] The process of removing the first central axis layer 308 on the surface of the composite layer 304 in the initial first region 301 includes one or both of dry etching and wet etching. In this embodiment, the process of removing the first central axis layer 308 on the surface of the composite layer 304 in the initial first region 301 is wet etching.

[0121] Please refer to Figure 17 , and a third sidewall 313 is formed on the sidewall of the trench 312.

[0122] The sidewall structure 314 further includes a third sidewall 313 on the sidewall of the first sidewall 309.

[0123] The sidewall structure 314 is used as a mask subsequently to form the first fin on the first region 301.

[0124] The method for forming the third sidewall 313 is: covering the surface of the first auxiliary layer 311, the surface of the first central axis layer structure 310, and the surface of the trench 312 to form a third sidewall material layer, and etching the third sidewall material layer until the surface of the first auxiliary layer 311, the surface of the first central axis layer structure 310, and the bottom surface of the trench 312 are exposed.

[0125] The process of etching the third sidewall material layer includes a dry etching process.

[0126] The material of the third sidewall 313 is an insulating dielectric material; the material of the third sidewall includes one or more of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride. In this embodiment, the material of the third sidewall 313 is SiN.

[0127] Please refer to Figure 18 , a third central layer 315 is formed in the trench, and a third central layer structure is formed with the third central layer 315 and the sidewall structure 314; after forming the third central layer structure, the first auxiliary layer 311 is removed; the first central layer 308 on the initial second region 302 is removed, and the second sidewall 316 is formed on the surface of the composite layer 304 on the initial second region 302.

[0128] The material of the third central layer 315 includes silicon carbide.

[0129] Subsequently, the third central layer 315 will be removed, while the sidewall structure 314 on the surface of the composite layer 304 is retained. To prevent the materials on the surface of the composite layer 304 and the sidewall structure 314 from being damaged during the removal of the third central layer 315, the material of the third central layer 315 is different from the material on the surface of the composite layer 304; the material of the third central layer 315 is different from the material of the sidewall structure 314. During the removal of the third central layer 315, the material of the third central layer 315 has a larger selectivity ratio compared to the material on the surface of the composite layer 304, and the third central layer 315 has a larger selectivity ratio compared to the sidewall structure 314.

[0130] The process of removing the first auxiliary layer 311 includes one or both of dry etching and wet etching processes.

[0131] The process of removing the first central layer 308 on the initial second region 302 includes one or both of dry etching and wet etching processes.

[0132] In this embodiment, the process of removing the first auxiliary layer 311 is dry etching, the process of removing the first central layer 308 is dry etching, and the first auxiliary layer 311 and the first central layer 308 are removed by etching in two steps. In other embodiments, the first auxiliary layer 311 and the first central layer 308 are removed simultaneously.

[0133] Please refer to Figure 19 , using the second sidewall 316 as a mask to etch the composite layer 304 and the initial second region 302 to form the second region 317 and the second fin 318 on the second region 317 (as Figure 18 shown).

[0134] The second fin portion 318 includes a second bottom structure 320 located on the second region 317, a plurality of overlapping second sacrificial layers 321 located on the second bottom structure 320, and second channel layers 322 located between adjacent two layers of the second sacrificial layers 321.

[0135] In this embodiment, a second hard mask layer 323 is further provided between the second fin portion 318 and the second sidewall 316.

[0136] The process of etching the composite layer 304 and the initial first region 301 is a dry etching process.

[0137] In this embodiment, it further includes: etching the composite layer 304 and the initial first region 301 using the third axis layer structure as a mask to form an initial first fin portion 319. The initial first fin portion 319 and the second fin portion 318 are formed simultaneously. The initial first fin portion 319 is used for forming the first fin portion subsequently, and the first fin portion is formed after the second fin portion is formed. In other embodiments, the second fin portion and the first fin portion are formed simultaneously.

[0138] The hard mask layer 306 on the initial first region 301 is etched to form an initial first hard mask layer 324.

[0139] The initial first region 301 is etched to form a transition first region 325.

[0140] In other embodiments, before forming the second fin portion, the first axis layer 315 on the surface of the composite layer 304 on the initial first region 301 is removed, and the composite layer 304 is etched simultaneously using the sidewall structure 314 and the second sidewall 316 as masks to form the first fin portion and the second fin portion.

[0141] Please refer to Figure 20 , a second auxiliary layer 326 is formed on the surface of the substrate 300, and the second auxiliary layer 326 also locates on the sidewalls of the second fin portion 318 and the initial first fin portion 319 (as Figure 19 shown).

[0142] The material of the second auxiliary layer 326 is different from that of the substrate 300.

[0143] The material of the second auxiliary layer 326 is different from that of the composite layer 304.

[0144] The material of the second auxiliary layer 326 includes amorphous carbon or photoresist.

[0145] The second auxiliary layer 326 is used to protect the second fin 318 during the etching for forming the first fin. After the first fin is formed, the second auxiliary layer 326 needs to be removed. During the process of removing the second auxiliary layer 326, the substrate 300 and the composite layer 304 need to be protected. Therefore, the material of the second auxiliary layer 326 is different from that of the substrate 300 and the composite layer 304. During the etching process of removing the second auxiliary layer 326, the second auxiliary layer 326 has a relatively large selectivity with respect to the substrate 300, and the second auxiliary layer 326 has a relatively large selectivity with respect to the composite layer 304.

[0146] Please refer to Figure 21 , remove the third axial layer 315, and etch the initial first fin 319 using the sidewall structure as a mask. In the initial first fin 319 (as Figure 19 shown), form the first opening 327 to form the first fin 328.

[0147] The process of removing the third axial layer 315 includes one or both of dry etching and wet etching. In this embodiment, the process of removing the third axial layer 315 is wet etching.

[0148] The first fin 328 includes a first bottom structure 329 located on the first region 332, a plurality of overlapping first sacrificial layers 330 located on the first bottom structure 329, and a first channel layer 331 located between two adjacent first sacrificial layers 330.

[0149] The transition first region 325 is etched to form the first region 332.

[0150] In this embodiment, the initial first hard mask layer 324 is etched to form the first hard mask layer 333, and there is a first hard mask layer 333 between the first fin 328 and the sidewall structure 314.

[0151] Please refer to Figure 22 , form a first isolation structure 334 in the first opening 327; after forming the first isolation structure 334, remove the second auxiliary layer 326; after removing the second auxiliary layer 326, form the second isolation structure 335.

[0152] In this embodiment, the first isolation structure 334 is used as an isolation device for PMOS devices and NMOS devices, and a P-type doped region and an N-type doped region will be formed on both sides of the first isolation structure 334 subsequently.

[0153] The second isolation structure 335 covers the sidewalls of the first bottom structure 329 of the first fin 328, and the second isolation structure 335 also covers the sidewalls of the second bottom structure 320 of the second fin 318.

[0154] The material of the first isolation structure 334 is an insulating dielectric material. In this embodiment, the material of the first isolation structure 334 is silicon oxide. In other embodiments, the material of the first isolation structure is an insulating dielectric material such as silicon nitride.

[0155] The material of the second isolation structure 335 is an insulating dielectric material. In this embodiment, the material of the second isolation structure 335 is silicon oxide. In other embodiments, the material of the second isolation structure is an insulating dielectric material such as silicon nitride.

[0156] The first isolation structure 334 and the second isolation structure 335 are used for electrical isolation of different devices.

[0157] The forming process of the first isolation structure 334 includes an HDP CVD (high density plasma chemical vapor deposition) process. The HDP CVD process uses a high-density ion plasma to bombard and sputter etch to prevent premature closing of the first opening 327 during chemical vapor deposition and to avoid voids in the first opening 327. The step coverage of HDP CVD is very good, and it can effectively fill the voids in the first opening 327.

[0158] The forming process of the second isolation structure 335 includes an HDP CVD process. The advantages of the HDP CVD process are as described above and will not be elaborated here.

[0159] The process of removing the second auxiliary layer 326 includes one or a combination of dry etching and wet etching processes. In this embodiment, the process of removing the second auxiliary layer 326 is wet etching.

[0160] Please refer to Figure 23 and reference Figure 24 and, refer to Figure 24 is Figure 23 a top view along the Y direction, forming a first dummy gate 336 across the first fin 328, the first dummy gate 336 being located on a partial top surface and a partial sidewall surface of the first fin 328; forming a second dummy gate 337 across the second fin 318, the second dummy gate 337 being located on a partial top surface and a partial sidewall surface of the second fin 318.

[0161] In this embodiment, before forming the first dummy gate 336 and the second dummy gate 337, it further includes: removing the second sidewall 316 and the second hard mask layer 323; removing the sidewall structure 314 and the first hard mask layer 333. In other embodiments, the first hard mask layer and the second hard mask layer are retained, and only the sidewall structure and the second sidewall are removed; or the sidewall structure, the first hard mask layer, the second sidewall, and the second hard mask layer are all retained.

[0162] In this embodiment, the top of the first dummy gate 336 is flush with the top surface of the first isolation structure 334. In other embodiments, the first dummy gate straddles two adjacent first fin portions and covers a part of the surface of the first isolation structure 334.

[0163] In this embodiment, the first dummy gate 336 and the second dummy gate 337 are formed simultaneously, and the forming method includes: forming a dummy gate material layer on the surface of the substrate 300, and the dummy gate material layer also covers the tops and sidewalls of the first fin portion 328 and the second fin portion 318; forming a patterned layer on the surface of the dummy gate material layer, and the patterned layer exposes the surface of the substrate 300 and exposes the tops and sidewalls of a part of the first fin portion 328 and the second fin portion 318; etching the dummy gate material layer with the patterned layer to form the first dummy gate 336 and the second dummy gate 337.

[0164] The materials of the first dummy gate 336 and the second dummy gate 337 include silicon. In this embodiment, the materials of the first dummy gate 336 and the second dummy gate 337 are polysilicon.

[0165] Please refer to Figure 23 and refer to Figure 25 and, refer to Figure 25 is Figure 23 is a top view along the Y direction. A first source / drain region 338 is formed in one of the first fin portions 328 on both sides of the first dummy gate 336; a second source / drain region 339 is formed in the other first fin portion 328 on both sides of the dummy gate 336; a third source / drain region 340 is formed in the second fin portion 318 on both sides of the second dummy gate 337.

[0166] The doping ions in the first source / drain region 338 are N-type or P-type; the doping ions in the second source / drain region 339 are N-type or P-type; the doping ions in the third source / drain region 340 are N-type or P-type. In this embodiment, the second fin portion 318 is used to form an N-type device, and the doping ions in the third source / drain region 340 are N-type ions; P-type doping regions and N-type doping regions are respectively formed on both sides of the first isolation structure 334, the doping ions in the first source / drain region 338 are N-type ions, and the doping ions in the second source / drain region 339 are P-type ions.

[0167] Please refer to Figure 26 , an interlayer dielectric layer 341 is formed on the surface of the substrate 300 and the surface of the first fin 328. The interlayer dielectric layer 341 is also located on the sidewalls of the first dummy gate 336 and exposes the top surface of the first dummy gate 336. The interlayer dielectric layer 341 is also located on the surface of the second fin 318 and the sidewalls of the second dummy gate 337 and exposes the top surface of the second dummy gate 337.

[0168] The interlayer dielectric layer 341 is used to isolate metal interconnects from devices in subsequent device manufacturing processes, reduce the parasitic capacitance between the metal and the substrate, and improve the parasitic field-effect transistors formed when the metal spans different regions.

[0169] The material of the interlayer dielectric layer 341 includes silicon oxide.

[0170] In this embodiment, the method for forming the interlayer dielectric layer 341 includes: using chemical vapor deposition to form an interlayer dielectric material layer on the surface of the substrate 300. The interlayer dielectric material layer is also located on the sidewalls and surfaces of the first dummy gate 336 and the second dummy gate 337, and the interlayer dielectric material layer is planarized by chemical mechanical polishing until the top surfaces of the first dummy gate 336 and the second dummy gate 337 are exposed.

[0171] Please refer to Figure 27 , the first dummy gate 336 is removed to form a first gate opening 342 in the interlayer dielectric layer 341; the second dummy gate 337 is removed to form a second gate opening 343 in the interlayer dielectric layer 341; the first sacrificial layer 330 (as shown in Figure 26 ) exposed at the bottom of the first gate opening 342 is removed, and a first groove 344 is formed between the first channel layers 331 exposed in the first gate opening 342; the second sacrificial layer 321 (as shown in Figure 26 ) exposed at the bottom of the second gate opening 343 is removed, and a second groove 345 is formed between the second channel layers 322 exposed in the second gate opening 343.

[0172] The process of removing the first dummy gate 336 and the second dummy gate 337 includes a wet etching process. In this embodiment, to save processes, the first dummy gate 336 and the second dummy gate 337 are removed simultaneously, and the process of removing the first dummy gate 336 and the second dummy gate 337 is a wet etching process. The method for removing the first dummy gate 336 and the second dummy gate 337 includes: the solution used includes tetramethylammonium hydroxide or potassium hydroxide solution, so that in the etching process of removing the dummy gate 336, the first dummy gate 336 and the second dummy gate 337 can have a large selectivity ratio.

[0173] The process of removing the first sacrificial layer 330 exposed at the bottom of the first gate opening 342 and removing the second sacrificial layer 321 exposed at the bottom of the second gate opening 343 includes a wet etching process. In this embodiment, the first sacrificial layer 330 and the second sacrificial layer 321 are etched and removed using the same process, reducing the process steps and saving production costs. During the etching process, the first sacrificial layer 330 and the second sacrificial layer 321 have a large selectivity ratio, which can protect the first channel layer 331 and the second channel layer 322 from damage.

[0174] The first groove 344 is formed after the removal of the first sacrificial layer 330 and occupies the position of the original first sacrificial layer 330. In this embodiment, the first groove 344 is also located between the first channel layer 331 and the first bottom structure 329.

[0175] Please refer to Figure 28 , a first gate 346 is formed in the first gate opening 342 and the first groove 344 on the first region 332; a second gate 347 is formed in the second gate opening 343 and the second groove 345 on the second region 317.

[0176] The materials of the first gate 346 and the second gate 347 include metal.

[0177] The forming process of the first gate 344 and the second gate 345 is an atomic layer deposition process. The atomic layer deposition process has a good step coverage rate, enabling good filling of the gate opening.

[0178] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including an initial first region; Forming a composite layer on the substrate, the composite layer including a plurality of overlapping initial sacrificial layers and initial channel layers located between adjacent two initial sacrificial layers; Forming a plurality of sidewall structures on the surface of the composite layer over the initial first region, the sidewall structures including two discrete first sidewalls; Using the sidewall structures as a mask to etch the composite layer and the initial first region, forming a first region and two discrete first fin portions located over the first region, there being a first opening between the two first fin portions, the first fin portions including a first bottom structure located over the first region, a plurality of overlapping first sacrificial layers located on the first bottom structure, and first channel layers located between adjacent two first sacrificial layers; Forming a second isolation structure on the substrate, the second isolation structure covering sidewalls of the first bottom structure of the first fin portions; Forming a first isolation structure in the first opening, the first isolation structure completely filling the first opening.

2. The method for forming a semiconductor structure according to claim 1, wherein The method for forming the sidewall structures includes: forming a plurality of first core layers on a part of the composite layer; forming a first sidewall material layer on sidewalls of the first core layers and on the composite layer; back-etching the first sidewall material layer to expose the surface of the composite layer and the surface of the first core layers, forming a first core layer structure, the first core layer structure including the first core layers and two first sidewalls on sidewalls of the first core layers; removing the first core layers on the surface of the composite layer over the initial first region.

3. The method for forming a semiconductor structure according to claim 2, wherein The process for removing the first core layers on the surface of the composite layer over the initial first region includes one or a combination of wet etching and dry etching.

4. The method for forming a semiconductor structure according to claim 2, wherein, Comprising: The material of the first core layers is different from the material of the first sidewalls; the material of the first core layers is different from the material on the surface of the composite layer; the material of the first core layers includes amorphous silicon.

5. The method for forming a semiconductor structure according to claim 2, wherein, The substrate further includes a second region; the method for forming the semiconductor structure further includes: forming a plurality of second fin portions on the second region, the second fin portions including a second bottom structure located over the second region, a plurality of overlapping second sacrificial layers located on the second bottom structure, and second channel layers located between adjacent two second sacrificial layers.

6. The method for forming a semiconductor structure according to claim 5, wherein, The second isolation structure further covers sidewalls of the second bottom structure of the second fin portions.

7. The method for forming a semiconductor structure according to claim 6, wherein, Comprising: The material of the second isolation structure is an insulating dielectric material; The material of the second isolation structure includes silicon oxide.

8. The method for forming a semiconductor structure according to claim 5, wherein The substrate further includes an initial second region, and the composite layer is further located over the initial second region; the method for forming the second fin portions and the second region includes: forming a plurality of second sidewalls on the surface of the composite layer over the initial second region; using the second sidewalls as a mask to etch the composite layer and the initial second region, forming the second region and a plurality of discrete second fin portions located over the second region.

9. The method for forming a semiconductor structure according to claim 8, wherein The method for forming the second sidewall includes: forming a second axis layer on the surface of the composite layer in the initial second region; covering the second axis layer and forming a second sidewall material layer on the surface of the composite layer; back-etching the second sidewall material layer to expose the surface of the composite layer and the surface of the second axis layer; removing the second axis layer to form the second sidewall.

10. The method for forming a semiconductor structure according to claim 9, wherein, The process for removing the second axis layer includes one or a combination of wet etching and dry etching.

11. The method for forming a semiconductor structure as claimed in claim 8, wherein, The second sidewall is formed simultaneously with the first sidewall. The methods for forming the first sidewall and the second sidewall include: the first axis layer structure is also located on a partial surface of the composite layer in the initial second region; removing the first axis layer on the initial first region and forming the first sidewall on the surface of the composite layer in the initial first region; removing the first axis layer on the initial second region and forming the second sidewall on the surface of the composite layer in the initial second region.

12. The method for forming a semiconductor structure according to claim 8, wherein, including: The material of the second sidewall is an insulating dielectric material; the material of the second sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, or silicon carbon oxynitride.

13. The method for forming a semiconductor structure according to claim 8, wherein, The sidewall structure further includes a third sidewall located on the sidewall of the first sidewall. The method for forming the third sidewall includes: after forming the first axis layer structure, forming a first auxiliary layer on the surface of the composite layer, and the first auxiliary layer is also located on the sidewall of the first axis layer structure; removing the first axis layer on the surface of the composite layer in the initial first region and forming a trench in the first sidewall; forming the third sidewall on the sidewall of the trench.

14. The method for forming a semiconductor structure as described in claim 13, wherein, including: The material of the third sidewall is an insulating dielectric material; the material of the third sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, or silicon carbon oxynitride.

15. The method for forming a semiconductor structure according to claim 13, wherein Before forming the first fin, form the second fin. The method for forming the second fin further includes: forming a third axis layer in the trench, and forming a third axis layer structure with the third axis layer and the sidewall structure; after forming the third axis layer structure, removing the first auxiliary layer; etching the composite layer and the initial second region with the second sidewall as a mask to form the second region and the second fin on the second region.

16. The method for forming a semiconductor structure according to claim 15, wherein, including: The material of the first auxiliary layer is different from the material on the surface of the composite layer; the material of the first auxiliary layer is different from the material of the third axis layer structure; The material of the first auxiliary layer is different from the material of the second sidewall; the material of the first auxiliary layer includes amorphous carbon or photoresist.

17. The method for forming a semiconductor structure according to claim 15, wherein, The process for removing the first auxiliary layer includes one or a combination of wet etching and dry etching.

18. The method for forming a semiconductor structure according to claim 15, wherein including: The material of the third axis layer is different from the material on the surface of the composite layer; the material of the third axis layer is different from the material of the sidewall structure; The material of the third axis layer includes silicon carbide.

19. The method for forming a semiconductor structure as described in claim 15, wherein, further including: etching the composite layer and the initial first region with the third axis layer structure as a mask to form an initial first fin; Form a second auxiliary layer on the surface of the substrate, and the second auxiliary layer is also located on the sidewalls of the second fin and the sidewalls of the initial first fin; remove the third axial layer, etch the initial first fin using the sidewall structure as a mask, form the first opening in the initial first fin, and form the first fin.

20. The method for forming a semiconductor structure according to claim 19, wherein, Further included are: After forming the first isolation structure, remove the second auxiliary layer; After removing the second auxiliary layer, form the second isolation structure.

21. The method for forming a semiconductor structure as described in claim 20, wherein, The process of removing the second auxiliary layer includes one or a combination of wet etching and dry etching.

22. The method for forming a semiconductor structure according to claim 19, wherein, Included are: The material of the second auxiliary layer is different from the material of the substrate; the material of the second auxiliary layer is different from the material of the composite layer; The material of the second auxiliary layer includes amorphous carbon or photoresist.

23. The method for forming a semiconductor structure as described in claim 5, characterized in that, Further included are: Form a first dummy gate spanning the first fin, and the first dummy gate is located on a partial top surface and a partial sidewall surface of the first fin; form a first source / drain region in one of the first fins on both sides of the first dummy gate; Form a second source / drain region in the other first fin on both sides of the first dummy gate; form an interlayer dielectric layer on the surface of the substrate and the surface of the first fin, and the interlayer dielectric layer is also located on the sidewalls of the first dummy gate and exposes the top surface of the first dummy gate; remove the first dummy gate to form a first gate opening in the interlayer dielectric layer; Remove the first sacrificial layer exposed at the bottom of the first gate opening, form a first groove between the first channel layers exposed in the first gate opening; form a first gate in the first gate opening and the first groove on the first region.

24. The method for forming a semiconductor structure according to claim 23, wherein, The doping ions of the first source / drain region are N-type, and the doping ions of the second source / drain region are P-type.

25. The method for forming a semiconductor structure according to claim 23, wherein, Further included are: Form a second dummy gate spanning the second fin, and the second dummy gate is located on a partial top surface and a partial sidewall surface of the second fin; Form a third source / drain region in the second fin on both sides of the second dummy gate; The interlayer dielectric layer is also located on the surface of the second fin and the sidewalls of the second dummy gate and exposes the top surface of the second dummy gate; remove the second dummy gate to form a second gate opening in the interlayer dielectric layer; Remove the second sacrificial layer exposed at the bottom of the second gate opening, and form a second groove between the second channel layers exposed in the second gate opening; Form a second gate in the second gate opening and the second groove on the second region.

26. The method for forming a semiconductor structure according to claim 1, wherein, The material of the initial sacrificial layer is different from the material of the initial channel layer.

27. The method for forming a semiconductor structure according to claim 26, wherein, The material of the initial sacrificial layer includes silicon; the material of the initial channel layer includes germanium silicon.

28. The method for forming a semiconductor structure as claimed in claim 1, wherein, Included are: The material of the first sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxide silicon, carbon nitride silicon, or carbon oxynitride silicon.

29. The method for forming a semiconductor structure according to claim 1, wherein, Included are: The material of the first isolation structure is an insulating dielectric material; The material of the first isolation structure includes silicon oxide.

30. The method for forming a semiconductor structure according to claim 1, wherein, Further included are: Before forming the sidewall structure, form a hard mask layer on the surface of the composite layer.

31. The method for forming a semiconductor structure according to claim 30, wherein, Included are: The material of the hard mask layer is different from that of the first sidewall; the material of the hard mask layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride.

32. A semiconductor structure formed by a method of forming a semiconductor structure as described in any one of claims 1 to 31.

Images