Silicon-based adapter plate with TSV holes with different depths and preparation method of silicon-based adapter plate

Abstract

The invention provides a silicon-based adapter plate with TSV holes with different depths and a preparation method thereof, and the method comprises the steps: carrying out the first photoetching technology to form a graphical first mask layer, carrying out the etching under the assistance of the first mask layer to form a first TSV hole, and carrying out the electroplating to form a first TSV copper column; and then carrying out a second photoetching process to form a patterned second mask layer, etching to form a second TSV hole with the depth different from that of the first TSV hole under the assistance of the second mask layer, and electroplating to form a second TSV copper column. The etching and electroplating problems of the TSV holes with different depths are effectively solved through the method of two-time patterning, two-time etching and two-time electroplating; the silicon-based adapter plate is prepared from a silicon wafer and is used for embedding a silicon bridge, so that the problem of thermal stress caused by mismatching of thermal expansion coefficients between the silicon bridge and a substrate for embedding the silicon bridge can be effectively solved.

Description

Technical Field

[0001] This invention relates to a method for manufacturing an adapter board, and more particularly to a silicon-based adapter board with TSV holes of different depths for embedding silicon bridges and its preparation method. Background Technology

[0002] As semiconductor packaging technology advances towards higher density and performance, substrate-embedded silicon bridge (BIP) packaging technology has garnered widespread attention due to its significant interconnect advantages. BIP packaging embeds small silicon bridges or other devices within a substrate, achieving electrical connections through interconnects within the substrate. This effectively shortens signal transmission paths, reduces package size, and ultimately meets the demands for higher density, better heat dissipation, and stronger performance interconnects. Traditional adapters used for BIP silicon bridges are mostly made of organic substrates. During high-density integration, heat concentration can occur because the mismatch in thermal expansion coefficients between the organic substrate and the silicon bridge can cause stress deformation, severely impacting structural reliability.

[0003] Therefore, adapting traditional organic substrates to silicon-based interposers can effectively reduce thermal stress problems caused by the mismatch of material thermal expansion coefficients. However, fabricating through-silicon vias (TSVs) of different depths on silicon-based interposers is often difficult, posing a challenge to both etching and electroplating. Therefore, developing new methods to fabricate silicon-based interposers with TSVs of different depths for silicon bridge embedding is of great significance. Summary of the Invention

[0004] To address the problems of the prior art, this invention provides a silicon-based adapter board with TSV holes of different depths and its preparation method, effectively solving the problems of etching and electroplating of silicon-based adapter boards with TSV holes of different depths.

[0005] This invention is achieved through the following technical solution: In a first aspect, the present invention provides a method for fabricating a silicon-based adapter plate with TSV vias of different depths, comprising the following steps: S1, a patterned first mask layer is formed on the first surface of a silicon wafer using a photolithography process; S2, using the first mask layer as a mask, patterning is performed on the first surface of the silicon wafer to obtain the first TSV hole; the first TSV hole is a blind hole; S3, remove the first mask layer, and fill the first TSV hole with copper using an electroplating process to obtain the first TSV copper pillar; S4, a patterned second mask layer is formed on the first surface of the silicon wafer through photolithography; S5, using the second mask layer as a mask, patterned etching is performed on the first surface of the silicon wafer to obtain the second TSV hole; the second TSV hole is a blind hole, and the depth of the second TSV hole is less than the depth of the first TSV hole; S6, remove the second mask layer, and fill the second TSV hole with copper by electroplating to obtain the second TSV copper pillar; S7, a patterned third mask layer is formed on the second surface of the silicon wafer using a photolithography process; the second surface of the silicon wafer is opposite to the first surface of the silicon wafer, and the area of ​​the third mask layer corresponds to the area of ​​the first TSV copper pillar; S8, etch the second surface of the silicon wafer until the second surface of the silicon wafer is flush with the second TSV copper pillar, to obtain a silicon-based adapter board with TSV holes of different depths.

[0006] Preferably, in S2, the first surface of the silicon wafer is patterned using the Bosch etching process.

[0007] Preferably, in S5, the first surface of the silicon wafer is patterned using the Bosch etching process.

[0008] Preferably, in S8, the second surface of the silicon wafer is patterned using the Bosch etching process.

[0009] Preferably, S3 specifically involves: cleaning the first TSV hole, depositing a dielectric layer on the inner wall of the first TSV hole using ALD, depositing an adhesion layer and a seed layer using PVD, and then filling it with copper using an electroplating process to obtain the first TSV copper pillar.

[0010] Preferably, S6 specifically involves: cleaning the second TSV hole, depositing a dielectric layer on the inner wall of the second TSV hole using ALD, depositing an adhesion layer and a seed layer using PVD, and then filling it with copper using an electroplating process to obtain the second TSV copper pillar.

[0011] Preferably, after S3 and before S4, the method further includes: removing copper from the first surface of the silicon wafer; after S6 and before S7, the method further includes: removing copper from the second surface of the silicon wafer.

[0012] Furthermore, copper on the first and second surfaces of the silicon wafer is removed by CMP.

[0013] Preferably, in S3, a dry adhesive removal process is used to remove the first mask layer; in S6, a dry adhesive removal process is used to remove the second mask layer.

[0014] Secondly, the present invention provides a silicon-based adapter board with TSV holes of different depths, comprising: a silicon wafer, on which a first TSV hole and a second TSV hole are formed, the first TSV hole being filled with a first TSV copper pillar, and the second TSV hole being filled with a second TSV copper pillar; wherein, one end face of the first TSV copper pillar and the second TSV copper pillar are flush with a first surface of the silicon wafer, the other end face of the second TSV copper pillar is flush with a second surface of the silicon wafer, and the other end of the first TSV copper pillar extends beyond the second surface of the silicon wafer; the second surface of the silicon wafer is opposite to the first surface of the silicon wafer.

[0015] Compared with the prior art, the present invention has the following beneficial effects: This invention first performs a photolithography process to form a patterned first mask layer. With the assistance of this first mask layer, a first TSV hole is etched and then electroplated to form a first TSV copper pillar. Then, a second photolithography process is performed to form a patterned second mask layer. With the assistance of this second mask layer, a second TSV hole with a different depth than the first TSV hole is etched and then electroplated to form a second TSV copper pillar. Therefore, this invention effectively solves the problems of etching and electroplating TSV holes of different depths by using a two-step patterning, two-step etching, and two-step electroplating method. This invention uses silicon wafers to fabricate a silicon-based interposer plate for silicon bridge embedding, which can effectively reduce the thermal stress problem caused by the mismatch of thermal expansion coefficients between the silicon bridge and the substrate used for silicon bridge embedding. At the same time, the silicon-based interposer plate can effectively avoid the problem of heat deformation and warping of the organic substrate. Compared with the fabrication of organic interposers using temporary glass substrates, this invention uses a silicon-based interposer plate for silicon bridge embedding, reducing the use of glass substrates, resulting in lower manufacturing costs and higher efficiency.

[0016] Furthermore, this invention employs the Bosch etching process to prepare TSV holes. The Bosch etching process, through alternating etching and passivation cycles, can achieve vertical etching of deep holes, avoiding the lateral drilling of wet etching. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a silicon wafer; Figure 2 A schematic diagram of forming a patterned first mask layer on a silicon wafer; Figure 3 This is a schematic diagram of etching the first TSV hole on a silicon wafer. Figure 4 A schematic diagram of electroplating and filling the first TSV copper pillar in the first TSV hole; Figure 5 A schematic diagram showing the formation of a patterned second mask layer on a silicon wafer; Figure 6 This is a schematic diagram of etching a second TSV hole on a silicon wafer. Figure 7 A schematic diagram of electroplating and filling the second TSV copper pillar inside the second TSV hole; Figure 8 A schematic diagram illustrating the formation of a patterned third mask layer on a silicon wafer; Figure 9 A schematic diagram of a silicon-based adapter board with TSV holes of different depths and diameters; Figure 10 This is a schematic diagram showing the interconnection of a 3D silicon bridge with a through-hole structure to a second TSV copper pillar via microbumps. Figure 11 This is a schematic diagram of the plastic encapsulation of a 3D silicon bridge interconnected with a silicon-based adapter board; Figure 12 This is a schematic diagram illustrating the thinning of the molding compound. Figure 13 A schematic diagram of the formation of an RDL layer; Figure 14 This is a schematic diagram showing the interconnection between the RDL layer and the chip via microbumps. Figure 15 A schematic diagram showing the filling at the bottom of the chip; Figure 16 This is a schematic diagram of the chip encapsulation process. Figure 17 This is a schematic diagram illustrating the process of thinning the molding compound on a chip and coating it with TIM adhesive. Figure 18 A schematic diagram for preparing solder bumps.

[0019] Wherein, 1-silicon wafer, 2-first mask layer, 3-first TSV hole, 4-first TSV copper pillar, 5-second mask layer, 6-second TSV hole, 7-second TSV copper pillar, 8-third mask layer, 9-silicon bridge, 10-molding compound, 11-RDL layer, 12-chip, 13-microbump, 14-TIM adhesive, 15-solder bump. Detailed Implementation

[0020] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0021] It should be noted that the process equipment or apparatus not specifically mentioned in the following embodiments are all conventional equipment or apparatus in the art.

[0022] It should be noted that the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. Furthermore, unless otherwise stated, the numbering of each method step is merely a convenient tool for identifying each method step, and not intended to limit the order of the method steps or define the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention.

[0023] Furthermore, it should be noted that the terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein.

[0024] The method for fabricating a silicon-based adapter plate with TSV vias of different depths according to the present invention includes the following steps: S1, a patterned first mask layer is formed on the first surface of a silicon wafer using a photolithography process; S2, using the first mask layer as a mask, patterning is performed on the first surface of the silicon wafer to obtain the first TSV hole; the first TSV hole is a blind hole; S3, remove the first mask layer, and fill the first TSV hole with copper using an electroplating process to obtain the first TSV copper pillar; S4, a patterned second mask layer is formed on the first surface of the silicon wafer through photolithography; S5, using the second mask layer as a mask, patterned etching is performed on the first surface of the silicon wafer to obtain the second TSV hole; the second TSV hole is a blind hole, and the depth of the second TSV hole is less than the depth of the first TSV hole; S6, remove the second mask layer, and fill the second TSV hole with copper by electroplating to obtain the second TSV copper pillar; S7, a patterned third mask layer is formed on the second surface of the silicon wafer using a photolithography process; the second surface of the silicon wafer is opposite to the first surface of the silicon wafer, and the third mask layer corresponds to the first TSV copper pillar; S8, etch the second surface of the silicon wafer until the second surface of the silicon wafer is flush with the second TSV copper pillar, to obtain a silicon-based adapter board with TSV holes of different depths.

[0025] In this invention, the photolithography process in S1, S4 and S7 can be a conventional photolithography process, specifically: first, a photoresist is coated, then exposed and developed to form a patterned mask layer.

[0026] In some preferred embodiments of the present invention, in step S2, the first surface of the silicon wafer is patterned using a Bosch etching process. The Bosch etching process for deep silicon etching includes a passivation step and an etching step, wherein the passivation step uses C4F8 gas and the etching step uses SF6 gas. The passivation step process conditions are: pressure: 5mT~200mT, C4F8 flow rate: 100sccm~400sccm, bias power: 0W~1160W, inductively coupled plasma power: 1200W~4800W, duty cycle: 20-80%, current ratio: 20%~80%, time: 0.3s-5s. The etching process conditions are as follows: pressure: 5mT~200mT, SF6 flow rate: 200sccm~800sccm, bias power: 0W~1160W, inductively coupled plasma power: 1200W~4800W, duty cycle: 20-80%, current ratio: 20%~80%, time: 0.3s-5s.

[0027] In some preferred embodiments of the present invention, S3 specifically involves: removing the first mask layer; cleaning and drying the residue inside the first TSV hole using a deep hole cleaning machine at room temperature with a cleaning solution and megasonic (or ultrasonic) cleaning method, adjusting the cleaning time according to different hole types; depositing a dielectric layer on the inner wall of the first TSV hole using atomic layer deposition (ALD) process, depositing an adhesion layer and a seed layer using physical vapor deposition (PVD) process, and then filling with copper using an electroplating process to obtain the first TSV copper pillar. Specifically, an adhesion layer and a seed layer are deposited using the PVD process; particularly, the adhesion layer is Ti, and the seed layer is Cu. The dielectric layer provides insulation, the adhesion layer effectively connects the dielectric layer and the seed layer and prevents the migration of copper atoms, and the seed layer provides a seed for subsequent ultra-deep hole copper electroplating.

[0028] The electroplating process conditions used in this invention are as follows: the first TSV hole is pre-vacuumed (25 torr-50 torr), water is injected for pre-wetting of the hole, and after pre-wetting, a 4-step electroplating process is carried out. The electroplating solution is at room temperature, and the circulation flow rate is 15-28 L / min. Specifically, the current density is as follows: the first step is 0 ASD / min; the second step is 0.05 ASD; the third step is 0.07 ASD; and the fourth step is 0.09 ASD. The time for the second to fourth steps is adjusted according to the different hole depths. In some preferred embodiments of the present invention, in S5, the Bosch etching process is used to pattern the first surface of the silicon wafer; in S8, to prevent etching of the copper pillar sidewalls, the Bosch etching process is still used to pattern the second surface of the silicon wafer. The conditions of the Bosch etching process in S5 and S8 can be the same as the conditions of the Bosch etching process in S2.

[0029] In some preferred embodiments of the present invention, S6 specifically involves: cleaning the second TSV hole, depositing a dielectric layer on the inner wall of the second TSV hole using an ALD process, depositing an adhesive layer and a seed layer using a PVD process, and then filling it with copper using an electroplating process to obtain the second TSV copper pillar.

[0030] In some preferred embodiments of the present invention, after S3 and before S4, the method further includes: removing copper from the first surface of the silicon wafer; after S6 and before S7, the method further includes: removing copper from the second surface of the silicon wafer. Specifically, chemical mechanical planarization (CMP) can be used to remove copper from the first and second surfaces of the silicon wafer.

[0031] In some preferred embodiments of the present invention, in S3, a dry adhesive removal process is used to remove the first mask layer; in S6, a dry adhesive removal process is used to remove the second mask layer.

[0032] In S8 of this invention, when the silicon wafer in the area not covered by the third mask layer is etched using the third mask layer as a mask, the third mask layer itself will also be consumed; after the third mask layer is completely consumed, the silicon wafer in the area covered by the third mask layer will also be etched, and finally a silicon-based adapter board is obtained.

[0033] In this invention, the depth of the first TSV via is 50-300 micrometers, and the depth of the second TSV via is 50-100 micrometers. The first TSV copper pillar is used to achieve 3D interconnection, while the second TSV copper pillar is used to interconnect with embedded functional chips. Both simultaneously achieve heterogeneous integration of multiple chips.

[0034] The silicon-based adapter board with different depths of TSV holes obtained by the above method of the present invention includes: a silicon wafer, on which a first TSV hole and a second TSV hole are formed, the first TSV hole is filled with a first TSV copper pillar, and the second TSV hole is filled with a second TSV copper pillar; wherein, one end face of the first TSV copper pillar and the second TSV copper pillar are flush with the first surface of the silicon wafer, the other end face of the second TSV copper pillar is flush with the second surface of the silicon wafer, and the other end of the first TSV copper pillar extends out of the second surface of the silicon wafer.

[0035] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0036] Example (1) The cleaned silicon wafer 1 ( Figure 1 The first surface of the first mask is used to prepare a patterned first mask layer 2 (e.g., by applying photoresist, exposing, and developing) through a photolithography process. Figure 2 (As shown); the thickness of silicon wafer 1 is 775 micrometers; (2) Using the Bosch etching process, the first surface of the silicon wafer 1 is patterned and etched using the first mask layer 2 as a mask, to obtain the following: Figure 3 The first TSV hole 3 shown has a depth of 300 micrometers and a diameter of 20 micrometers. The residual photoresist on the surface is removed using a dry photoresist removal process. (3) The residue in the first TSV hole was cleaned and dried using a deep hole cleaning machine at room temperature with a cleaning solution and ultrasonic cleaning method; after cleaning the first TSV hole 3, a dielectric layer was deposited on the inner wall of the first TSV hole 3 using the ALD process, an adhesion layer and a seed layer were deposited using the PVD process, and then copper was filled using the electroplating process to obtain the following result. Figure 4 The first TSV copper pillar 4 is shown; (4) Remove the copper from the first surface of silicon wafer 1 by CMP, then coat the first surface of silicon wafer 1 with photoresist, expose and develop it to prepare a patterned second mask layer 5 (e.g., Figure 5 (as shown) (5) Using the Bosch etching process, the first surface of the silicon wafer 1 is patterned and etched using the second mask layer 5 to obtain the following: Figure 6 The second TSV hole 6 shown has a depth of 150 micrometers and a diameter of 8 micrometers. The residual photoresist on the first surface of the silicon wafer 1 is removed using a dry photoresist removal process. (6) Clean the second TSV hole 6 according to the method in step (3). After cleaning the second TSV hole 6, deposit a dielectric layer on the inner wall of the second TSV hole 6 using the ALD process, deposit an adhesion layer and a seed layer using the PVD process, and then fill the hole with copper using the electroplating process to obtain the desired result. Figure 7The second TSV copper pillar 7 is shown; (7) Photoresist is coated, exposed, and developed on the second surface of silicon wafer 1 to prepare a patterned third mask layer 8 (e.g., ...). Figure 8 As shown), to prevent etching of the copper pillar sidewalls, the Bosch etching process is still used to etch the second surface of silicon wafer 1. When etching the silicon wafer outside the area covered by the third mask layer using the third mask layer as a mask, the third mask layer itself will also be consumed; after the third mask layer is completely consumed, the silicon wafer covered by the third mask layer will also be etched, forming as shown. Figure 9 The diagram shows a silicon-based adapter board with TSV holes of different depths and diameters for embedding silicon bridges.

[0037] Semiconductor devices can be fabricated using the silicon-based adapter obtained above: such as Figure 10 As shown, the 3D silicon bridge 9 with a through-hole structure is interconnected with the second TSV copper pillar 7 via microbumps, followed by wafer-level molding (e.g., Figure 11 As shown), a molding compound is formed, and then the molding compound is thinned (as shown). Figure 12 (as shown), then prepare as follows Figure 13 The RDL (Redistribution Layer) 11 shown is interconnected with the chip 12 via microbumps 13 (e.g., ...). Figure 14 (as shown), then fill the bottom of chip 12 (as shown). Figure 15 (as shown) and plastic sealing (as shown) Figure 16 As shown), thin it again and coat it with TIM adhesive (Thermal Interface Material) 14 (as shown). Figure 17 As shown), finally, flip-mount the solder bumps 15 (as shown). Figure 18 (As shown).

Claims

1. A method for fabricating a silicon-based adapter board with TSV vias of different depths, characterized in that, Includes the following steps: S1, a patterned first mask layer is formed on the first surface of a silicon wafer using a photolithography process; S2, using the first mask layer as a mask, patterning is performed on the first surface of the silicon wafer to obtain the first TSV hole; the first TSV hole is a blind hole; S3, remove the first mask layer, and fill the first TSV hole with copper using an electroplating process to obtain the first TSV copper pillar; S4, a patterned second mask layer is formed on the first surface of the silicon wafer through photolithography; S5, using the second mask layer as a mask, patterning is performed on the first surface of the silicon wafer to obtain the second TSV hole; The second TSV hole is a blind hole, and the depth of the second TSV hole is less than the depth of the first TSV hole; S6, remove the second mask layer, and fill the second TSV hole with copper by electroplating to obtain the second TSV copper pillar; S7, a patterned third mask layer is formed on the second surface of the silicon wafer using a photolithography process; the second surface of the silicon wafer is opposite to the first surface of the silicon wafer, and the area of ​​the third mask layer corresponds to the area of ​​the first TSV copper pillar; S8, etch the second surface of the silicon wafer until the second surface of the silicon wafer is flush with the second TSV copper pillar, to obtain a silicon-based adapter board with TSV holes of different depths.

2. The method for fabricating a silicon-based adapter plate with TSV holes of different depths according to claim 1, characterized in that, In S2, the Bosch etching process is used to pattern the first surface of the silicon wafer.

3. The method for fabricating a silicon-based adapter plate with TSV vias of different depths according to claim 1, characterized in that, In S5, the Bosch etching process is used to pattern the first surface of the silicon wafer.

4. The method for fabricating a silicon-based adapter plate with TSV holes of different depths according to claim 1, characterized in that, In S8, the Bosch etching process is used to pattern the second surface of the silicon wafer.

5. The method for fabricating a silicon-based adapter plate with TSV holes of different depths according to claim 1, characterized in that, S3 specifically involves cleaning the first TSV hole, depositing a dielectric layer on the inner wall of the first TSV hole using ALD, depositing an adhesion layer and a seed layer using PVD, and then filling it with copper using an electroplating process to obtain the first TSV copper pillar.

6. The method for fabricating a silicon-based adapter plate with TSV holes of different depths according to claim 1, characterized in that, S6 specifically involves cleaning the second TSV hole, depositing a dielectric layer on the inner wall of the second TSV hole using ALD, depositing an adhesion layer and a seed layer using PVD, and then filling it with copper using an electroplating process to obtain the second TSV copper pillar.

7. The method for fabricating a silicon-based adapter plate with TSV vias of different depths according to claim 1, characterized in that, After S3 and before S4, the process also includes: removing copper from the first surface of the silicon wafer; after S6 and before S7, the process also includes: removing copper from the second surface of the silicon wafer.

8. The method for fabricating a silicon-based adapter plate with TSV holes of different depths according to claim 7, characterized in that, Copper is removed from the first and second surfaces of a silicon wafer by CMP.

9. The method for fabricating a silicon-based adapter plate with TSV holes of different depths according to claim 1, characterized in that, In S3, a dry adhesive removal process is used to remove the first mask layer; in S6, a dry adhesive removal process is used to remove the second mask layer.

10. A silicon-based adapter board with TSV holes of different depths, characterized in that, include: A silicon wafer has a first TSV hole and a second TSV hole. The first TSV hole is filled with a first TSV copper pillar, and the second TSV hole is filled with a second TSV copper pillar. One end face of the first TSV copper pillar and the second TSV copper pillar are flush with the first surface of the silicon wafer, and the other end face of the second TSV copper pillar is flush with the second surface of the silicon wafer. The other end of the first TSV copper pillar extends out of the second surface of the silicon wafer. The second surface of the silicon wafer is opposite to the first surface of the silicon wafer.

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