Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate including an active region; a plurality of conductive structures formed over the semiconductor substrate; an isolation layer filling spaces between the conductive structures and having openings exposing the active region between the conductive structures; a pad formed at a bottom of the openings and in contact with the active region; a plug liner conformally formed over sidewalls of the openings and exposing the pad; and a contact plug formed over the pad inside the openings.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0117593, filed on September 14, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure relate to a semiconductor device and a method for manufacturing the same. More specifically, embodiments of this disclosure relate to a semiconductor device including a memory node contact portion and a method for manufacturing the semiconductor device. Background Technology

[0004] As the integration density of semiconductor devices increases and their size shrinks, the size of contact plugs decreases. With the miniaturization of contact plugs, the aspect ratio of contact holes increases.

[0005] However, during the etching process used to form contact holes with high aspect ratios, misalignment and some contact holes may not have openings.

[0006] High aspect ratios can lead to contact hole defects, which degrade the electrical properties of semiconductor devices and make the manufacturing process of contact plugs more difficult. Summary of the Invention

[0007] The embodiments disclosed herein are dedicated to semiconductor devices with excellent electrical properties and methods for manufacturing the same.

[0008] According to one embodiment of this disclosure, a semiconductor device includes: a semiconductor substrate including an active region; a plurality of conductive structures formed on the semiconductor substrate; an isolation layer filling a space between the conductive structures and having an opening exposing the active region between the conductive structures; a pad formed in the bottom of the opening and in contact with the active region; a plug liner conformally formed on the sidewall of the opening and exposing the pad; and a contact plug formed on the pad inside the opening.

[0009] According to another embodiment of the disclosure, a semiconductor device includes a semiconductor substrate including active regions; a plurality of bit line structures formed over the semiconductor substrate; an isolation layer filling spaces between the bit line structures and having openings exposing the active regions between the bit line structures; a pad formed in a bottom of the openings and in contact with the active regions; a first spacer conformally formed on sidewalls of the openings and exposing the pad; a plug liner formed to cover a lower portion of the first spacer; a second spacer formed over the plug liner to cover an upper portion of the first spacer; and a contact plug formed over the pad inside the openings.

[0010] According to another embodiment of the disclosure, a semiconductor device includes a semiconductor substrate including active regions; a plurality of bit line structures formed over the semiconductor substrate; an isolation layer filling spaces between the bit line structures and having openings exposing the active regions between the bit line structures; a pad formed in a bottom of the openings and in contact with the active regions; a first spacer conformally formed on sidewalls of the openings and exposing the pad; a plug liner formed to cover a lower portion of the first spacer; a second spacer formed over the plug liner to cover an upper portion of the first spacer; and a contact plug formed over the pad inside the openings.

[0011] According to another embodiment of the disclosure, a semiconductor device includes a semiconductor substrate including active regions; a plurality of bit line structures formed over the semiconductor substrate; an isolation layer filling spaces between the bit line structures and having openings exposing the active regions between the bit line structures; a pad formed in a bottom of the openings and in contact with the active regions; a first spacer conformally formed on sidewalls of the openings and exposing the pad; a plug liner formed to cover a lower portion of the first spacer; a second spacer formed over the plug liner to cover an upper portion of the first spacer; and a contact plug formed over the pad inside the openings.

[0012] According to another embodiment of the disclosure, a semiconductor device includes a semiconductor substrate including active regions; a plurality of bit line structures formed over the semiconductor substrate; an isolation layer filling spaces between the bit line structures and having openings exposing the active regions between the bit line structures; a pad formed in a bottom of the openings and in contact with the active regions; a first spacer conformally formed on sidewalls of the openings and exposing the pad; a plug liner formed to cover a lower portion of the first spacer; a second spacer formed over the plug liner to cover an upper portion of the first spacer; and a contact plug formed over the pad inside the openings.

[0013] These and other advantages of the present application will become more apparent in the following description in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a plan view showing a semiconductor device according to one embodiment of the present disclosure.

[0015] Figure 2A and Figure 2B is a cross-sectional view showing an example of a semiconductor device according to one embodiment of the present disclosure.

[0016] Figure 3A and Figure 3B is a cross-sectional view showing another example of a semiconductor device according to one embodiment of the present disclosure.

[0017] Figures 4A to 4U is a cross-sectional view showing a method of manufacturing a semiconductor device by presenting a cross section taken along a line A-A' of Figure 1

[0018] Figures 5A to 5U is a cross-sectional view showing a method of manufacturing a semiconductor device by presenting a cross section taken along a line B-B' of Figure 1 DETAILED DESCRIPTION

[0019] Various embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings. However, the present disclosure can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the present disclosure, like reference numerals refer to like parts throughout the various drawings and embodiments of the present disclosure.

[0020] The drawings are not necessarily to scale and, in some instances, proportions can have been exaggerated in order to clearly convey certain features of embodiments. When a first layer is referred to as being "on" or "over" a second layer, it can mean that the first layer is directly formed on the second layer or that a third layer is present between the first layer and the second layer.

[0021] Hereinafter, in embodiments of the present disclosure, a high aspect ratio pattern can include an opening, a contact hole, a trench, and a source / drain recess. For a high aspect ratio, the ratio of height to width can be greater than about 1:1. The high aspect ratio pattern can be filled with a contact plug. The lower portion of the high aspect ratio pattern can be filled with a pad. That is, a contact plug can be formed over a pad. The pad can also be referred to as a contact pad or a landing pad.

[0022] ​​The pad can be filled with an epitaxial layer by a bottom-up growth process. The bottom-up growth process can include a selective epitaxial growth (SEG) process.

[0023] Figure 1 is a plan view showing a semiconductor device according to one embodiment of the present disclosure. Figure 2A and Figure 2B is a cross-sectional view showing an example of a semiconductor device according to one embodiment of the present disclosure.

[0024] Referring to Figure 1 , Figure 2A and Figure 2B , the semiconductor device can include a plurality of memory cells. Each memory cell can include a cell transistor including a buried word line 107, a bit line 112, and a storage element 121.

[0025] An isolation layer 102 and an active region 103 can be formed in a substrate 101. A plurality of active regions 103 can be defined by the isolation layer 102. The substrate 101 can be formed of a silicon-containing material. The substrate 101 can include silicon, single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a plurality of layers thereof. The substrate 101 can further include other semiconductor materials, such as germanium. The substrate 101 can include a III / V semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide (GaAs). The substrate 101 can include a silicon-on-insulator (SOI) substrate. The isolation layer 102 can be formed, for example, by a shallow trench isolation (STI) process.

[0026] A linear buried gate structure BG extending in a short-axis direction of the active region 103 can be formed in the substrate 101. The buried gate structure BG can include a gate dielectric layer 106 formed on a surface of a gate trench 105, a gate electrode 107 formed over the gate dielectric layer 106 to fill the gate trench 105, and a gate cap layer 108.

[0027] Specifically, a linear gate trench 105 extending in a short axis direction of the active region 103 can be formed in the substrate 101. The gate trench 105 can be formed to a predetermined depth in a region defined by the hard mask layer 104 formed on a surface of the substrate 101. A lower surface of the gate trench 105 can be located at a higher level than a lower surface of the isolation layer 102. For example, the gate trench 105 can have a shallower depth than the isolation layer 102. A bottom of the gate trench 105 can be flat. According to another embodiment of the disclosure (not shown), the bottom of the gate trench 105 can have a curvature. According to another embodiment of the disclosure, the isolation layer 102 in a direction in which the gate trench 105 extends can be etched to a predetermined depth to form a fin region Fin in the active region 103.

[0028] A gate dielectric layer 106 can be formed on a surface of the gate trench 105. A gate electrode 107 filling a portion of the gate trench 105 can be formed on the gate dielectric layer 106. A gate capping layer 108 filling a remaining portion of the gate trench 105 can be formed on the gate electrode 107. An upper surface of the gate capping layer 108 can be located at the same level as an upper surface of the hard mask layer 104. An upper surface of the gate electrode 107 can be located at a lower level than an upper surface of the substrate 101. The gate electrode 107 can be formed of a low-resistance metal material including, for example, sequentially stacked titanium nitride and tungsten. According to another embodiment of the disclosure, the gate electrode 107 can be formed of only titanium nitride. The gate electrode 107 can be referred to as a buried word line.

[0029] A first impurity region 109 and a second impurity region 110 can be formed in the substrate 101. The first impurity region 109 and the second impurity region 110 can be referred to as source / drain regions. The first impurity region 109 and the second impurity region 110 can be spaced apart from each other by the gate trench 105. The gate electrode 107 and the first impurity region 109 and the second impurity region 110 can also be referred to as a unit transistor. The unit transistor can exhibit an improved short channel effect by the gate electrode 107.

[0030] Bit line contact plugs 111 can be formed on the first impurity region 109 of the substrate 101. Bit line contact plugs 111 can be coupled to the first impurity region 109, for example, through direct contact. Bit line contact plugs 111 can be located in bit line contact holes. Bit line contact holes can expose the first impurity region 109. The lower surface of the bit line contact plug 111 can be lower than the upper surface of the substrate 101. Bit line contact plugs 111 can be formed of, for example, polysilicon or a metallic material. A portion of the bit line contact plug 111 can have a linewidth smaller than the diameter of the bit line contact hole. Therefore, gaps G can be formed on both sides of the bit line contact plug 111. Gap G can be formed independently on both sides of the bit line contact plug 111. As a result, a bit line contact plug 111 and a pair of gaps G can be located in the bit line contact hole, and the pair of gaps G can be isolated by the bit line contact plug 111. The gaps can be located between the bit line contact plug 111 and the contact plug 120.

[0031] A bitline structure BL can be formed, comprising: a bitline contact plug 111, a bitline 112 formed on the bitline contact plug 111, and a bitline hard mask 113 formed on the bitline 112. The bitline structure BL may have a linear shape extending in a direction intersecting the buried gate structure BG (i.e., in the direction of the long axis of the active region 103). A portion of the bitline 112 may be coupled to the bitline contact plug 111, for example, through direct contact. Viewed from the line A-A' direction, the bitline 112 and the bitline contact plug 111 may have the same linewidth. Therefore, the bitline 112 may extend in one direction while covering the bitline contact plug 111. The bitline 112 may comprise a metallic material. The bitline hard mask 113 may be formed of or comprise a dielectric material.

[0032] Bit line spacer 114 may be formed on the sidewall of bit line structure BL. The bottom of bit line spacer 114 may fill the gap G on both sides of bit line contact plug 111. Bit line spacer 114 may be formed of or include a dielectric material. Bit line spacer 114 may be formed of, for example, silicon oxide, silicon nitride, or a combination thereof, or include, for example, silicon oxide, silicon nitride, or a combination thereof. Bit line spacer 114 may include a NON (nitride-oxide-nitride) structure. According to another embodiment of this disclosure, bit line spacer 114 may include an air gap. For example, it may include a NAN (nitride-air gap-nitride) structure.

[0033] Viewed from a direction parallel to the bitline structure BL, a plug isolation layer 115 may be formed between adjacent contact plugs 120. The plug isolation layer 115 may be formed between adjacent bitline structures BL and may define island-shaped rectangular openings 116 that are separated from each other. The opening 116 may be a square opening defined by the bitline structure BL and the bitline isolation layer 115. The linewidth of the opening 116 from top to bottom and from left to right may be controlled by the bitline structure and the bitline spacers BL and 114.

[0034] A recess 116R may be formed in the bottom of the opening 116. The recess 116R may extend into the substrate 101. The lower surface of the recess 116R may be at a lower level than the upper surface of the substrate 101. The lower surface of the recess 116R may be at a higher level than the lower surface of the bit line contact plug 111.

[0035] A pad 117 in contact with the second source / drain region 110 can be formed in the recess 116R. The pad 117 can fill the recess 116R. The pad 117 can couple the contact plug 120 and the second impurity region 110 to each other. The pad 117 can be formed, for example, by a selective epitaxial growth process.

[0036] The pad 117 can be formed, for example, using a bottom-up growth process. The bottom-up growth process can include an epitaxial growth process. The epitaxial growth process can include a selective epitaxial growth process. The pad 117 can include a silicon-containing epitaxial layer. For example, the pad 117 can include a silicon epitaxial layer. The pad 117 can include SEG Si.

[0037] Pad 117 may include a dopant. Therefore, pad 117 may be a doped epitaxial layer. The dopant may include an N-type dopant. An N-type dopant may include phosphorus, arsenic, antimony, or a combination thereof. Pad 117 may include a phosphorus-doped silicon epitaxial layer formed by a selective epitaxial growth process, i.e., a heavily doped SEG SiP. Here, in low-concentration SEG SiP and high-concentration SEG SiP, each of low concentration and high concentration may refer to the concentration of phosphorus.

[0038] According to another embodiment of the present invention, the pad 117 may include SEG SiGe or SEG SiC doped with N-type dopant.

[0039] The recesses 116R between pads 117 can be filled using spacers 118. That is, spacers 118 can be formed on the sidewalls of bit line spacers 114. Spacers 118 can be formed of or comprise a dielectric material. Spacers 118 can be formed of, for example, silicon oxide, or comprise, for example, silicon oxide.

[0040] The plug liner 119 may be formed on the sidewall of the spacer 118. The plug liner 119 may be formed on the upper part of the pad 117. The plug liner 119 may be formed of, for example, polysilicon, or include, for example, polysilicon.

[0041] Contact plug 120 may be formed on the upper portion of pad 117. Contact plug 120 may be formed between adjacent bit line structures BL. Contact plug 120 may be formed in opening 116. Contact plug 120 may be coupled to second impurity region 110 via pad 117. Contact plug 120 may be or include conductive material. Contact plug 120 may be formed of, for example, polysilicon or metal material, or include, for example, polysilicon or metal material.

[0042] According to embodiments of this disclosure, the plug liner 119 can be used together with the contact plug 120 as a contact plug. The plug liner 119 and the contact plug 120 can be referred to as "memory node contact plugs". For example, the width of the memory node contact plug can be increased as much as the thickness of the plug liner 119 to ensure overlap margin with the subsequently formed memory element 121 and reduce contact resistance.

[0043] Storage element 121 may be formed on contact plug 120. Storage element 121 may include a capacitor containing a storage node. The storage node may be, for example, a cylindrical storage node. Although not shown, a dielectric layer and plate-type nodes may be further formed on the storage node. In one embodiment, the storage node may have a cylindrical shape. The storage node may be coupled to contact plug 120, for example, via direct contact.

[0044] According to another embodiment of this disclosure, storage elements implemented on contact plug 120 in various ways can be directly or indirectly coupled to contact plug 120.

[0045] Figure 3A and Figure 3B This is a cross-sectional view illustrating another example of a semiconductor device according to an embodiment of the present disclosure. Figure 3A and 3B The semiconductor device shown includes those having the same characteristics as... Figure 2A and 2B Different structures, including storage node contact plugs (SNCs) for semiconductor devices.

[0046] See Figure 3A and Figure 3B The semiconductor device may include multiple memory cells. Each memory cell may include a cell transistor, which includes a gate electrode 207, a bit line 212, and a memory element 223.

[0047] Gate electrode 207 and bit line 212 can have the same characteristics as... Figure 2Aand Figure 2B Same structure.

[0048] An island-shaped rectangular opening 216 can be defined by a plug isolation layer 215 formed between adjacent bit line structures BL. The vertical line width and horizontal line width of each opening 216 can be controlled by the bit line structure BL and the bit line spacer 214.

[0049] A recess 216R may be formed in the bottom of an opening 216. The recess 216R may extend into the substrate 201. The lower surface of the recess 216R may be located at a lower level than the upper surface of the substrate 201. The lower surface of the recess 216R may be located at a higher level than the lower surface of the bit line contact plug 211.

[0050] A pad 217 that contacts the second source / drain region 210 can be formed in the recess 216R. The pad 217 can fill the recess 216R. The pad 217 can couple the contact plug SNC and the second impurity region 210. The pad 217 can be formed, for example, by a selective epitaxial growth process.

[0051] For example, pad 217 can be formed using a bottom-up growth process. The bottom-up growth process can include an epitaxial growth process. The epitaxial growth process can include a selective epitaxial growth process. Pad 217 can include a silicon-containing epitaxial layer. For example, pad 217 can include a silicon epitaxial layer. Pad 217 can include SEG Si.

[0052] The recesses 216R retained between the pads 217 can be filled using a first spacer 218. The first spacer 218 can be formed on the sidewall of the bit line spacer 214. The first spacer 218 can be formed of or include a dielectric material. The first spacer 218 can be formed of, for example, silicon oxide, or include, for example, silicon oxide.

[0053] The plug liner 219 may be formed on a portion of each sidewall of the first spacer 218. The plug liner 219 may be formed on the upper portion of the pad 217. The plug liner 219 may be formed of, for example, polysilicon, or may include, for example, polysilicon.

[0054] The first contact plug 220 may be formed on the pad 217 to directly contact the upper part of the pad 217. The first contact plug 220 may be formed between adjacent bit line structures BL. The first contact plug 220 may be coupled to the second impurity region 210 via the pad 217. The first contact plug 220 may be or include a conductive material. The first contact plug 220 may be formed of, for example, polysilicon or a metallic material, or include, for example, polysilicon or a metallic material. The upper surface of the first contact plug 220 may be located at the same level as the upper surface of the plug liner 219.

[0055] According to one embodiment of this disclosure, the plug liner 219 may be used together with the first contact plug 220 as a contact plug.

[0056] The second spacer 221 may be formed on the plug liner 219. The second spacer 221 may be formed on a portion of each of the two sidewalls of the first spacer 218. The second spacer 221 may be formed of or include a dielectric material. The second spacer 221 may be or include silicon nitride.

[0057] The second contact plug 222 may be formed on top of the first contact plug 220. The second contact plug 222 may be in direct contact with the first contact plug 220. The second contact plug 222 may comprise the same material as the first contact plug 220. The contact plug structure SNC may be defined by the first contact plug 220 and the second contact plug 222. Furthermore, according to one embodiment of this disclosure, a plug liner 219 may be included in the contact plug structure SNC. For example, the lower contact portion of the contact plug structure SNC may be the plug liner 219 and the first contact plug 220, while the upper contact portion may be the second contact plug 222. In this case, the lower contact portion may have a wider width than the upper contact portion.

[0058] According to another embodiment of this disclosure, an ohmic contact layer and an interface doped layer may also be included between the first contact plug 220 and the second contact plug 222.

[0059] The storage element 223 may be formed on the second contact plug 222. The storage element 223 may be in direct contact with the second contact plug 222.

[0060] Figures 4A to 4U By presenting along Figure 1 The cross section taken by line A-A' is used to illustrate a cross-sectional view of a method for manufacturing semiconductor devices. Figures 5A to 5U By presenting along Figure 1 The cross section taken by line B-B' is used to illustrate a cross-sectional view of a method for manufacturing semiconductor devices.

[0061] like Figure 4A and Figure 5AAs shown, an isolation layer 12 can be formed in a substrate 11. The isolation layer 12 can define an active region 13. The active region 13 can include a plurality of active regions 13. The isolation layer 12 can be formed, for example, by a shallow trench isolation (STI) process. The STI process can include etching the substrate 11 to form an isolation trench (not shown). The isolation trench can be filled with a dielectric material to form the isolation layer 12. The isolation layer 12 can be formed of, for example, silicon oxide, silicon nitride, or a combination thereof, or include, for example, silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition processes can be used to fill the isolation trench with a dielectric material. Planarization processes such as chemical mechanical polishing (CMP) can also be used.

[0062] See Figure 4B and Figure 5B A buried gate structure can be formed in the substrate 11. The buried gate structure can be referred to as a buried word line structure. The buried gate structure may include: a gate trench 15, a gate dielectric layer 16 covering the lower surface and sidewalls of the gate trench 15, a gate electrode 17 partially filling the gate trench 15 above the gate dielectric layer 16, and a gate capping layer 18 formed above the gate electrode 17.

[0063] The following methods can be used to form a buried grid structure.

[0064] First, a gate trench 15 can be formed in the substrate 11. The gate trench 15 can have a line shape intersecting the active region 13 and the isolation layer 12. The gate trench 15 can be formed by forming a mask pattern (not shown) on the substrate 11 and performing an etching process using the mask pattern as an etching mask. To form the gate trench 15, a hard mask layer 14 can be used as an etching barrier layer. The hard mask layer 14 can be formed of or include TEOS (tetraethyl orthosilicate). The gate trench 15 can be formed to be shallower than the isolation trench. For example, the lower surface of the gate trench 15 can be located at a higher level than the lower surface of the isolation layer 12. The gate trench 15 can have sufficient depth to increase the average cross-sectional area of ​​the gate electrode 17. Therefore, the resistance of the gate electrode 17 can be reduced. The bottom edge of the gate trench 15 can be straight. According to another embodiment of the present disclosure (not shown), the bottom edge of the gate trench 15 can have curvature. By forming the bottom edge of the gate trench 15 with curvature, irregularities at the bottom of the gate trench 15 can be minimized, making it easier to fill the gate electrode 17.

[0065] Although not shown, a fin region can be formed after the grid trench 15 is formed. The fin region can be formed by recessing a portion of the isolation layer 12.

[0066] Subsequently, a gate dielectric layer 16 can be formed on the lower surface and sidewalls of the gate trench 15. Before forming the gate dielectric layer 16, the etch damage on the surface of the gate trench 15 can be cured. For example, in the curing process, a thermal oxidation process for curing the surface of the gate trench 15 and a process for removing the sacrificial oxide formed on the surface of the gate trench 15 by thermal oxidation can be performed sequentially.

[0067] The gate dielectric layer 16 can be formed, for example, by a thermal oxidation process. For example, the gate dielectric layer 16 can be formed by oxidizing the bottom and sidewalls of the gate trench 15.

[0068] According to another embodiment of this disclosure, the gate dielectric layer 16 can be formed, for example, by a vapor deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate dielectric layer 16 may include, for example, a high-k material, an oxide, a nitride, an oxide oxynitride, or a combination thereof. The high-k material may include, for example, a hafnium-containing material. The hafnium-containing material may include: hafnium oxide, hafnium silicon oxide, hafnium silicon oxide nitride, or a combination thereof. According to another embodiment of this disclosure, the high-k material may include, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxide nitride, aluminum oxide, or a combination thereof. Other known high-k materials may be selectively used.

[0069] According to another embodiment of this disclosure, the gate dielectric layer 16 can be formed by depositing an inner polysilicon liner layer and then thoroughly oxidizing the inner polysilicon liner layer.

[0070] According to yet another embodiment of this disclosure, the gate dielectric layer 16 can be formed by forming an inner silicon nitride layer and then thoroughly oxidizing the inner silicon nitride layer.

[0071] Subsequently, a gate electrode 17 can be formed on the gate dielectric layer 16. To form the gate electrode 17, a recess process can be performed after forming a conductive layer (not shown) to fill the gate trench 15. The recess process can be performed as an etch-back process, or it can be performed by sequentially performing a CMP process and an etch-back process. The gate electrode 17 can have a recessed shape that only partially fills the gate trench 15. For example, the upper surface of the gate electrode 17 can be located at a lower level than the upper surface of the active region 13. The gate electrode 17 can include, for example, a metal, a metal nitride, or a combination thereof. For example, the gate electrode 17 can be formed of titanium nitride (TiN), tungsten (W), or titanium nitride / tungsten (TiN / W). Titanium nitride / tungsten (TiN / W) can have a structure in which titanium nitride is formed conformally, and then the gate trench 15 is partially filled using tungsten. As the gate electrode 17, titanium nitride can be used alone, and this can be referred to as a gate electrode 17 with a "TiN-only" structure.

[0072] Subsequently, a gate capping layer 18 can be formed over the gate electrode 17. The gate capping layer 18 can be formed of or include a dielectric material. The remaining portion of the gate trench 15 over the gate electrode 17 can be filled using the gate capping layer 18. The gate capping layer 18 can be formed of, for example, silicon oxide, or include, for example, silicon oxide. According to another embodiment of this disclosure, the gate capping layer 18 can have a NON (nitride-oxide-nitride) structure. The upper surface of the gate capping layer 18 can be located at the same level as the upper surface of the hard mask layer 14. For this purpose, when forming the gate capping layer 18, a chemical mechanical polishing (CMP) process can be performed by setting the upper surface of the hard mask layer 14 as an etch stop target.

[0073] After forming the buried gate structure as described above, a first impurity region 19 and a second impurity region 20 can be formed. The first impurity region 19 and the second impurity region 20 can be formed, for example, by a doping process such as an implantation process. The first impurity region 19 and the second impurity region 20 can have the same depth. According to another embodiment of this disclosure, the first impurity region 19 can be deeper than the second impurity region 20. The first impurity region 19 and the second impurity region 20 can be referred to as source regions / drain regions. The first impurity region 19 can be a region coupled to a bit line contact plug. The second impurity region 20 can be a region coupled to a memory node contact plug.

[0074] The unit transistor of the memory cell can be formed by a gate electrode 17, a first impurity region 19, and a second impurity region 20.

[0075] See Figure 4C and Figure 5CA first contact hole 21 can be formed. The first contact hole 21 can be formed by etching a hard mask layer 14 using a contact mask (not shown). When viewed from a plan view, the first contact hole 21 can be circular or elliptical. A portion of the substrate 11 can be exposed by the first contact hole 21. The first contact hole 21 can have a diameter controlled to a predetermined linewidth. The first contact hole 21 can have a shape that exposes a portion of the active region 13. For example, a first impurity region 19 can be exposed through the first contact hole 21. The diameter of the first contact hole 21 can be larger than the width of the minor axis of the active region 13. Therefore, in the etching process used to form the first contact hole 21, a portion of the first impurity region 19, the isolation layer 12, and the gate capping layer 18 can be etched. For example, the gate capping layer 18, the first impurity region 19, and the isolation layer 12 below the first contact hole 21 can be recessed to a predetermined depth. Therefore, the bottom of the first contact hole 21 can extend into the substrate 11. As the first contact hole 21 extends, the surface of the first impurity region 19 can be recessed, and the surface of the first impurity region 19 can be located at a lower level than the surface of the active region 13. The first contact hole 21 can be referred to as a "bit line contact hole".

[0076] See Figure 4D and Figure 5D A primary plug 22A can be formed. The primary plug 22A can be formed, for example, by a selective epitaxial growth (SEG) process. For example, the primary plug 22A may include SEG SiP. For example, the primary plug 22A can be formed without voids by selective epitaxial growth. According to another embodiment of this disclosure, the primary plug 22A can be formed by depositing polysilicon and performing a CMP process. The primary plug 22A can fill the first contact hole 21. The upper surface of the primary plug 22A can be located at the same level as the upper surface of the hard mask layer 14.

[0077] See Figure 4E and Figure 5E A conductive layer 23A and a hard mask material layer 24A can be stacked. The conductive layer 23A and the hard mask material layer 24A can be sequentially stacked on top of the primary plug 22A and the hard mask layer 14. The conductive layer 23A can include a metal-containing material. The conductive layer 23A can include a metal, a metal nitride, a metal silicide, or a combination thereof. According to one embodiment of this disclosure, the conductive layer 23A can include tungsten (W). According to another embodiment of this disclosure, the conductive layer 23A can include a stack of titanium nitride and tungsten (TiN / W). Titanium nitride can be used as a barrier layer. The hard mask material layer 24A can be formed of a dielectric material having etch selectivity relative to the conductive layer 23A and the primary plug 22A. The hard mask material layer 24A can be formed of, for example, silicon oxide or silicon nitride, or include, for example, silicon oxide or silicon nitride.

[0078] A bit line mask layer 25 can be formed on top of the hard mask material layer 24A. The bit line mask layer 25 can be formed of a material with etching selectivity relative to the conductive layer 23A and the hard mask material layer 24A. The bit line mask layer 25 may include a photoresist pattern. The bit line mask layer 25 can be formed, for example, by a patterning method such as SPT (spacer patterning technology) or DPT (double patterning technology). When viewed from a planar perspective, the bit line mask layer 25 may have a linear shape extending in one direction.

[0079] like Figure 4F and Figure 5F As shown, bit line 23 and bit line contact plug 22 can be formed. Bit line 23 and bit line contact plug 22 can be formed simultaneously using a single etching process. For example, bit line 23 and bit line contact plug 22 can be formed using an etching process utilizing bit line mask layer 25 (see...). Figure 4E ).

[0080] The hard mask material layer 24A can be etched by using the bit line mask layer 25 as an etch barrier layer (see...). Figure 4E ) and conductive layer 23A (see Figure 4E Therefore, a bit line structure including bit line 23 and bit line hard mask layer 24 can be formed. Bit line 23 can be formed by etching conductive layer 23A. Bit line hard mask layer 24 can be formed by etching hard mask material layer 24A.

[0081] Subsequently, the primary plug 22A can be etched with the same linewidth as bit line 23 (see...). Figure 4E As a result, a bit line contact plug 22 can be formed. The bit line contact plug 22 can be formed on the first impurity region 19. The bit line contact plug 22 can couple the first impurity region 19 and the bit line 23 to each other. The bit line contact plug 22 can be formed in the first contact hole 21. The linewidth of the bit line contact plug 22 can be smaller than the diameter of the first contact hole 21. As a result, a gap G can be formed around the bit line contact plug 22.

[0082] As described above, a gap G can be formed inside the first contact hole 21 by forming the bit line contact plug 22. This is because the bit line contact plug 22 is formed by etching a diameter smaller than that of the first contact hole 21. The gap G may not have a surrounding shape around the bit line contact plug 22, but can be formed independently on each of the two sidewalls of the bit line contact plug 22. Therefore, a bit line contact plug 22 and a pair of gaps G can be located in the first contact hole 21, and the pair of gaps G can be isolated by the bit line contact plug 22. The lower surface of the gap G can be located at the same level as the upper surface of the recess of the first impurity region 19. According to another embodiment of the present disclosure, the lower surface of the gap G can extend into the isolation layer 12. For example, the lower surface of the gap G can be located at a lower level than the upper surface of the recess of the first impurity region 19.

[0083] Subsequently, the bit line mask layer 25 can be removed (see...) Figure 4E ).

[0084] See Figure 4G and Figure 5G A bit line spacer 26 can be formed. The bit line spacer 26 can be located on the sidewalls of the bit line contact plug 22 and the bit line 23. The bit line spacer 26 can have a linear shape extending parallel to the two sidewalls of the bit line 23.

[0085] The lower end of the bit line spacer 26 can fill the gap G while covering the two sidewalls of the bit line contact plug 22. To form the bit line spacer 26, bit line spacer material (not shown) can be deposited and an etch-back process can be performed.

[0086] Bit line spacers 26 may be formed of, for example, silicon oxide, silicon nitride, or combinations thereof, or may include, for example, silicon oxide, silicon nitride, or combinations thereof. Bit line spacers 26 may include a NON (nitride-oxide-nitride) structure. According to another embodiment of this disclosure, bit line spacers 26 may include an air gap. For example, it may include a NAN (nitride-air gap-nitride) structure.

[0087] See Figure 4H and Figure 5H A sacrificial layer 27 can be formed. The sacrificial layer 27 can fill the spaces between the bit line structures BL. The sacrificial layer 27 can be formed of, for example, silicon oxide, or include, for example, silicon oxide. The sacrificial layer 27 can include, for example, a spin-on-dielectric (SOD) material. The sacrificial layer 27 can be formed by forming a dielectric material for filling the spaces between the bit line structures, followed by a planarization process. The upper surface of the sacrificial layer 27 can be located at the same level as the upper surface of the bit line structures.

[0088] See Figure 4I andFigure 5I An intercalation isolation mask layer 28 can be formed on the sacrificial layer 27. The intercalation isolation mask layer 28 can be formed of a material that has etch selectivity relative to the bit line hard mask layer 24 and the sacrificial layer 27. The intercalation isolation mask layer 28 may include a photoresist. The intercalation isolation mask layer 28 can be formed as a line. The intercalation isolation mask layer 28 can have a line shape extending in a direction intersecting the bit line 23. For example, the intercalation isolation mask layer 28 can have a line shape extending in a direction parallel to the gate electrode 17. The intercalation isolation mask layer 28 can be formed so that it does not overlap with the gate electrode 17. For example, the intercalation isolation mask layer 28 can be patterned such that the portion overlapping with the gate electrode 17 is open.

[0089] See Figure 4J and Figure 5J The sacrificial layer 27 can be etched by using the plug isolation mask layer 28 as an etching barrier layer. As a result, the plug isolation portion 29 can be formed.

[0090] See Figure 4K and Figure 5K The plug isolation mask layer 28 can be removed (see Figure 4J ).

[0091] Subsequently, a plug isolation layer 30 can be formed in the plug isolation portion 29. To form the plug isolation layer 30, a dielectric material can be formed to fill the plug isolation portion 29, and then a planarization process can be performed. The plug isolation layer 30 may include a material that has etch selectivity relative to the sacrificial layer 27. For example, the plug isolation layer 30 may be made of silicon nitride, or may include silicon nitride.

[0092] See Figure 4L and Figure 5L This can remove the remaining sacrificial layers 27 (see Figure 4K The remaining sacrificial layer 27 can be removed, for example, by a wet etching process. The remaining sacrificial layer can also be removed, for example, by an immersion process. The process of removing the remaining sacrificial layer 27 can be performed with etching selectivity relative to the plug isolation layer 30 and the bit line hard mask layer 24. Therefore, only the remaining sacrificial layer 27 can be removed without loss of other structures.

[0093] When the remaining sacrificial layer is removed, opening 31 can be formed by the plug isolation layer 30 and the bit line structure BL. Opening 31 can have the shape of a separate island. Opening 31 can be referred to as a storage node contact hole.

[0094] As described above, the opening 31 can be formed by sequentially depositing the sacrificial layer 27, forming the plug isolation portion 29, forming the plug isolation layer 30, and removing the sacrificial layer 27. This series of processes can be referred to as the "damascus process," and the opening 31 can be formed by the damascus process.

[0095] From a plan view perspective, opening 31 can have a rectangular shape. The dimensions of opening 31 can be determined by the bit line spacer 26 and the plug isolation layer 30.

[0096] See Figure 4M and Figure 5M A portion of the plug isolation layer 30 and a portion of the bit line spacer 26 can be etched to increase the width of the opening 31.

[0097] Subsequently, a recess 31R can be formed below the opening 31. To form the recess 31R, the hard mask layer 14, the isolation layer 12, and the second impurity region 20 can be etched to a predetermined depth. The recess 31R can extend into the substrate 11. The lower surface of the recess 31R can be located at a lower level than the upper surface of the bit line contact plug 22. The lower surface of the recess 31R can also be located at a higher level than the lower surface of the bit line contact plug 22.

[0098] See Figure 4N and Figure 5N A pad 32 can be formed to fill a portion of the recess 31R. The pad 32 can be formed, for example, by a bottom-up growth process. The pad 32 can be formed, for example, by a selective epitaxial growth (SEG) process. The pad 32 can be grown by using a second impurity region 20 as a seed. The pad 32 can include a silicon-containing material. The pad 32 can be an epitaxial layer. The pad 32 can be, for example, a silicon-containing epitaxial layer. The pad 32 can include, for example, SEG Si, SEG SiGe, or SEG SiC. According to another embodiment of this disclosure, the pad 32 can include, for example, SEG Si, SEG SiGe, or SEG SiG doped with an N-type dopant. For example, the pad 32 can include SEG SiP. The pad 32 can be formed by using a silicon source gas and an auxiliary gas. The silicon source gas can include silane (SiH4), dichlorosilane (SiH2Cl2, DCS), or mixtures thereof. The auxiliary gas can include HCl.

[0099] The upper surface of pad 32 can be located at a lower level than the upper surface of bit line contact plug 22.

[0100] As described above, the process can be simplified by performing selective epitaxial growth to form the pads 32. Furthermore, the interior of the recess 31R can be filled with the pads 32 without any gaps.

[0101] Specifically, in this embodiment, the plug isolation layer 30 can be formed by defining a separate island-shaped opening 31 through the plug isolation layer 30 and the bit line structure, and by forming a pad 32 at the bottom of the opening 31 to form the plug isolation layer 30, thereby preventing short circuits caused by bridging between the contact plugs of the memory node. That is, since the pad 32 is only formed inside the island-shaped opening 31, epitaxial growth can be performed regardless of the growth degree of the pad 32. Therefore, detailed conditions for controlling the growth of the pad 32 can be adopted, thereby reducing the process complexity.

[0102] According to one embodiment of this disclosure, after the pad 32 is formed, in-situ annealing can be performed in a hydrogen (H2) environment. Silicon migration may occur due to in-situ annealing in a hydrogen environment.

[0103] For example, pad 32 can be formed from SEG Si or SEG SiP. When pad 32 is formed from SEG SiP, the contact resistance with the silicon active region can be increased. SEG SiP can be formed by co-flushing PH3 gas during the SEG process.

[0104] The method for forming the SEG SiP pad 32 is as follows.

[0105] SEG SiP can be formed using phosphorus-containing gases, silicon-containing gases, and chlorine-containing gases. Chlorine-containing gases may include HCl. Phosphorus-containing gases and silicon-containing gases may be referred to as phosphorus-containing precursors and silicon-containing precursors, respectively. For example, the phosphorus-containing gas may be or include phosphine (PH3). Furthermore, silicon-containing gases may include, for example, silanes (SiH4), dichlorosilanes (Si2H6), propanes (Si3H8), dichlorosilanes (SiH2Cl2:DCS), or combinations thereof. In selective epitaxial growth (SEG), it may be difficult to ensure selectivity for the dielectric material. Therefore, in this embodiment, epitaxial growth can be performed by mixing dichlorosilanes (DCS) and silanes (SiH4) to ensure selectivity relative to the dielectric material. Therefore, by controlling the Cl functional groups on the epitaxial growth surface, the growth rate can be increased as adsorption accelerates. Therefore, the window for ensuring selectivity through HCl may become larger. When dichlorosilanes (SiH2Cl2) and silanes (SiH4) are mixed, the phosphorus doping level in the SEG SiP may be increased.

[0106] The formation of SEG SiP can include in-situ doping processes. For example, an in-situ doping process can be performed simultaneously with the deposition of a silicon epitaxial layer by co-flushing phosphine (PH3).

[0107] As described above, SEG SiP can be formed at a low temperature of approximately 550°C to 650°C using silane (SiH4), dichlorosilane (DCS), HCl, and phosphine (PH3).

[0108] See Figure 4O and Figure 5O A first spacer layer 33A can be formed. The first spacer layer 33A can cover the pad 32. The first spacer layer 33A can cover the bit line spacer 26. The first spacer layer 33A can fill the remaining portion of the recess 31R where the pad 32 is formed. The first spacer layer 33A can be formed of, for example, silicon oxide, or include, for example, silicon oxide.

[0109] See Figure 4P and Figure 5P An inner liner layer 34A may be formed over the first spacer layer 33A. The inner liner layer 34A may be formed of, for example, polysilicon, or polysilicon.

[0110] See Figure 4Q and Figure 5Q The substrate 34A and the first spacer layer 33A can be etched to expose the pads 32.

[0111] Therefore, a first spacer 33 and a plug liner 34 can be formed on the position line spacer 26 (i.e., the sidewall of the position line spacer 26). That is, a spacer structure in which the position line spacer 26, the first spacer 33, and the plug liner 34 are stacked can be formed on the sidewall of the position line 23.

[0112] Specifically, in this embodiment, the parasitic capacitance of the bit line can be reduced by forming a first spacer 33 of oxide. Furthermore, by forming a silicon plug liner 34, damage to the first spacer 33 can be prevented during subsequent cleaning processes. Additionally, since the plug liner 34 can be used as a storage node contact plug together with the conductive material filling the opening 31 in subsequent processes, the width of the storage node contact plug can be increased.

[0113] After the etching process is completed, a cleaning process can be performed. This can be done using the inner liner 34A (see...). Figure 4P ) to prevent the first spacer layer 33A (see Figure 4P ) damage.

[0114] See Figure 4R and Figure 5RA first plug 35 can be formed on the pad 32 to fill the lower part of the opening 31. The first plug 35 can directly contact the pad 32. The first plug 35 can be a silicon-containing material or a metallic material. The first plug 35 can be formed of, for example, polysilicon, or include, for example, polysilicon. To form the first plug 35, a recess process can be performed after depositing polysilicon to fill the opening 31. The upper surface of the first plug 35 and the upper surface of the bit line 23 can be at the same level. During the recess process for forming the first plug 35, the plug liner 34 can be recessed together, so that it can remain only on the sidewall of the first plug 35. For example, the plug liner 34 can have an upper surface at the same level as the first plug 35. The plug liner 34 can be used together with the first plug 35 as a contact plug.

[0115] See Figure 4S and Figure 5S The second spacer 36 may be formed on the plug liner 34, i.e. on the sidewall of the first spacer 33. The second spacer 36 may be formed of silicon nitride or include silicon nitride.

[0116] See Figure 4T and Figure 5T A second plug 37 can be formed on top of the first plug 35 to fill the remainder of the opening 31.

[0117] The second plug 37 can be a metallic material. The second plug 37 can be formed of or comprise tungsten. The second plug 37 can be a material having a lower resistance than the first plug 35. The second plug 37 can be formed of, or comprise titanium, titanium nitride, tungsten, or a combination thereof. For example, the second plug 27 can be TiN / W, wherein tungsten is laminated on top of titanium nitride.

[0118] According to another embodiment of this disclosure, an ohmic contact layer may be further formed between the first plug 35 and the second plug 37. The ohmic contact layer may include a metal silicide. The ohmic contact layer may include cobalt silicide, titanium silicide, or nickel silicide. Contact resistance can be reduced by the ohmic contact layer.

[0119] According to another embodiment of this disclosure, an interface doped layer can be further formed between the first plug 35 and the ohmic contact layer. The interface doped layer can be formed by doping an impurity in the upper region of the first plug 35. The interface doped layer may be doped with phosphorus. The first plug 35 and the interface doped layer may be doped with the same dopant. The first plug 35 and the interface doped layer may have different dopant concentrations. The dopant concentration of the interface doped layer may be greater than the dopant concentration of the first plug 35. The interface doped layer can reduce the contact resistance.

[0120] The contact plug SNC can be formed by a first plug 35 and a second plug 37. The contact plug SNC can be referred to as a "storage node contact plug". When the contact plug SNC is formed on the pad 32, connection failures between storage node contact plugs can be minimized.

[0121] See Figure 4U and Figure 5U A storage element 38, including a capacitor, can be formed on the second plug 37.

[0122] Storage element 38 may include a capacitor, which includes a storage node. The storage node may be, for example, cylindrical. Although not shown, a dielectric layer and plate-like nodes may be further formed on top of the storage node. In one embodiment, the storage node may have a cylindrical shape.

[0123] According to one embodiment of this disclosure, the reliability of a semiconductor device can be improved by applying pads formed by a selective epitaxial growth (SEG) process to the bottom of each isolated opening.

[0124] Although the present invention has been described with reference to the specific embodiments described above, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A semiconductor device comprising: A semiconductor substrate, including an active region; Multiple conductive structures are formed on the semiconductor substrate; An isolation layer that fills the space between the conductive structures and has openings that expose the active regions between the conductive structures; A pad is formed in the bottom of the opening and contacts the active area; A plug liner, conformally formed on the sidewall of the opening and exposing the solder pads; and A contact plug is formed on the pad inside the opening. The plug liner comprises polycrystalline silicon.

2. The semiconductor device according to claim 1, wherein, The pads include an epitaxial layer.

3. The semiconductor device according to claim 1, further comprising: An oxide spacer is located between the sidewall of the opening and the plug liner.

4. The semiconductor device according to claim 1, wherein, The bottom of the opening is located at a lower level than the upper surface of the active region.

5. The semiconductor device according to claim 1, wherein, The upper surface of the isolation layer is at the same level as the upper surface of the conductive structure.

6. A semiconductor device comprising: A semiconductor substrate, including an active region; Multiple bit line structures are formed on the semiconductor substrate; An isolation layer that fills the space between the bit line structures and has openings that expose the active regions between the bit line structures; A pad is formed in the bottom of the opening and contacts the active area; A first spacer is formed conformally on the sidewall of the opening and exposes the pads; The insert liner is formed to cover the lower part of the first spacer; A second spacer is formed on the plug liner to cover the upper part of the first spacer; as well as A contact plug is formed on the pad inside the opening. The plug liner comprises polycrystalline silicon.

7. The semiconductor device according to claim 6, wherein, The contact plug includes: A first plug, having an upper surface at the same level as the plug liner; and The second plug is formed on top of the first plug and has an upper surface at the same level as the second spacer.

8. The semiconductor device according to claim 6, wherein, The pads include an epitaxial layer.

9. The semiconductor device according to claim 6, wherein, The first spacer comprises silicon oxide, and the second spacer comprises silicon nitride.

10. The semiconductor device according to claim 6, further comprising: Word lines, which are embedded in the semiconductor substrate; The first source / drain region and the second source / drain region are formed in the semiconductor substrate on both sides of the word line; Bit line contact plugs are formed on the first source / drain region; and Bit line, which is above the bit line contact plug. The pad is coupled to the second source / drain region.

11. A method for manufacturing a semiconductor device, comprising: Provides a substrate comprising multiple active regions; Multiple bit line structures are formed on the upper part of the substrate; An isolation layer is formed to fill the space between the bit line structures and has openings that expose the active regions between the bit line structures; A pad is formed at the bottom of the opening; A plug liner is formed on the sidewall of the opening and exposes the pad; as well as Form a contact plug that fills the opening above the pad. The plug liner comprises polycrystalline silicon.

12. The method according to claim 11, wherein, When forming pads at the bottom of the opening, Selective epitaxial growth is performed from the active region.

13. The method according to claim 11, wherein, The pads comprise a silicon-containing epitaxial layer.

14. The method according to claim 11, wherein, An isolation layer that forms the space between the bit line structures and has openings exposing the active regions between the bit line structures includes: A dielectric layer is formed to fill the space between the bit line structures; A line mask is formed on the bit line structure and the dielectric layer, intersecting with the bit line structure; Etch the dielectric layer exposed between the line mask and the bit line structure; An isolation layer is formed to fill the space between the etched dielectric layers; Remove the line mask; and Remove the dielectric layer between the isolation layers.

15. The method according to claim 14, wherein, The isolation layer is a dielectric material that is selectively etchable relative to the dielectric layer.

16. The method of claim 14, wherein, The line mask has etching selectivity relative to the bit line structure and the dielectric layer.

17. A method for manufacturing a semiconductor device, comprising: Multiple conductive structures are formed on the upper part of the substrate; An isolation layer is formed, the isolation layer having openings that expose the substrate between the conductive structures while filling the spaces between the conductive structures; A pad is formed at the bottom of the opening; The spacers and plug liners of the pads are sequentially formed on the sidewalls of the opening and expose the pads. as well as Form a contact plug that fills the opening above the pad. The plug liner comprises polycrystalline silicon.

18. The method according to claim 17, wherein, When forming pads at the bottom of the opening, Selective epitaxial growth process is performed in the active region.

19. The method of claim 17, wherein, The spacer comprises silicon oxide.

20. A method for manufacturing a semiconductor device, comprising: Provides a substrate comprising multiple active regions; Multiple bit line structures are formed on the upper part of the substrate; An isolation layer is formed, the isolation layer having openings that expose the active regions between the bit line structures while filling the spaces between the bit line structures; A pad is formed at the bottom of the opening; A first spacer is formed on the sidewall of the opening and exposes the pad; A plug liner is formed covering the lower part of the first spacer; Form a first contact plug that fills a portion of the opening above the pad; A second spacer is formed on the inner liner of the plug and covers the upper part of the first spacer; as well as A second contact plug is formed to fill the remainder of the opening above the first contact plug.

21. The method according to claim 20, wherein, The first spacer comprises silicon oxide.

22. The method according to claim 20, wherein, The plug liner comprises polycrystalline silicon.

23. The method of claim 20, wherein, The second spacer comprises silicon nitride.

24. The method of claim 20, wherein, The first contact plug and the second contact plug comprise: polysilicon, metal, metal nitride, or a combination thereof.

25. The method according to claim 20, wherein, When forming pads at the bottom of the opening, Selective epitaxial growth process is performed from the active region.

Images