Semiconductor Structure and Method for Forming the Same

Abstract

A semiconductor structure and a method for forming the same, wherein the method includes: providing a substrate; forming a plurality of gate structures and a first dielectric layer covering the sidewall surfaces of the gate structures on the substrate; forming a plurality of partition structures in the first dielectric layer, each of the partition structures being located on one side or both sides of the gate structure. Thereby, the difficulty of the process for forming the semiconductor structure is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly relates to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits has been continuously reduced, so that the operating speed of the entire integrated circuit can be effectively improved. As the size requirement of components becomes smaller and smaller, the size of the corresponding formed conductive structure becomes smaller and smaller.

[0003] However, in the process of forming the interconnect structure, the forming process is more difficult. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to reduce the difficulty of the process for forming the semiconductor structure.

[0005] To solve the above technical problem, the technical solution of the present invention provides a semiconductor structure, including: a substrate; and a plurality of gate structures located on the substrate; a first dielectric layer located on the substrate, and the first dielectric layer also located on the side wall surfaces of the gate structures; a plurality of partition structures located in the first dielectric layer, each of the partition structures located on one side or both sides of the gate structure.

[0006] Optionally, it further includes: a gate protection structure located on the surface of the gate structure, and the first dielectric layer also located on the side wall surface of the gate protection structure.

[0007] Optionally, the first dielectric layer further has a plurality of interconnect openings, and at least one of the interconnect openings exposes the surface of the substrate and the side wall surface of the partition structure.

[0008] Optionally, it further includes: an interconnect structure located in the interconnect opening.

[0009] Optionally, the material of the partition structure includes: one or more of a dielectric material of a non-metallic compound, a semiconductor material, a metal material, and a metal compound.

[0010] Optionally, the material of the gate protection structure includes a dielectric material.

[0011] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of gate structures on the substrate and a first dielectric layer covering the side wall surfaces of the gate structures; forming a plurality of partition structures in the first dielectric layer, each of the partition structures located on one side or both sides of the gate structure.

[0012] Optionally, the method for forming a plurality of the partition structures includes: forming a partition mask layer on the surface of the first dielectric layer and the surface of the gate structure, the partition mask layer having a plurality of partition mask openings, each of the partition mask openings exposing the surface of the first dielectric layer on one or both sides of the gate structure; using the partition mask layer as a mask to etch the first dielectric layer until a plurality of the partition openings are formed in the first dielectric layer; and forming partition structures in the partition openings.

[0013] Optionally, the method for forming the partition structures further includes: forming a partition structure material layer on the surface of the first dielectric layer, the surface of the gate structure, and within the partition openings; and planarizing the partition structure material layer until the surface of the first dielectric structure is exposed.

[0014] Optionally, it further includes: forming a gate protection structure on the surface of the gate structure before forming the partition structures, and the first dielectric layer is also located on the sidewall surface of the gate protection structure.

[0015] Optionally, it further includes: after forming the partition structures, etching the first dielectric layer to form a plurality of interconnect openings in the first dielectric layer, and at least one of the interconnect openings exposes the surface of the substrate and the sidewall surface of the partition structures.

[0016] Optionally, the method for forming the interconnect openings includes: forming an interconnect mask layer on the surface of the partition structures and the first dielectric layer, the interconnect mask layer having a plurality of interconnect mask openings spanning the partition structures, the interconnect mask openings exposing a portion of the first dielectric layer and the surface of the partition structures; using the interconnect mask layer and the partition structures as a mask to etch the first dielectric layer until the surface of the substrate is exposed.

[0017] Optionally, in the process of etching the first dielectric layer, the etching selectivity of the first dielectric layer to the partition structures is 5:1 or more.

[0018] Optionally, it further includes: forming an interconnect structure in the interconnect openings.

[0019] Optionally, it further includes: after forming the interconnect structure, removing the partition structures; and after removing the partition structures, forming a second dielectric layer in the partition openings, and the second dielectric layer is also located on the sidewall surface of the interconnect structure.

[0020] Optionally, the substrate includes a substrate and a plurality of fin structures located on the substrate, and the gate structure spans the fin structures.

[0021] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0022] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the partition structure is used to partition adjacent interconnect structures when forming the interconnect structure subsequently. Since a plurality of partition structures are formed in the first dielectric layer on one side or both sides of the gate structure, the partition structures can be spaced apart by the gate structure in the direction perpendicular to the extension direction of the gate structure. Thus, on the one hand, when forming the partition structure, in the direction perpendicular to the extension direction of the gate structure, the precision requirement for the graphic size of the partition structure is reduced, the process window size for forming the partition structure is increased, and further the process difficulty is reduced; on the other hand, in the direction perpendicular to the extension direction of the gate structure, the size of the partition structure can be increased, and by increasing the size of the partition structure, the reliability of the partition structure for partitioning the interconnect structure is improved. Thus, when forming the interconnect structure subsequently, the overlay precision requirement between the interconnect structure graphic and the partition structure graphic is reduced, the process window size for the forming processes of the partition structure and the interconnect structure is increased, and further the process difficulty is reduced.

[0023] Further, a partition structure is formed in the partition opening, that is, the shape of the partition structure is defined by the partition opening. Since it is easier to remove the materials on the top of the partition mask layer and the first dielectric layer when forming the partition mask opening and the partition opening, the risk of foot defects in the small-sized partition structure is reduced, and the graphic precision of the partition structure of the small-sized graphic is improved. Thus, during the subsequent process of forming the interconnect structure, the overlay precision requirement between the interconnect structure graphic and the partition structure graphic can be reduced, the process window size for the forming processes of the partition structure and the interconnect structure is increased, and further the process difficulty is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figures 1 to 4 is a schematic structural diagram of each step of a method for forming a semiconductor structure;

[0025] Figures 5 to 20 is a schematic structural diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] As described in the background art, during the process of forming the interconnect structure, the process difficulty is relatively large. Now, specific embodiments are combined for analysis and description.

[0027] It should be noted that the "surface" in this specification is used to describe the relative positional relationship in space and does not limit whether it is in direct contact.

[0028] Figures 1 to 4 is a schematic structural diagram of each step of a method for forming a semiconductor structure.

[0029] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic top view structural diagram of a semiconductor structure,Figure 2 is Figure 1 A schematic cross-sectional view along the A-A1 direction, providing a substrate 100, where the substrate 100 includes a substrate (not shown) and a plurality of fin structures (not shown) located on the substrate; a plurality of gate structures 120 and a dielectric layer 110 spanning the fin structures are formed on the substrate 100, and the dielectric layer 110 is also located on the sidewall surfaces of the gate structures 120; a hard mask material layer 130 is formed on the surfaces of the gate structures 120 and the dielectric layer 110, and the hard mask material layer provides materials for forming a hard mask layer, and the hard mask layer is used as a mask for defining the pattern of the interconnect structure in the subsequent process; a barrier structure material layer 140 is formed on the surface of the hard mask material layer 130; on the surface of the barrier structure material layer 140, a plurality of barrier pattern structures 150 are formed by an exposure and development process, and the barrier pattern structures 150 are located on the substrate on both sides of the gate structures 120.

[0030] Please refer to Figure 3 and Figure 4 , Figure 3 is a top-view structural schematic diagram of a semiconductor structure, Figure 4 is Figure 1 A schematic cross-sectional view along the A-A1 direction. Using the barrier pattern structure 150 as a mask, the barrier structure material layer 140 is etched to form a plurality of barrier structures 141; an interconnect mask material layer 160 is formed on the surfaces of the barrier structures 141 and the hard mask material layer 130; on the surface of the interconnect mask material layer 160, an interconnect pattern layer 170 is formed by an exposure and development process. The interconnect pattern layer 170 has a plurality of interconnect pattern openings 171, and the interconnect pattern openings 171 are located on the substrate 100 on both sides of the gate structures 120, and the interconnect pattern openings 171 span the barrier structures 141; using the interconnect pattern layer 170 as a mask, the interconnect mask material layer 160 is etched until the hard mask material layer 130 is exposed to form an interconnect mask layer (not shown); using the interconnect mask layer and the barrier structures 141 as masks, the hard mask material layer 130 is etched until the surface of the dielectric layer 110 is exposed to form a hard mask layer (not shown); using the hard mask layer as a mask, the dielectric layer 110 is etched until the surface of the substrate 100 is exposed to form an interconnect opening (not shown) in the dielectric layer 110; an interconnect structure is formed in the interconnect opening.

[0031] However, in the above method, in the development process of forming the barrier pattern structure 150, when the barrier pattern structure 150 is a small-size pattern, the barrier pattern material at the bottom of the barrier pattern structure 150 is more difficult to remove compared to the top. Therefore, region C (such as Figure 2The barrier pattern structure 150 (as shown in FIG. 1 ) is prone to produce a footing defect with a larger bottom size and a smaller top size, forming an island structure, and the footing defect is transmitted to the barrier structure 141. The footing defect is prone to cause adjacent barrier pattern structures 150 to be connected. Therefore, when forming the barrier pattern structure 150, it is necessary to more accurately control the end spacing B of adjacent barrier structures 150 (as shown in FIG. Figure 1 As shown), thus, in the direction X (as Figure 1 as shown) and direction Y (as shown Figure 1 As shown in FIG. 1 , the process window for forming the blocking pattern structure 150 and the blocking structure 141 is small, and the process difficulty is relatively high. At the same time, since the foot defect is transmitted to the blocking structure 141, the pattern accuracy of the blocking structure 141 is relatively poor, which reduces the margin of the overlay accuracy range between the blocking structure 141 and the interconnection pattern opening 171, resulting in a small process window for forming the interconnection pattern layer 170, and a relatively high process difficulty.

[0032] To solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, by forming a plurality of partition structures in a first dielectric layer, each of which is located on one side or both sides of a gate structure, thereby reducing the difficulty of the process of forming the semiconductor structure.

[0033] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figures 5 to 20 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0035] Please refer to Figure 5 and Figure 6 , Figure 5 yes Figure 6 A schematic diagram of the top view structure along the direction X3, Figure 6 yes Figure 5 A schematic cross-sectional structure diagram along the direction X1 - X2 is provided for a substrate 200 .

[0036] In this embodiment, the base 200 includes a substrate (not shown) and a plurality of fin structures (not shown) separated from each other and located on the substrate.

[0037] In other embodiments, the substrate is a planar substrate.

[0038] The material of the substrate includes semiconductor material.

[0039] In this embodiment, the material of the substrate is silicon.

[0040] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI), etc. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0041] Please continue to refer to Figure 5 and Figure 6 , and a plurality of gate structures 220 are formed on the substrate 200, and a first dielectric layer 210 covering the side wall surfaces of the gate structures 220 is formed.

[0042] In this embodiment, a plurality of gate openings (not shown) are formed in the first dielectric layer 210, and the gate openings straddle the fin structures.

[0043] In this embodiment, the method for forming the first dielectric layer 210 includes: forming a plurality of dummy gate structures (not shown) straddling the fin structures on the surface of the substrate 200; forming a first dielectric structure material layer (not shown) covering the surface of the dummy gate structures on the substrate 200; planarizing the first dielectric structure material layer until the top surface of the dummy gate structures is exposed to form the first dielectric layer 210; after forming the first dielectric layer 210, removing the dummy gate structures to form a plurality of the gate openings in the first dielectric layer 210.

[0044] In this embodiment, the first dielectric layer 210 provides support for the subsequent formation of the gate structures 220.

[0045] In this embodiment, the method for forming the dummy gate structures includes: forming a dummy gate material film covering the surface of the fin structures on the substrate 200; patterning the dummy gate material film until the surface of the substrate 200 is exposed, and forming dummy gate structures straddling the fin structures on the substrate 200, and the top surface of the dummy gate structures is higher than the top surface of the fin structures.

[0046] In this embodiment, the method for forming the semiconductor structure further includes: forming a substrate dielectric layer 201 on the surface of the substrate before forming the dummy gate structures, and the substrate dielectric layer 201 also covers part of the side wall surfaces of the fin structures.

[0047] The function of the substrate dielectric layer 201 is to electrically insulate between adjacent fin structures and between the semiconductor device and the substrate.

[0048] In this embodiment, the method for forming the semiconductor structure further includes: forming source-drain doping layers (not shown in the figure) in the fin structures on both sides of the dummy gate structures after forming the dummy gate structures and before forming the first dielectric layer 210.

[0049] The method for forming the source-drain doping layer includes: forming source-drain openings (not shown in the figure) in the fin structures on both sides of the pseudo-gate structure; and forming the source-drain doping layer in the source-drain openings by using an epitaxial process.

[0050] In this embodiment, the gate structure 220 straddles the fin structure, and the top surface of the gate structure 220 is lower than the surface of the first dielectric layer 210.

[0051] The function that the surface of the gate structure 220 is lower than the surface of the first dielectric layer 210 is to provide space for forming a gate protection structure (Gate Cap) on the surface of the gate structure 220 in the gate opening subsequently.

[0052] In other embodiments, the surface of the gate structure is flush with the surface of the first dielectric structure.

[0053] In this embodiment, the method for forming a plurality of the gate structures 220 includes: forming a gate structure material layer (not shown) on the side wall surface and the bottom surface of the gate opening, and on the surface of the first dielectric layer 210; etching the gate structure material layer until the gate structure material layer on the surface of the first dielectric layer 210 is removed, and the top surface of the gate structure material layer in the gate opening is lower than the surface of the first dielectric layer 210.

[0054] In this embodiment, the gate structure 220 includes: a gate dielectric layer (not shown) located on the side wall surface and the bottom surface of the gate opening, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0055] In this embodiment, the material of the gate dielectric layer includes a high-k material (dielectric constant greater than 3.9). The high-k materials include: hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate or aluminum oxide, etc.

[0056] In this embodiment, the material of the gate electrode layer includes a metal material, such as: one or a combination of several of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, tantalum.

[0057] In this embodiment, the material of the work function layer includes titanium nitride, tantalum nitride or titanium aluminum.

[0058] In this embodiment, the method for the semiconductor structure further includes: forming a gate protection structure 221 on the surface of the gate structure 220, and the first dielectric layer 210 is also located on the side wall surface of the gate protection structure 221.

[0059] In this embodiment, the material of the gate protection structure 221 includes a dielectric material.

[0060] In other embodiments, no gate protection structure is formed.

[0061] Next, a plurality of partition structures are formed in the first dielectric layer 210, and each partition structure is located on one side or both sides of the gate structure 220. For the specific process of forming the partition structures, please refer to Figures 7 to 12 .

[0062] Please refer to Figure 7 and Figure 8 , Figure 7 is Figure 8 the top view structural schematic diagram along the direction X3 in Figure 8 is Figure 7 the cross-sectional structural schematic diagram along the direction X1-X2 in . A partition mask layer 230 is formed on the surface of the first dielectric layer 210 and the surface of the gate structure 220. The partition mask layer 230 has a plurality of partition mask openings 231, and each partition mask opening 231 exposes the surface of the first dielectric layer 210 on one side or both sides of the gate structure 220.

[0063] It should be noted that for the sake of easy understanding, Figure 7 and Figure 8 schematically show: a plurality of partition mask openings 231 that expose the surface of the first dielectric layer 210 on one side of the gate structure 220, and one partition mask opening 231 that exposes the surface of the first dielectric layer 210 on both sides of the gate structure 220. And the partition mask opening 231 that exposes the surface of the first dielectric layer 210 on both sides of the gate structure 220 straddles the gate structure 220.

[0064] The method of forming the partition mask layer 230 includes: forming a partition mask material layer (not shown) on the surface of the first dielectric layer 210 and the surface of the gate structure 220; forming a photoresist partition pattern structure 240 on the surface of the partition mask material layer. The photoresist partition pattern structure 240 has a plurality of photoresist partition openings 241, and each photoresist partition opening 241 exposes the surface of the partition mask material layer on one side or both sides of the gate structure 220; using the photoresist partition pattern structure 240 as a mask to etch the partition mask material layer until the surface of the first dielectric layer 210 is exposed.

[0065] In this embodiment, the photoresist isolation pattern structure 240 includes an isolation photoresist layer (not shown) and an isolation anti-reflection layer (not shown). The function of the isolation anti-reflection layer is to improve the anti-reflection ability of the isolation photoresist layer during the exposure process of forming the isolation photoresist layer. The isolation anti-reflection layer includes: a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0066] The process of forming the isolation mask material layer includes: a spin coating process or a deposition process, etc. The deposition process is, for example, a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), or an atomic layer deposition process (ALD), etc.

[0067] The process of etching the isolation mask material layer includes a dry etching process or a wet etching process.

[0068] The material of the isolation mask layer 230 includes: spin-on carbon (SOC) or a carbon-containing organic material.

[0069] Please refer to Figure 9 and Figure 10 , Figure 9 is Figure 10 a top view structural schematic diagram along the direction X3 in Figure 10 is Figure 9 a cross-sectional structural schematic diagram along the direction X1-X2 in , etching the first dielectric layer 210 with the isolation mask layer 230 as a mask until a plurality of isolation openings 211 are formed in the first dielectric layer 210, and each isolation opening 211 is located on one side or both sides of the gate structure 220.

[0070] The isolation opening 211 provides space for forming an isolation structure, that is, an isolation structure is formed in the isolation opening 211 subsequently, and the isolation opening 211 defines the size of the isolation structure.

[0071] In this embodiment, the pattern of the photoresist isolation opening 241 is used to define the pattern of the isolation mask opening 231, and the pattern of the isolation mask opening 231 is used to define the pattern of the isolation opening 211, that is, by transferring the pattern of the photoresist isolation opening 241, the isolation opening 211 is formed.

[0072] When forming the photoresist isolation opening 241, it is easier to remove the material at the top of the photoresist isolation pattern structure 240. Similarly, when forming the isolation mask opening 231, it is easier to remove the material at the top of the isolation mask layer 230. When forming the isolation opening 211, it is easier to remove the material at the top of the first dielectric layer 210. Therefore, the risk of foot defects in the small-sized isolation structure 250 is reduced, and the pattern accuracy of the isolation structure 250 of the small-sized pattern is improved. Thus, during the subsequent process of forming the interconnect structure, the overlay accuracy requirement between the interconnect structure pattern and the isolation structure 250 can be reduced, the process window size of the isolation structure 250 formation process is increased, and further, the process difficulty is reduced.

[0073] It should be noted that the depth of the isolation opening 211 is determined by the etching selectivity of the first dielectric layer 210 and the isolation structure in the etching process of forming the interconnect opening subsequently, so as to ensure that the isolation structure is not completely consumed in advance during the etching process of forming the interconnect opening, so as to form spaced interconnect openings. Further, the risk of short circuit between adjacent interconnect structures is reduced.

[0074] In this embodiment, the process of etching the first dielectric layer 210 using the isolation mask layer 230 as a mask includes a dry etching process or a wet etching process.

[0075] In this embodiment, after forming the isolation opening 211, the isolation mask layer 230 is removed.

[0076] Please refer to Figure 11 and Figure 12 , Figure 11 is Figure 12 the top view structure schematic diagram along the X3 direction in Figure 12 is Figure 11 the cross-sectional structure schematic diagram along the X1-X2 direction in , and an isolation structure 250 is formed in a plurality of the isolation openings 211, and each isolation structure 250 is located on one side or both sides of the gate structure 220.

[0077] Since a plurality of partition structures 250 are formed in the first dielectric layer 210 on one or both sides of the gate structure 220, the partition structures 250 can be spaced apart by the gate structure 220 in a direction perpendicular to the extending direction of the gate structure 220. Thus, on the one hand, when forming the partition structures 250, in the direction perpendicular to the extending direction of the gate structure 220, the accuracy requirement for the pattern size of the partition structures 250 is reduced, the process window size for forming the partition structures 250 is increased, and further the process difficulty is reduced; on the other hand, in the direction perpendicular to the extending direction of the gate structure 220, the size of the partition structures 250 can be increased, and by increasing the size of the partition structures 250, the reliability of the partition structures 250 for partitioning the interconnect structure is improved. Thus, when forming the interconnect structure subsequently, the overlay accuracy requirement between the pattern of the interconnect structure and the pattern of the partition structures 250 is reduced, the process window size for the forming processes of the partition structures 250 and the interconnect structure is increased, and further the process difficulty is reduced.

[0078] The method for forming the partition structures 250 includes: forming a partition structure material layer (not shown) on the surface of the first dielectric layer 210, on the surface of the gate structure 220, and within the partition openings 211; and planarizing the partition structure material layer until the surface of the first dielectric layer 210 is exposed.

[0079] It should be noted that since in this embodiment, a gate protection structure is formed on the surface of the gate structure 210, forming the partition structure material layer on the surface of the gate structure 220 means forming the partition structure material layer on the surface of the gate protection structure 221.

[0080] The process for forming the partition structure material layer includes: a spin coating process or a deposition process, etc. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc.

[0081] The process for planarizing the partition structure material layer includes: an etch-back process or a chemical mechanical polishing process (CMP).

[0082] In this embodiment, the material of the partition structures 250 includes one or more of a semiconductor material, a metal material, and a metal compound, for example, silicon, silicon germanium, a multi-element semiconductor material composed of group III-V elements, etc.

[0083] In another embodiment, the material of the partition structure includes a dielectric material of a non-metal compound, for example, silicon carbide, silicon nitride, silicon oxycarbide, etc.

[0084] Next, after forming the partition structure 250, etch the first dielectric layer 210 to form a plurality of interconnect openings in the first dielectric layer 210, and at least one of the interconnect openings exposes the surface of the substrate 200 and the side wall surface of the partition structure 250. For the specific process of forming the interconnect openings, please refer to Figures 13 to 16 。

[0085] Please refer to Figure 13 and Figure 14 , Figure 13 is Figure 14 the top view structural schematic diagram along the direction X3 in Figure 14 is Figure 13 the cross-sectional structural schematic diagram along the direction X1-X2 in

[0086] During the process of forming the interconnect openings, the interconnect mask layer 260 and the isolation structure 250 together act as a mask to define the graphic size of the interconnect openings.

[0087] In this embodiment, the interconnect mask layer 260 is a hard mask layer (Hard Mask).

[0088] In this embodiment, the material of the interconnect mask layer 260 includes silicon nitride, silicon oxynitride, silicon carbonitride, etc.

[0089] The method of forming the interconnect mask layer 260 includes: forming an interconnect mask material layer (not shown) on the surfaces of the partition structure 250 and the first dielectric layer 210; forming an intermediate mask material layer (not shown) on the surface of the interconnect mask material layer; forming a photoresist interconnect pattern structure 270 on the surface of the intermediate mask material layer. The photoresist interconnect pattern structure 270 has a plurality of photoresist interconnect openings 271. Each of the photoresist interconnect openings 271 at least straddles one partition structure 250, and the photoresist interconnect openings 271 expose a part of the surface of the intermediate mask material layer. The photoresist interconnect pattern structure 270 is used to pattern the interconnect mask material layer; using the photoresist interconnect pattern structure 270 as a mask, etch the intermediate mask material layer until the surface of the interconnect mask material layer is exposed to form an intermediate mask layer 272; using the intermediate mask layer 272 as a mask, etch the interconnect mask material layer until the surface of the first dielectric layer 210 is exposed to form the interconnect mask layer 260.

[0090] In this embodiment, the process of forming the interconnect mask material layer includes a spin coating process or a deposition process, etc. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc.

[0091] In this embodiment, the process of etching the interconnect mask material layer includes a dry etching process or a wet etching process.

[0092] In this embodiment, the intermediate mask material layer is used to improve the pattern stability during the process of transferring the photoresist interconnect pattern structure 270.

[0093] In this embodiment, the process of forming the intermediate mask material layer includes a spin coating process or a deposition process, etc. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc.

[0094] In this embodiment, the material of the intermediate mask material layer includes spin-on carbon or carbon-containing organic materials.

[0095] In this embodiment, the photoresist interconnect pattern structure 270 includes an interconnect photoresist layer (not shown) and an interconnect anti-reflection layer (not shown). The function of the interconnect anti-reflection layer is to improve the anti-reflection ability of the interconnect photoresist layer during the exposure process of forming the interconnect photoresist layer. The interconnect anti-reflection layer includes: a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0096] In this embodiment, after forming the interconnect mask structure 260, the intermediate mask layer 272 and the photoresist interconnect pattern structure 270 are removed.

[0097] Please refer to Figure 15 and Figure 16 , Figure 15 is Figure 16 a top view structural schematic diagram along the direction X3 in Figure 16 is Figure 15 a cross-sectional structural schematic diagram along the direction X1-X2 in

[0098] Using the interconnect mask layer 260 and the partition structure 250 as masks, the first dielectric layer 210 is etched until the surface of the substrate 200 is exposed, so as to form a plurality of interconnect openings 212 in the first dielectric layer 210, and at least one of the interconnect openings 212 exposes the surface of the substrate 200 and the side wall surface of the partition structure 250.

[0099] The process of etching the first dielectric layer 210 includes a dry etching process or a wet etching process.

[0100] In this embodiment, in the process of etching the first dielectric layer 210, the etching selectivity between the first dielectric layer 210 and the partition structure 250 is above 5:1. Thus, due to the relatively large etching selectivity between the first dielectric layer 210 and the partition structure 250, during the etching of the first dielectric layer 210, the loss of the partition structure 250 caused by the etching process is reduced, so as to better form the spaced interconnect openings 212 through the partition structure 250.

[0101] In this embodiment, after forming the interconnect openings 212, the interconnect mask layer 260 is removed.

[0102] Please refer to Figure 17 and Figure 18 , Figure 17 which is Figure 18 a top view structural schematic diagram along the X3 direction in Figure 18 and Figure 17 is a cross-sectional structural schematic diagram along the X1-X2 direction in , and an interconnect structure 280 is formed in the interconnect openings 212.

[0103] The method of forming the interconnect structure 280 includes: forming an interconnect structure material layer (not shown) on the surface of the first dielectric layer 210 and the surface of the isolation structure 250 within the interconnect openings 212; planarizing the interconnect structure material layer until the surface of the first dielectric layer 210 and the surface of the isolation structure 250 are exposed.

[0104] In this embodiment, the process of forming the interconnect structure material layer includes a metal electroplating process or a deposition process, etc.

[0105] The material of the interconnect structure 280 is different from that of the isolation structure 250.

[0106] In this embodiment, the material of the interconnect structure 280 includes polysilicon or a metal material, and the metal material is, for example, copper, tungsten, or aluminum, etc.

[0107] Please refer to Figure 19 and Figure 20 , Figure 19 which is Figure 20 a top view structural schematic diagram along the X3 direction in Figure 20 and Figure 19 is a cross-sectional structural schematic diagram along the X1-X2 direction in . After forming the interconnect structure 280, the partition structure 250 is removed; after removing the partition structure 250, a second dielectric layer 290 is formed in the partition openings 211, and the second dielectric layer 290 also lies on the side wall surface of the interconnect structure 280.

[0108] In this embodiment, since the material of the partition structure 250 includes one or more of semiconductor materials, metal materials, and metal compounds, by removing the partition structure 250 and forming a second dielectric layer 290 within the partition opening 211, that is, replacing the partition structure 250 with the second dielectric layer 290, electrical insulation between the interconnect structures 280 connected to the partition structure 250 is achieved, and moreover, the influence of metal ions in the material of the partition structure on the materials of other structures in subsequent processes is reduced.

[0109] In another embodiment, since the material of the partition structure includes a dielectric material of a non-metallic compound, the partition structure is not removed.

[0110] In this embodiment, the process of removing the partition structure 250 includes a dry etching process or a wet etching process.

[0111] In this embodiment, the method of forming the second dielectric layer 290 includes: forming a second dielectric material layer within the partition opening 211 and on the surface of the first dielectric layer 210; planarizing the second dielectric material layer until the surface of the first dielectric layer 210 is exposed.

[0112] The process of forming the second dielectric layer includes a spin coating process or a deposition process.

[0113] The process of planarizing the second dielectric material layer includes an etch-back process or a chemical mechanical polishing process.

[0114] In other embodiments, no planarization process is performed on the second dielectric material layer.

[0115] In other embodiments, the second dielectric material layer is planarized to form the second dielectric layer, and the surface of the second dielectric layer is higher than the surface of the first dielectric layer.

[0116] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method. Please continue to refer to Figure 17 and Figure 18 , which includes: a substrate 200; a plurality of gate structures 220 located on the substrate 200; a first dielectric layer 210 located on the substrate 200, and the first dielectric layer 210 also located on the sidewall surfaces of the gate structures 220; a plurality of partition structures 250 located within the first dielectric layer 210, each of the partition structures 250 located on one side or both sides of the gate structure 220.

[0117] The following will make a detailed description of the specific embodiments of the present invention with reference to the accompanying drawings.

[0118] In this embodiment, the substrate 200 includes a substrate (not shown) and a plurality of fin structures (not shown) that are separately located on the substrate, and the gate structure 220 straddles the fin structures.

[0119] In other embodiments, the substrate is a planar substrate.

[0120] The material of the substrate includes semiconductor materials.

[0121] In this embodiment, the material of the substrate is silicon.

[0122] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI), etc. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0123] In this embodiment, the semiconductor structure further includes: a substrate dielectric layer 201 located on the surface of the substrate, and the substrate dielectric layer 201 also locates on partial sidewall surfaces of the fin structures.

[0124] In this embodiment, the semiconductor structure further includes: source / drain doping layers (not shown in the figure) located in the fin structures on both sides of the gate structure 220.

[0125] In this embodiment, the first dielectric layer 210 has a plurality of gate openings (not shown), the gate structure 220 is located in the gate openings, and the top surface of the gate structure 220 is lower than the surface of the first dielectric layer 210.

[0126] Specifically, the gate structure 220 includes: a gate dielectric layer (not shown) located on the sidewall surface and bottom surface of the gate opening 211, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer.

[0127] The material of the gate dielectric layer includes a high-k material (dielectric constant greater than 3.9). The high-k materials include: hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, or aluminum oxide, etc.

[0128] The material of the gate electrode layer includes a metal material, for example: one or several combinations of tungsten, copper, tungsten, aluminum, titanium, titanium nitride, or tantalum.

[0129] The material of the work function layer includes titanium nitride, tantalum nitride, or titanium aluminum.

[0130] In this embodiment, the semiconductor structure further includes: a gate protection structure 221 located on the surface of the gate structure 220, and the first dielectric layer 210 also covers the sidewall surface of the gate protection structure 221.

[0131] In this embodiment, the material of the gate protection structure 221 includes a dielectric material.

[0132] In other embodiments, the surface of the gate structure is flush with the surface of the first dielectric structure, and the semiconductor structure does not include the gate protection structure.

[0133] In this embodiment, the material of the partition structure 250 includes one or more of semiconductor materials, metal materials, and metal compounds, such as silicon, silicon germanium, and ternary semiconductor materials composed of group III-V elements.

[0134] In another embodiment, the material of the partition structure includes a dielectric material of a non-metallic compound, such as silicon carbide, silicon nitride, silicon carbonitride, etc.

[0135] In this embodiment, the first dielectric layer 210 further has a plurality of interconnect openings 212 (as Figure 15 shown), and at least one of the interconnect openings 212 exposes the surface of the substrate 200 and the sidewall surface of the partition structure 250.

[0136] In this embodiment, the semiconductor structure further includes: an interconnect structure 280 located within the interconnect openings 212.

[0137] The material of the interconnect structure 280 is different from the material of the isolation structure 250.

[0138] In this embodiment, the material of the interconnect structure 280 includes polysilicon or a metal material, and the metal material is, for example, copper, tungsten, or aluminum.

[0139] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, it includes: a substrate; a plurality of gate structures located on the substrate; a first dielectric layer located on the substrate, and the first dielectric layer also located on the sidewall surfaces of the gate structures; a plurality of partition structures located within the first dielectric layer, each partition structure located on one or both sides of a gate structure; interconnection openings located within the first dielectric layer, at least one of the interconnection openings exposing the substrate surface and the sidewall surfaces of the partition structures; the partition structures are used to form spaced-apart interconnection openings; an interconnection structure located within the interconnection openings, the interconnection structure exposing the surface of the first dielectric layer and the surface of the partition structures.

2. The semiconductor structure according to claim 1, characterized in that, it further includes: a gate protection structure located on the surface of the gate structure, and the first dielectric layer also located on the sidewall surface of the gate protection structure.

3. The semiconductor structure according to claim 1, characterized in that, the material of the partition structures includes one or more of: dielectric materials of non-metallic compounds, semiconductor materials, metal materials, and metal compounds.

4. The semiconductor structure according to claim 2, characterized in that, the material of the gate protection structure includes a dielectric material.

5. A method for forming a semiconductor structure, characterized in that, it includes: providing a substrate; forming a plurality of gate structures on the substrate and a first dielectric layer covering the sidewall surfaces of the gate structures; forming a plurality of partition structures within the first dielectric layer, each partition structure located on one or both sides of a gate structure; after forming the partition structures, etching the first dielectric layer to form a plurality of interconnection openings within the first dielectric layer, and at least 1 of the interconnection openings exposing the substrate surface and the sidewall surfaces of the partition structures; the partition structures are used to form spaced-apart interconnection openings; forming an interconnection structure within the interconnection openings, the interconnection structure exposing the surface of the first dielectric layer and the surface of the partition structures.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, the method for forming a plurality of the partition structures includes: forming a partition mask layer on the surface of the first dielectric layer and the surface of the gate structures, the partition mask layer having a plurality of partition mask openings, each partition mask opening exposing the surface of the first dielectric layer on one or both sides of a gate structure; using the partition mask layer as a mask to etch the first dielectric layer until a plurality of partition openings are formed within the first dielectric layer; forming partition structures within the partition openings.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, the method for forming the partition structures further includes: forming a partition structure material layer on the surface of the first dielectric layer, the surface of the gate structures, and within the partition openings; planarizing the partition structure material layer until the surface of the first dielectric layer is exposed.

8. The method for forming a semiconductor structure according to claim 5, characterized in that, it further includes: before forming the partition structures, forming a gate protection structure on the surface of the gate structures, and the first dielectric layer also located on the sidewall surface of the gate protection structure.

9. The method for forming a semiconductor structure as claimed in claim 5, wherein, the method for forming the interconnect opening includes: forming an interconnect mask layer on the surface of the partition structure and the first dielectric layer, the interconnect mask layer having a plurality of interconnect mask openings spanning the partition structure, the interconnect mask openings exposing a part of the first dielectric layer and the surface of the partition structure; using the interconnect mask layer and the partition structure as a mask to etch the first dielectric layer until the surface of the substrate is exposed.

10. The method for forming a semiconductor structure as claimed in claim 5, wherein, in the process of etching the first dielectric layer, the etching selectivity of the first dielectric layer to the partition structure is above 5:

1.

11. The method for forming a semiconductor structure as claimed in claim 6, wherein, further comprising: after forming the interconnect structure, removing the partition structure; after removing the partition structure, forming a second dielectric layer in the partition opening, and the second dielectric layer also located on the sidewall surface of the interconnect structure.

12. The method for forming a semiconductor structure as claimed in claim 5, wherein, the substrate includes a substrate and a plurality of fin structures located on the substrate, and the gate structure spans the fin structures.

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