Methods for fabricating three-dimensional memory

Abstract

This disclosure provides a method for fabricating a three-dimensional memory, comprising: forming a stacked structure including a core region and a step region on a substrate; forming a first dielectric layer covering the core region and the step region; performing a first etching on the first dielectric layer covering the core region to expose at least a portion of the core region; forming a second dielectric layer covering the remaining first dielectric layer and the exposed core region; wherein the distance between the surface of the second dielectric layer covering the step region and the substrate is greater than the distance between the surface of the core region and the substrate; performing a second etching on the second dielectric layer covering the core region to expose at least a portion of the core region; and after the second etching, planarizing the step region and the core region to make the surface of the step region flush with the surface of the core region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a three-dimensional memory. Background Technology

[0002] 3D memory comprises multiple memory cells stacked vertically, allowing for significantly increased integration density and reduced costs per unit area of ​​wafer. In NAND-structured 3D memory devices, a 3D stacked structure provides devices such as select transistors and storage transistors. The 3D stacked structure includes a core array region for storage and a stair-step region for electrical connections. The ends of the gate structure are located in the stair-step region, are stepped, and are connected to the word lines via conductive channels.

[0003] As the number of stacked memory cell layers in memory devices increases, thicker dielectric layers are needed to fill the step regions, ensuring that the filled step regions are flush with the surface of the core region. This provides a smooth surface for the formation of subsequent film layer structures. During the formation of these dielectric-filled step regions, part of the dielectric layer will cover the core region; therefore, a core planarization (CPL) process is required. Currently, this planarization process is quite challenging. Summary of the Invention

[0004] In view of this, the present disclosure provides a method for manufacturing a three-dimensional memory, comprising:

[0005] A stacked structure including a core region and a step region is formed on the substrate;

[0006] A first dielectric layer is formed covering the core area and the step area;

[0007] A first etching is performed on the first dielectric layer covering the core region to expose at least a portion of the core region;

[0008] A second dielectric layer is formed to cover the remaining first dielectric layer and the exposed area of ​​the core region; wherein the distance between the surface of the second dielectric layer covering the step region and the substrate is greater than the distance between the surface of the core region and the substrate;

[0009] A second etching is performed on the second dielectric layer covering the core region to expose at least a portion of the core region;

[0010] After the second etching, the step area and the core area are planarized so that the surface of the step area is flush with the surface of the core area.

[0011] In some embodiments, the second dielectric layer includes a third sublayer and a fourth sublayer;

[0012] The second dielectric layer forming the coverage of the remaining first dielectric layer and the exposed area of ​​the core region includes:

[0013] A third sublayer is formed to cover the remaining first dielectric layer and the exposed area of ​​the core region;

[0014] A fourth sublayer is formed that covers the third sublayer; wherein the step coverage rate of the third sublayer is greater than the step coverage rate of the fourth sublayer.

[0015] In some embodiments, prior to forming the first dielectric layer, the method further includes: forming a barrier layer covering the core region;

[0016] The first etching of the first dielectric layer covering the core region to expose at least a portion of the core region includes: etching the first dielectric layer covering the core region until the barrier layer is exposed.

[0017] In some embodiments, the second etching of the second dielectric layer covering the core region to expose at least a portion of the core region includes:

[0018] The second dielectric layer of the core region is etched a second time until the barrier layer is exposed.

[0019] In some embodiments, the planarization process for the step region and the core region, so that the surface of the step region is flush with the surface of the core region, includes:

[0020] The second dielectric layer covering the step area and the core area, as well as the first dielectric layer, are planarized until the surface of the step area is flush with the barrier layer covering the core area.

[0021] In some embodiments, prior to performing the flattening process, the method further includes:

[0022] The stepped area is subjected to a first heat treatment.

[0023] In some embodiments, after performing the flattening process, the method further includes:

[0024] The stepped area is subjected to a second heat treatment.

[0025] In some embodiments, the first dielectric layer includes a first sublayer and a second sublayer;

[0026] The formation of the first dielectric layer covering the core region and the step region includes:

[0027] A first sub-layer is formed covering the core area and the stepped area;

[0028] A second sublayer is formed that covers the first sublayer.

[0029] In some embodiments, the first dielectric layer comprises plasma oxide;

[0030] The second dielectric layer comprises: plasma oxide and / or tetraethyl orthosilicate oxide.

[0031] In some embodiments, the thickness of the first dielectric layer is 2 micrometers to 8 micrometers;

[0032] The thickness of the second dielectric layer is 2 micrometers to 8 micrometers.

[0033] In related technologies, after depositing dielectric layers in the core and step regions, the dielectric layer in the core region is etched, and then the remaining dielectric layer is planarized. Because the dielectric layer has a large thickness, it generates significant stress on the wafer, leading to wafer bending. After etching the dielectric layer in the core region, the dielectric layer covering the boundary between the step and core regions forms sharp corners with considerable height, posing a significant challenge to the planarization process, increasing the probability of planarization defects, and reducing the device planarization effect.

[0034] In this embodiment, a first dielectric layer is first formed and a first etching is performed on the core region. Then, a second dielectric layer is formed and a second etching is performed on the second dielectric layer. Finally, planarization is performed to make the surfaces of the core region and the step region flush. The first etching removes a portion of the first dielectric layer in the core region, reducing wafer stress and improving wafer bending. After the first etching, the first dielectric layer forms a first sharp corner with a relatively small height. The deposition rate of the second dielectric layer above the first sharp corner is lower than the deposition rate on the flat surface. Therefore, the height of the second sharp corner formed after the second etching is less than the height of the sharp corner formed after etching the dielectric layer in the core region in related technologies. This reduces the amount of material removed during planarization, which helps to expand the planarization process window, reduce the probability of planarization defects, and improve the flatness of the core region and the step region. Furthermore, a flatter device surface also facilitates the deposition of mask layers in subsequent processes, thereby improving the yield of memory devices. Attached Figure Description

[0035] Figure 1 This is a flowchart illustrating a method for manufacturing a three-dimensional memory according to an exemplary embodiment;

[0036] Figures 2a to 2c This is a schematic diagram illustrating a method for manufacturing a three-dimensional memory according to an exemplary embodiment;

[0037] Figure 3 This is a schematic flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure;

[0038] Figures 4a to 4e This is a schematic diagram illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure;

[0039] Figure 5a and 5b This is a schematic diagram illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure. Detailed Implementation

[0040] The technical solution of this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] In this embodiment of the disclosure, the terms "first," "second," etc., are used to distinguish similar objects, and not to describe a specific order or sequence.

[0042] In this embodiment of the disclosure, the term "A in contact with B" includes the case where A and B are in direct contact, or the case where there are other components between A and B and A is indirectly in contact with B.

[0043] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. Layers may extend horizontally, vertically, and / or along inclined surfaces. Furthermore, a layer may comprise multiple sublayers.

[0044] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0045] It should be noted that although this specification describes the embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0046] Figure 1This is a schematic flowchart illustrating a method for fabricating a three-dimensional memory according to an exemplary embodiment. Figures 2a to 2c This is a schematic diagram illustrating a method for fabricating a three-dimensional memory according to an exemplary embodiment. (In conjunction with...) Figure 1 , Figures 2a to 2c As shown, the method includes the following steps:

[0047] S101: Reference Figure 2a As shown, a stacked structure including a core region 110 and a step region 120 is formed on a substrate 100; a dielectric layer 131 is formed covering the core region 110 and the step region 120.

[0048] S102: Reference Figure 2b As shown, the dielectric layer 131 covering the core region 110 is etched to expose at least a portion of the core region 110.

[0049] S103: Reference Figure 2c As shown, after etching, the step region 120 and the core region 110 are planarized to make the surface of the step region 120 and the surface of the core region 110 flush.

[0050] For example, in a three-dimensional NAND memory architecture, a stacked structure provides devices such as select transistors and memory transistors. The stacked structure includes a core region for storage and a stair-step region for electrical connections. The stacked structure may consist of a control gate and an interlayer insulating layer sequentially stacked on a substrate. The materials used to construct the control gate include, but are not limited to, tungsten and polysilicon. The materials used to construct the interlayer insulating layer include, but are not limited to, silicon oxide, silicon nitride, and silicon oxynitride. The ends of the control gate are located in the stair-step region and can be connected to word lines via conductive channels, thereby applying different control voltages to the control gate to achieve read, write, or erase operations on the memory.

[0051] It is understood that a step includes at least one control gate and an interlayer insulating layer adjacent to the control gate. The step region may have multiple steps of different heights.

[0052] Specifically, refer to Figure 2aAs shown, the surface of the step region 120 and the surface of the core region 110 have a certain height difference. The height between the surface of the core region 110 and the substrate 100 is greater than or equal to the height between the surface of the step region 120 and the substrate 100. A deposition medium layer 131 covers the step region 120 and the core region 110 to eliminate this height difference. The deposition medium layer 131 covers both the core region 110 and the step region 120, and the distance between the surface of the medium layer 131 and the substrate 100 is greater than or equal to the distance between the surface of the core region 110 and the substrate 100. In other words, the medium layer covers the step region 120 to eliminate the height difference, achieving complete filling of the step region 120.

[0053] As the number of memory stacking layers increases, the height difference also increases, requiring a thicker dielectric layer. Excessive dielectric layer deposition will lead to uneven wafer stress distribution, causing wafer bending, affecting subsequent process execution, and reducing device yield.

[0054] Reference Figure 2b As shown, etching is performed on the dielectric layer 131 of the core region 110, exposing a portion of the core region 110. Simultaneously, the etched dielectric layer 131 forms sharp corners 160 protruding from the surface of the core region 110. The height of the sharp corners 160 is related to the thickness of the dielectric layer 131; the thicker the dielectric layer, the higher the sharp corner. High-height sharp corners increase the difficulty of the planarization process in step S103, increasing the probability of planarization defects and reducing the planarization effect. Furthermore, in actual manufacturing, high-height sharp corners also increase the risk of damage to the polishing pad in the chemical mechanical polishing process, reducing the lifespan of the polishing pad and increasing manufacturing costs.

[0055] Based on this, the present disclosure provides a method for manufacturing a three-dimensional memory.

[0056] Figure 3 This is a schematic flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure. Figures 4a to 4e This is a schematic diagram illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure. (In conjunction with...) Figure 3 , Figures 4a to 4e As shown, the method includes the following steps:

[0057] S301: Reference Figure 4a As shown, a stacked structure including a core region 110 and a step region 120 is formed on the substrate 100;

[0058] S302: Reference Figure 4a As shown, a first dielectric layer 141 is formed covering the core region 110 and the step region 120;

[0059] S303: Reference Figure 4bAs shown, a first etching is performed on the first dielectric layer 141 covering the core region 110 to expose at least a portion of the core region 110;

[0060] S304: Reference Figure 4c As shown, a second dielectric layer 142 is formed to cover the remaining first dielectric layer 141 and the exposed area of ​​the core region 110; wherein, the distance between the surface of the second dielectric layer 142 covering the step region 120 and the substrate 100 is greater than the distance between the surface of the core region 110 and the substrate 100.

[0061] S305: Reference Figure 4d As shown, a second etching is performed on the second dielectric layer 142 covering the core region 110 to expose at least a portion of the core region 110;

[0062] S306: Reference Figure 4e As shown, after the second etching, the step region 120 and the core region 110 are planarized so that the surface of the step region 120 is flush with the surface of the core region 110.

[0063] For example, the constituent materials of the substrate 100 may include: elemental semiconductor materials (e.g., silicon, germanium), group III-V compound semiconductor materials, group II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. In this embodiment, polycrystalline silicon is preferred.

[0064] For example, the first etching process may include one or any combination of dry etching and wet etching.

[0065] For example, the second etching process may include one or any combination of dry etching and wet etching.

[0066] For example, the planarization process may include chemical mechanical polishing or a combination of chemical mechanical polishing, wheel milling, and cleaning.

[0067] In some embodiments, refer to Figure 4a As shown, the distance between the surface of the core region 110 and the substrate 100 is greater than or equal to the distance between the surface of the step region 120 and the substrate 100. Therefore, in the direction perpendicular to the substrate 100, the surface of the step region 120 and the surface of the core region 110 have a certain height difference, and steps at different heights have different height differences with the surface of the core region 110.

[0068] It should be emphasized that in steps S302 and S303, the thickness of the first dielectric layer 141 cannot completely eliminate the height difference between the step area 120 and the core area 110, that is, the thickness of the first dielectric layer 141 is insufficient to eliminate all the height differences between the steps and the surface of the core area 110.

[0069] Reference Figure 4c As shown, after executing step S304, the first dielectric layer 141 and the second dielectric layer 142 of the step region 120 fill the entire step region 120, and the distance between the surface of the second dielectric layer 142 covering the step region 120 and the substrate 100 is greater than the distance between the surface of the core region 110 and the substrate 100. That is, the total thickness of the first dielectric layer 141 and the second dielectric layer 142 can eliminate the height difference between all steps of the step region 120 and the surface of the core region 110.

[0070] Furthermore, to achieve higher storage density, the memory's stacked structure has more layers, and the height difference between the step region and the core region also increases accordingly. During the deposition and filling process of the step region, a single deposition process is insufficient to achieve good coverage. Steps S302 and S304 form the first dielectric layer and the second dielectric layer in two separate steps, which can improve the step coverage of the first and second dielectric layers on the step, enhance the coverage performance of the step region, and reduce the generation of void defects in the step region.

[0071] Continue to refer to Figure 4c As shown, the distance between the surface of the second dielectric layer 142 of the step region 120 and the substrate 100 is greater than the distance between the surface of the core region 110 and the substrate 100. It should be understood that the distance D1 of the second dielectric layer 142 relative to the surface of the substrate 100 is greater than the distance D2 between the surface of the core region 110 and the upper surface of the substrate 100.

[0072] Understandably, because the stepped region has raised stepped structures of varying heights, during the deposition of the first and second dielectric layers, the first and second dielectric layers in the stepped region will also conformally form raised structures following the shape of the stepped structures. Therefore, compared to the first and second dielectric layers deposited on the flat surface of the core region, the dielectric layers in the stepped region have raised structures.

[0073] Reference Figure 4b As shown, a portion of the first dielectric layer 141 of the core region 110 is etched to expose at least a portion of the core region 110. The first etching targets only the first dielectric layer 141 of the core region 110 and does not contact the first dielectric layer 141 of the step region 120, thus avoiding etching away the first dielectric layer 141 deposited in the step region 120. Before performing the first etching, photoresist can be applied to the core region and the step region to pattern the photoresist. Using the patterned photoresist as a mask, the first etching is performed on the first dielectric layer.

[0074] By adjusting the position of the photolithography pattern, more of the core area can be exposed through the first etching, or even all of it can be exposed. This reduces the difficulty of the planarization process in step S306, expands the planarization process window, and reduces the probability of planarization defects. Furthermore, the first etching removes part of the first dielectric layer in the core area, which can reduce the stress of the first dielectric layer on the wafer surface and improve wafer bending.

[0075] Similarly, refer to Figure 4d As shown, the second etching only targets the second dielectric layer 142 of the core region 110, without contacting the second dielectric layer 142 of the step region 120 or the first dielectric layer 141 of the step region 120. Alternatively, by adjusting the position of the photolithography pattern, more of the core region 110 can be exposed, or all of it can be exposed, reducing the difficulty of planarization.

[0076] Reference Figure 4c and Figure 4d As shown, it can be understood that the second etching can not only etch a portion of the second dielectric layer 142 in the core region 110, but also remove a portion of the second dielectric layer 142 in the core region 110 and the portion of the first dielectric layer 141 remaining in the core region 110 after step S303 by adjusting the position of the photolithography pattern. This further reduces the difficulty of the planarization process in step S306, helps to expand the planarization process window, and helps to reduce the generation of planarization defects.

[0077] Continue to refer to Figure 4b and 4d As shown, after the first dielectric layer 141 is etched, a first sharp corner 161 higher than the surface of the core region 110 is generated. After the second etching in step S305, the second dielectric layer 142 of the core region 110 also generates a second sharp corner 162 higher than the surface of the core region 110. It should be emphasized that, under the same dielectric layer deposition process, the deposition rate of the second dielectric layer on the surface of the first sharp corner is lower than the deposition rate on the flat surface. Therefore, the second dielectric layer formed on the surface of the first sharp corner is thinner than the second dielectric layer formed on the flat surface.

[0078] Therefore, compared to the single etching of related technologies, the present invention performs a first etching to form a first sharp corner, which can reduce the height of the sharp corner generated by the second etching, reduce the amount of material removed during planarization, reduce the generation of defects in the planarization process, and facilitate the expansion of the planarization process window.

[0079] In this embodiment, a first dielectric layer is first formed and a first etching is performed on the core region, then a second dielectric layer is formed and a second etching is performed on the second dielectric layer, and finally a planarization process is performed to make the surface of the core region and the surface of the step region flush.

[0080] The first etching removes a portion of the first dielectric layer in the core region, reducing wafer stress and improving wafer bending. After the first etching, the first dielectric layer forms a relatively small first sharp corner. The deposition rate of the second dielectric layer above the first sharp corner is lower than the deposition rate on the flat surface. Therefore, the height of the second sharp corner formed after the second etching is less than the height of the sharp corner formed after etching the dielectric layer in the core region in related technologies. This reduces the amount of material removed for planarization, which helps to expand the planarization process window, reduces the probability of planarization defects, and improves the flatness of the core region and the step region. Furthermore, a flatter device surface also facilitates the deposition of mask layers in subsequent processes, thereby improving the yield of memory devices.

[0081] In some embodiments, refer to Figure 5a As shown, the second dielectric layer 142 includes a third sublayer 145 and a fourth sublayer 146;

[0082] Step S304 includes:

[0083] A third sublayer 145 is formed, covering the remaining first dielectric layer 141 and the exposed area of ​​the core region 110;

[0084] A fourth sublayer 146 is formed that covers the third sublayer 145; wherein the step coverage rate of the third sublayer 145 is greater than the step coverage rate of the fourth sublayer 146.

[0085] After step S303 is executed, a second dielectric layer 142 is formed on the surface of the remaining first dielectric layer 141 after the first etching. The second dielectric layer 142 is formed by deposition in two stages: first, a third sublayer 145 is deposited, and then a fourth sublayer 146 is deposited. The third sublayer 145 and the fourth sublayer 146 together complete the coverage of the step region 120 and the core region 110.

[0086] For example, step coverage is a parameter characterizing the uniformity of film formation during the deposition process. In this embodiment, when filling the step region with a dielectric material, the aforementioned step coverage can be reflected by the difference between the film thickness of the dielectric material on the step sidewall and the film thickness on the step surface. It is understood that dielectric materials with a high step coverage have better filling performance in the step region, fewer filling defects, and can form a more uniform film thickness.

[0087] In some embodiments, the step coverage of the dielectric material can be characterized by the ratio of A to B. A is the thickness of the dielectric material deposited on the step sidewall, and B is the thickness of the dielectric material deposited on the step surface. A larger ratio indicates a higher step coverage and better filling performance. In this embodiment, the film thicknesses A and B can be measured by slicing and then using a scanning electron microscope or transmission electron microscope, or directly by measuring the step area using an optical film thickness measurement machine. A and B can be calculated using the same measurement method, taking the average value of multiple samples to improve measurement accuracy.

[0088] In this embodiment of the disclosure, the third sublayer 145 has a larger step coverage than the fourth sublayer 146. The third sublayer may include a dielectric layer formed by a high-density plasma chemical vapor deposition (HDPCVD) process, and the fourth sublayer may include a tetraethyl orthosilicate oxide dielectric layer formed by a plasma-enhanced chemical vapor deposition (PECVD) process.

[0089] After etching, the first dielectric layer 141 forms an uneven surface. The third sublayer 145 has a larger step coverage than the fourth sublayer 146, which allows for better contact between the third sublayer 145 and the first dielectric layer 141. This reduces voids and defects caused by the lower step coverage of the third sublayer 145, providing a smoother contact surface for the formation of the fourth sublayer 146 and facilitating the coverage of the step area. Depositing a fourth dielectric layer with a relatively smaller step coverage on the third sublayer 145 can effectively cover the step area 120 and the core area 110 while reducing process costs.

[0090] In some embodiments, refer to Figure 4a As shown, before performing step S302, the method further includes: forming a barrier layer 151 covering the core region 110;

[0091] Reference Figure 4b As shown, step S303 includes: performing a first etching on the first dielectric layer 141 covering the core region 110 until the barrier layer 151 is exposed.

[0092] For example, the barrier layer 151 may include, but is not limited to, silicon nitride, silicon oxynitride, amorphous carbon, polycrystalline silicon, titanium nitride, etc.

[0093] Before forming the first dielectric layer 141 covering the core region 110 and the step region 120, a barrier layer 151 is formed on the surface of the core region 110. During the first etching process in step S303, the etching rate of the first etch on the barrier layer 151 is lower than the etching rate of the first etch on the first dielectric layer 141, or the first etch does not etch the barrier layer 151. The first etch may stop on the surface of the barrier layer 151, or it may partially etch the barrier layer 151 but not penetrate it.

[0094] The embodiments disclosed herein protect the core area from damage caused by the first etching by forming a barrier layer, which helps to reduce the risk of memory device failure.

[0095] In some embodiments, refer to Figure 4d As shown, step S305 includes:

[0096] The second dielectric layer 142 of the core region 110 is etched a second time until the barrier layer 151 is exposed.

[0097] During the second etching process, the etching rate of the second etch on the barrier layer 151 is lower than the etching rate of the second etch on the second dielectric layer 142, or the second etch does not etch the barrier layer 151 at all. The second etch may stop at the surface of the barrier layer 151, or it may partially etch the barrier layer 151 but not penetrate it.

[0098] The embodiments disclosed herein can protect the core area from damage by the second etching by forming a barrier layer, which helps to reduce the risk of memory device failure.

[0099] In some embodiments, refer to Figure 4e As shown, step S306 includes:

[0100] The second dielectric layer 142 and the first dielectric layer 141 covering the step area 120 and the core area 110 are planarized until the surface of the step area 120 is flush with the barrier layer 151 covering the core area 110.

[0101] In the embodiments of this disclosure, the planarization process includes, but is not limited to, chemical mechanical polishing. During the planarization process, the removal rate of the barrier layer 151 by the planarization process is lower than the removal rate of the second dielectric layer 142 and the first dielectric layer 141 by the planarization process, or the barrier layer 151 is not removed by the planarization process.

[0102] To address the mechanical abrasive action and wet etching effect of the abrasive in chemical mechanical polishing (CMP) processes, a barrier layer can be selected, which may be a material with higher hardness than the first and second dielectric layers, a material more resistant to abrasive etching than the first and second dielectric layers, or a material that simultaneously satisfies both high hardness and resistance to abrasive etching. Those skilled in the art can select the barrier layer based on process requirements.

[0103] The embodiments disclosed herein can protect the core area from damage caused by planarization by forming a barrier layer, thereby reducing the risk of storage device failure.

[0104] In some embodiments, before performing step S306, the method further includes:

[0105] The step region 120 is subjected to a first heat treatment to reduce the contact stress between the first dielectric layer 141 and the second dielectric layer 142.

[0106] For example, the first heat treatment process includes, but is not limited to, furnace tube annealing.

[0107] The first dielectric layer 141 and the second dielectric layer 142 in the step region have a large thickness, which generates large stress on the wafer surface, causing the wafer to bend. Before performing planarization, the step region 120 is subjected to a first heat treatment to reduce the contact stress between the first dielectric layer 141 and the second dielectric layer 142, reduce wafer bending, improve the planarization effect, and reduce the risk of wafer breakage during the planarization process.

[0108] In some embodiments, after performing step S306, the method further includes:

[0109] The step zone 120 is subjected to a second heat treatment.

[0110] For example, the second heat treatment process includes, but is not limited to, furnace tube annealing.

[0111] During the planarization process, the wafer surface is mechanically polished. Under the pressure of mechanical polishing, stress is generated in the first dielectric layer 141 and the second dielectric layer 142 in the step region. The second heat treatment can reduce the accumulation of stress, thereby improving the stability of the device.

[0112] In some embodiments, refer to Figure 5b As shown, the first dielectric layer 141 includes a first sublayer 143 and a second sublayer 144;

[0113] Step S302 includes:

[0114] Forming the first sub-layer 143 covering the core area 110 and the stepped area 120;

[0115] A second sublayer 144 is formed, covering the first sublayer 143.

[0116] To achieve higher storage density, memory stacking structures have more layers of memory cells, including but not limited to 32 layers, 64 layers, 96 layers, and 128 layers. The depth of the step region also increases accordingly. A single deposition of a thick first dielectric layer 141 makes it difficult to achieve good coverage of the step region 120, easily leading to void defects at the contact surface between the step region 120 and the first dielectric layer 141. Dividing the first dielectric layer 141 into a first sub-layer 143 and a second sub-layer 144 for step-by-step filling can improve filling performance, reduce void defects, and enhance device stability.

[0117] It is understood that the first sub-layer and the second sub-layer in this embodiment are only for distinguishing similar objects. The first dielectric layer may also include more sub-layers depending on the depth of the step area to achieve better filling and coverage of the step area.

[0118] In some embodiments, refer to Figure 4a and 4c As shown, the first dielectric layer 141 includes plasma oxide;

[0119] The second dielectric layer 142 includes: plasma oxide and / or tetraethyl orthosilicate oxide.

[0120] The first dielectric layer 141 includes, but is not limited to, a dielectric layer formed by high-density plasma chemical vapor deposition (HDPCVD).

[0121] The second dielectric layer 142 includes plasma oxide and / or tetraethyl orthosilicate oxide, and the formation process includes, but is not limited to, high-density plasma chemical vapor deposition (HDPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0122] The first dielectric layer has a higher density and step coverage compared to the tetraethyl orthosilicate dielectric layer, enabling better coverage of the stepped region and reducing void defects. The tetraethyl orthosilicate dielectric layer exhibits lower stress; with the first dielectric layer already providing good coverage of the stepped region, the second dielectric layer can further reduce stress in the stepped region, thus improving device stability.

[0123] In some embodiments, refer to Figure 4a and 4c As shown, the thickness of the first dielectric layer 141 is 2 micrometers to 8 micrometers;

[0124] The thickness of the second dielectric layer 142 is 2 micrometers to 8 micrometers.

[0125] To ensure adequate coverage of the step region, the first dielectric layer 141 and the second dielectric layer 142 have a certain thickness. In this embodiment, the preferred thicknesses of the first dielectric layer 141 and the second dielectric layer 142 are 2 to 8 micrometers. This not only ensures good filling and coverage of the step region but also reduces the difficulty of planarization, minimizes stress concentration in the step region that could lead to wafer bending, and improves device stability.

[0126] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: A stacked structure including a core region and a stepped region is formed on the substrate; A first dielectric layer is formed covering the core area and the step area; The distance between a portion of the surface of the first dielectric layer and the substrate is smaller than the distance between the surface of the core region and the substrate; A first etching is performed on the first dielectric layer covering the core region to expose at least a portion of the core region; Forming a second dielectric layer covering the remaining first dielectric layer and the exposed area of ​​the core region includes: forming a third sub-layer covering the remaining first dielectric layer and the exposed area of ​​the core region; forming a fourth sub-layer covering the third sub-layer; the step coverage of the third sub-layer is greater than the step coverage of the fourth sub-layer; wherein the distance between the surface of the second dielectric layer covering the step region and the substrate is greater than the distance between the surface of the core region and the substrate; A second etching is performed on the second dielectric layer covering the core region to expose at least a portion of the core region; After the second etching, the step area and the core area are planarized so that the surface of the step area is flush with the surface of the core area.

2. The method according to claim 1, characterized in that, Before forming the first dielectric layer, the method further includes: forming a barrier layer covering the core region; The first etching of the first dielectric layer covering the core region to expose at least a portion of the core region includes: etching the first dielectric layer covering the core region until the barrier layer is exposed.

3. The method according to claim 2, characterized in that, The second etching of the second dielectric layer covering the core region to expose at least a portion of the core region includes: The second dielectric layer of the core region is etched a second time until the barrier layer is exposed.

4. The method according to claim 2, characterized in that, The planarization process for the stepped area and the core area, so that the surface of the stepped area is flush with the surface of the core area, includes: The second dielectric layer covering the step area and the core area, as well as the first dielectric layer, are planarized until the surface of the step area is flush with the barrier layer covering the core area.

5. The method according to claim 1, characterized in that, Before performing the flattening process, the method further includes: The stepped area is subjected to a first heat treatment.

6. The method according to claim 1, characterized in that, After performing the flattening process, the method further includes: The stepped area is subjected to a second heat treatment.

7. The method according to claim 1, characterized in that, The first dielectric layer includes a first sublayer and a second sublayer; The formation of the first dielectric layer covering the core region and the step region includes: A first sub-layer is formed covering the core area and the stepped area; A second sublayer is formed that covers the first sublayer.

8. The method according to claim 1, characterized in that, The first dielectric layer comprises plasma oxide; The second dielectric layer comprises: plasma oxide and / or tetraethyl orthosilicate oxide.

9. The method according to claim 1, characterized in that, The thickness of the first dielectric layer is 2 micrometers to 8 micrometers; The thickness of the second dielectric layer is 2 micrometers to 8 micrometers.

Images