Method for manufacturing semiconductor device, semiconductor device, and memory

Abstract

The application discloses a semiconductor device manufacturing method, a semiconductor device and a memory. The method comprises the following steps: providing a substrate and a stack layer on the substrate, wherein the stack layer comprises a top selection gate; forming a film layer structure on the stack layer, wherein the film layer structure comprises a self-alignment pattern; forming a top selection gate cut groove along the self-alignment pattern, and the top selection gate cut groove penetrates the top selection gate; and forming a top selection gate isolation line in the top selection gate cut groove. The application can simplify the manufacturing difficulty of the top selection gate isolation line and improve the performance of the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device manufacturing method, a semiconductor device and a memory. BACKGROUND

[0002] The existing semiconductor device etches a top select gate cut (TSG CUT) between two adjacent rows of storage channel holes (CH) through a mask layer, but the opening size corresponding to the top select gate cut in the mask layer is small, which increases the difficulty of optical proximity correction (OPC), and if the cross section of the top select cut is wavy, the difficulty of optical proximity correction is further increased, which further leads to difficulty in forming a top select gate cut meeting the requirements. In addition, using a mask layer for etching leads to difficulty in controlling the overlay (OVL) of the top select gate cut between two adjacent rows of storage channel holes, which further easily leads to too small spacing between the top select gate cut and the adjacent storage channel hole, affecting the performance of the semiconductor device. SUMMARY

[0003] The present application provides a semiconductor device manufacturing method, a semiconductor device and a memory, which can simplify the manufacturing difficulty of the top select gate spacer and improve the performance of the semiconductor device.

[0004] The present application provides a semiconductor device manufacturing method, comprising:

[0005] providing a substrate and a stack layer on the substrate, the stack layer comprising a top select gate;

[0006] forming a film layer structure on the stack layer, the film layer structure comprising a self-aligned pattern;

[0007] forming a top select gate cut along the self-aligned pattern, and the top select gate cut penetrating the top select gate;

[0008] forming a top select gate spacer in the top select gate cut.

[0009] Further preferably, the width of the top select gate spacer is less than a preset width.

[0010] Further preferably, the cross section of the top select gate spacer is curved.

[0011] Further preferably, the film layer structure further comprises a stop layer;

[0012] the upper surface of the stop layer is flush with the upper surface of the self-aligned pattern.

[0013] Further preferably, the step of forming a film layer structure on the stack layer comprises:

[0014] forming an initial self-aligned pattern on the stack layer;

[0015] forming an initial stop layer on the stack layer and the initial self-aligned pattern;

[0016] polishing the initial stop layer and the initial self-aligned pattern, so that the polished initial stop layer constitutes the stop layer, and the polished initial self-aligned pattern constitutes the self-aligned pattern.

[0017] Further preferably, the step of forming an initial self-aligned pattern on the stack layer comprises:

[0018] forming a medium layer on the stack layer;

[0019] forming a mask layer on the medium layer;

[0020] etching the medium layer through the mask layer, so that the etched medium layer constitutes the initial self-aligned pattern;

[0021] removing the mask layer.

[0022] Further preferably, the step of forming a top select gate cut along the self-aligned pattern comprises:

[0023] etching the film layer structure and the stack layer to remove the self-aligned pattern and the top select gate corresponding to the self-aligned pattern, so as to obtain the self-aligned top select gate cut.

[0024] Further preferably, the stack layer comprises a stack structure, and the stack structure comprises the top select gate;

[0025] a plurality of rows of storage channel structures are formed in the stack layer and penetrate the stack structure, the top select gate separation line is located between two adjacent rows of storage channel structures, and the distance between the top select gate separation line and the two adjacent rows of storage channel structures is equal.

[0026] Further preferably, the peripheral side of the storage channel structure further forms a transition layer, and the peripheral side of the transition layer further forms a barrier layer;

[0027] The distance between the top select gate separation line and the two adjacent rows of storage channel structures is greater than the sum of the thicknesses of the transition layer and the barrier layer.

[0028] Further preferably, the step of forming a top select gate separation line in the top select gate cut comprises:

[0029] filling an insulating layer in the top select gate cut;

[0030] The film layer structure, partial stack layer and partial insulation layer are removed, and the remaining insulation layer in the top select gate slot forms a top select gate spacer line.

[0031] Further preferably, the storage channel structure comprises a sacrificial layer on top of the storage channel structure.

[0032] The step of removing the film layer structure, partial stack layer and partial insulation layer comprises:

[0033] The film layer structure, the stack layer and the insulation layer are ground to remove the film layer structure, partial stack layer and partial insulation layer on the side of the sacrificial layer away from the substrate, and the sacrificial layer is exposed.

[0034] Further preferably, the method further comprises:

[0035] The sacrificial layer is removed, and a plug is formed on top of the storage channel structure.

[0036] Further preferably, the step of removing the sacrificial layer and forming a plug on top of the storage channel structure comprises:

[0037] The sacrificial layer is removed, and the side of the sacrificial layer is etched to form an opening on top of the storage channel structure.

[0038] The plug is filled in the opening.

[0039] Correspondingly, the application also provides a semiconductor device, comprising:

[0040] a substrate;

[0041] a stack structure on the substrate, the stack structure comprising a top select gate;

[0042] a top select gate spacer line penetrating through the top select gate, the width of the top select gate spacer line being less than a preset width.

[0043] Further preferably, the cross section of the top select gate spacer line is curved.

[0044] Further preferably, the semiconductor device further comprises a plurality of rows of storage channel structures penetrating through the stack structure.

[0045] The top select gate spacer line is located between two adjacent rows of storage channel structures, and the distance between the top select gate spacer line and the two adjacent rows of storage channel structures is equal.

[0046] Further preferably, the side of the storage channel structure further comprises a transition layer, and the side of the transition layer further comprises a barrier layer.

[0047] The distance between the top select gate isolation line and the adjacent two rows of storage channel structures is greater than the sum of the thicknesses of the transition layer and the blocking layer.

[0048] Further preferably, the storage channel structure comprises an isolation layer, a channel layer arranged around the isolation layer, a storage medium layer arranged at the channel layer, and a plug arranged on top of the isolation layer.

[0049] The plug is connected with the channel layer, and the top of the isolation layer is projected onto the plug.

[0050] Correspondingly, the application also provides a memory, comprising a storage array structure and a peripheral structure connected with the storage array structure.

[0051] The storage array structure comprises the semiconductor device.

[0052] The application has the following beneficial effects: by forming a film layer structure with a self-aligned pattern on a stack layer, forming a top select gate cutout in the stack layer along the self-aligned pattern, making the top select gate cutout pass through a top select gate in the stack layer, and forming a top select gate isolation line in the top select gate cutout without using a mask layer to etch the top select gate cutout, the manufacturing difficulty of the top select gate cutout is reduced, and the manufacturing difficulty of the top select gate isolation line is further reduced, and the overlay alignment problem of the top select gate cutout between adjacent two rows of storage channel structures is solved, the distance between the top select gate isolation line and the adjacent storage channel structures is ensured, and the performance of the semiconductor device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only show some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0054] Figure 1 A flowchart of a manufacturing method of a semiconductor device provided by the embodiment of the application is shown in the figure.

[0055] Figure 2a A top view of a stack layer region arrangement in a semiconductor device provided by the embodiment of the application is shown in the figure.

[0056] Figure 2b A top view of another stack layer region arrangement in a semiconductor device provided by the embodiment of the application is shown in the figure.

[0057] Figures 3a to 3i A structural diagram of a manufacturing method of a semiconductor device provided by the embodiment of the application is shown in the figure.

[0058] Figure 4 A connection diagram of the memory channel structure and the common source structure in the semiconductor device provided by the embodiment of the present application is shown in Fig. 1;

[0059] Figure 5 Another connection diagram of the memory channel structure and the common source structure in the semiconductor device provided by the embodiment of the present application is shown in Fig. 2;

[0060] Figure 6 Still another connection diagram of the memory channel structure and the common source structure in the semiconductor device provided by the embodiment of the present application is shown in Fig. 3;

[0061] Figure 7 A structure diagram of the memory provided by the embodiment of the present application is shown in Fig. 4. DETAILED DESCRIPTION

[0062] The specific structure and functional details disclosed herein are merely representative and are intended for the purpose of describing exemplary embodiments of the present application. However, the present application can be embodied in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0063] In the description of the present application, it needs to be understood that the orientation or positional relationship indicated by the terms "center", "transverse", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the purpose of facilitating the description of the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as a limitation of the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified and limited, the meaning of "a plurality of" is two or more. In addition, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0064] In the description of the present application, it needs to be understood that, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0065] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0066] Referring to Figure 1 FIG. 1 is a flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0067] As shown in Figure 1 FIG. 1, the method for manufacturing a semiconductor device according to an embodiment of the present application includes steps 101 to 104, which are specifically as follows.

[0068] In step 101, a substrate and a stack layer on the substrate are provided, and the stack layer includes a top select gate.

[0069] In the embodiment of the present application, the substrate can be a substrate such as a silicon substrate or a substrate including other elemental semiconductors or compound semiconductors. The substrate can also include a plurality of semiconductor layers stacked one on another, which can be polysilicon or the like. The substrate can also include other film layers, which are not specifically limited herein.

[0070] The stack layer can include a stack structure and a cap layer on the stack structure. The stack structure includes a plurality of gate layers and interlayer insulating layers alternately stacked in a longitudinal direction, which is a direction perpendicular to the upper surface of the substrate. The number of layers of the gate layers and the interlayer insulating layers is not limited, and can be, for example, 48 layers, 64 layers, 128 layers, or the like. The gate layers include, but are not limited to, tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide. The interlayer insulating layers include, but are not limited to, any one or a combination of two or more of silicon oxide, silicon nitride, and silicon oxynitride. The cap layer includes, but is not limited to, any one or a combination of two or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0071] The stack layer can include a core region SS and a step region Core. As shown in Figure 2a The step region SS can be located on opposite sides of the core region Core, i.e., the number of step regions SS can be two, and one step region SS is connected to each of the opposite sides of the core region Core. As shown in Figure 2b The core region Core can also be located on opposite sides of the step region SS, i.e., the number of core regions Core can be two, and one core region Core is connected to each of the opposite sides of the step region SS. The core region SS and the step region Core can also have other positional relationships, which are not specifically limited herein.

[0072] The step region SS of the stack layer is formed with a step structure. The core region Core of the stack layer is formed with a plurality of memory channel structures longitudinally penetrating the stack structure, and the cover layer is located on the stack structure and covers the memory channel structures.

[0073] As shown in Figure 3a , a substrate 1 and a stack layer 2 located on the substrate 1 are provided, the stack layer 2 includes a stack structure 21 located on the substrate 1, and the stack structure 21 includes a plurality of interlayer insulating layers 211 and gate layers 212 longitudinally alternately stacked, and at least one gate layer at the top of the stack structure 21 can be a top selection gate 212a. As shown in Figures 4 to 6 , a barrier layer 24 can also be formed between the gate layer 212 and the interlayer insulating layer 211, and a transition layer 25 can also be formed between the barrier layer 24 and the gate layer 212. The barrier layer 24 includes but is not limited to aluminum oxide, and the transition layer 25 includes but is not limited to titanium nitride, which is used to improve the adhesion of the gate layer 212.

[0074] The core region Core of the stack layer 2 is formed with a plurality of memory channel structures 3 longitudinally penetrating the stack structure 21 and extending into the substrate 1. The plurality of memory channel structures 3 can be distributed in multiple rows, and any two adjacent rows of memory channel structures 3 can be staggered. The stack layer 2 further includes a cover layer 22 located on the stack structure 21 and covering the memory channel structures 3.

[0075] The memory channel structure 3 includes a channel layer 31 and a storage medium layer 32 arranged around the channel layer 31. The storage medium layer 32 includes a tunnel layer (not shown in the figure) arranged around the channel layer 31, a charge storage layer (not shown in the figure) arranged around the tunnel layer, and a charge blocking layer (not shown in the figure) arranged around the charge storage layer. The channel layer 31 can be polysilicon or the like, the tunnel layer can be silicon oxide, silicon nitride, silicon oxynitride or other oxides, the charge storage layer can be an insulating layer containing quantum dots or nanocrystals or a compound containing nitrogen and silicon, and the charge blocking layer can be silicon oxide or other oxides. The memory channel structure 3 further includes an isolation layer 33 surrounded by the channel layer 31, and the isolation layer 33 can be silicon oxide or other oxides. In some embodiments, the stack structure 21 can include a first sub-stack structure 21a, a second sub-stack structure 21b and a third sub-stack structure 21c. The second sub-stack structure 21b is located on the first sub-stack structure 21a, and the third sub-stack structure 21c is located on the second sub-stack structure 21b. The first sub-stack structure 21a, the second sub-stack structure 21b and the third sub-stack structure 21c each include a plurality of interlayer insulating layers 211 and gate layers 212 longitudinally alternately stacked, and at least one gate layer at the top of the third sub-stack structure 21c can be a top selection gate 212a.

[0076] The storage channel structure 3 includes a first sub-storage channel structure 3a, a second sub-storage channel structure 3b, and a third sub-storage channel structure 3c. The first sub-storage channel structure 3a extends longitudinally through the first sub-stacking structure 21a and into the substrate 1. The second sub-storage channel structure 3b extends longitudinally through the second sub-stacking structure 21b, and the channel layer 31 in the second sub-storage channel structure 3b is connected to the channel layer 31 in the first sub-storage channel structure 3a. The third sub-storage channel structure 3c extends longitudinally through the third sub-stacking structure 21c, and the channel layer 31 in the third sub-storage channel structure 3c is connected to the channel layer 31 in the second sub-storage channel structure 3b.

[0077] In addition, the core region of the stacked layer 2 also forms a slit structure 4, which extends longitudinally through the stacked layer 2 and into the substrate 1. The slit structure 4 can be an insulating material or a semiconductor material such as polysilicon. When the slit structure 4 is a semiconductor material, it can serve as a common source structure.

[0078] The channel layer 31 in the storage channel structure 3 can be connected to the common source structure in different ways. In the first embodiment, such as... Figure 4 As shown, substrate 1 includes a common source layer 11, which is a common source structure. The common source layer 11 can be an N-type doped or P-type doped polysilicon layer. Stacked structure 21 is located on the common source layer 11. The channel layer 31 in the memory channel structure 3 extends longitudinally through the stacked structure 21 and into the common source layer 11 to connect with the common source layer 11. The memory dielectric layer 32 in the memory channel structure 3 is located on the common source layer 11 and is disposed around the channel layer 31. Slit structure 4 extends longitudinally through the stacked structure 21 and into the common source layer 11. Slit structure 4 can be an insulating material.

[0079] The substrate 1 may also include an insulating dielectric layer 12 and conductive contacts 13. The insulating dielectric layer 12 is located on the side of the common source layer 11 opposite to the stacked structure 21, and the conductive contacts 13 penetrate the insulating dielectric layer 12 and extend into the common source layer 11.

[0080] In the second embodiment, such as Figure 5 As shown, substrate 1 includes a first semiconductor layer 14, a second semiconductor layer 15, and a third semiconductor layer 16. The second semiconductor layer 15 is located on the first semiconductor layer 14, the third semiconductor layer 16 is located on the second semiconductor layer 15, and the stacked structure 21 is located on the third semiconductor layer 16. The first semiconductor layer 14, the second semiconductor layer 15, and the third semiconductor layer 16 can all be N-type doped or P-type doped polycrystalline silicon layers.

[0081] The channel layer 31 in the memory channel structure 3 longitudinally penetrates the stacked structure 21, the third semiconductor layer 16, and the second semiconductor layer 15, and extends into the first semiconductor layer 14. The memory dielectric layer 32 in the memory channel structure 3 is disposed around the channel layer 31. The second semiconductor layer 15 laterally penetrates the memory dielectric layer 32 to connect with the channel layer 31; that is, the memory dielectric layer 32 is disconnected at the second semiconductor layer 15 to ensure that the second semiconductor layer 15 can connect with the channel layer 31. The second semiconductor layer 15 can be an epitaxial layer. The slit structure 4 can include a common-source structure 41 and a barrier layer 42. The common-source structure 41 longitudinally penetrates the stacked structure 21 and the third semiconductor layer 16, and extends into the second semiconductor layer 15. The barrier layer 42 is disposed around the common-source structure 41. The slit structure 4 can also include a transition layer 43, which is located between the common-source structure 41 and the barrier layer 42.

[0082] In the third embodiment, such as Figure 6 As shown, substrate 1 includes substrate 17, which can be a semiconductor substrate, such as a silicon substrate, or a substrate including other element semiconductors or compound semiconductors. An epitaxial layer 18 can be disposed at the bottom of the channel layer 31 in the memory channel structure 3, such that the channel layer 31 is connected to the substrate 17 through the epitaxial layer 18. A memory dielectric layer 32 is disposed around the channel layer 31 in the memory channel structure 3. Slit structure 4 can include a common source structure 41 and a barrier layer 42. The common source structure 41 extends longitudinally through the stacked structure 21 and into the substrate 17, and the barrier layer 42 is disposed around the common source structure 41. Slit structure 4 can also include a transition layer 43, which is located between the common source structure 41 and the barrier layer 42. A doped region 19 is disposed in the substrate 17 at the bottom of slit structure 4, such that the common source structure 41 is connected to the doped region 19. The doped region 19 can be an N-type doped region or a P-type doped region.

[0083] Step 102: Form a film structure on the stacked layer, the film structure including a self-aligned pattern.

[0084] In this embodiment of the invention, the position of the self-aligned pattern can correspond to the position of the top selection gate line to be formed subsequently, and the cross-section of the self-aligned pattern can be exactly the same as the cross-section of the top selection gate line to be formed subsequently. The width of the self-aligned pattern is less than a preset width, which can be the width of the top selection gate groove etched by the mask layer in the prior art. That is, in this embodiment, the width of the self-aligned pattern is less than the width of the top selection gate groove in the prior art. The film structure also includes a stop layer. The stop layer and the self-aligned pattern are both located on the stacked layer, and the upper surface of the stop layer is flush with the upper surface of the self-aligned pattern to ensure that the top selection gate groove is quickly etched according to the self-aligned pattern.

[0085] Specifically, the step 102 of forming a film structure on the stack layer includes:

[0086] An initial self-aligned pattern is formed on the stack layer;

[0087] An initial stop layer is formed on the stack layer and the initial self-alignment pattern;

[0088] The initial stop layer and the initial self-alignment pattern are ground so that the ground initial stop layer constitutes the stop layer and the ground initial self-alignment pattern constitutes the self-alignment pattern.

[0089] The initial self-aligned pattern can be obtained by etching the dielectric layer. Specifically, the step of forming the initial self-aligned pattern on the stack layer includes:

[0090] A dielectric layer is formed on the stack layer;

[0091] A mask layer is formed on the dielectric layer;

[0092] The dielectric layer is etched through the mask layer, so that the etched dielectric layer forms the initial self-aligned pattern;

[0093] Remove the mask layer.

[0094] like Figure 3a As shown, a dielectric layer 5 is formed on the stack layer 2. The dielectric layer 5 can be an oxide such as silicon oxide. Then, a mask layer 6 is formed on the dielectric layer 5. The mask layer 6 can be a photoresist or the like. The mask layer 6 has an opening 61, which corresponds to other positions in the dielectric layer 5. These other positions refer to positions in the dielectric layer 5 other than the positions where the initial self-aligned pattern is to be formed.

[0095] like Figure 3b As shown, the dielectric layer 5 is etched through the opening 61 in the mask layer 6 to remove the film layer corresponding to the opening 61 in the dielectric layer 5. The remaining dielectric layer 5 constitutes the initial self-alignment pattern 51. The width of the initial self-alignment pattern 51 is less than a preset width. The initial self-alignment pattern 51 corresponds to the gap between two adjacent rows of memory channel structures 3 in the stack layer 2, and the spacing between the initial self-alignment pattern 51 and the two adjacent rows of memory channel structures 3 can be equal. When the two adjacent rows of memory channel structures 3 are staggered, the cross-section of the initial self-alignment pattern 51 can be curved, for example, it can be wavy.

[0096] The embodiment forms the initial self-aligned pattern 51 in the dielectric layer 5 by using the mask layer 6, which reduces the cost and the width of the top select gate cut formed subsequently, and thus makes it easier to control the etching position of the top select gate cut and reduce the overlay deviation of the top select gate cut between the two adjacent rows of the memory channel structures.

[0097] After the initial self-aligned pattern 51 is formed, the mask layer 6 is removed, as shown in FIG. 2B. Figure 3c The initial stop layer 7 is formed on the stack layer 2 and the initial self-aligned pattern 51, as shown in FIG. 2C. Figure 3d The initial stop layer 7 can be poly, for example, and the material of the initial stop layer 7 is different from that of the initial self-aligned pattern 51. The thickness of the initial stop layer 7 can be smaller than that of the initial self-aligned pattern 51, and the initial stop layer 7 covers the initial self-aligned pattern 51. Thus, the initial stop layer 7 and the initial self-aligned pattern 51 can be polished by chemical mechanical polishing (CMP) to remove part of the initial stop layer 7 covering the initial self-aligned pattern 51 and part of the initial self-aligned pattern 51, so that the polished initial stop layer 7 forms a stop layer 71 located on the stack layer 2 only, and the polished initial self-aligned pattern 51 forms a self-aligned pattern 52, and the upper surface of the self-aligned pattern 52 is flush with that of the stop layer 71. The self-aligned pattern 52 and the stop layer 71 form a film layer structure 10, as shown in FIG. 2D. Figure 3e The width of the self-aligned pattern 52 is smaller than a preset width, and the self-aligned pattern 52 corresponds to the gap between the two adjacent rows of the memory channel structures 3 in the stack layer 2, and the distance between the self-aligned pattern 52 and the two adjacent rows of the memory channel structures 3 can be equal. The cross section of the self-aligned pattern 52 can be curved, for example, in a wave shape.

[0098] In some embodiments, after the initial self-aligned pattern 51 is formed, the mask layer 6 can also be removed, and the initial stop layer 7 is formed directly on the stack layer 2 and the mask layer 6. Then, the initial stop layer 7, the mask layer 6 and the initial self-aligned pattern 51 are polished to remove part of the initial stop layer 7 covering the initial self-aligned pattern 51 and the mask layer 6 and part of the initial self-aligned pattern 51. Similarly, the polished initial stop layer 7 forms the stop layer 71, and the polished initial self-aligned pattern 51 forms the self-aligned pattern 52, and the upper surface of the self-aligned pattern 52 is flush with that of the stop layer 71. The self-aligned pattern 52 and the stop layer 71 form the film layer structure 10.

[0099] In step 103, a top select gate cut is formed along the self-aligned pattern, and the top select gate cut penetrates the top select gate.

[0100] In this embodiment of the invention, since the film structure 10 has a self-aligned pattern 52, the top selected gate groove that meets the requirements can be formed by etching the film structure 10 and the stack layer 2 using self-aligned technology.

[0101] Specifically, the step 103 of forming a top selection grid groove along the self-aligned pattern includes:

[0102] The film structure and the stack layer are etched to remove the self-aligned pattern and the top selected gate corresponding to the self-aligned pattern, thereby obtaining the self-aligned top selected gate slot.

[0103] like Figure 3f As shown, a self-aligned technique is used to remove the self-aligned pattern 52 in the film structure 10, leaving only the stop layer 71 in the film structure 10. Simultaneously, the stack layer 2 is etched along the self-aligned pattern 52 in the film structure 10 to remove the top select gate 212a corresponding to the self-aligned pattern 52, as well as the interlayer insulating layer 211 and capping layer 22 above the top select gate 212a corresponding to the self-aligned pattern 52, thereby forming a top select gate groove 23.

[0104] Since the self-alignment pattern 52 corresponds to the gap between two adjacent rows of memory channel structures 3 in the stack layer 2, and the width of the self-alignment pattern 52 is less than the preset width, the top selection gate slot 23 is located between two adjacent rows of memory channel structures 3 in the stack layer 2. Furthermore, the width of the top selection gate slot 23 is less than the preset width. With the spacing between the two adjacent rows of memory channel structures 3 remaining unchanged, the adjustable range of the top selection gate slot 23 between the two adjacent rows of memory channel structures 3 can be increased, reducing the overlay deviation between the top selection gate slot 23 and the two adjacent rows of memory channel structures 3. In addition, the spacing between the top selection gate slot 23 and the two adjacent rows of memory channel structures 3 can be equal, further solving the overlay alignment problem between the top selection gate slot 23 and the two adjacent rows of memory channel structures 3. Since the cross-section of the self-alignment pattern 52 can be curved, the cross-section of the top selection gate slot 23 can also be curved, for example, wavy.

[0105] Step 104: Form a top selection grid line in the top selection grid cutout.

[0106] In this embodiment of the invention, top selection gate lines can be formed in the top selection gate slot 23 by filling it with an insulating material, such as an oxide like silicon oxide. These top selection gate lines are used to divide the core area of ​​the stack layer 2 into multiple storage blocks.

[0107] Specifically, step 104, forming a top selection gate spacing line in the top selection gate slot, includes:

[0108] An insulating layer is filled into the top selected grid slot;

[0109] Remove the film structure, part of the stacked layer, and part of the insulating layer so that the remaining insulating layer in the top select gate slot forms the top select gate line.

[0110] like Figure 3g As shown, an insulating layer 8 is formed on the film structure 10, and the insulating layer 8 fills the top selection gate slot 23. Then, a portion of the insulating layer 8 on the film structure 10, a portion of the insulating layer 8 in the top selection gate slot 23, the film structure 10, and a portion of the stacked layer 2 are removed, such that the remaining insulating layer 8 in the top selection gate slot 23 constitutes the top selection gate line.

[0111] Specifically, the step of removing the film structure, part of the stacked layer, and part of the insulating layer includes:

[0112] The film structure, the stacked layer, and the insulating layer are polished to remove the film structure, part of the stacked layer, and part of the insulating layer on the side of the sacrificial layer facing away from the substrate, thus exposing the sacrificial layer.

[0113] The storage channel structure 3 also includes a sacrificial layer 34 located on top of the storage channel structure 3. Specifically, the sacrificial layer 34 is located on top of the isolation layer 33 in the storage channel structure 3, that is, the sacrificial layer 34 is also surrounded by the channel layer 31. Figure 3h As shown, chemical mechanical polishing is used to polish the film structure 10, the stacked layer 2 and the insulating layer 8 to remove the sacrificial layer 34 from the side of the film structure 10 facing away from the substrate 1, part of the stacked layer 2 (i.e., the capping layer 22) and part of the insulating layer 8 (including part of the insulating layer 8 on the film structure 10 and part of the insulating layer 8 in the top selection gate groove 23), thereby exposing the sacrificial layer 34. The remaining insulating layer 8 in the top selection gate groove 23 constitutes the top selection gate line 81.

[0114] The width of the top select gate cut groove 23 (i.e. the length of the top select gate cut groove 23 in the direction A) is less than the preset width, so that the width of the top select gate spacer line 81 (i.e. the length of the top select gate spacer line 81 in the direction A) is less than the preset width. The distance between the top select gate cut groove 23 and the adjacent two rows of the storage channel structure 3 in the direction A can be equal, so that the distance between the top select gate spacer line 81 and the adjacent two rows of the storage channel structure 3 in the direction A can be equal. In addition, the peripheral side of the storage channel structure 3 can further form a transition layer, and the peripheral side of the transition layer can further form a barrier layer. The distance between the top select gate spacer line 81 and the adjacent storage channel structure 3 is greater than the sum of the thicknesses of the transition layer and the barrier layer, thereby avoiding damage to the transition layer and the barrier layer caused by the formation of the top select gate spacer line 81, and improving the performance of the semiconductor device. The cross section of the top select gate cut groove 23 is in a curved shape, so that the cross section of the top select gate spacer line 81 is in a curved shape, for example, a wave shape. The curved top select gate spacer line 81 can reduce the distance between the top select gate spacer line 81 and the adjacent storage channel structure 3, increase the number of storage channel structures 3 per unit area, and thus improve the storage density.

[0115] In addition, the slit structure 4 is ground at the same time as the film layer structure 10, the stack layer 2 and the insulating layer 8 are ground, so that the upper surfaces of the ground slit structure 4, the stack layer 2 and the top select gate spacer line 81 are flush. The ground slit structure 4 longitudinally penetrates the stacked structure 21 and extends into the substrate 1.

[0116] After the sacrificial layer 34 is exposed, the method further comprises:

[0117] The sacrificial layer is removed, and a plug is formed on the top of the storage channel structure.

[0118] The sacrificial layer 34 on the top of the isolation layer 33 in the storage channel structure 3 is replaced with a plug, so that the plug is connected with the channel layer 31. The plug can be a semiconductor material, such as polysilicon.

[0119] Specifically, the step of removing the sacrificial layer and forming a plug on the top of the storage channel structure comprises:

[0120] The sacrificial layer is removed, and the peripheral side of the sacrificial layer is etched to form an opening on the top of the storage channel structure.

[0121] The plug is filled in the opening.

[0122] As Figure 3iAs shown, while removing the sacrificial layer 34 on the top of the isolation layer 33 of the storage channel structure 3, the peripheral side of the sacrificial layer 34 is etched, for example, the channel layer 31, the storage medium layer 32 and the stack layer 2 on the peripheral side of the sacrificial layer 34 are etched, to form an opening on the top of the storage channel structure 3, the cross-sectional area of the opening is larger than the cross-sectional area of the sacrificial layer 34, and the depth of the opening is equal to the thickness of the sacrificial layer 34. Then, the plug 35 is filled in the opening, so that the cross-sectional area of the plug 35 is larger than the cross-sectional area of the sacrificial layer 34, so that when the contact structure is formed on the storage channel structure 3 subsequently, the connection window of the contact structure to the plug 35 can be increased.

[0123] As can be seen from the above, the manufacturing method of the semiconductor device provided by the embodiment of the present application can form a film layer structure with a self-aligned pattern on the stack layer, form a top selection gate cut groove in the stack layer along the self-aligned pattern, make the top selection gate cut groove penetrate through the top selection gate in the stack layer, and form a top selection gate separation line in the top selection gate cut groove, without using a mask layer to etch the top selection gate cut groove, thereby reducing the manufacturing difficulty of the top selection gate cut groove, and further reducing the manufacturing difficulty of the top selection gate separation line, while solving the overlay alignment problem of the top selection gate cut groove between the two adjacent rows of storage channel structures, ensuring the spacing between the top selection gate separation line and the adjacent storage channel structures, and improving the performance of the semiconductor device.

[0124] Correspondingly, the embodiment of the present application also provides a semiconductor device, which can be manufactured by using the manufacturing method of the semiconductor device.

[0125] Referring to Figure 3i , it is a structure schematic diagram of the semiconductor device provided by the embodiment of the present application.

[0126] As Figure 3i shown, the embodiment provides a semiconductor device, which includes a substrate 1, a stack structure 21, a plurality of storage channel structures 3 and a top selection gate separation line 81.

[0127] The substrate 1 can be a substrate, for example, can be a silicon substrate, or can be a substrate including other element semiconductors or compound semiconductors. The substrate 1 can also include a plurality of semiconductor layers stacked, and the semiconductor layer can be polysilicon or the like. The substrate 1 can also include other film layers, which are not limited here. The film layers in the substrate 1 can refer to Figures 4 to 6 , which will not be described in detail here.

[0128] The stack structure 21 is located on the substrate 1, and the stack structure 21 can include a plurality of longitudinally-alternately-stacked gate layers 212 and interlayer insulation layers 211. The number of stacked layers of the gate layers 212 and the interlayer insulation layers 211 is not limited, for example, 48 layers, 64 layers, 128 layers, etc. At least one gate layer located at the top of the stack structure 21 can be a top select gate 212a.

[0129] The stack structure 21 can include a core region SS and a step region Core. The specific positional relationship of the core region SS and the step region Core can be referred to in Figure 2a and Figure 2b , which will not be described in detail here. The core region Core of the stack structure 21 is formed with a plurality of storage channel structures 3 longitudinally penetrating the stack structure 21 and extending into the substrate 1. The plurality of storage channel structures 3 can be distributed in multiple rows, and any two adjacent rows of storage channel structures 3 can be staggered.

[0130] The storage channel structure 3 includes an isolation layer 33, a channel layer 31 disposed around the isolation layer 33, and a storage medium layer 32 disposed around the channel layer 31. The storage medium layer 32 includes a tunnel layer (not shown in the figure) disposed around the channel layer 31, a charge storage layer (not shown in the figure) disposed around the tunnel layer, and a charge blocking layer (not shown in the figure) disposed around the charge storage layer. The core region Core of the stack structure 21 is also formed with a slit structure 4 longitudinally penetrating the stack structure 21 and extending into the substrate 1. The slit structure 4 can be an insulating material, or a semiconductor material such as polysilicon, and when the slit structure 4 is a semiconductor material, the slit structure 4 can serve as a common source structure. The specific connection relationship of the channel layer 31 in the storage channel structure 3 and the common source structure can be referred to in Figures 4 to 6 , which will not be described in detail here.

[0131] The storage channel structure 3 also includes a plug 35 located at the top of the isolation layer 33, and the top of the isolation layer 33 is orthogonally projected onto the plug 35 and located in the plug 35. The cross-sectional area of the plug 35 is greater than the area of the upper surface of the isolation layer 33. The plug 35 can also be located at the top of the channel layer 31 and the storage medium layer 32, and the top of the channel layer 31 and the storage medium layer 32 is orthogonally projected onto the plug 35 and also located in the plug 35, i.e., the cross-sectional area of the plug 35 is greater than the sum of the areas of the upper surfaces of the isolation layer 33, the channel layer 31 and the storage medium layer 32, so that when a contact structure is subsequently formed on the storage channel structure 3, the connection window of the contact structure to the storage channel structure 3 can be increased.

[0132] The top select gate spacer line 81 extends longitudinally from the upper surface of the stack structure 21 and penetrates the top select gate 212a. The width of the top select gate spacer line 81 is less than the preset width, which increases the adjustable range of the top select gate spacer line 81 between two adjacent rows of the storage channel structures 3. The top select gate spacer line 81 is located between two adjacent rows of the storage channel structures 3, and the spacing of the top select gate spacer line 81 and the two adjacent rows of the storage channel structures 3 in the direction A can be equal. The top select gate spacer line is used to divide the core area Core of the stack structure 21 into a plurality of storage blocks.

[0133] Further, the top select gate spacer line 81 has a curved cross section, for example, a wave shape. The curved top select gate spacer line 81 can reduce the spacing between the top select gate spacer line 81 and the adjacent storage channel structure 3, increase the number of storage channel structures 3 per unit area, and thus improve the storage density.

[0134] Further, the storage channel structure 3 further has a transition layer (not shown in the figure) on the peripheral side, and the transition layer further has a blocking layer (not shown in the figure) on the peripheral side. The spacing between the top select gate spacer line 81 and the two adjacent rows of the storage channel structures 3 is greater than the sum of the thicknesses of the transition layer and the blocking layer, thereby avoiding damage to the transition layer and the blocking layer caused by the formation of the top select gate spacer line 81, and improving the performance of the semiconductor device.

[0135] Referring to Figure 7 , it is a structure schematic diagram of a memory provided by an embodiment of the present application.

[0136] As Figure 7 shown, the memory includes a storage array structure 100 and a peripheral structure 200 connected to the storage array structure 100. The storage array structure 100 can be a non-volatile memory array structure, for example, the storage array structure 100 can be a NAND flash memory, a NOR flash memory, etc. The storage array structure 100 can include the above semiconductor device, which will not be described in detail here.

[0137] The peripheral structure 200 can include CMOS (complementary metal oxide semiconductor), SRAM (static random access memory), DRAM (dynamic random access memory), FPGA (field programmable gate array), CPU (central processing unit), Xpoint chip, etc.

[0138] Specifically, the peripheral structure 200 can be located on the storage array structure 100, and the peripheral structure 200 is connected with the storage array structure 100. The storage array structure 100 and the peripheral structure 200 can also adopt other architecture forms, for example, the peripheral structure 200 is located below the storage array structure 100, that is, a PUC (periphery under core array) architecture, or the peripheral structure 200 is arranged side by side with the storage array structure 100, that is, a PNC (periphery near core array) architecture, etc., which is not specifically limited here.

[0139] In summary, although the present application has been disclosed with the preferred embodiments as above, the above preferred embodiments are not intended to limit the present application, and those skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is subject to the scope defined by the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate and a stacked layer on the substrate are provided, the stacked layer including a top selection gate; A film structure is formed on the stacked layer, the film structure including a self-aligned pattern formed by etching a dielectric layer and a stop layer formed on the stacked layer and the self-aligned pattern; a top select gate ditch is formed along the self-aligned pattern, and the top select gate ditch penetrates the top select gate; A top selection grid line is formed in the top selection grid cutout.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The width of the selected grid line at the top is less than the preset width.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The cross-section of the top selected grid line is curved.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The upper surface of the stop layer is flush with the upper surface of the self-aligned pattern.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The step of forming a film structure on the stack layer includes: An initial self-aligned pattern is formed on the stack layer; An initial stop layer is formed on the stack layer and the initial self-alignment pattern; The initial stop layer and the initial self-alignment pattern are ground so that the ground initial stop layer constitutes the stop layer and the ground initial self-alignment pattern constitutes the self-alignment pattern.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The step of forming an initial self-aligned pattern on the stack layer includes: A dielectric layer is formed on the stack layer; A mask layer is formed on the dielectric layer; The dielectric layer is etched through the mask layer, so that the etched dielectric layer forms the initial self-aligned pattern; Remove the mask layer.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming a top selection grid cut along the self-aligned pattern includes: The film structure and the stack layer are etched to remove the self-aligned pattern and the top selected gate corresponding to the self-aligned pattern, thereby obtaining the self-aligned top selected gate slot.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The stack layer includes a stack structure, the stack structure including the top selected gate; The stack layer forms multiple rows of memory channel structures that run through the stack structure. The top select gate line is located between two adjacent rows of memory channel structures, and the spacing between the top select gate line and the two adjacent rows of memory channel structures is equal.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, A transition layer is also formed on the periphery of the storage channel structure, and a barrier layer is also formed on the periphery of the transition layer. The spacing between the top selection grid line and the adjacent two rows of storage channel structures is greater than the sum of the thicknesses of the transition layer and the barrier layer.

10. The method for fabricating a semiconductor device according to claim 8, characterized in that, The step of forming a top selection grid line in the top selection grid cutout includes: An insulating layer is filled into the top selected grid slot; Remove the film structure, part of the stacked layer, and part of the insulating layer so that the remaining insulating layer in the top select gate slot forms the top select gate line.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The storage channel structure includes a sacrificial layer located on top of the storage channel structure; The step of removing the film structure, part of the stacked layer, and part of the insulating layer includes: The film structure, the stacked layer, and the insulating layer are polished to remove the film structure, part of the stacked layer, and part of the insulating layer on the side of the sacrificial layer facing away from the substrate, thus exposing the sacrificial layer.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The method further includes: Remove the sacrificial layer and form a plug on top of the storage channel structure.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, The step of removing the sacrificial layer and forming a plug on top of the storage channel structure includes: The sacrificial layer is removed, and the periphery of the sacrificial layer is etched to form an opening at the top of the storage channel structure; The plug is filled into the opening.

14. A semiconductor device, characterized in that, The semiconductor device is prepared by the method of fabrication of any one of claims 1-13, wherein the semiconductor device comprises: Base; A stacked structure located on the substrate, the stacked structure including a top selection gate; A top selection gate line runs through the top selection gate, and the width of the top selection gate line is less than a preset width.

15. The semiconductor device according to claim 14, characterized in that, The cross-section of the top selected grid line is curved.

16. The semiconductor device according to claim 14, characterized in that, The semiconductor device also includes a multi-row memory channel structure that runs through the stacked structure; The top selection gate line is located between two adjacent rows of storage channel structures, and the spacing between the top selection gate line and the two adjacent rows of storage channel structures is equal.

17. The semiconductor device according to claim 16, characterized in that, The storage channel structure also has a transition layer on its periphery, and the transition layer also has a barrier layer on its periphery. The distance between the top selected grid line and the two adjacent rows of storage channel structures is greater than the sum of the thicknesses of the transition layer and the barrier layer.

18. The semiconductor device according to claim 16, characterized in that, The storage channel structure includes an isolation layer, a channel layer disposed around the isolation layer, a storage medium layer disposed on the channel layer, and a plug disposed on top of the isolation layer; The plug is connected to the channel layer, and the top of the isolation layer is projected onto the plug, with its orthographic projection located inside the plug.

19. A memory, characterized in that, It includes a storage array structure and peripheral structures connected to the storage array structure; The memory array structure includes the semiconductor device as described in any one of claims 14 to 18.

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