Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate has a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. The first gate oxide layer is disposed at least partially in the recess. The first gate oxide layer includes a raised portion disposed adjacent to the edge of the recess, and a height of the raised portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the raised portion of the first gate oxide layer in a vertical direction.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device including a gate oxide layer disposed in a recess and a method of fabricating the same. BACKGROUND

[0002] In power devices with high voltage handling capability, double-diffused MOS (DMOS) transistor devices continue to receive attention. Common DMOS transistor devices include vertical double-diffused MOS (VDMOS) and lateral double-diffused MOS (LDMOS) transistor devices. LDMOS transistor devices have been widely used in high voltage operating environments, such as CPU power supply, power management system, AC / DC converter, and high power or high frequency power amplifier, because of their high operating frequency and efficiency, and planar structure that is easy to integrate with other integrated circuits. The main feature of LDMOS transistor devices is to use a lateral diffusion drift region with low doping concentration and large area to moderate the high voltage between the source terminal and the drain terminal, so that the LDMOS transistor device can achieve a high breakdown voltage. In an extended-drain MOS (EDMOS) transistor, a thicker gate oxide layer is usually disposed near the drain terminal and a thinner gate oxide layer is disposed near the source terminal to achieve relatively high voltage and relatively low voltage operation in a single transistor by having gate oxide layers with different thicknesses. However, gate oxide layers with different thicknesses can easily cause the surface to have too much fluctuation, which can affect the shape of the gate electrode formed on the gate oxide layer and related fabrication processes, and negatively impact the manufacturing yield and electrical performance of the product. SUMMARY

[0003] The present application provides a semiconductor device and a method of fabricating the same, which uses a gate oxide layer disposed in a recess to increase the thickness of part of the gate oxide layer and reduce the negative impact of the gate oxide layer on the gate structure and its formation method.

[0004] An embodiment of the present invention provides a semiconductor device including a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at the boundary between the first and second regions. The first gate oxide layer is at least partially disposed in the recess, and the first gate oxide layer includes a raised portion disposed adjacent to the edge of the recess, the height of the raised portion being less than the depth of the recess. The gate structure is disposed on the first and second regions of the semiconductor substrate, and the gate structure overlaps with the raised portion of the first gate oxide layer in a vertical direction.

[0005] An embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: A semiconductor substrate is provided, the semiconductor substrate including a first region and a second region adjacent to the first region. A recess is formed in the first region of the semiconductor substrate, and an edge of the recess is located at the boundary between the first region and the second region. A first gate oxide layer is formed on the semiconductor substrate, and the first gate oxide layer is at least partially disposed in the recess. The first gate oxide layer includes a raised portion disposed adjacent to the edge of the recess, and the height of the raised portion is less than the depth of the recess. A gate structure is formed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps with the raised portion of the first gate oxide layer in a vertical direction. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a semiconductor device according to a first embodiment of the present invention;

[0007] Figure 2 This is a schematic diagram of the layout of a semiconductor device according to the first embodiment of the present invention;

[0008] Figures 3 to 10 This is a schematic diagram of a method for fabricating a semiconductor device according to a first embodiment of the present invention, wherein...

[0009] Figure 4 for Figure 3 A diagram illustrating the subsequent situation;

[0010] Figure 5 for Figure 4 A diagram illustrating the subsequent situation;

[0011] Figure 6 for Figure 5 A diagram illustrating the subsequent situation;

[0012] Figure 7 for Figure 6 A diagram illustrating the subsequent situation;

[0013] Figure 8 for Figure 7 A diagram illustrating the subsequent situation;

[0014] Figure 9 Fig. 1 is a schematic view of a semiconductor device according to a first embodiment of the present application; Figure 8 Fig. 2 is a schematic view of the subsequent state;

[0015] Figure 10 Fig. 3 is a schematic view of a semiconductor device according to a second embodiment of the present application; Figure 9 Fig. 4 is a schematic view of the subsequent state;

[0016] Figure 11 Fig. 5 is a schematic view of a semiconductor device according to a third embodiment of the present application;

[0017] Figures 12 to 18 Fig. 6 is a schematic view of a manufacturing method of a semiconductor device according to a fourth embodiment of the present application, wherein

[0018] Figure 13 Fig. 7 is a schematic view of a semiconductor device according to a fifth embodiment of the present application; Figure 12 Fig. 8 is a schematic view of the subsequent state;

[0019] Figure 14 Fig. 9 is a schematic view of a semiconductor device according to a sixth embodiment of the present application; Figure 13 Fig. 10 is a schematic view of the subsequent state;

[0020] Figure 15 Fig. 11 is a schematic view of a semiconductor device according to a seventh embodiment of the present application; Figure 14 Fig. 12 is a schematic view of the subsequent state;

[0021] Figure 16 Fig. 13 is a schematic view of a semiconductor device according to an eighth embodiment of the present application; Figure 15 Fig. 14 is a schematic view of the subsequent state;

[0022] Figure 17 Fig. 15 is a schematic view of a semiconductor device according to a ninth embodiment of the present application; Figure 16 Fig. 16 is a schematic view of the subsequent state;

[0023] Figure 18 Fig. 17 is a schematic view of a semiconductor device according to a tenth embodiment of the present application; Figure 17 Fig. 18 is a schematic view of the subsequent state.

[0024] Figure 19 Fig. 19 is a schematic view of a semiconductor device according to an eleventh embodiment of the present application;

[0025] Figure 20 Fig. 20 is a schematic view of a semiconductor device according to a twelfth embodiment of the present application.

[0026] Explanation of main element symbols

[0027] 10 semiconductor substrate

[0028] 10A upper surface

[0029] 10B lower surface

[0030] 12 pad oxide layer

[0031] 14 mask layer

[0032] 16 extension oxide layer

[0033] 18 isolation structure

[0034] 20 first gate oxide layer

[0035] 22 first layer

[0036] 24 second layer

[0037] 32 patterned mask layer

[0038] 34 second gate oxide layer

[0039] 34A first portion

[0040] 34B second portion

[0041] 36 third gate oxide layer

[0042] 42 dummy gate structure

[0043] 44 gate cap layer

[0044] 46 first spacer

[0045] 48 second spacer

[0046] 50 dielectric layer

[0047] 91 oxidation fabrication process

[0048] 92 etching fabrication process

[0049] 101 semiconductor device

[0050] 102 semiconductor device

[0051] 103 semiconductor device

[0052] 104 semiconductor device

[0053] AA active region pattern

[0054] BS bottom surface

[0055] CT1 contact pattern

[0056] CT2 contact pattern

[0057] D1 first direction

[0058] D2 second direction

[0059] D3 third direction

[0060] DP depth

[0061] DR drift region

[0062] EG edge

[0063] GS gate structure

[0064] H height

[0065] HK gate dielectric layer

[0066] L1 length

[0067] L2 length

[0068] L3 length

[0069] LD1 lightly doped region

[0070] LD2 lightly doped region

[0071] LD3 lightly doped region

[0072] LD4 lightly doped region

[0073] LD5 lightly doped region

[0074] M1 mask pattern

[0075] M2 mask pattern

[0076] OP1 opening

[0077] OP2 opening

[0078] P1 protrusion

[0079] P2 main body

[0080] P3 recess

[0081] PL gate pattern

[0082] R1 first region

[0083] R2 second region

[0084] R3 third region

[0085] R4 fourth region

[0086] R5 fifth region

[0087] RC recess

[0088] S1 upper surface

[0089] S2 upper surface

[0090] S3 upper surface

[0091] SD1 source / drain region

[0092] SD2 source / drain region

[0093] SD3 source / drain region

[0094] SD4 source / drain region

[0095] SD5 source / drain region

[0096] SP spacing

[0097] TK1 thickness

[0098] TK2 thickness

[0099] W1 well region

[0100] W3 well region

[0101] W4 well region

[0102] W5 well region DETAILED DESCRIPTION

[0103] The following detailed description of the application discloses sufficient information to enable those skilled in the art to practice the application. The embodiments described below are exemplary and not limiting. It is apparent to a person of ordinary skill in the art that modifications and variations can be made without departing from the spirit and scope of the application.

[0104] Before further description of the embodiments, certain terms employed in the specification, are first explained.

[0105] The terms "on," "over," and "above" are to be interpreted in the broadest context to mean not only "directly on" something, but also to include the meaning of being on something with other intervening features or layers therebetween, and "over" or "above" something not only means "over" or "above" something, but also can include the meaning of being "over" or "above" something without other intervening features or layers therebetween (i.e., directly on something).

[0106] The use of ordinal terms such as "first," "second," etc., in the specification and claims to modify a claim element does not imply and should not be construed as implying, any priority or order among the claim elements. The use of ordinal terms such as "first," "second," etc., in the specification and claims to modify a claim element does not imply and should not be construed as implying, any priority or order among the claim elements. The use of ordinal terms such as "first," "second," etc., in the specification and claims to modify a claim element does not imply and should not be construed as implying, any priority or order among the claim elements.

[0107] The term "etching" is generally used herein to describe a fabrication process for patterning material such that at least a portion of the material is left after etching. When a material is "etched," at least a portion of the material is retained after etching. Conversely, when a material is "removed," essentially all of the material can be removed during the process. However, in some embodiments, "removal" can be considered a broad term that includes etching.

[0108] The terms “forming” or “setting” are used below to describe the behavior of applying a layer of material to a substrate. These terms are intended to describe any feasible layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0109] Please see Figure 1 . Figure 1 The illustration shows a schematic diagram of a semiconductor device according to a first embodiment of the present invention. Figure 1 As shown, the semiconductor device 101 includes a semiconductor substrate 10, a recess RC, a first gate oxide layer 20, and a gate structure GS. The semiconductor substrate 10 includes a first region R1 and a second region R2 adjacent to the first region R1. The recess RC is disposed in the first region R1 of the semiconductor substrate 10, and an edge EG of the recess RC is located at the boundary between the first region R1 and the second region R2. The first gate oxide layer 20 is at least partially disposed in the recess RC, and the first gate oxide layer 20 includes a protrusion P1 disposed adjacent to the edge EG of the recess RC, and the height H of the protrusion P1 is less than the depth DP of the recess RC. The gate structure GS is disposed on the first region R1 and the second region R2 of the semiconductor substrate 10, and the gate structure GS is in a vertical direction (e.g., Figure 1 The first direction (D1) shown overlaps with the protrusion P1 of the first gate oxide layer 20.

[0110] Further explanation: In some embodiments, the first region R1 may be directly connected to the second region R2, and the location of the boundary between the first region R1 and the second region R2 may be defined by the edge EG of the recessed RC, but is not limited thereto. Furthermore, in some embodiments, the aforementioned first direction D1 may be considered as the thickness direction of the semiconductor substrate 10, and the semiconductor substrate 10 may have an opposing upper surface 10A and a lower surface 10B on the first direction D1, and the recessed RC, the first gate oxide layer 20, and the gate structure GS may be disposed on one side of the upper surface 10A, but is not limited thereto. Additionally, a horizontal direction substantially orthogonal to the first direction D1 (e.g., Figure 1The second direction D2 and the third direction D3 can be substantially parallel to the upper surface 10A and / or the lower surface 10B of the semiconductor substrate 10, but are not limited thereto. In addition, in the context that a position or / and a component in the first direction D1 is relatively higher than the lower surface 10B of the semiconductor substrate 10, the distance in the first direction D1 between the position or / and the component and the lower surface 10B of the semiconductor substrate 10 is greater than the distance in the first direction D1 between a position or / and a component that is relatively lower than the lower surface 10B of the semiconductor substrate 10, the lower portion or bottom of each component can be closer to the lower surface 10B of the semiconductor substrate 10 in the first direction D1 than the upper portion or top of the component, another component above a certain component can be considered to be relatively farther away from the lower surface 10B of the semiconductor substrate 10 in the first direction D1, and another component below a certain component can be considered to be relatively closer to the lower surface 10B of the semiconductor substrate 10 in the first direction D1.

[0111] In some embodiments, the first gate oxide layer 20 can further include a body portion P2 connected to the protrusion portion P1, and the gate structure GS can further overlap the body portion P2 in the first direction D1. An upper surface S2 of the body portion P2 can be lower than an upper surface S1 of the protrusion portion P1 in the first direction D1, and a thickness TK1 of the body portion P2 in the first direction D1 can be greater than the height H of the protrusion portion P1. In some embodiments, the upper surface S2 of the body portion P2 of the first gate oxide layer 20 can be the topmost surface of the body portion P2 in the first direction D1, the upper surface S1 of the protrusion portion P1 of the first gate oxide layer 20 can be the topmost surface of the protrusion portion P1 in the first direction D1, and the height H of the protrusion portion P1 can be considered as the height difference or / and distance between the upper surface S1 and the upper surface S2 in the first direction D1. In addition, the depth DP of the recess RC can be considered as the height difference or / and distance between the bottom surface BS of the recess RC and the upper surface 10A of the semiconductor substrate 10 in the first direction D1, or the depth DP of the recess RC can also be considered as the height difference or / and distance between the bottom surface BS of the recess RC and the edge EG of the recess RC in the first direction D1. In other words, when the bottom surface BS of the recess RC is the bottommost surface of the recess RC in the first direction D1, the depth DP of the recess RC can represent the maximum depth value of the recess RC.

[0112] In some embodiments, the thickness TK1 of the main portion P2 of the first gate oxide layer 20 can be substantially equal to the depth DP of the recess RC, thereby improving the negative impact of the over-thick main portion P2 on the gate structure GS and the fabrication process of the gate structure GS. For example, the thickness TK1 of the main portion P2 can be between 90% of the depth DP of the recess RC and 110% of the depth DP of the recess RC (i.e., greater than or equal to 0.9 times the depth DP of the recess RC and less than or equal to 1.1 times the depth DP of the recess RC), taking into account the impact of fabrication process variations. In some embodiments, the thickness TK1 of the main portion P2 can be greater than or equal to 0.95 times the depth DP of the recess RC and less than or equal to 1.05 times the depth DP of the recess RC. Furthermore, in some embodiments, the height H of the protrusion portion PI can be less than or equal to 15% of the depth DP of the recess RC, thereby improving the negative impact of the protrusion portion PI on the gate structure GS and the fabrication process of the gate structure GS, but not limited thereto. In some embodiments, the height H of the protrusion portion PI can be less than or equal to 10% of the depth DP of the recess RC, or the height H of the protrusion portion PI can be less than or equal to 5% of the depth DP of the recess RC. Furthermore, the protrusion portion PI can be disposed between the edge EG of the recess RC and at least a portion of the main portion P2 in a horizontal direction (e.g., the second direction D2), and the length LI of the protrusion portion PI in the second direction D2 can be less than the length L2 of the main portion P2 in the second direction D2, thereby further reducing the negative impact of the protrusion portion PI on the gate structure GS and the fabrication process of the gate structure GS.

[0113] In some embodiments, the semiconductor device 101 can further include a second gate oxide layer 34 disposed on the second region R2 of the semiconductor substrate 10. The second gate oxide layer 34 can be thinner than the first gate oxide layer 20, and the gate structure GS can further overlap the second gate oxide layer 34 in the first direction D1. For example, the thickness TK2 of the second gate oxide layer 34 in the first direction D1 can be smaller than the thickness of the main portion P2 of the first gate oxide layer 20, but since the first gate oxide layer 20 can be disposed at least mostly in the recess RC, the difference in height between the upper surface of the second gate oxide layer 34 and the upper surface of the first gate oxide layer 20 in the first direction D1 can be reduced. In addition, in some embodiments, the second gate oxide layer 34 can be directly connected to the first gate oxide layer 20, but the disclosure is not limited thereto. It is worth noting that in some embodiments, when the gate structure GS, the first gate oxide layer 20, and the second gate oxide layer 34 are part of the same semiconductor device (such as but not limited to a transistor), the semiconductor device can have gate oxide layers of different thicknesses covered by the gate structure GS and can therefore be applied to operation at different voltages. In addition, since the relatively thick first gate oxide layer 20 is at least mostly disposed in the recess RC, the negative impact of disposing the first gate oxide layer 20 on the gate structure GS and the manufacturing process of the gate structure GS can be reduced.

[0114] In some embodiments, the semiconductor device 101 can further include a gate dielectric layer HK disposed between the gate structure GS and the semiconductor substrate 10, a portion of the gate dielectric layer HK can be disposed between the gate structure GS and the first gate oxide layer 20 in the first direction D1, and another portion of the gate dielectric layer HK can be disposed between the gate structure GS and the second gate oxide layer 34 in the first direction D1. In some embodiments, the gate dielectric layer HK can be formed conformally on the second gate oxide layer 34 and the first gate oxide layer 20, so the gate dielectric layer HK can have a protrusion corresponding to the protrusion PI of the first gate oxide layer 20, but the disclosure is not limited thereto.

[0115] In some embodiments, the semiconductor substrate 10 can include a silicon substrate, a silicon germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or a semiconductor substrate formed of other suitable materials. The first gate oxide layer 20 and the second gate oxide layer 34 can respectively include silicon oxide or other suitable oxide materials. The gate dielectric layer HK can include a high-k dielectric material or other suitable dielectric materials. The high-k dielectric material described above can include hafnium oxide (HfO X), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), or other suitable high-k materials. The gate structure GS can include a non-metallic conductive material (e.g., doped polysilicon) or a metallic conductive material, such as a metal gate structure stacked by a work function layer and a low resistive layer, but the disclosure is not limited thereto. The work function layer can include titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium tri-aluminide (TiAl3), aluminum titanium nitride (TiAlN), or other suitable conductive work function materials, and the low resistive layer can include, for example, tungsten, aluminum, copper, titanium aluminide, titanium, or other suitable low resistive materials.

[0116] Referring to Figure 2 and Figure 1 . Figure 2 The layout pattern diagram of the semiconductor device of the first embodiment of the present disclosure is shown. As Figure 1 and Figure 2 shown, in some embodiments, the active area pattern AA can be used to define the range of the active area of the semiconductor device 101, such as including the range of the active area of the first region R1 and the second region R2 shown in Figure 1 , the gate pattern PL can be used to define the gate structure GS or / and a dummy gate structure (not shown) corresponding to the gate structure GS, the contact pattern CT1 and the contact pattern CT2 can be used to define the contact structure (not shown) corresponding to the gate structure GS and the contact structure (not shown) corresponding to the source / drain region formed in the active area, respectively, and the mask pattern M1 and the mask pattern M2 can be used to define the recess RC and the first gate oxide layer 20, but the disclosure is not limited thereto. In addition, the area within the dashed box of the mask pattern M1 can be used as the opening in the mask used in the related manufacturing process, and the area within the dashed box of the mask pattern M2 can be used as the portion of the mask used in the related manufacturing process, but the disclosure is not limited thereto.

[0117] Referring to Figures 1 to 10. Figures 3 to 10 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to a first embodiment of the present invention, wherein... Figure 4 It is illustrated Figure 3 A diagram illustrating the subsequent situation. Figure 5 It is illustrated Figure 4 A diagram illustrating the subsequent situation. Figure 6 It is illustrated Figure 5 A diagram illustrating the subsequent situation. Figure 7 It is illustrated Figure 6 A diagram illustrating the subsequent situation. Figure 8 It is illustrated Figure 7 A diagram illustrating the subsequent situation. Figure 9 It is illustrated Figure 8 A diagram illustrating the subsequent situation. Figure 10 It is illustrated Figure 9 The following is a diagram illustrating the situation, and Figure 1 It can be regarded as a drawing Figure 10 A diagram illustrating the subsequent situation. (See example.) Figure 1 As shown, the method for fabricating the semiconductor device 101 in this embodiment may include the following steps. First, a semiconductor substrate 10 is provided, the semiconductor substrate 10 including a first region R1 and a second region R2 adjacent to the first region R1. A recess RC is formed in the first region R1 of the semiconductor substrate 10, and the edge EG of the recess RC is located at the boundary between the first region R1 and the second region R2. A first gate oxide layer 20 is formed on the semiconductor substrate 10, and the first gate oxide layer 20 is at least partially disposed in the recess RC. The first gate oxide layer 20 includes a protrusion P1 disposed adjacent to the edge EG of the recess RC, and the height H of the protrusion P1 is less than the depth DP of the recess RC. A gate structure GS is formed on the first region R1 and the second region R2 of the semiconductor substrate 10, and the gate structure GS overlaps with the protrusion P1 of the first gate oxide layer 20 in the vertical direction (e.g., the first direction D1).

[0118] Further explanation: the manufacturing method of this embodiment may include, but is not limited to, the following steps. For example, the steps for forming the above-mentioned recessed RC may include, but are not limited to, the following steps. First, as... Figure 3 As shown, a pad oxide layer 12 is formed on the semiconductor substrate 10, and a mask layer 14 is formed on the pad oxide layer 12. In some embodiments, the pad oxide layer 12 may include silicon oxide or other suitable oxide materials, and the mask layer 14 may include silicon nitride or other suitable mask materials. Furthermore, the pad oxide layer 12 and the mask layer 14 may be formed entirely on the semiconductor substrate 10, thus the pad oxide layer 12 and the mask layer 14 may be formed on the first region R1 and the second region R2. Then, as... Figures 3 to 4As shown, a portion of the liner oxide layer 12 and a portion of the mask layer 14 are removed to expose a portion of the first region Rl of the semiconductor substrate 10. In some embodiments, the method of removing a portion of the liner oxide layer 12 and a portion of the mask layer 14 can include a photolithographic process or other suitable patterning method, and can utilize the mask pattern M2 of Figure 2 to define the positions of the liner oxide layer 12 and the mask layer 14 in Figure 4 , for example. It is not intended to be limited to this example. Figure 4 As shown, a portion of the liner oxide layer 12 and a portion of the mask layer 14 are removed to expose a portion of the first region Rl of the semiconductor substrate 10. In some embodiments, the method of removing a portion of the liner oxide layer 12 and a portion of the mask layer 14 can include a photolithographic process or other suitable patterning method, and can utilize the mask pattern M2 of Figure 2 to define the positions of the liner oxide layer 12 and the mask layer 14 in Figure 4 , for example. It is not intended to be limited to this example.

[0119] Then, as shown in Figures 4 to 5 , an oxidation process 91 can be performed on the exposed first region Rl of the semiconductor substrate 10 to form an extended oxide layer 16, which can be partially embedded in the semiconductor substrate 10 and connected to the liner oxide layer 12. In some embodiments, the oxidation process 91 can include a thermal oxidation process or other suitable oxidation method to oxidize the exposed semiconductor substrate 10 to form the extended oxide layer 16. In some embodiments, a portion of the semiconductor substrate 10 that was originally covered by the mask layer 14 and the liner oxide layer 12 can also be oxidized by the oxidation process 91 to become a portion of the extended oxide layer 16, so the mask layer 14 at the edge can be lifted by the extended oxide layer 16, but it is not intended to be limited to this example. Furthermore, in some embodiments, the size of the extended oxide layer 16 can be controlled by adjusting the process conditions (e.g., time, temperature, etc.) of the oxidation process 91, so that the interface between the extended oxide layer 16 and the liner oxide layer 12 substantially overlaps the interface between the first region Rl and the second region R2 in the first direction Dl, but it is not intended to be limited to this example.

[0120] Then, as shown in Figures 5 to 6 , the extended oxide layer 16, the liner oxide layer 12, and the mask layer 14 are removed to form a recess RC. In other words, the thickness of the extended oxide layer 16 can be controlled by adjusting the oxidation process 91, and can further control the depth DP of the formed recess RC. In some embodiments, the depth DP of the recess RC can be equal to the height difference or / and distance between the bottom surface BS of the recess RC and the upper surface 10A of the semiconductor substrate 10 in the first direction Dl, and the depth DP of the recess RC can also be equal to the height difference or / and distance between the bottom surface BS of the recess RC and the edge EG of the recess RC in the first direction Dl.

[0121] Then, as shown in Figure 7As shown, a first gate oxide layer 20 is formed on a semiconductor substrate 10. In some embodiments, the first gate oxide layer 20 may be formed entirely on the semiconductor substrate 10, and thus the first gate oxide layer 20 may be formed on the first region R1 and the second region R2. Furthermore, in some embodiments, the first gate oxide layer 20 may comprise a single layer or multiple layers of oxide material. For example, the first gate oxide layer 20 may comprise a first layer 22 and a second layer 24 disposed on the first layer 22, and the method of forming the second layer 24 may differ from the method of forming the first layer 22. For example, in some embodiments, the first layer 22 may comprise an oxide layer formed by an in-situ-steam-generation (ISSG) fabrication process, and the second layer 24 may comprise an oxide layer formed by an atomic layer deposition (ALD) fabrication process, thereby allowing for more precise control over the thickness of the first gate oxide layer 20 during formation, but this is not a limitation.

[0122] After that, as Figure 8 and Figure 9 As shown, a patterned mask layer 32 is formed on the first gate oxide layer 20, and an etching process 92 is performed on the first gate oxide layer 20 using the patterned mask layer 32 as a mask to remove the first gate oxide layer 20 on the second region R2 and form the protrusion P1 of the first gate oxide layer 20. In some embodiments, the patterned mask layer 32 can be removed after the etching process 92, and the patterned mask layer 32 can utilize the above-described... Figure 2 The patterned mask layer 32 is defined by the mask pattern M1, but is not limited thereto. In some embodiments, the patterned mask layer 32 may not completely cover the first gate oxide layer 20 located on the recess RC, thereby avoiding the negative impact of an excessively large height H of the formed protrusion P1. In other words, a portion of the first gate oxide layer 20 on the second region R2 and on the recess RC may be exposed after the formation of the patterned mask layer 32 and during the etching process 92, thereby allowing the etching process 92 to etch the thicker first gate oxide layer 20 near the edge EG of the recess RC to reduce the height H of the protrusion P1, but is not limited thereto. In some embodiments, the above can be adjusted Figure 2 The mask pattern M1, mask pattern M2 and / or the spacing SP between mask pattern M1 and mask pattern M2 are used to control the condition of the recess RC and the first gate oxide layer 20 formed on the recess RC (e.g., the height, position and size of its protrusion P1, etc.), but are not limited thereto.

[0123] Then, as Figure 10As shown, after the first gate oxide layer 20 is formed, a second gate oxide layer 34 can be formed on the second region R2 of the semiconductor base 10, and the second gate oxide layer 34 can be thinner than the first gate oxide layer 20. In some embodiments, the second gate oxide layer 34 can be formed by oxidizing the exposed second region R2 of the semiconductor base 10, so that a portion of the semiconductor base 10 is oxidized to become at least a portion of the second gate oxide layer 34, and the upper surface 10A of the semiconductor base 10 can be slightly lowered after the second gate oxide layer 34 is formed, but the application is not limited thereto. The oxidation process can include a thermal oxidation process, a chemical oxidation process, or other suitable oxidation process, and the second gate oxide layer 34 can be formed by other suitable method (e.g. a deposition process) as needed.

[0124] As shown, after the first gate oxide layer 20 is formed, a second gate oxide layer 34 can be formed on the second region R2 of the semiconductor base 10, and the second gate oxide layer 34 can be thinner than the first gate oxide layer 20. In some embodiments, the second gate oxide layer 34 can be formed by oxidizing the exposed second region R2 of the semiconductor base 10, so that a portion of the semiconductor base 10 is oxidized to become at least a portion of the second gate oxide layer 34, and the upper surface 10A of the semiconductor base 10 can be slightly lowered after the second gate oxide layer 34 is formed, but the application is not limited thereto. The oxidation process can include a thermal oxidation process, a chemical oxidation process, or other suitable oxidation process, and the second gate oxide layer 34 can be formed by other suitable method (e.g. a deposition process) as needed. Figure 10 With Figure 1 As shown, after the first gate oxide layer 20 is formed, a second gate oxide layer 34 can be formed on the second region R2 of the semiconductor base 10, and the second gate oxide layer 34 can be thinner than the first gate oxide layer 20. In some embodiments, the second gate oxide layer 34 can be formed by oxidizing the exposed second region R2 of the semiconductor base 10, so that a portion of the semiconductor base 10 is oxidized to become at least a portion of the second gate oxide layer 34, and the upper surface 10A of the semiconductor base 10 can be slightly lowered after the second gate oxide layer 34 is formed, but the application is not limited thereto. The oxidation process can include a thermal oxidation process, a chemical oxidation process, or other suitable oxidation process, and the second gate oxide layer 34 can be formed by other suitable method (e.g. a deposition process) as needed.

[0125] The following will describe different embodiments of the application, and for simplicity of description, the following description will mainly focus on the differences between the embodiments, and will not repeat the same parts. In addition, the same elements in the embodiments of the application are marked with the same reference numerals for mutual reference between the embodiments.

[0126] Please refer to Figure 11 . Figure 11 The drawing shows a schematic view of a semiconductor device 102 according to a second embodiment of the application. As shown, Figure 11As shown, the semiconductor device 102 can further include an isolation structure 18, a first spacer 46, a second spacer 48, a dielectric layer 50, a lightly doped region LD1, a lightly doped region LD2, a well region W1, a source / drain region SD1, and a source / drain region SD2. The isolation structure 18 can be disposed at least partially in the semiconductor base 10, and the isolation structure 18 can include a single layer or multiple layers of insulating material such as oxide insulating material (e.g., silicon oxide, polysilazane) or other suitable insulating material. The lightly doped region LD1, the lightly doped region LD2, the well region W1, the source / drain region SD1, and the source / drain region SD2 can include doped regions formed in the semiconductor base 10 using a doping process (e.g., an implantation process). The source / drain region SD1 and the source / drain region SD2 can be disposed in the semiconductor base 10 and disposed on opposite sides of the gate structure GS in the second direction D2, the lightly doped region LD1 can be disposed adjacent to the source / drain region SD1, and the lightly doped region LD2 can be disposed adjacent to the source / drain region SD2.

[0127] In some embodiments, the source / drain region SD1 can serve as a drain region of a high-voltage semiconductor element, and the source / drain region SD2 can serve as a source region of the high-voltage semiconductor element, but the application is not limited thereto. The well region W1 can be disposed in the semiconductor base 10 and partially under the first gate oxide layer 20, and the lightly doped region LD1 and the source / drain region SD1 can be disposed in the well region W1. The first spacer 46 and the second spacer 48 can be disposed on sidewalls of the gate structure GS, and the dielectric layer 50 can be disposed on the semiconductor base 10 and around the first spacer 46 and the second spacer 48. In some embodiments, the first spacer 46, the second spacer 48, and the dielectric layer 50 can include dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric material. In some embodiments, the semiconductor device 102 can further include an opening OP1, and the opening OP1 can extend through the first gate oxide layer 20 in the first direction D1, and the source / drain region SD1 can be disposed in the first direction D1 corresponding to the opening OP1, so that an upper surface of the source / drain region SD1 can be lower than an upper surface of the source / drain region SD2 in the first direction D1, but the application is not limited thereto.

[0128] Referring to Figures 11 to 18 . Figures 12 to 18 The semiconductor device of the present embodiment is shown in a schematic view of a method of manufacturing the semiconductor device, Figure 13 The semiconductor device of the present embodiment is shown in a schematic view of a method of manufacturing the semiconductor device, Figure 12 The semiconductor device of the present embodiment is shown in a schematic view of a method of manufacturing the semiconductor device, Figure 14 The semiconductor device of the present embodiment is shown in a schematic view of a method of manufacturing the semiconductor device, Figure 13 The semiconductor device of the present embodiment is shown in a schematic view of a method of manufacturing the semiconductor device, Figure 15 The semiconductor device of the present embodiment is shown in a schematic view of a method of manufacturing the semiconductor device, Figure 14 The semiconductor device of the present embodiment is shown in a schematic view of a method of manufacturing the semiconductor device, Figure 16 The semiconductor device of the present embodiment is shown in a schematic view of a method of manufacturing the semiconductor device, Figure 15A subsequent status diagram, Figure 17 is illustrated Figure 16 A subsequent status diagram, Figure 18 is illustrated Figure 17 A subsequent status diagram, Figure 11 may be considered to illustrate Figure 18 A subsequent status diagram of a partial region. The method of manufacturing the semiconductor device of the present embodiment can include, but is not limited to, the following steps. First, as shown in Figure 12 , a semiconductor substrate 10 is provided, and a recess RC is formed in the semiconductor substrate 10. The method of forming the recess RC of the present embodiment can be similar to that of the first embodiment described above, and thus will not be described again here. It is worth mentioning that the semiconductor substrate 10 of the present embodiment can further include a third region R3, a fourth region R4, and a fifth region R5, and the recess RC can be disposed in the first region R1 and the third region R3 of the semiconductor substrate 10.

[0129] Then, as shown in Figure 13 , an isolation structure 18, a well region W1, a lightly doped region LD1, a well region W3, a lightly doped region LD3, and a first gate oxide layer 20 are formed. In some embodiments, part of the isolation structure 18 can be formed at the junction between the first region R1 and the third region R3, the junction between the second region R2 and the fourth region R4, and the junction between the fourth region R4 and the fifth region R5, but not limited thereto. The well region W1 and the lightly doped region LD1 can be formed in the first region R1, and the well region W3 and the lightly doped region LD3 are formed in the third region R3. The first gate oxide layer 20 can be formed on the first region R1, the second region R2, the third region R3, the fourth region R4, and the fifth region R5 and partially in the recess RC. Then, as shown in Figures 13 to 14 , the first gate oxide layer 20 on the second region R2 and the fourth region R4 is removed, thereby forming the protruding portion P1 and the main body portion P2 of the first gate oxide layer 20 described above. Then, as shown in Figures 14 to 15 , the second gate oxide layer 34 described above is formed, and a well region W4 and a well region W5 are formed in the semiconductor substrate 10. The first portion 34A of the second gate oxide layer 34 can be formed on the second region R2, and the second portion 34B of the second gate oxide layer 34 can be formed on the fourth region R4. The well region W4 can be formed in the fourth region R4 and below the second portion 34B of the second gate oxide layer 34, and the well region W5 can be formed in the fifth region R5 and below the first gate oxide layer 20.

[0130] Then, as shown in Figures 15 to 16 , the first gate oxide layer 20 on the fifth region R5 can be removed, and a third gate oxide layer 36 is formed on the fifth region R5. In some embodiments, the third gate oxide layer 36 can be thinner than the second gate oxide layer 34, but not limited thereto. Then, as shown inFigure 17 As shown, a plurality of dummy gate structures 42, a plurality of gate capping layers 44, and a plurality of first spacers 46 can be formed on the semiconductor substrate 10. At least one dummy gate structure 42 can be formed on both the first region Rl and the second region R2 and partially overlap the first gate oxide layer 20 and the second gate oxide layer 34, respectively, in the first direction Dl. In addition, at least one dummy gate structure 42 can be formed on the third region R3, the fourth region R4, and the fifth region R5, but the present application is not limited thereto. Each gate capping layer 44 can be disposed on a corresponding dummy gate structure 42, and each first spacer 46 can be disposed on a sidewall of a corresponding dummy gate structure 42. In some embodiments, the dummy gate structure 42 can include a silicon-containing material such as polysilicon, amorphous silicon, or other suitable material, and the gate capping layer 44 can include silicon nitride or other suitable dielectric material.

[0131] Then, a lightly doped region LD2, a lightly doped region LD4, and a lightly doped region LD5 can be formed in the second region R2, the fourth region R4, and the fifth region R5, respectively. In some embodiments, two lightly doped regions LD3 can be formed in the third region R3 on opposite sides of the dummy gate structure 42 in the third region R3, two lightly doped regions LD4 can be formed in the fourth region R4 on opposite sides of the dummy gate structure 42 in the fourth region R4, and two lightly doped regions LD5 can be formed in the fifth region R5 on opposite sides of the dummy gate structure 42 in the fifth region R5, but the present application is not limited thereto. The lightly doped regions LD3, LD4, and LD5 can have the same or different dopants as desired for the characteristics of the semiconductor device to be formed.

[0132] Next, as shown in FIG. 4, a second gate oxide layer 50 can be formed on the semiconductor substrate 10. The second gate oxide layer 50 can be formed on the semiconductor substrate 10 by a thermal oxidation process, a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD) process, or other suitable process. The second gate oxide layer 50 can be formed on the semiconductor substrate 10 by a thermal oxidation process, a CVD process, a PECVD process, or other suitable process. The second gate oxide layer 50 can be formed on the semiconductor substrate 10 by a thermal oxidation process, a CVD process, a PECVD process, or other suitable process. Figure 18As shown, second spacers 48 are formed on the sidewalls of each first spacer 46, and source / drain regions SD1, source / drain regions SD2, source / drain regions SD3, source / drain regions SD4, and source / drain regions SD5 are formed in the semiconductor substrate 10. It is worth mentioning that, in order to avoid the thick first gate oxide layer 20 affecting the formation of the source / drain regions SD1 and SD3, openings OP1 and OP2 are formed to respectively pass through the first gate oxide layer 20 on the first region R1 and the first gate oxide layer 20 on the third region R3, so as to expose the portions of the semiconductor substrate 10 corresponding to the source / drain regions SD1 and SD3, and then the source / drain regions SD1 and SD3 are formed in the semiconductor substrate 10 by a doping fabrication process (e.g. an implantation fabrication process). Therefore, the source / drain regions SD1 can correspond to the openings OP1 in the first direction D1, and the source / drain regions SD2 can correspond to the openings OP2 in the first direction D1. In some embodiments, the source / drain regions SD1 and SD2 are located on opposite sides of the dummy gate structure 42 disposed on the first region R1 and the second region R2, two source / drain regions SD3 can be formed in the third region R3 and located on opposite sides of the dummy gate structure 42 on the third region R3, two source / drain regions SD4 can be formed in the fourth region R4 and located on opposite sides of the dummy gate structure 42 on the fourth region R4, and two source / drain regions SD5 can be formed in the fifth region R5 and located on opposite sides of the dummy gate structure 42 on the fifth region R5, but the present application is not limited thereto.

[0133] As Figure 18 With Figure 11As shown, in some embodiments, dummy gate structures 42 located on the first region R1 and the second region R2 can overlap with the protrusion P1 of the first gate oxide layer 20 in the first direction D1. In addition, the dummy gate structures 42 can be removed by a replacement metal gate fabrication process and replaced by gate structures GS, but the application is not limited thereto. Further, in some embodiments, after the source / drain regions SD1, SD2, SD3, SD4 and SD5 are formed, a dielectric layer 50 can be formed on the semiconductor substrate 10 to cover the dummy gate structures 42. Then, a planarization fabrication process can be performed to remove part of the dielectric layer 50 and remove the gate cap layer 44, thereby exposing the dummy gate structures 42. Next, the exposed dummy gate structures 42 can be removed to form trenches surrounded by spacers on the regions, and gate dielectric layers HK and gate structures GS can be formed in the trenches. The planarization fabrication process can include a chemical mechanical polishing (CMP) fabrication process, an etch-back fabrication process or other suitable planarization methods. In some embodiments, after the dummy gate structures 42 are removed and before the gate structures GS are formed, a gate dielectric layer HK can be formed on the semiconductor substrate 10, and the gate dielectric layer HK can have a substantially U-shaped structure surrounding the gate structures GS in a cross-sectional view of the semiconductor device 102 (e.g. Figure 11 ), but the application is not limited thereto. In addition, the dummy gate structures 42 can also be considered as being replaced by the gate dielectric layers HK and the gate structures GS, but the application is not limited thereto.

[0134] In some embodiments, the semiconductor devices 102 formed on the first region R1 and the second region R2 can be applied to different operating voltages due to the different thicknesses of the gate oxide layers, the semiconductor devices formed on the third region R3 can be operated at a relatively high voltage due to the relatively thick gate oxide layer, the semiconductor devices formed on the fourth region R4 can be operated at a relatively low voltage due to the relatively thin gate oxide layer, and the semiconductor devices formed on the fifth region R5 can correspond to devices (e.g., core devices) that require a relatively thin gate oxide layer, but the application is not limited thereto. In other words, semiconductor devices applied to different operating voltages can be formed by the fabrication method of the present embodiment, thereby achieving the effect of process integration. Furthermore, by forming the relatively thick first gate oxide layer 20 in the recess RC and controlling the height of the raised portion P1 of the first gate oxide layer 20, the negative effects of providing the relatively thick first gate oxide layer 20 on the gate structure GS and the fabrication process of forming the gate structure GS (e.g., the replacement metal gate fabrication process described above) can be reduced, thereby improving the electrical performance or / and the fabrication process yield of the semiconductor device.

[0135] Referring to Figure 19 . Figure 19 A schematic diagram of a semiconductor device 103 according to a third embodiment of the present application is shown. As Figure 19As shown, the semiconductor device 103 may further include a drift region DR disposed in the semiconductor substrate 10 and partially located below the first gate oxide layer 20 in the first direction D1. In other words, the method of fabricating the semiconductor device 103 may further include forming the drift region DR in the semiconductor substrate 10. In some embodiments, the drain region (e.g., the source / drain region SD1) of the semiconductor device 103 may be partially disposed in the drift region DR and partially disposed in the well region W1. In some embodiments, a portion of the isolation structure 18 may be located in the drift region DR and located between the first gate oxide layer 20 and the source / drain region SD1 in the second direction D2, while another portion of the isolation structure 18 may be located between the drift region DR and the well region W1, but is not limited thereto. In some embodiments, the semiconductor substrate 10 may have a first conductivity type or include a region with a first conductivity type, while the drift region DR and the well region W1 may have a second conductivity type, and the second conductivity type may be complementary to the first conductivity type, but is not limited thereto. For example, the first conductivity type mentioned above can be p-type, and the second conductivity type can be n-type. Therefore, the semiconductor substrate 10 can be a p-type semiconductor substrate or a semiconductor substrate with a p-type well. The drift region DR and the well region W1 can be n-type wells, and the source / drain regions SD1, SD2, and lightly doped region LD2 can be n-type doped regions, but are not limited thereto. By setting the drift region DR in this embodiment, the breakdown voltage capability of the semiconductor device 103 can be further improved, and the drift region DR in this embodiment can also be applied to other embodiments of the present invention as needed.

[0136] Please see Figure 20 . Figure 20 The illustration shows a schematic diagram of a semiconductor device 104 according to a fourth embodiment of the present invention. Figure 20 As shown, the first gate oxide layer 20 in this embodiment may further include a recessed portion P3, which may be located between the raised portion P1 and the second gate oxide layer 34 in the second direction D2. An upper surface S3 of the recessed portion P3 may be lower than the upper surface S2 of the main body portion P2 in the first direction D1, and the length L3 of the recessed portion P3 in the second direction D2 may be shorter than the length L2 of the main body portion P2 in the second direction D2. In some embodiments, the above-mentioned... Figure 2 The spacing SP between mask patterns M1 and M2 is used to further reduce the height H of the raised portion P1 of the formed first gate oxide layer 20, but this approach results in a larger amount of the first gate oxide layer 20 being formed. Figure 8 The recessed portion P3 in this embodiment is formed by removing material during the etching process 92. Therefore, the above can be adjusted according to the design requirements of the product. Figure 2The spacing SP between the mask patterns M1 and M2 is such that the height H of the raised portion P1 of the first gate oxide layer 20 can meet the requirements and / or the visual design needs determine whether to form a recess P3.

[0137] In summary, in the semiconductor device and its manufacturing method of the present invention, a gate oxide layer can be disposed in a recess of the semiconductor substrate, thereby increasing the thickness of a portion of the gate oxide layer and reducing the negative impact of a thicker gate oxide layer on the gate structure and its formation method, thereby improving the electrical performance and / or manufacturing yield of the semiconductor device.

[0138] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, characterized by comprising: comprising: a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region adjacent to the first region, wherein the first region and the second region are both active regions; a recess disposed in the first region of the semiconductor substrate, wherein an edge of the recess is located at an interface between the first region and the second region; a first gate oxide layer at least partially disposed in the recess, wherein the first gate oxide layer comprises a bump portion disposed adjacent to the edge of the recess, and a height of the bump portion is less than a depth of the recess; and a gate structure disposed on the first region and the second region of the semiconductor substrate, wherein the gate structure overlaps the bump portion of the first gate oxide layer in a vertical direction.

2. The semiconductor device of claim 1, wherein the height of the bump portion is less than or equal to 15% of the depth of the recess.

3. The semiconductor device of claim 1, wherein the first gate oxide layer further comprises: a body portion connected to the bump portion, wherein an upper surface of the body portion is lower than an upper surface of the bump portion in the vertical direction, and a thickness of the body portion is greater than the height of the bump portion.

4. The semiconductor device of claim 3, wherein the bump portion is disposed between the edge of the recess and at least a portion of the body portion in a horizontal direction, and a length of the bump portion in the horizontal direction is less than a length of the body portion in the horizontal direction.

5. The semiconductor device of claim 3, wherein the gate structure further overlaps the body portion in the vertical direction.

6. The semiconductor device of claim 3, wherein the thickness of the body portion is between 90% of the depth of the recess and 110% of the depth of the recess.

7. The semiconductor device of claim 1, further comprising: a second gate oxide layer disposed on the second region of the semiconductor substrate, wherein the second gate oxide layer is thinner than the first gate oxide layer, and the gate structure further overlaps the second gate oxide layer in the vertical direction.

8. The semiconductor device of claim 7, further comprising: a gate dielectric layer disposed between the gate structure and the semiconductor substrate, wherein a portion of the gate dielectric layer is disposed between the gate structure and the first gate oxide layer in the vertical direction and another portion of the gate dielectric layer is disposed between the gate structure and the second gate oxide layer in the vertical direction.

9. The semiconductor device of claim 1, further comprising: an opening penetrating the first gate oxide layer in the vertical direction; and a drain region disposed in the semiconductor substrate and corresponding to the opening in the vertical direction.

10. The semiconductor device of claim 1, further comprising: a drift region disposed in the semiconductor substrate and partially under the first gate oxide layer in the vertical direction; and a drain region at least partially disposed in the drift region.

11. A method for fabricating a semiconductor device, comprising: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region adjacent to the first region, wherein the first region and the second region are both active regions; forming a recess in the first region of the semiconductor substrate, wherein an edge of the recess is located at an interface between the first region and the second region; forming a first gate oxide layer at least partially in the recess, wherein the first gate oxide layer comprises a bump portion disposed adjacent to the edge of the recess, and a height of the bump portion is less than a depth of the recess; and forming a gate structure on the first region and the second region of the semiconductor substrate, wherein the gate structure overlaps the bump portion of the first gate oxide layer in a vertical direction. forming a recess in the first region of the semiconductor substrate, wherein an edge of the recess is located at an interface between the first region and the second region; forming a first gate oxide layer on the semiconductor substrate, wherein the first gate oxide layer is disposed at least partially in the recess, the first gate oxide layer includes a protrusion disposed adjacent to the edge of the recess, and a height of the protrusion is less than a depth of the recess; and forming a gate structure on the first region and the second region of the semiconductor substrate, wherein the gate structure overlaps the protrusion of the first gate oxide layer in a vertical direction.

12. The method of claim 11, wherein forming the recess comprises: forming a pad oxide layer on the semiconductor substrate; forming a mask layer on the pad oxide layer, wherein the pad oxide layer and the mask layer are formed on the first region and the second region; removing a portion of the pad oxide layer and a portion of the mask layer to expose a portion of the first region of the semiconductor substrate; performing an oxidation fabrication process on the exposed first region of the semiconductor substrate to form an extension oxide layer, wherein the extension oxide layer is partially embedded in the semiconductor substrate and connected to the pad oxide layer; and removing the extension oxide layer, the pad oxide layer, and the mask layer to form the recess.

13. The method of claim 11, wherein the first gate oxide layer is partially formed in the recess and partially formed on the second region, and forming the first gate oxide layer comprises: forming a patterned mask layer on the first gate oxide layer; and performing an etching fabrication process on the first gate oxide layer using the patterned mask layer as a mask to remove the first gate oxide layer on the second region and form the protrusion of the first gate oxide layer, wherein the first gate oxide layer on the second region and a portion of the first gate oxide layer on the recess are exposed after forming the patterned mask layer and during the etching fabrication process.

14. The method of claim 11, wherein the height of the protrusion is less than or equal to 15% of the depth of the recess.

15. The method of claim 11, wherein the first gate oxide layer further comprises: a body portion connected to the protrusion, wherein an upper surface of the body portion is lower than an upper surface of the protrusion in the vertical direction, a thickness of the body portion is greater than the height of the protrusion, a length of the protrusion in a horizontal direction is less than a length of the body portion in the horizontal direction, and the gate structure further overlaps the body portion in the vertical direction.

16. The method of claim 11, further comprising: forming a second gate oxide layer on the second region of the semiconductor substrate after forming the first gate oxide layer, wherein the second gate oxide layer is thinner than the first gate oxide layer, and the gate structure further overlaps the second gate oxide layer in the vertical direction. ​ ​ 17. The method of claim 16, further comprising: forming a dummy gate structure on the semiconductor substrate, wherein the dummy gate structure overlaps the raised portion of the first gate oxide layer in the vertical direction; and removing the dummy gate structure and replacing the dummy gate structure with the gate structure.

18. The method of claim 17, further comprising: forming a gate dielectric layer on the semiconductor substrate after removing the dummy gate structure and before forming the gate structure, wherein a portion of the gate dielectric layer is disposed between the gate structure and the first gate oxide layer in the vertical direction and another portion of the gate dielectric layer is disposed between the gate structure and the second gate oxide layer in the vertical direction.

19. The method of claim 11, further comprising: forming an opening through the first gate oxide layer in the vertical direction; and forming a drain region in the semiconductor substrate, wherein the drain region corresponds to the opening in the vertical direction.

20. The method of claim 11, further comprising: forming a drift region in the semiconductor substrate, wherein the drift region is partially located under the first gate oxide layer in the vertical direction; and forming a drain region in the semiconductor substrate, wherein the drain region is at least partially disposed in the drift region. ​

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