Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same. The method includes providing a substrate, forming a doped layer on the substrate, the doped layer including a plurality of adjacent first regions and second regions, forming a channel pillar on the first regions, and forming a contact layer on the surface of the second regions. The contact layer covers the surface of the second regions, reduces the resistance of the surface of the second regions, and effectively reduces the contact resistance between the doped layer and a first conductive plug on the contact layer when the doped layer is connected to an external circuit through the first conductive plug. On the other hand, the contact layer effectively reduces the parasitic capacitance between the first conductive plug on the surface of the second regions and a second conductive plug on the surface of the channel pillar.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the current semiconductor field, the FinFET (Fin Field-Effect Transistor) is an emerging multi-gate device. Compared with planar metal-oxide-semiconductor field-effect transistors (MOSFETs), FinFETs have stronger short-channel rejection and higher operating current, and are now widely used in various semiconductor devices. However, with the further development of semiconductor technology, the transistor size has shrunk to below a few nanometers. The size of FinFETs themselves has been reduced to its limit. Limitations in fin spacing, short-channel effect, leakage current, and materials have made transistor manufacturing precarious, and even the physical structure cannot be completed.

[0003] Gate-all-around (GAA) technology has become a new direction for research and development in the industry. This technology is characterized by the gate completely surrounding the channel on all four sides. The source and drain no longer contact the substrate; instead, multiple source and drain electrodes, arranged laterally and perpendicularly to the gate in linear (rod-like), planar, or sheet-like shapes, are used to achieve the basic structure and function of a MOSFET. This design largely solves various problems caused by reducing the gate pitch, including capacitance effects. Furthermore, since the channel is surrounded by the gate on all four sides, the channel current flows more smoothly than with the three-sided enclosure of FinFETs. Industry experts estimate that the application of GAA technology can essentially solve the semiconductor manufacturing problems of 3nm and even smaller dimensions.

[0004] However, as an important direction for development in the industry, GAA technology still needs improvement. Summary of the Invention

[0005] This invention provides a semiconductor structure and a method for forming the same, in order to improve the performance of the semiconductor structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate; a doped layer on the substrate, the doped layer comprising an adjacent first region and a second region; a channel pillar on the first region; and a contact layer on the surface of the second region.

[0007] Optionally, it may also include a first conductive plug located on the surface of the contact layer portion.

[0008] Optionally, it may also include a gate dielectric layer located on the sidewall of the channel post and the surface of the first region.

[0009] Optionally, the material of the gate dielectric layer includes a high-k dielectric material.

[0010] Optionally, it may also include: an isolation layer located on the surface of the doped layer and the contact layer, the isolation layer being located on a portion of the gate dielectric layer surface on the sidewall of the channel pillar, and the surface of the isolation layer being lower than the top surface of the channel pillar.

[0011] Optionally, it also includes a gate oxide layer located between the gate dielectric layer and the channel post sidewall and the surface of the first region.

[0012] Optionally, the material of the gate oxide layer includes silicon oxide.

[0013] Optionally, it may also include a cover layer located between the isolation layer and the gate dielectric layer.

[0014] Optionally, the material of the covering layer includes oxides.

[0015] Optionally, it further includes: a gate layer located on the surface of the gate dielectric layer on the sidewall of the channel pillar, the gate layer surrounding the channel pillar, and the gate layer also located on the surface of the isolation layer on the first region.

[0016] Optionally, a work function layer may be further provided between the gate layer and the gate dielectric layer.

[0017] Optionally, the material of the gate layer includes metal.

[0018] Optionally, it may also include an interlayer dielectric layer located on the surface of the isolation layer, the interlayer dielectric layer also being located on the surface of the gate layer.

[0019] Optionally, the first conductive plug is also located within the interlayer dielectric layer and the isolation layer.

[0020] Optionally, the doped layer and the channel pillar are doped with N-type ions or P-type ions.

[0021] Optionally, the material of the contact layer includes metal silicides.

[0022] Optionally, it may also include a hard mask layer located on the top surface of the channel post.

[0023] Optionally, the material of the hard mask layer includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon oxynitride.

[0024] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a doped layer on the substrate, the doped layer comprising an adjacent first region and a second region; forming a channel pillar on the first region; and forming a contact layer on the surface of the second region.

[0025] Optionally, it may also include forming a first conductive plug on a portion of the surface of the contact layer.

[0026] Optionally, before forming the contact layer, the method further includes: forming a gate dielectric layer on the sidewall of the channel post and the surface of the first region, and a sacrificial sidewall located on the sidewall surface of the gate dielectric layer.

[0027] Optionally, the method for forming the contact layer includes: using the sacrificial sidewall as a mask, forming the contact layer on the surface of the second region using a self-aligned siliconization process; and removing the sacrificial sidewall after forming the contact layer.

[0028] Optionally, the material of the sacrificial sidewall includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon oxynitride.

[0029] Optionally, the material of the gate dielectric layer includes a high-k dielectric material.

[0030] Optionally, before forming the first conductive plug, an isolation layer is formed on the surfaces of the doped layer and the contact layer, the isolation layer being located on a portion of the gate dielectric layer surface of the channel post sidewall, and the surface of the isolation layer being lower than the top surface of the channel post.

[0031] Optionally, the method for forming the gate dielectric layer and the sacrificial sidewall includes: forming a gate dielectric material layer on the surface of the doped layer and on the sidewall and top surface of the channel pillar; forming a sacrificial sidewall material layer on the surface of the gate dielectric material layer; and etching back the sacrificial sidewall material layer and the gate dielectric material layer until the top surface of the channel pillar and the surface of the second region are exposed, thereby forming the sacrificial sidewall and the gate dielectric layer.

[0032] Optionally, it further includes: forming a gate oxide layer on the surface of the doped layer and the sidewalls and top surface of the channel pillar before forming the gate dielectric material layer; and etching the gate oxide layer to form a gate oxide layer after etching back the gate dielectric material layer.

[0033] Optionally, the material of the gate oxide layer includes silicon oxide.

[0034] Optionally, a cover layer may also be formed between the isolation layer and the gate dielectric layer.

[0035] Optionally, the method for forming the capping layer includes: forming a capping material layer on the gate dielectric material layer before forming the sacrificial sidewall material layer; etching the capping material layer to form an initial capping layer after etching back the sacrificial sidewall material layer; and removing the initial capping layer exposed by the isolation layer after forming the isolation layer to form the capping layer.

[0036] Optionally, the material of the initial coating layer may include oxides.

[0037] Optionally, after the cover layer is formed and before the first conductive plug is formed, the method further includes: forming a gate layer on the surface of the gate dielectric layer of the channel pillar sidewall exposed by the isolation layer, the gate layer surrounding the channel pillar.

[0038] Optionally, it may also include: forming a function layer between the gate layer and the gate dielectric layer.

[0039] Optionally, the material of the work function layer includes a metal compound.

[0040] Optionally, after the gate layer is formed and before the first conductive plug is formed, the method further includes: forming an interlayer dielectric layer on the surface of the isolation layer, wherein the interlayer dielectric layer is also located on the surface of the gate layer.

[0041] Optionally, the method for forming the first conductive plug includes: forming a through hole in the interlayer dielectric layer and the isolation layer, wherein the bottom of the through hole exposes the surface of the contact layer; and filling the through hole with a conductive material to form the first conductive plug.

[0042] Optionally, N-type or P-type ions may be incorporated into the doped layer and the channel pillar.

[0043] Optionally, the material of the contact layer includes metal silicides.

[0044] Optionally, it also includes forming a hard mask layer on the top surface of the channel post.

[0045] Optionally, the material of the hard mask layer includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon oxynitride.

[0046] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0047] In the semiconductor structure provided by the present invention, a doped layer is located on the substrate, the doped layer includes multiple adjacent first and second regions, a channel pillar located on the first region, and a contact layer located on the surface of the second region. The contact layer covers the surface of the second region, thereby reducing the surface resistance of the second region. When the doped layer is connected to an external circuit through a first conductive plug located on the contact layer, the contact resistance between the doped layer and the first conductive plug is effectively reduced. On the other hand, the contact layer and the channel pillar are located on the first region and the surface of the second region, respectively. Since the contact layer and the channel pillar are located in different regions, when the doped layer and the channel pillar are connected to an external circuit, the distance between the first conductive plug located on the surface of the second region and the second conductive plug located on the surface of the channel pillar is relatively large, effectively reducing the parasitic capacitance between the first conductive plug and the second conductive plug.

[0048] In the semiconductor structure formation method of the present invention, a doped layer is formed on the substrate. The doped layer includes a plurality of adjacent first regions and second regions. A channel pillar is formed on the first region, and a contact layer is formed on the surface of the second region. The contact layer covers the surface of the second region, thereby reducing the surface resistance of the second region. When the doped layer is connected to an external circuit through a first conductive plug located on the contact layer, the contact resistance between the doped layer and the first conductive plug is effectively reduced. On the other hand, the contact layer and the channel pillar are located on the surfaces of the first region and the second region, respectively. Since the contact layer and the channel pillar are located in different regions, the distance between the first conductive plug located on the surface of the second region and the second conductive plug located on the surface of the channel pillar is relatively large when the doped layer and the channel pillar are connected to an external circuit, effectively reducing the parasitic capacitance between the first conductive plug and the second conductive plug. Attached Figure Description

[0049] Figures 1 to 3 This is a schematic cross-sectional view of a semiconductor structure.

[0050] Figures 4 to 12 This is a schematic cross-sectional view of each step in the semiconductor structure formation method according to an embodiment of the present invention. Detailed Implementation

[0051] As described in the background section, the performance of semiconductor structures formed using existing GAA (Glass Acrylic Alignment) technology urgently needs improvement. This paper will now illustrate and analyze one such semiconductor structure.

[0052] It should be noted that the term "surface" used in the implementation of this invention is used to define the relative positions between structures and does not limit direct contact between structures.

[0053] Figures 1 to 3This is a schematic diagram of a cross-sectional structure of a semiconductor.

[0054] Please refer to Figure 1 A substrate 100 is provided, the substrate including a base 101 and a doped layer 102 located on the surface of the base 101; a fin 103 is formed on the doped layer 102; an isolation structure 104 is formed on the surface of the doped layer 102, the isolation structure 104 is also located on a portion of the sidewall of the fin 103, and the top surface of the isolation structure 104 is lower than the top surface of the fin 103.

[0055] Please refer to Figure 2 A gate dielectric layer 105 is formed on the sidewall of the fin portion 103, and the gate dielectric layer 105 is also located on the isolation structure 104. The top of the gate dielectric layer 105 is lower than the top surface of the fin portion 103. A gate layer 106 is formed on the surface of the gate dielectric layer.

[0056] Please refer to Figure 3 An interlayer dielectric layer 107 is formed on the surface of the isolation structure 104, and the interlayer dielectric layer 107 is also located on the sidewall of the gate layer 106 and the fin 103; a contact hole (not shown) is formed in the interlayer dielectric layer 107, and the bottom of the contact hole exposes the surface of the doped layer 102; a contact layer 108 is formed at the bottom of the contact hole; and a conductive plug 109 is formed by filling the contact hole with conductive material.

[0057] In the GAA device formed by the above method, the contact layer 108 only covers a portion of the surface of the doped layer 102. The contact surface of the contact layer 108 is small, which cannot effectively reduce the contact resistance between the doped layer 102 and the first plug 109.

[0058] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. A doped layer is formed on a substrate, the doped layer comprising multiple adjacent first and second regions. A channel pillar is formed on the first region, and a contact layer is formed on the surface of the second region. The contact layer covers the surface of the second region, reducing its surface resistance. This effectively reduces the contact resistance between the doped layer and the first conductive plug when the doped layer connects to an external circuit via a first conductive plug located on the contact layer. Furthermore, since the contact layer and the channel pillar are located on the surfaces of the first and second regions respectively, and are in different regions, the distance between the first conductive plug on the surface of the second region and the second conductive plug on the surface of the channel pillar is greater when the doped layer and the channel pillar are connected to an external circuit, effectively reducing the parasitic capacitance between the first and second conductive plugs.

[0059] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0060] Figures 4 to 12 This is a schematic cross-sectional view of each step in the semiconductor structure formation method according to an embodiment of the present invention.

[0061] Please refer to Figure 4 A substrate 201 is provided; a doped layer 202 is formed on the substrate 201, the doped layer 202 including a plurality of adjacent first regions I and second regions II; a channel pillar 203 is formed on the first region I.

[0062] The substrate 201 is made of silicon.

[0063] The doped layer 202 is made of materials such as silicon, germanium silicon, and silicon carbide, and is used to form the source (drain) electrode subsequently. In this embodiment, the material of the doped layer 202 is silicon.

[0064] The method for forming the doped layer 202 includes: forming a doped material layer on the substrate 201; and incorporating N-type ions or P-type ions into the doped material layer to form the doped layer 202. In this embodiment, the doped ions in the doped layer 202 are N-type, and the process of incorporating N-type ions or P-type ions into the doped material layer is an ion implantation process or an in-situ doping process.

[0065] The channel pillar 203 is made of silicon, silicon germanium, or silicon carbide, and is used to subsequently form the channel region and the drain (source) electrode. In this embodiment, the channel pillar 203 is made of silicon.

[0066] The method for forming the channel 203 includes: forming an initial channel material layer on the surface of the doped layer; doping the initial channel material layer with N-type or P-type ions to form an initial channel region; forming a patterned hard mask layer 204 on the top surface of the initial channel material layer; and etching the initial channel material layer using the hard mask layer 204 as a mask to form the channel pillar 203. In this embodiment, the dopant ions in the initial channel material layer are P-type.

[0067] In this embodiment, the material of the hard mask layer 204 includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, or silicon carbonitride. The hard mask layer 204 is used to protect the channel pillar 203 and prevent it from being damaged during subsequent processes.

[0068] In this embodiment, a gate dielectric layer and a sacrificial sidewall located on the sidewall surface of the gate dielectric layer are subsequently formed on the sidewall of the channel post 203 and the surface of the first region I. The method for forming the gate dielectric layer and the sacrificial sidewall is as follows: Figures 5 to 6 As shown.

[0069] Please refer to Figure 5 A gate dielectric material layer 205 is formed on the surface of the doped layer 202 and on the sidewalls and top surface of the channel pillar 203; a sacrificial sidewall material layer 206 is formed on the surface of the gate dielectric material layer 205.

[0070] The gate dielectric material layer 205 is used to subsequently form the gate dielectric layer. The material of the gate dielectric material layer 205 includes a high-k dielectric material. In this embodiment, the material of the gate dielectric material layer 205 is hafnium oxide.

[0071] In this embodiment, the method further includes forming a gate oxide material layer 207 on the surface of the doped layer 202 and on the sidewalls and top surface of the channel pillar 203 before forming the gate dielectric material layer 205.

[0072] The gate oxide material layer 207 is used for subsequent formation of the gate oxide layer, and the material of the gate oxide material layer 207 is silicon oxide. In another embodiment, the material of the gate oxide material layer 207 is silicon oxynitride.

[0073] In this embodiment, the method further includes forming a cover material layer 208 on the gate dielectric material layer 205 before forming the sacrificial sidewall material layer 206.

[0074] The material of the cover material layer 208 includes oxides. In this embodiment, the material of the cover material layer 208 is silicon oxide. The cover material layer 208 is used to subsequently form an initial cover layer, which is used to subsequently form the cover layer.

[0075] The material of the sacrificial sidewall material layer 206 includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbonitride. The sacrificial sidewall material layer 206 is used to form a sacrificial sidewall, and subsequently, using the sacrificial sidewall as a mask, a self-aligned silicide process is used to form the contact layer on the surface of the second region II.

[0076] Please refer to Figure 6 , back etch the sacrificial sidewall material layer 206 (e.g. Figure 5 (as shown) and the gate dielectric material layer 205 (as shown) Figure 5 As shown), until the top surface of the trench post 203 and the surface of the second region II are exposed, the sacrificial sidewall 209 and the grid dielectric layer 210 are formed.

[0077] After etching back the gate dielectric material layer 205, etch the gate oxide material layer 207 (e.g.) Figure 5 (As shown) to form a gate oxide layer 211. In this embodiment, the gate oxide layer 207 is made of silicon oxide. In another embodiment, the gate oxide layer is made of silicon oxynitride. The gate oxide layer 211 is used to improve the interface states between the gate dielectric layer 210 and the channel pillar 203.

[0078] After re-etching the sacrificial sidewall material layer 206, etch the cover material layer 208 (e.g. Figure 5 As shown, an initial capping layer 212 is formed. In this embodiment, the material of the initial capping layer is silicon oxide. The initial capping layer 212 is used to form a capping layer and, when the sacrificial sidewall 209 is subsequently removed, to protect the gate dielectric layer 210 from damage.

[0079] The thickness of the sacrificial sidewall 209 ranges from 3 nanometers to 15 nanometers. The sacrificial sidewall is used to position the subsequently formed contact layer. A first conductive plug is then formed on the contact layer; a second conductive plug is formed on the channel post. The thickness of the sacrificial sidewall 209 determines the distance between the first and second conductive plugs, thereby reducing the parasitic capacitance between them by adjusting the thickness of the sacrificial sidewall.

[0080] Please refer to Figure 7 After the sacrificial sidewall 209 and the gate dielectric layer 210 are formed, a contact layer 213 is formed on the surface of the second region II; after the contact layer 213 is formed, the sacrificial sidewall 209 (not shown in the figure) is removed.

[0081] The method for forming the contact layer 213 includes: using the sacrificial sidewall 209 as a mask, forming a metal film on the surface of the second region II; after forming the metal film, performing two rapid thermal annealing treatments on the metal film and the second region; and forming a metal silicide on the surface of the second region II through a self-aligned silicide process to form the contact layer 213.

[0082] The thickness of the contact layer 213 ranges from 4 nanometers to 20 nanometers.

[0083] The contact layer 213 is made of metal silicides, such as tungsten silicide, cobalt silicide, titanium silicide, cobalt silicide, nickel platinum silicide, etc. In this embodiment, the contact layer 213 is made of tungsten silicide. The contact layer 213 covers the surface of the second region II, reducing the surface resistance of the second region II. When the doped layer 202 is connected to the external circuit through the first conductive plug located on the contact layer, the contact resistance between the doped layer 202 and the first conductive plug is effectively reduced. On the other hand, the contact layer 213 and the channel post 203 are located on the first region I and the surface of the second region II, respectively. The fact that the contact layer 213 and the channel post 203 are located in different regions allows for a greater distance between the first conductive plug on the surface of the second region II and the second conductive plug on the surface of the channel post 203 when the doped layer 202 and the channel post 203 are connected to the external circuit, effectively reducing the parasitic capacitance between the first conductive plug and the second conductive plug.

[0084] Please refer to Figure 8 An isolation layer 214 is formed on the surfaces of the doped layer 202 and the contact layer 213. The isolation layer 214 is located on a portion of the gate dielectric layer 210 surface on the sidewall of the channel post 203, and the surface of the isolation layer 214 is lower than the top surface of the channel post 203.

[0085] In this embodiment, the method further includes: after forming the isolation layer 214, removing the initial cover layer 212 exposed by the isolation layer 214 to form the cover layer 215. The cover layer 215 serves as an adhesive layer between the isolation layer 214 and the gate dielectric layer 210.

[0086] The method for forming the isolation layer 214 includes: depositing a silicon oxide material layer on the surfaces of the doped layer 202 and the contact layer 213; planarizing the silicon oxide material layer; and etching back the silicon oxide material layer until a portion of the gate dielectric layer 210 surface and the top surface of the channel pillar 203 are exposed, thereby forming the isolation layer 214. In this embodiment, the silicon oxide material layer is etched back until a portion of the initial capping layer 212 surface and the top surface of the channel pillar 203 are exposed.

[0087] The process for depositing the silicon oxide material layer includes chemical vapor deposition. In this embodiment, the process for depositing the silicon oxide material layer is fluid chemical vapor deposition. The isolation layer 214 formed by fluid chemical vapor deposition is less prone to defects such as voids.

[0088] The isolation layer 214 is made of one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon oxynitride. The isolation layer 214 is used to isolate the contact layer 213 from the subsequently formed gate layer, and to provide electrical insulation between conductive plugs and between conductive plugs and the gate layer.

[0089] Subsequently, a gate layer is formed on the surface of the gate dielectric layer 210 exposed on the sidewall of the channel pillar 203 by the isolation layer 214, the gate layer surrounding the channel pillar 203, and the gate layer is formed by the following method: Figures 9 to 10 As shown.

[0090] Please refer to Figure 9 A gate material layer 315 is formed on the surface of the isolation layer 214. The gate material layer 315 is also located on the top surface of the channel pillar 203 and the surface of the gate dielectric layer 210 on the sidewall of the channel pillar 203.

[0091] The gate material layer 315 is also located on the surface of the hard mask layer 204.

[0092] The gate material layer 315 is made of a metal, including copper, aluminum, or tungsten. In this embodiment, the gate material layer 315 is made of aluminum.

[0093] The formation process of the gate material layer 315 includes atomic layer deposition, physical vapor deposition, or electroplating. In this embodiment, the gate material layer 315 is formed using atomic layer deposition.

[0094] In this embodiment, before forming the gate material layer 315, a work function material layer 216 is formed on the surface of the isolation layer 214. The work function material layer 216 is also located on the surface of the hard mask layer 204 and the surface of the gate dielectric layer 210 on the sidewall of the channel pillar 203.

[0095] Please refer to Figure 10 The gate material layer 315 is etched back until the surface of the isolation layer 214 and the top surface of the channel pillar 203 are exposed, forming the gate layer 217.

[0096] In this embodiment, the method further includes removing the hard mask layer 204 from the top of the channel post 203.

[0097] In this embodiment, the method further includes: after etching back the gate material layer 315, etching the gate dielectric layer 210 and the gate oxide layer 211 until a portion of the sidewall surface of the channel pillar is exposed, wherein the gate dielectric layer 210 and the gate oxide layer 211 are partially retained. In another embodiment, only the gate material layer is etched back, and the gate dielectric layer and the gate oxide layer on the sidewall of the channel pillar 203 are fully retained.

[0098] In this embodiment, the process further includes etching the work function material layer 216 to form the work function layer 218. In this embodiment, the material of the work function material layer 216 is TaAlN. In another embodiment, the material of the work function material layer 216 is TaN. The work function material layer 216 is used to subsequently form a work function layer, which is used to adjust the threshold voltage of the subsequently formed semiconductor device.

[0099] In another embodiment, the work function layer is formed before the gate layer is formed and before the gate material layer is formed. The method for forming the work function layer and the gate layer includes: forming a work function material layer on the surface of the isolation layer, the work function material layer also being located on the surface of the hard mask layer and the gate dielectric layer surface of the channel pillar sidewall; etching back the work function material layer until the surface of the isolation layer, the top surface of the channel pillar and a portion of the sidewall of the channel pillar are exposed, forming the work function layer; covering the work function layer to form a gate material layer; etching back the gate material layer until the surface of the isolation layer, the top surface of the channel pillar and a portion of the sidewall of the channel pillar are exposed, forming the gate layer.

[0100] In this embodiment, a portion of the gate material layer 315 and a portion of the work function material layer 216 on the isolation layer 214 are retained, and an "L-shaped" gate layer is formed on one side of the channel pillar 203 to facilitate the subsequent formation of a third conductive plug on the gate layer 217 on the isolation layer 214.

[0101] Please refer to Figure 11 N-type or P-type ions are doped into the exposed channel pillar 203 to form a doped region 219; an interlayer dielectric layer 220 is formed on the surface of the isolation layer 214, and the interlayer dielectric layer 220 is also located on the surface of the gate layer 217 and the surface of the exposed channel pillar 203.

[0102] In this embodiment, N-type ions are doped into the exposed channel pillar 203 to form a doped region 219. The doped region 219 is used to form the source (drain) electrode.

[0103] The interlayer dielectric layer 220 is used to isolate metal interconnects and devices in subsequent device manufacturing processes, reduce parasitic capacitance between metal and substrate, and improve the formation of parasitic field-effect transistors when metal spans different regions.

[0104] The material of the interlayer dielectric layer 220 includes silicon oxide.

[0105] The method for forming the interlayer dielectric layer 220 includes: forming a dielectric material layer on the surface of the isolation layer 214, the sidewall and surface of the channel pillar 203, and the surface of the gate layer 217 using a chemical vapor deposition process; and planarizing the dielectric material layer using a chemical mechanical polishing process.

[0106] Please refer to Figure 12 A first conductive plug 221 is formed on a portion of the surface of the contact layer 213.

[0107] The method for forming the first conductive plug 221 includes: forming a through hole (not shown in the figure) in the interlayer dielectric layer 220 and the isolation layer 214, the bottom of the through hole exposing the surface of the contact layer 213; filling the through hole with conductive material to form the first conductive plug 221.

[0108] In this embodiment, the method further includes: forming a second conductive plug 222 on a portion of the surface of the channel post 203, the second conductive plug 222 also being located within the interlayer dielectric layer 220; and forming a third conductive plug 223 on the gate layer 217, the third conductive plug 223 also being located within the interlayer dielectric layer 220. In this embodiment, the third conductive plug 223 is located on the gate layer 217 on the isolation layer 214, and is located on a different side of the channel post 203 from the first conductive plug 221, in order to reduce the parasitic capacitance between the third conductive plug 223 and the first conductive plug 221.

[0109] Accordingly, the present invention also provides an embodiment of the semiconductor structure formed by the above-described forming method. Please refer to the following for details. Figure 12 It includes: a substrate 201; a doped layer 202 located on the substrate 201, the doped layer 202 including a plurality of adjacent first regions I and second regions II; a channel pillar 203 located on the first region I; and a contact layer 213 located on the surface of the second region II.

[0110] The contact layer 213 covers the surface of the second region II, reducing the surface resistance of the second region II. When the doped layer 202 is connected to an external circuit through the first conductive plug located on the contact layer 213, the contact resistance between the doped layer 202 and the first conductive plug is effectively reduced. On the other hand, the contact layer 213 and the channel post 203 are located on the first region I and the surface of the second region II, respectively. Since the contact layer 213 and the channel post 203 are located in different regions, when the doped layer 202 and the channel post 203 are connected to an external circuit, the distance between the first conductive plug located on the surface of the second region II and the second conductive plug located on the surface of the channel post 203 is relatively large, effectively reducing the parasitic capacitance between the first conductive plug and the second conductive plug.

[0111] The semiconductor structure further includes a first conductive plug 221 located on a portion of the surface of the contact layer 213.

[0112] The semiconductor structure further includes a gate dielectric layer 210 located on the sidewall of the channel pillar 203 and the surface of the first region I.

[0113] The material of the gate dielectric layer 210 includes a high-K dielectric material.

[0114] The semiconductor structure further includes an isolation layer 214 located on the surfaces of the doped layer 202 and the contact layer 213. The isolation layer 214 is located on a portion of the gate dielectric layer 210 on the sidewall of the channel pillar 203, and the surface of the isolation layer 214 is lower than the top surface of the channel pillar 203.

[0115] The semiconductor structure further includes a gate oxide layer 211 located between the gate dielectric layer 210 and the sidewall of the channel pillar 203 and the surface of the first region I.

[0116] The material of the gate oxide layer 211 includes silicon oxide.

[0117] The semiconductor structure further includes a capping layer 215 located between the isolation layer 214 and the gate dielectric layer 210.

[0118] The material of the cover layer 215 includes oxides.

[0119] The semiconductor structure further includes a gate layer 217 located on the surface of the gate dielectric layer 210 on the sidewall of the channel pillar 203, the gate layer 217 surrounding the channel pillar 203, and the gate layer 217 also located on the surface of the isolation layer 214 on the first region I.

[0120] The semiconductor structure includes a work function layer 218 between the gate layer 217 and the gate dielectric layer 210.

[0121] The material of the gate layer 217 includes metal.

[0122] The semiconductor structure further includes an interlayer dielectric layer 220 located on the surface of the isolation layer 214, and the interlayer dielectric layer 220 is also located on the surface of the gate layer 217.

[0123] The first conductive plug 221 is also located within the interlayer dielectric layer 220 and the isolation layer 214.

[0124] The doped layer 202 and the channel pillar 203 are doped with N-type ions or P-type ions.

[0125] The contact layer 213 is made of metal silicides, such as tungsten silicide, cobalt silicide, titanium silicide, cobalt silicide, and nickel platinum silicide. In this embodiment, the contact layer 213 is made of tungsten silicide. The contact layer 213 is used to reduce the contact resistance between the doped layer 202 and the first conductive plug 221.

[0126] The semiconductor structure further includes: a hard mask layer 204 located on the top surface of the channel pillar 203 (e.g., Figure 9 (As shown).

[0127] The material of the hard mask layer 204 includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon oxynitride.

[0128] The doped region 219 is located within the channel pillar 203 exposed in the gate layer 217.

[0129] An interlayer dielectric layer 220 is formed on the surface of the isolation layer 214, and the interlayer dielectric layer 220 is also located on the surface of the gate layer 217 and the surface of the exposed channel pillar 203.

[0130] A second conductive plug 222 is located on a portion of the surface of the channel post 203, and the second conductive plug 222 is also located within the interlayer dielectric layer 220; a third conductive plug 223 is located on the gate layer 217, and the third conductive plug 223 is also located within the interlayer dielectric layer 220. The third conductive plug 223 is located on the gate layer 217 on the isolation layer 214, and is located on a different side of the channel post 203 from the first conductive plug 221, which can reduce the parasitic capacitance between the third conductive plug 223 and the first conductive plug 221.

[0131] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A doped layer located on the substrate, the doped layer comprising an adjacent first region and a second region; The channel column is located in the first zone; The contact layer located on the surface of the second region; A first conductive plug located on the surface of the contact layer portion; A grid dielectric layer located on the sidewall of the channel post and on the surface of the first region; An isolation layer is located on the surface of the doped layer and the contact layer, the isolation layer is located on a portion of the gate dielectric layer surface on the sidewall of the channel pillar, and the surface of the isolation layer is lower than the top surface of the channel pillar; A cover layer located between the isolation layer and the gate dielectric layer.

2. The semiconductor structure as described in claim 1, characterized in that, The material of the gate dielectric layer includes a high-K dielectric material.

3. The semiconductor structure as described in claim 1, characterized in that, Also includes: The gate oxide layer is located between the gate dielectric layer and the channel post sidewall, and the surface of the first region.

4. The semiconductor structure as described in claim 3, characterized in that, The material of the gate oxide layer includes silicon oxide.

5. The semiconductor structure as described in claim 1, characterized in that, The material of the covering layer includes oxides.

6. The semiconductor structure as described in claim 1, characterized in that, Also includes: A gate layer is located on the surface of the gate dielectric layer on the sidewall of the channel pillar, the gate layer surrounds the channel pillar, and the gate layer is also located on the surface of the isolation layer on the first region.

7. The semiconductor structure as described in claim 6, characterized in that, include: There is also a work function layer between the gate layer and the gate dielectric layer.

8. The semiconductor structure as described in claim 6, characterized in that, The material of the gate layer includes metal.

9. The semiconductor structure as described in claim 6, characterized in that, Also includes: An interlayer dielectric layer is located on the surface of the isolation layer, and the interlayer dielectric layer is also located on the surface of the gate layer.

10. The semiconductor structure as described in claim 9, characterized in that, The first conductive plug is also located within the interlayer dielectric layer and the isolation layer.

11. The semiconductor structure as claimed in claim 1, characterized in that, The doped layer and the channel pillar are doped with N-type or P-type ions.

12. The semiconductor structure as claimed in claim 1, characterized in that, The material of the contact layer includes metal silicides.

13. The semiconductor structure as claimed in claim 1, characterized in that, Also includes: A hard mask layer located on the top surface of the channel post.

14. The semiconductor structure as described in claim 13, characterized in that, The material of the hard mask layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon oxynitride.

15. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A doped layer is formed on the substrate, the doped layer comprising an adjacent first region and a second region; A channel column is formed in the first region; A grid dielectric layer and a sacrificial sidewall are formed on the sidewall of the grid dielectric layer and the surface of the first region. After the sacrificial sidewall and the grid dielectric layer are formed, a contact layer is formed on the surface of the second region; An isolation layer is formed on the surfaces of the doped layer and the contact layer, the isolation layer being located on a portion of the gate dielectric layer surface on the sidewall of the channel pillar, and the surface of the isolation layer being lower than the top surface of the channel pillar; After the isolation layer is formed, a first conductive plug is formed on a portion of the surface of the contact layer; A cover layer is also formed between the isolation layer and the gate dielectric layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The method for forming the contact layer includes: using the sacrificial sidewall as a mask, forming the contact layer on the surface of the second region using a self-aligned siliconization process; and removing the sacrificial sidewall after forming the contact layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The material of the sacrificial sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon oxynitride.

18. The method for forming a semiconductor structure as described in claim 15, characterized in that, The material of the gate dielectric layer includes a high-K dielectric material.

19. The method for forming a semiconductor structure as described in claim 15, characterized in that, The method for forming the gate dielectric layer and the sacrificial sidewall includes: forming a gate dielectric material layer on the surface of the doped layer and on the sidewall and top surface of the channel pillar; forming a sacrificial sidewall material layer on the surface of the gate dielectric material layer; and etching back the sacrificial sidewall material layer and the gate dielectric material layer until the top surface of the channel pillar and the surface of the second region are exposed, thereby forming the sacrificial sidewall and the gate dielectric layer.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, Also includes: Before forming the gate dielectric material layer, a gate oxide material layer is formed on the surface of the doped layer and on the sidewalls and top surface of the channel pillar; After etching back the gate dielectric material layer, the gate oxide material layer is etched to form the gate oxide layer.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The material of the gate oxide layer includes silicon oxide.

22. The method for forming a semiconductor structure as described in claim 19, characterized in that, The method for forming the capping layer includes: forming a capping material layer on the gate dielectric material layer before forming the sacrificial sidewall material layer; etching the capping material layer to form an initial capping layer after etching back the sacrificial sidewall material layer; and removing the initial capping layer exposed by the isolation layer after forming the isolation layer to form the capping layer.

23. The method for forming a semiconductor structure as described in claim 22, characterized in that, Also includes: The material of the initial coating layer includes oxides.

24. The method for forming a semiconductor structure as described in claim 22, characterized in that, After the cover layer is formed and before the first conductive plug is formed, the method further includes: forming a gate layer on the surface of the gate dielectric layer of the channel pillar sidewall exposed by the isolation layer, the gate layer surrounding the channel pillar.

25. The method for forming a semiconductor structure as described in claim 24, characterized in that, Also includes: A function layer is also formed between the gate layer and the gate dielectric layer.

26. The method for forming a semiconductor structure as described in claim 25, characterized in that, The material of the work function layer includes metallic compounds.

27. The method for forming a semiconductor structure as described in claim 24, characterized in that, After the gate layer is formed and before the first conductive plug is formed, the method further includes: forming an interlayer dielectric layer on the surface of the isolation layer, wherein the interlayer dielectric layer is also located on the surface of the gate layer.

28. The method for forming a semiconductor structure as described in claim 27, characterized in that, The method for forming the first conductive plug includes: forming a through hole in the interlayer dielectric layer and the isolation layer, wherein the bottom of the through hole exposes the surface of the contact layer; and filling the through hole with a conductive material to form the first conductive plug.

29. The method for forming a semiconductor structure as described in claim 15, characterized in that, N-type or P-type ions are incorporated into the doped layer and the channel pillar.

30. The method for forming a semiconductor structure as described in claim 15, characterized in that, The material of the contact layer includes metal silicides.

31. The method for forming a semiconductor structure as described in claim 15, characterized in that, Also includes: A hard mask layer is formed on the top surface of the channel column.

32. The method for forming a semiconductor structure as described in claim 31, characterized in that, The material of the hard mask layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon oxynitride.

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