Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: a base, the base including a substrate and a fin protruding from the substrate; a channel structure layer located on and spaced apart from the fin, the channel structure layer including one or more spaced apart channel layers; a device gate structure spanning the fin and the channel structure layer and surrounding the channel layer; source / drain doped layers located in the channel structure layer and the fin on both sides of the device gate structure; and an interlayer dielectric layer located on top of the source / drain doped layers and covering the sidewalls of the device gate structure. The source / drain doped layers are also located in the fin, thereby increasing the volume of the source / drain doped layers and correspondingly increasing the channel stress generated by the source / drain doped layers, thereby improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration. Semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the channel length of transistors has to be continuously shortened to adapt to the reduction of process nodes.

[0003] To better adapt to the scaling requirements of device sizes, semiconductor processes are gradually transitioning from planar transistors to more efficient three-dimensional transistors, such as gate-all-around (GAA) transistors. In a GAA transistor, the gate surrounds the channel area on all sides. Compared with planar transistors, the gate of a GAA transistor has stronger control over the channel and can better suppress short channel effects. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the electrical performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a base, the base comprising a substrate and a fin protruding from the substrate; a channel structure layer, located on the fin and spaced apart from the fin, the channel structure layer comprising one or more spaced apart channel layers; a device gate structure, spanning the fin and the channel structure layer and surrounding the channel layer; a source-drain doped layer, located in the channel structure layer and the fin on both sides of the device gate structure; and an interlayer dielectric layer, located on top of the source-drain doped layer and covering the sidewalls of the device gate structure.

[0006] Optionally, along a direction parallel to the substrate and perpendicular to the extension direction of the device gate structure, the sidewall of the device gate structure located directly below the channel layer is retracted inward relative to the sidewall of the channel layer; the semiconductor structure also includes: an inner wall layer, located between the sidewall of the device gate structure directly below the channel layer and the source and drain doping layer.

[0007] Optionally, the source-drain doped layer includes: a first source-drain doped layer, located in the channel structure layer on both sides of the device gate structure; a second source-drain doped layer, located in the fin at the bottom of the first source-drain doped layer, and the side walls of the second source-drain doped layer are indented inward relative to the side walls of the first source-drain doped layer in a direction parallel to the substrate and perpendicular to the extension direction of the device gate structure.

[0008] Optionally, the sidewall of the second source / drain doped layer is retracted inwardly by 2 nm to 5 nm relative to the sidewall of the first source / drain doped layer.

[0009] Optionally, the device gate structure is a metal gate structure.

[0010] Optionally, the source-drain doped layer is located in a partial thickness of the fin.

[0011] Optionally, the distance from the bottom of the source / drain doping layer to the top of the fin is 20 nm to 60 nm.

[0012] Accordingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a base, the base comprising a substrate and a fin protruding from the substrate, one or more stacked channel stacks being formed on the fin, each of the channel stacks comprising a sacrificial layer and a channel layer located on the sacrificial layer; forming a gate structure spanning the channel stack and the fin on the substrate, the gate structure covering part of the top and part of the sidewalls of the channel stack; forming grooves in the channel stack and the fin on both sides of the gate structure, the sidewalls of the grooves exposing the channel stack and the fin; and forming a source-drain doping layer in the groove.

[0013] Optionally, along a direction parallel to the substrate and perpendicular to the extension direction of the device gate structure, the sidewall of the device gate structure located directly below the channel layer is retracted inward relative to the sidewall of the channel layer; the semiconductor structure also includes: an inner wall layer, located between the sidewall of the device gate structure directly below the channel layer and the source and drain doping layer.

[0014] Optionally, the step of forming the groove includes: forming a first groove in the channel stack on both sides of the gate structure, the sidewalls of the first groove expose the channel stack, and the bottom of the first groove exposes the fin; etching the fin at the bottom of the first groove to form a second groove in the fin, the top of the second groove is connected to the bottom of the first groove, the second groove and the first groove are used to constitute the groove, along a direction parallel to the substrate and perpendicular to the extension direction of the gate structure, the width of the second groove is smaller than the width of the first groove, and the sidewalls of the second groove are retracted inward relative to the sidewalls of the first groove.

[0015] Optionally, the grooves are formed in the channel stacks on both sides of the gate structure and in a partial thickness of the fin.

[0016] Optionally, after forming the first groove and before etching the fin at the bottom of the first groove, the method for forming the semiconductor structure further includes: forming a protective layer on the sidewalls of the first groove and the sidewalls of the gate structure; the step of forming the second groove includes: using the protective layer as a mask, etching the fin of a partial thickness at the bottom of the first groove to form a second groove; after forming the second groove and before forming the source-drain doping layer, the method for forming the semiconductor structure further includes: removing the protective layer located on the sidewalls of the first groove and the sidewalls of the gate structure.

[0017] Optionally, after forming the first groove and before forming the protective layer, the method for forming the semiconductor structure further includes: laterally etching the portion of the sacrificial layer exposed on the sidewall of the first groove in a direction parallel to the substrate and perpendicular to the extension direction of the gate structure to form a third groove, wherein the third groove is surrounded by the adjacent channel layer and the remaining sacrificial layer, or the third groove is surrounded by the fin, the channel layer adjacent to the fin, and the remaining sacrificial layer; in the step of forming the protective layer, the protective layer also fills the third groove; in the step of removing the protective layer located on the sidewall of the first groove and the sidewall of the gate structure, the remaining protective layer filling the third groove is retained as an inner wall layer.

[0018] Optionally, the step of removing the protection layer located on the sidewalls of the first groove and the sidewalls of the gate structure includes: etching the protection layer using an anisotropic dry etching process.

[0019] Optionally, the step of forming the protective layer includes: forming a protective material layer on the sidewalls of the channel stack exposed by the first groove, the sidewalls and top of the gate structure, and the fin surface at the bottom of the first groove; removing the protective material layer located on the top of the gate structure and the fin surface, and using the protective material layer located on the sidewalls of the gate structure and the sidewalls of the channel stack exposed by the first groove as the protective layer.

[0020] Optionally, the process of forming the protective material layer includes an atomic layer deposition process or a chemical vapor deposition process.

[0021] Optionally, an anisotropic dry etching process is used to etch the channel stack and the fins on both sides of the gate structure to form the groove.

[0022] Optionally, in the step of forming the groove, a distance from the bottom of the groove to the top of the fin is 20 nm to 60 nm.

[0023] Optionally, in the step of forming the protection layer, the thickness of the protection layer located on the sidewall of the gate structure is 2 nm to 5 nm.

[0024] Optionally, an epitaxial process is used to form a source-drain doped layer in the groove.

[0025] Optionally, after forming the source / drain doping layer, the formation method further includes: forming an interlayer dielectric layer on top of the source / drain doping layer, the interlayer dielectric layer covering the side walls of the gate structure; removing the gate structure, forming a gate opening in the interlayer dielectric layer; removing the sacrificial layer exposed by the gate opening, and forming a through groove connected to the gate opening below the channel layer; forming a device gate structure in the gate opening and the through groove, the device gate structure surrounding the channel layer.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] An embodiment of the present invention provides a semiconductor structure, wherein the source-drain doped layer is located in the channel structure layer and the fin on both sides of the device gate structure. Therefore, compared with the solution in which the source-drain doped layer is only located in the channel structure layer on both sides of the device gate structure, the bottom of the source-drain doped layer extends into the fin, thereby increasing the volume of the source-drain doped layer, correspondingly increasing the channel stress generated by the source-drain doped layer, and thereby improving the electrical performance of the semiconductor structure.

[0028] An embodiment of the present invention also provides a method for forming a semiconductor structure, forming a gate structure across the channel stack on a substrate, the gate structure covering a portion of the top and a portion of the sidewall of the channel stack, etching the channel stack and the fins on both sides of the gate structure, and forming grooves in the channel stack and the fins on both sides of the gate structure. After the grooves are formed, source-drain doping layers are formed in the grooves. Therefore, compared with the solution of forming grooves only in the channel stacks on both sides of the gate structure, the bottom of the grooves extends into the fins, thereby increasing the volume of the source-drain doping layers, correspondingly increasing the channel stress generated by the source-drain doping layers, and thereby improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 12 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0030] The performance of currently available all-around gate transistors still needs to be improved. Specifically, in current all-around gate transistors, the source and drain doping layers are located in the channel structure layer on both sides of the gate structure. The source and drain doping layers on both sides of the device gate structure are too small, and the channel stress generated by the source and drain doping layers is correspondingly small, which reduces the carrier mobility in the channel and, in turn, the electrical performance of the semiconductor structure.

[0031] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a base, the base including a substrate and a fin protruding from the substrate; a channel structure layer, located on the fin and spaced apart from the fin, the channel structure layer including one or more spaced apart channel layers; a device gate structure, spanning the fin and the channel structure layer and surrounding the channel layer; a source-drain doped layer, located in the channel structure layer and the fin on both sides of the device gate structure; an interlayer dielectric layer, located on top of the source-drain doped layer and covering the sidewalls of the device gate structure.

[0032] In the solution disclosed in the embodiment of the present invention, the source-drain doped layer is located in the channel structure layer and the fin on both sides of the device gate structure. Therefore, compared with the solution in which the source-drain doped layer is only located in the channel structure layer on both sides of the device gate structure, the bottom of the source-drain doped layer extends into the fin, thereby increasing the volume of the source-drain doped layer, and correspondingly increasing the channel stress generated by the source-drain doped layer, thereby improving the electrical performance of the semiconductor structure.

[0033] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figures 1 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for manufacturing a semiconductor structure of the present invention.

[0035] refer to Figure 1 , providing a base, the base including a substrate 100 and a fin 101 protruding from the substrate 100, one or more stacked channel stacks 102 are formed on the fin 101, and each of the channel stacks 102 includes a sacrificial layer 1021 and a channel layer 1022 located on the sacrificial layer 1021.

[0036] The substrate is used to provide a process platform for forming gate-all-around (GAA) transistors.

[0037] In this embodiment, the substrate is a three-dimensional substrate, which includes a substrate 100 and a fin 101 protruding from the substrate 100 .

[0038] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0039] The fin 101 exposes a portion of the substrate 100 , thereby providing a process basis for forming an isolation layer.

[0040] In this embodiment, the fin 101 is made of the same material as the substrate 100, that is, silicon. In other embodiments, the fin 101 may be made of a semiconductor material suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The fin may also be made of a different material than the substrate.

[0041] In this embodiment, the channel stack 102 is located on top of the fin 101 , and the extending direction of the channel stack 102 is the same as that of the fin 101 .

[0042] In this embodiment, there are multiple channel stacks 102 , and the stacking direction of the multiple stacked channel stacks 102 is perpendicular to the surface of the substrate 100 .

[0043] Each of the channel stacks 102 includes a sacrificial layer 1021 and a channel layer 1022 located on the sacrificial layer 1021. The channel stack 102 provides a process foundation for the subsequent formation of the suspended channel layer 1022. Specifically, the sacrificial layer 1021 supports the channel layer 1022, thereby providing a process foundation for the subsequent suspended arrangement of the channel layer 1022 and also occupies a space for the subsequent formation of the device gate structure. The channel layer 1022 is used to provide a conductive channel for the fully enclosed gate transistor.

[0044] Correspondingly, when there are multiple channel stacks 102 , there are also multiple channel layers 1022 , and the multiple channel layers 1022 are arranged at intervals.

[0045] In this embodiment, taking the case where there are multiple channel layers 1022 as an example, the multiple channel layers 1022 arranged at intervals constitute the channel structure layer 130. In other embodiments, the channel structure layer may also include only one channel layer.

[0046] In this embodiment, the material of the channel layer 1022 is Si, and the material of the sacrificial layer 1021 is SiGe. During the subsequent removal of the sacrificial layer 1021, SiGe and Si have relatively high etching selectivity. Therefore, by setting the material of the sacrificial layer 1021 to SiGe and the material of the channel layer 1022 to Si, the impact of the sacrificial layer 1021 removal process on the channel layer 1022 can be effectively reduced, thereby improving the quality of the channel layer 1022 and further improving device performance. In other embodiments, when forming a PMOS transistor, to improve the performance of the PMOS transistor, SiGe channel technology can be used, with the material of the fin and channel layer being SiGe and the material of the sacrificial layer being Si.

[0047] In this embodiment, the number of the channel stacks 102 is two. In other embodiments, the number of the channel stacks may be other.

[0048] In this embodiment, an isolation layer (not shown) is further formed on the substrate 100 at the side of the fin 101 , and the isolation layer exposes the channel stack 102 .

[0049] The isolation layer is used to isolate adjacent fins 101 .

[0050] In this embodiment, the material of the isolation layer is silicon oxide.

[0051] refer to Figure 2 A gate structure 104 is formed on the substrate 100 , spanning the channel stack 102 and the fin 101 . The gate structure 104 covers a portion of the top and a portion of the sidewall of the channel stack 102 .

[0052] In this embodiment, the gate structure 104 is a dummy gate structure, which occupies a space for a device gate structure to be formed later. In this embodiment, the gate structure 104 includes a dummy gate layer. The material of the dummy gate layer includes polysilicon.

[0053] In this embodiment, the steps of forming the gate structure 104 include: forming a gate material layer (not shown) on the channel stack 102; forming a gate mask layer 105 on the gate material layer; using the gate mask layer 105 as a mask, removing the gate material layer exposed by the gate mask layer 105, and the remaining gate material layer located on the channel stack 102 serves as the gate structure 104.

[0054] The gate mask layer 105 is used as an etching mask when forming the gate structure 104 . The gate mask layer 105 can also protect the top of the gate structure 104 in subsequent processes.

[0055] In this embodiment, the material of the gate mask layer 105 is silicon nitride.

[0056] In this embodiment, before forming the gate structure 104 , the method for forming the semiconductor structure further includes: forming a gate oxide layer 106 on the top surface of the channel stack 102 .

[0057] The gate oxide layer 106 is used to protect the channel stack 102 . The gate oxide layer 106 can also serve as a stop layer in the subsequent step of removing the gate structure 104 , thereby reducing damage to the channel stack 102 caused by the process of removing the gate structure 104 .

[0058] In this embodiment, the gate oxide layer 106 is made of silicon oxide.

[0059] In this embodiment, after forming the gate structure 104 , the method for forming the semiconductor structure further includes: forming a spacer 103 on a sidewall of the gate structure 104 .

[0060] The sidewall spacer 103 is used as an etching mask in a subsequent etching process to define the formation area of the source / drain doped layer. The sidewall spacer 103 is also used to protect the sidewall of the gate structure 104 .

[0061] In this embodiment, the sidewall spacer 103 is a single-layer structure, and the material of the sidewall spacer 103 is silicon nitride.

[0062] refer to Figures 3 to 7 , grooves 121 are formed in the channel stack 102 and the fin 101 on both sides of the gate structure 104 , and sidewalls of the grooves 121 expose the channel stack 102 and the fin 101 .

[0063] The groove 121 provides a space for the subsequent formation of source and drain doping layers.

[0064] It should be noted that the groove 121 described in this embodiment is not only formed in the channel stack 102, but also extends to the fin 101. Compared with the solution in which the groove is only located in the channel stack, the space of the groove described in this embodiment is larger, thereby increasing the volume of the subsequent source and drain doping layer, and correspondingly increasing the channel stress generated by the source and drain doping layer, thereby improving the electrical performance of the semiconductor.

[0065] In this embodiment, an anisotropic dry etching process is used to etch the channel stack 102 and the fin 101 on both sides of the gate structure 104 to form the groove 121. The anisotropic dry etching process has good profile controllability, which is conducive to improving the cross-sectional morphology quality of the groove 121. Moreover, the dry etching process has high process controllability, which is conducive to accurately controlling the depth of the groove. In addition, the selected anisotropic dry etching process is conducive to achieving a high etching selectivity, thereby reducing the probability of causing inadvertent etching of other film layers.

[0066] In this embodiment, the steps of forming the groove 121 include:

[0067] like Figure 3 As shown, first grooves 107 are formed in the channel stacks 102 on both sides of the gate structure 104 . The sidewalls of the first grooves 107 expose the channel stacks 102 , and the bottoms of the first grooves 107 expose the fins 101 .

[0068] The first groove 107 occupies space for the subsequent formation of source and drain doping layers. Moreover, by exposing the fin 101 at the bottom of the first groove 107 , preparation is made for the subsequent etching of the fin 101 at the bottom of the first groove 107 .

[0069] In this embodiment, the gate structure 104 and the sidewall spacer 103 are used as masks to etch the channel stack 102 to form the first groove 107 .

[0070] In this embodiment, a dry etching process, such as an anisotropic dry etching process, is used to etch the channel stacks 102 on both sides of the gate structure 104. The dry etching process has good profile controllability, which is beneficial for improving the cross-sectional morphology quality of the first groove 107. The dry etching process is also beneficial for achieving a high etching selectivity, thereby reducing the probability of inadvertent etching of other film layers.

[0071] Combined with reference Figure 4 In this embodiment, after forming the first groove 107, the method for forming the semiconductor structure further includes: laterally etching the portion of the sacrificial layer 1021 exposed on the sidewall of the first groove 107 in a direction parallel to the substrate 100 and perpendicular to the extension direction of the gate structure to form a third groove 108, wherein the third groove 108 is surrounded by the adjacent channel layer 1022 and the remaining sacrificial layer 1021, or the third groove 108 is surrounded by the fin 101, the channel layer 1022 adjacent to the fin 101, and the remaining sacrificial layer 1021.

[0072] The third groove 108 is used to provide a spatial position for the subsequent formation of an inner wall layer, so that after the source and drain doping layers are subsequently formed and the device gate structure is formed at the sacrificial layer position, the inner wall layer is located between the source and drain doping layers and the device gate structure. The inner wall layer can isolate the source and drain doping layers from the device gate structure, which is beneficial to increase the distance between the source and drain doping layers and the device gate structure, and further beneficial to reduce the parasitic capacitance between the source and drain doping layers and the device gate structure.

[0073] In this embodiment, third grooves 108 are formed between adjacent channel layers 1022 and between the channel layer 1022 and the fin 101 .

[0074] In this embodiment, a wet etching process is used to laterally etch the portion of the sacrificial layer 1021 exposed by the sidewalls of the first recess 107 to form the third recess 108. The wet etching process is an isotropic etching process, and thus can etch the sacrificial layer 1021 in a direction parallel to the substrate 100 and perpendicular to the extension direction of the gate structure. The wet etching process also easily achieves a large etching selectivity, which helps reduce the difficulty of etching the sacrificial layer 1021 and reduces the probability of damage to other film structures.

[0075] In this embodiment, the material of the sacrificial layer 1021 is SiGe, and the material of the channel layer 1022 is Si. The exposed sacrificial layer 1021 is wet-etched using HCl vapor. The etching rate of HCl vapor on SiGe is much higher than that on Si. Therefore, using HCl vapor to etch the portion of the sacrificial layer 1021 on the side of the first groove 107 can effectively reduce the probability of damage to the channel layer 1022.

[0076] In other embodiments, when the material of the channel layer is SiGe and the material of the sacrificial layer is Si, the etching solution used in the wet etching process is a tetramethylammonium hydroxide (TMAH) solution. The difference between the etching rate of the tetramethylammonium hydroxide solution on the Si material and the etching rate on the SiGe material is large. Therefore, using the tetramethylammonium hydroxide solution to etch the sacrificial layer can also effectively reduce the probability of channel layer loss.

[0077] like Figures 5 to 7 As shown, the fin 101 at the bottom of the first groove 107 is etched to form a second groove 111 in the fin 101 (as shown in FIG. Figure 7 ), the top of the second groove 111 is connected to the bottom of the first groove 107, and the second groove 111 and the first groove 107 are used to form the groove 121. In a direction parallel to the substrate 100 and perpendicular to the extension direction of the gate structure 104, the width of the second groove 111 is smaller than the width of the first groove 107, and the sidewalls of the second groove 111 are retracted inward relative to the sidewalls of the first groove.

[0078] The second groove 111 also occupies space for subsequently forming a source / drain doped layer.

[0079] It should be noted that, in the process of etching the fin to form the second groove 111, since the fin 101 is easily affected by the lateral etching rate, by controlling the width of the second groove 111 to be smaller than the width of the first groove 107 (that is, the sidewalls of the second groove 111 are retracted inward relative to the sidewalls of the first groove 107), when the semiconductor structure is working, the source and drain doping layers in the fin 101 are not easy to penetrate each other, thereby reducing the probability of short circuit between the source and drain doping layers, thereby improving the electrical performance of the semiconductor structure.

[0080] In this embodiment, in the step of etching the fin 101 at the bottom of the first groove 107 to form the second groove 111 , a partial thickness of the fin 101 is etched.

[0081] It should be noted that, in the process of etching the fin to form the second groove 111, since the fin 101 is easily affected by the lateral etching rate, by controlling the thickness of the etched portion of the fin 101, when the semiconductor structure is working, the source and drain doping layers in the fin 101 are not easy to penetrate each other, thereby reducing the probability of short circuit between the source and drain doping layers, thereby improving the electrical performance of the semiconductor structure.

[0082] In this embodiment, a dry etching process, for example, an anisotropic dry etching process, is used to etch the fin 101 at the bottom of the first groove 107 to form the second groove 111 .

[0083] It should be noted that in the step of forming the groove 121, the distance from the bottom of the groove 121 to the top of the fin 101 should not be too small or too large. If the distance from the bottom of the groove 121 to the top of the fin 101 is too small, it is easy to cause the space for the subsequent source and drain doping layers to be too small, and the volume of the source and drain doping layers is too small, which can easily lead to too small channel stress and difficulty in meeting process requirements, thereby affecting the electrical performance of the semiconductor; if the distance from the bottom of the groove 121 to the top of the fin 101 is too large, it is easy to increase the risk of punch-through between the source and drain doping layers, increasing the probability of short circuit between the source and drain doping layers, thereby affecting the electrical performance of the semiconductor. To this end, in this embodiment, the distance from the bottom of the groove 121 to the top of the fin 101 is 20nm to 60nm. For example, the distance from the bottom of the groove 121 to the top of the fin 101 is 20nm, 40nm or 60nm.

[0084] That is, the depth of the second groove 111 is 20 nm to 60 nm.

[0085] It should also be noted that, in conjunction with the reference Figures 5 and 6In this embodiment, after forming the first groove 107 and before etching the fin 101 at the bottom of the first groove 107, the method for forming the semiconductor structure further includes: forming a protective layer 110 on the sidewalls of the first groove 107 and the sidewalls of the gate structure.

[0086] By forming the protective layer 110, during the step of etching the partial thickness of the fin 101 at the bottom of the first groove 107, the protective layer 110 can protect the channel stack 102 on the side wall of the first groove 107, which is beneficial to reducing the probability of damage to the channel stack 102, especially reducing the probability of damage to the channel layer 1022.

[0087] In this embodiment, the protection layer 110 is also formed on the sidewalls of the gate structure 104 . The protection layer 110 on the sidewalls of the gate structure 104 can protect the sidewalls of the gate structure 104 during the step of etching the fin 101 at the bottom of the first groove 107 .

[0088] Moreover, in this embodiment, in the step of forming the protective layer 110, the protective layer 110 also fills the third groove 108. The protective layer 110 filled in the third groove 108 is used for the subsequent formation of the inner wall layer.

[0089] In addition, in this embodiment, during the subsequent etching of the fin 101 to form a second groove, the protection layer 110 also serves as an etching mask, so that the sidewalls of the second groove are retracted inwardly relative to the sidewalls of the first groove 107 .

[0090] The thickness of the protective layer 110 located on the sidewalls of the gate structure should not be too large or too small. If the thickness of the protective layer 110 located on the sidewalls of the gate structure is too large, in the subsequent step of etching the fin 101 using the protective layer as a hard mask to form a second groove, it is easy to cause the opening size of the second groove to be too small, thereby causing the volume of the source and drain doped layer to be too small, reducing the channel stress generated by the source and drain doped layer. At the same time, it will also cause the parasitic resistance between the subsequently formed device gate structure and the source and drain doped layer to increase, thereby affecting the electrical performance of the semiconductor. If the thickness of the protective layer 110 located on the sidewalls of the gate structure is too small, in the subsequent step of etching the fin 101 using the protective layer as a hard mask to form a second groove, it is easy to cause the second groove to be too large, thereby causing the volume of the source and drain doped layer to be too large, thereby increasing the probability of short circuit between the source and drain doped layers. At the same time, it will also cause the parasitic capacitance between the subsequently formed device gate structure and the source and drain doped layer to increase, thereby affecting the electrical performance of the semiconductor. For this reason, in this embodiment, the thickness of the protective layer is 2nm to 5nm.

[0091] Therefore, if Figure 7As shown, in this embodiment, the step of forming the second groove 111 includes: using the protection layer 110 as a mask, etching the fin 101 at the bottom of the first groove 107 to form the second groove 111 .

[0092] It should be noted that, in this embodiment, by forming the protective layer with the help of a subsequent process for forming the inner wall layer, the process steps can be reduced, the process cost can be lowered, and the process efficiency of the semiconductor can be improved.

[0093] In this embodiment, the material of the protective layer 110 is a dielectric material. The material of the protective layer 110 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material. In this embodiment, the material of the protective layer 110 is silicon nitride.

[0094] In this embodiment, the steps of forming the protective layer 110 include: Figure 5 As shown, a protective material layer 109 is formed on the sidewalls of the channel stack 102 exposed by the first groove 107, the sidewalls and top of the gate structure 104, and the surface of the fin 101 at the bottom of the first groove 107; Figure 6 As shown, the protection material layer 109 located on the top of the gate structure 104 and the surface of the fin 101 is removed, and the remaining protection material layer 109 located on the sidewall of the gate structure 104 and the sidewall of the channel stack 102 exposed by the first groove 107 serves as the protection layer 110.

[0095] The process for forming the protective material layer 109 includes an atomic layer deposition process or a chemical vapor deposition process, so that the protective material layer 109 can fill the third groove 108 and has conformal coverage. In this embodiment, the process for forming the protective material layer 109 is an atomic layer deposition process.

[0096] In this embodiment, a dry etching process, such as an anisotropic dry etching process, is used to remove the protective material layer 109 located on the top of the gate structure 104 and the surface of the fin 101. The anisotropic dry etching process has the characteristic of anisotropic etching, so that during the process of removing the protective material layer 109 located on the top of the gate structure 104 and the surface of the fin 101, the probability of causing lateral etching of the protective material layer 109 located on the sidewalls of the channel stack 102 is low, so that the protective material layer 109 located on the sidewalls of the channel stack 102 can be retained as the protected layer 110.

[0097] refer to Figure 8 After forming the second groove 111 , the formation of the semiconductor structure further includes: removing the protection layer 110 located on the sidewalls of the first groove 107 and the sidewalls of the gate structure.

[0098] By removing the protective layer 110 located on the sidewalls of the channel layer 1022, the sidewalls of the channel layer 1022 are exposed, preparing for the subsequent formation of source and drain doped layers in contact with the channel layer 1022. In this embodiment, the protective layer 110 located on the sidewalls of the channel layer 1022 is removed by an anisotropic dry etching process.

[0099] The anisotropic dry etching process has better profile controllability, which is beneficial to improving the quality of the profile morphology. By selecting the dry etching process, it is beneficial to achieve a higher etching selectivity, thereby reducing the probability of mis-etching other film layers.

[0100] In this embodiment, the protective layer 110 is also filled in the third groove 108. Therefore, in the step of removing the protective layer located on the sidewalls of the first groove 107 and the sidewalls of the gate structure 104, the remaining protective layer 110 filled in the third groove 108 is retained to serve as the inner wall layer 112.

[0101] In this embodiment, the process steps of removing the protection layer 110 located on the sidewalls of the channel layer 1022 and forming the inner wall layer 112 are integrated, which is beneficial to improving process integration and process compatibility.

[0102] After the source-drain doping layer is subsequently formed in the groove and the device gate structure is formed at the position of the sacrificial layer 1021, the inner wall layer 112 is located between the source-drain doping layer and the device gate structure, which can isolate the source-drain doping layer and the device gate structure and is beneficial to reducing the parasitic capacitance between the source-drain doping layer and the device gate structure.

[0103] It should be noted that, in this embodiment, in the step of removing the protection layer 110 located on the sidewalls of the channel layer 1022 , the protection layer 110 located on the sidewalls of the gate structure 104 is also removed.

[0104] refer to Figure 9 , a source-drain doped layer 113 is formed in the groove 121 .

[0105] In this embodiment, the source-drain doped layer 113 includes: a first source-drain doped layer 1131, located in the first groove 107; a second source-drain doped layer 1132, located in the second groove 111, and the side walls of the second source-drain doped layer 1132 are retracted inward relative to the side walls of the first source-drain doped layer 1131 in a direction parallel to the substrate 100 and perpendicular to the extension direction of the gate structure 104.

[0106] In this embodiment, the step of forming the source-drain doped layer 113 includes: forming a stress layer in the groove by using an epitaxial process, and in-situ self-doping ions to form the source-drain doped layer 113 during the process of forming the stress layer.

[0107] Among them, when the fully enclosed gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the source and drain doping layer 113 are P-type ions; when the fully enclosed gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SiC, and the doped ions in the source and drain doping layer 113 are N-type ions.

[0108] In this embodiment, the source-drain doping layer 113 covers the sidewalls of the channel layer 1022 and the inner wall layer 112 .

[0109] In this embodiment, the top surface of the source / drain doped layer 113 is higher than the top surface of the channel stack 102 and also covers part of the sidewall of the spacer 103. In other embodiments, the top surface of the source / drain doped layer 113 may also be flush with the top surface of the channel stack.

[0110] refer to Figure 10 An interlayer dielectric layer 114 is formed on top of the source / drain doped layer 113 , and the interlayer dielectric layer 114 covers the sidewalls of the gate structure 104 .

[0111] The interlayer dielectric layer 114 is used to achieve electrical isolation between adjacent devices.

[0112] In this embodiment, the material of the interlayer dielectric layer 114 is silicon oxide.

[0113] In this embodiment, the steps of forming the interlayer dielectric layer 114 include: forming a dielectric material layer (not shown) on the substrate of the sidewall of the gate structure 104, and the dielectric material layer also covers the top of the gate structure 104; removing the dielectric material layer above the top of the gate structure 104, and the remaining dielectric material layer serves as the interlayer dielectric layer 114.

[0114] refer to Figure 11 After the interlayer dielectric layer 114 is formed, subsequent process steps also include: removing the gate structure 104 and forming a gate opening 115 in the interlayer dielectric layer 114; removing the sacrificial layer 1021 exposed by the gate opening 115, and forming a through groove 116 connected to the gate opening 115 under the channel layer 1022; the through groove 116 is surrounded by the fin and the channel layer 1022, or the through groove 116 is surrounded by the adjacent channel layer 1022 and the source-drain doped layer 113, and the through groove 116 is connected to the gate opening 115.

[0115] Specifically, the gate structure 104 and the gate oxide layer 106 located at the bottom of the gate structure 104 are removed, and a gate opening 115 is formed in the interlayer dielectric layer 114 to expose part of the top and part of the sidewall of the channel stack 102; the sacrificial layer 1021 in the channel stack 102 is removed to form a through groove 116, which is surrounded by the fin and the channel layer 1022, or the through groove 116 is surrounded by the adjacent channel layer 1022 and the source-drain doped layer 113, and the through groove 116 is connected to the gate opening 115.

[0116] The gate opening 115 and the through-groove 116 are used to provide a space for the subsequent formation of a device gate structure.

[0117] In this embodiment, a dry etching process is used to remove the gate structure 104 and the gate oxide layer 125 located at the bottom of the gate structure 104 .

[0118] In this embodiment, before removing the gate structure 104 , the method for forming the semiconductor structure further includes removing the gate mask layer 105 . The gate mask layer 105 is removed to expose the top of the gate structure 104 , preparing for removing the gate structure 104 .

[0119] In this embodiment, a wet etching process is used to remove the sacrificial layer 1021. Specifically, the material of the channel layer 1022 is Si, and the material of the sacrificial layer 1021 is SiGe. Therefore, the sacrificial layer 1021 exposed by the gate opening 115 is removed by HCl vapor. The wet etching process has a much higher etching rate for the sacrificial layer 1021 than for the channel layer 1022 and the fin 101.

[0120] The sacrificial layer 1021 is removed after the source and drain doped layer 113 is formed. Therefore, after removing the sacrificial layer 1021, the two ends of the channel layer 1022 are connected to the source and drain doped layer 113 along the extension direction of the fin 101 and are suspended in the gate opening 115, thereby providing a basis for the subsequent device gate structure to surround the channel layer 1022.

[0121] After the sacrificial layer 1021 is removed, the channel layers 1022 are spaced apart, and the remaining channel layers 1022 constitute the channel structure layer 130 . The channel structure layer 130 is located on the fin 101 and spaced apart from the fin 101 .

[0122] refer to Figure 12 A device gate structure 118 is formed in the gate opening 115 and the through-groove 116 , and the gate structure 118 surrounds the channel layer 1022 .

[0123] The device gate structure 118 is used to control the opening and closing of the conductive channel when the device is in operation.

[0124] Specifically, the device gate structure 118 is a metal gate structure 118 .

[0125] The gate opening 115 is connected to the through-trench 116 . Therefore, during the process of forming the device gate structure 118 in the gate opening 115 , the device gate structure 118 is also filled in the through-trench 116 .

[0126] Specifically, the device gate structure 118 spans the channel structure layer 130 and covers a portion of the top of the channel structure layer 130. The device gate structure 118 also surrounds the channel layer 1022. The device gate structure 118 located in the through-trench 116 is a first portion (not labeled), and the device gate structure 118 located in the gate opening 115 is a second portion (not labeled).

[0127] The device gate structure 118 includes a high-k gate dielectric layer (not shown) and a metal gate electrode layer (not shown) located on the high-k gate dielectric layer. Specifically, the high-k gate dielectric layer is located on the upper surface, lower surface, and side surfaces of the channel layer 1022 and also covers a portion of the top and sidewalls of the fin 1022.

[0128] In this embodiment, the material of the high-k gate dielectric layer is HfO 2 .

[0129] In this embodiment, the material of the metal gate electrode layer is W.

[0130] The device gate structure may further include other functional layers, such as a work function layer.

[0131] Accordingly, the present invention also provides a semiconductor structure. Figure 12 , showing a structural schematic diagram of an embodiment of a semiconductor structure of the present invention.

[0132] The semiconductor structure includes: a base (not shown), the base including a substrate 100 and a fin 101 protruding from the substrate 100; a channel structure layer 130, located on the fin 101 and spaced apart from the fin 101, the channel structure layer 130 including one or more spaced apart channel layers 1022; a device gate structure 118, spanning the fin 101 and the channel structure layer 130 and surrounding the channel layer 1022; a source-drain doped layer 113, located in the channel layer 1022 and the fin 101 on both sides of the device gate structure 118; and an interlayer dielectric layer 114, located on top of the source-drain doped layer 113 and covering the sidewalls of the device gate structure 118.

[0133] The substrate is used to provide a process platform for forming gate-all-around (GAA) transistors.

[0134] In this embodiment, the substrate is a three-dimensional substrate, which includes a substrate 100 and a fin 101 protruding from the substrate 100 .

[0135] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0136] The fin 101 exposes a portion of the substrate 100 , thereby providing a process basis for forming an isolation layer.

[0137] In this embodiment, the fin 101 is made of the same material as the substrate 100, that is, silicon. In other embodiments, the fin 101 may be made of a semiconductor material suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The fin may also be made of a different material than the substrate.

[0138] Each channel structure layer 130 includes one or more channel layers 1022 disposed at intervals.

[0139] In this embodiment, the channel structure layer 130 includes a plurality of spaced channel layers 1022, and the stacking direction of the plurality of stacked channel layers 1022 is perpendicular to the surface of the substrate 100. In this embodiment, the number of channel layers 1022 is two. In other embodiments, the number of channel layers may not be limited to two.

[0140] In this embodiment, the channel structure layer 130 and the fin 110 are made of the same material, that is, Si.

[0141] The device gate structure 118 is used to control the opening and closing of the conductive channel when the device is in operation.

[0142] Specifically, the device gate structure 118 is a metal gate structure.

[0143] The device gate structure 118 includes a high-k gate dielectric layer (not shown) and a metal gate electrode layer (not shown) located on the high-k gate dielectric layer. Specifically, the high-k gate dielectric layer is located on the upper surface, lower surface, and side surfaces of the channel layer 1022 and also covers a portion of the top and sidewalls of the fin 1022.

[0144] In this embodiment, the material of the high-k gate dielectric layer is HfO 2 .

[0145] In this embodiment, the material of the metal gate electrode layer is W.

[0146] In this embodiment, the device gate structure 118 located directly below the channel layer 1022 serves as the first portion (not labeled), and the remaining device gate structure 118 serves as the second portion (not labeled).

[0147] It should be noted that, in this embodiment, along a direction parallel to the substrate 100 and perpendicular to the extension direction of the device gate structure 118 , the sidewall of the device gate structure 118 located directly below the channel layer 1022 is retracted inward relative to the sidewall of the channel layer 1022 .

[0148] It should also be noted that, in some other embodiments, the device gate structure may also be a polysilicon gate structure. In other embodiments, the device gate structure may also refer to a dummy gate structure.

[0149] The semiconductor structure further includes a sidewall spacer 103 located on a sidewall of the device gate structure 118. Specifically, the sidewall spacer 103 is located on a sidewall of the second portion.

[0150] In this embodiment, the sidewall spacer 103 is a single-layer structure, and the material of the sidewall spacer 103 is silicon nitride.

[0151] In this embodiment, the device gate structure 118 is formed by a process of forming a high-k gate dielectric layer and then forming a metal gate electrode (Highk last metal gate last), and before forming the device gate structure 118, the device gate structure used is a stacked structure, so the semiconductor structure also includes: a gate oxide layer 106 located between the side wall 103 and the channel structure layer 130.

[0152] In this embodiment, the gate oxide layer 106 is made of silicon oxide.

[0153] In this embodiment, the source-drain doped layer 113 is located in the channel structure layer 130 and the fin 101 on both sides of the gate structure 118 .

[0154] Among them, when the fully enclosed gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the source and drain doping layer 113 are P-type ions; when the fully enclosed gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SiC, and the doped ions in the source and drain doping layer 113 are N-type ions.

[0155] In this embodiment, the top surface of the source / drain doped layer 113 is higher than the top surface of the channel stack 102 and also covers part of the sidewall of the spacer 103. In other embodiments, the top surface of the source / drain doped layer 113 may also be flush with the top surface of the channel stack.

[0156] In this embodiment, the source-drain doped layer 113 is located in a partial thickness of the fin 101 .

[0157] It should be noted that, during the process of forming the source-drain doped layer 113, since the fin 101 is easily affected by the lateral etching rate, the source-drain doped layer 113 is located in a partial thickness of the fin 101. The source-drain doped layers in the fin 101 are not easy to penetrate each other, which reduces the probability of short circuit between the source-drain doped layers, thereby improving the electrical performance of the semiconductor structure.

[0158] In this embodiment, the source-drain doping layer 113 includes: a first source-drain doping layer 1131, located in the channel structure layer 130 on both sides of the device gate structure 118; a second source-drain doping layer 1132, located in the fin 101 at the bottom of the first source-drain doping layer 1131, and the side walls of the second source-drain doping layer 1132 are retracted inward relative to the side walls of the first source-drain doping layer 1131 in a direction parallel to the substrate 100 and perpendicular to the extension direction of the device gate structure 118.

[0159] It should be noted that the side walls of the second source-drain doped layer 1132 are retracted inward relative to the side walls of the first source-drain doped layer 1131, thereby increasing the distance between adjacent second source-drain doped layers 1132 in the direction parallel to the substrate surface, making it difficult for the second source-drain doped layers 1132 in the fin 101 to penetrate each other, reducing the probability of short circuit between the source-drain doped layers 113, and thus improving the electrical performance of the semiconductor structure.

[0160] In this embodiment, the sidewalls of the second source / drain doped layer 1132 are retracted inwardly by 2 nm to 5 nm relative to the sidewalls of the first source / drain doped layer 1131 .

[0161] It should be noted that the distance by which the sidewalls of the second source / drain doped layer 1132 are indented relative to the sidewalls of the first source / drain doped layer 1131 should not be too small or too large. If the distance by which the sidewalls of the second source / drain doped layer 1132 are indented relative to the sidewalls of the first source / drain doped layer 1131 is too small, it is easy to cause the source / drain doped layer 113 to be too large, which can easily increase the probability of short circuit between the source / drain doped layers 113. It can also cause the parasitic capacitance between the back-device gate structure 118 and the source / drain doped layer 113 to increase, thereby affecting the electrical performance of the semiconductor. If the distance by which the sidewalls of the second source / drain doped layer 1132 are indented relative to the sidewalls of the first source / drain doped layer 1131 is too large, it can easily cause the source / drain doped layer 113 to be too small, which can reduce the channel stress generated by the source / drain doped layer 113. It can also cause the parasitic resistance between the device gate structure 118 and the source / drain doped layer 113 to increase, thereby affecting the electrical performance of the semiconductor.

[0162] In this embodiment, the distance from the bottom of the source / drain doping layer 113 to the top of the fin 101 is 20 nm to 60 nm.

[0163] It should be noted that the distance from the bottom of the source-drain doped layer 113 to the top of the fin 101 should not be too large or too small. If the distance from the bottom of the source-drain doped layer 113 to the top of the fin 101 is too large, it is easy to increase the risk of punch-through of the source-drain doped layer 113 and the probability of short circuit between the source-drain doped layers 113, thereby affecting the electrical performance of the semiconductor. If the distance from the bottom of the source-drain doped layer 113 to the top of the fin 101 is too small, it is easy to cause the volume of the source-drain doped layer 113 to be too small, which in turn easily leads to too small channel stress, making it difficult to meet process requirements, thereby affecting the electrical performance of the semiconductor.

[0164] In this embodiment, the semiconductor structure also includes: an inner wall layer 112, located between the side wall of the device gate structure 118 directly below the channel layer 1022 and the source-drain doped layer 113, that is, the inner wall layer 112 is located between the side wall of the first part and the source-drain doped layer 113.

[0165] The inner wall layer 112 serves as an inner sidewall, which increases the distance between the device gate structure 118 and the source / drain doped layer 113 , and is beneficial to reducing the parasitic capacitance between the device gate structure 118 and the source / drain doped layer 113 .

[0166] In this embodiment, the material of the inner wall layer 170 is silicon nitride.

[0167] The semiconductor structure further includes an interlayer dielectric layer 114 located on top of the source / drain doped layer 113 and covering the sidewalls of the device gate structure 118. The interlayer dielectric layer 114 is used to achieve electrical isolation between adjacent devices.

[0168] In this embodiment, the material of the interlayer dielectric layer 114 is silicon oxide.

[0169] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0170] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a base, the base comprising a substrate and a fin protruding from the substrate; a channel structure layer, located on the fin portion and spaced apart from the fin portion, the channel structure layer comprising one or more spaced apart channel layers; a device gate structure, spanning the fin and the channel structure layer and surrounding the channel layer; Source-drain doped layers are located in the channel structure layer and the fin on both sides of the device gate structure, the source-drain doped layers comprising: a first source-drain doped layer is located in the channel structure layer on both sides of the device gate structure; a second source-drain doped layer is located in the fin at the bottom of the first source-drain doped layer, sidewalls of the second source-drain doped layer are retracted inward relative to sidewalls of the first source-drain doped layer in a direction parallel to the substrate and perpendicular to the extension direction of the device gate structure, and a bottom width of the first source-drain doped layer is greater than a top width of the second source-drain doped layer; The interlayer dielectric layer is located on top of the source-drain doped layer and covers the sidewalls of the device gate structure.

2. The semiconductor structure according to claim 1, wherein Along a direction parallel to the substrate and perpendicular to the extension direction of the device gate structure, a sidewall of the device gate structure directly below the channel layer is retracted inwardly relative to a sidewall of the channel layer; The semiconductor structure further includes an inner wall layer located between the sidewall of the device gate structure directly below the channel layer and the source / drain doping layer.

3. The semiconductor structure according to claim 1, wherein: The sidewall of the second source / drain doped layer is retracted inward by 2 nm to 5 nm relative to the sidewall of the first source / drain doped layer.

4. The semiconductor structure according to claim 1, wherein: The device gate structure is a metal gate structure.

5. The semiconductor structure according to claim 1, wherein The source-drain doping layer is located in a partial thickness of the fin.

6. The semiconductor structure according to claim 1, wherein The distance from the bottom of the source / drain doping layer to the top of the fin is 20 nm to 60 nm.

7. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate and a fin protruding from the substrate, one or more stacked channel stacks formed on the fin, each of the channel stacks comprising a sacrificial layer and a channel layer located on the sacrificial layer; forming a gate structure across the channel stack and the fin on the substrate, wherein the gate structure covers a portion of the top and a portion of the sidewall of the channel stack; Recesses are formed in the channel stacks and fins on both sides of the gate structure, with sidewalls of the recesses exposing the channel stacks and the fins, the steps of forming the recesses comprising: forming first recesses in the channel stacks on both sides of the gate structure, with sidewalls of the first recess exposing the channel stacks and a bottom of the first recess exposing the fins; etching the fins at the bottom of the first recesses to form second recesses in the fins, with a top of the second recess communicating with a bottom of the first recess, the second recess and the first recess constituting the recess, a width of the second recess being smaller than a width of the first recess in a direction parallel to the substrate and perpendicular to an extension direction of the gate structure, a sidewall of the second recess being indented inwardly relative to a sidewall of the first recess, and a top surface width of the second recess being smaller than a bottom surface width of the first recess; A source-drain doping layer is formed in the groove.

8. The method for forming a semiconductor structure according to claim 7, wherein: The recess is formed in the channel stack on both sides of the gate structure and in a partial thickness of the fin.

9. The method for forming a semiconductor structure according to claim 7, wherein: After forming the first groove and before etching the fin at the bottom of the first groove, the method for forming the semiconductor structure further includes: forming a protection layer on the sidewalls of the first groove and the sidewalls of the gate structure; The step of forming the second groove includes: using the protective layer as a mask, etching a fin portion having a partial thickness at the bottom of the first groove to form the second groove; After forming the second groove and before forming the source / drain doped layer, the method for forming the semiconductor structure further includes: removing the protection layer located on the sidewalls of the first groove and the sidewalls of the gate structure.

10. The method for forming a semiconductor structure according to claim 9, wherein: After forming the first groove and before forming the protection layer, the method for forming the semiconductor structure further includes: laterally etching a portion of the sacrificial layer exposed by a sidewall of the first groove in a direction parallel to the substrate and perpendicular to an extension direction of the gate structure to form a third groove, wherein the third groove is surrounded by the adjacent channel layer and the remaining sacrificial layer, or the third groove is surrounded by the fin, the channel layer adjacent to the fin, and the remaining sacrificial layer; In the step of forming the protective layer, the protective layer also fills the third groove; In the step of removing the protection layer located on the sidewalls of the first groove and the sidewalls of the gate structure, the remaining protection layer filling the third groove is retained to serve as an inner wall layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The step of removing the protection layer located on the sidewalls of the first groove and the sidewalls of the gate structure includes: etching the protection layer using an anisotropic dry etching process.

12. The method for forming a semiconductor structure according to claim 9, wherein: The steps of forming the protective layer include: forming a protective material layer on the sidewalls of the channel stack exposed by the first groove, the sidewalls and top of the gate structure, and the fin surface at the bottom of the first groove; removing the protective material layer located on the top of the gate structure and the fin surface, and using the protective material layer located on the sidewalls of the gate structure and the sidewalls of the channel stack exposed by the first groove as the protective layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The process of forming the protective material layer includes an atomic layer deposition process or a chemical vapor deposition process.

14. The method for forming a semiconductor structure according to claim 7, wherein: The channel stack and the fins on both sides of the gate structure are etched using an anisotropic dry etching process to form the groove.

15. The method for forming a semiconductor structure according to claim 7, wherein: In the step of forming the groove, a distance from a bottom of the groove to a top of the fin is 20 nm to 60 nm.

16. The method for forming a semiconductor structure according to claim 9, wherein: In the step of forming the protection layer, the thickness of the protection layer located on the sidewall of the gate structure is 2 nm to 5 nm.

17. The method for forming a semiconductor structure according to claim 7, wherein: An epitaxial process is adopted to form a source-drain doping layer in the groove.

18. The method for forming a semiconductor structure according to claim 7, wherein: After forming the source-drain doped layer, the forming method further comprises: forming an interlayer dielectric layer on top of the source-drain doped layer, wherein the interlayer dielectric layer covers the sidewalls of the gate structure; removing the gate structure and forming a gate opening in the interlayer dielectric layer; removing the sacrificial layer exposed by the gate opening, and forming a through groove communicating with the gate opening below the channel layer; A device gate structure is formed in the gate opening and the through-groove, and the device gate structure surrounds the channel layer.

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