Optical proximity correction method, mask manufacturing and semiconductor structure forming method

Abstract

An optical proximity correction method, mask production and semiconductor structure formation method, comprising: providing a first target layout, wherein the first target layout includes a first target pattern and a second target pattern; obtaining a first exposure image, wherein the first exposure image includes a first exposure pattern and a second exposure pattern; detecting the first exposure image according to the first target layout to obtain a first defect pattern and a second defect pattern; obtaining a compensation size according to the first defect pattern and the second defect pattern; compensating and correcting the first target layout according to the compensation size to obtain a second target layout. Since the pattern in the obtained second target layout has been compensated and corrected, the deviation of the pattern position caused by the mutual attraction between the first target pattern and the second target pattern can be reduced, thereby improving the effect of the corrected pattern, and thus improving the performance of the semiconductor structure finally formed by the second target layout.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an optical proximity correction method, a mask manufacturing method and a semiconductor structure forming method. Background Art

[0002] Photolithography is a crucial technology in semiconductor manufacturing. It can transfer patterns from masks to the surface of silicon wafers to form semiconductor products that meet design requirements. However, existing photolithography technology is often accompanied by optical proximity effect.

[0003] In order to correct the optical proximity effect, optical proximity correction (OPC) was created. The core idea of ​​optical proximity correction is to establish an optical proximity correction model based on the consideration of offsetting the optical proximity effect, and to design the photomask pattern according to the optical proximity correction model. In this way, although the optical proximity effect occurs in the photolithography pattern corresponding to the photomask pattern after photolithography, since the offset of this phenomenon has been considered when designing the photomask pattern according to the optical proximity correction model, the photolithography pattern after photolithography is close to the target pattern that the user actually wants to obtain.

[0004] However, the yield of the semiconductor structure formed by the mask after optical proximity correction in the prior art still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide an optical proximity correction method, a mask manufacturing method and a semiconductor structure forming method, which can effectively improve the performance of the finally formed semiconductor structure.

[0006] To solve the above problems, the present invention provides an optical proximity correction method, comprising: providing a first target layout, wherein the first target layout includes a plurality of first target patterns and a plurality of second target patterns arranged in parallel along a first direction; acquiring a first exposure image according to the first target layout, wherein the first exposure image includes a plurality of first exposure patterns and a plurality of second exposure patterns, wherein the first exposure pattern corresponds to the first target pattern, and the second exposure pattern corresponds to the second target pattern; detecting the first exposure image according to the first target layout, acquiring a first defect pattern in the plurality of first exposure patterns, and acquiring a second defect pattern in the plurality of second exposure patterns, wherein the first defect pattern and the second defect pattern are adjacent to each other, and the first defect pattern and the second defect pattern have defects; acquiring a compensation size according to the first defect pattern and the second defect pattern; and compensating and correcting the first target layout according to the compensation size to acquire a second target layout.

[0007] Optionally, the method for acquiring the first exposure image includes: performing optical proximity correction processing on the first target layout several times to acquire a first optical proximity correction layout; and performing simulated exposure processing on the first optical proximity correction layout to acquire the first exposure image.

[0008] Optionally, the method for obtaining the first exposure image includes: performing optical proximity correction processing on the first target layout several times to obtain a first optical proximity correction layout; providing a substrate; performing a patterning process on the substrate according to the first optical proximity correction layout to form a semiconductor structure; and performing actual exposure processing on the semiconductor structure to obtain the first exposure image.

[0009] Optionally, both the first target graphic and the second target graphic extend along a second direction, the first direction is perpendicular to the second direction, and a length dimension of the second target graphic is greater than a length dimension of the first target graphic, and the length dimension is along the second direction.

[0010] Optionally, the method for obtaining adjacent first defect patterns and second defect patterns includes: obtaining a number of first target spacings between adjacent first target patterns and second target patterns in the first target layout; obtaining a number of first measurement spacings between adjacent first exposure patterns and second exposure patterns corresponding to the adjacent first target patterns and the second target patterns in the first exposure image, the first measurement spacings being equal in number and corresponding one-to-one to the first target spacings; comparing the corresponding first target spacings with the first measurement spacings, and if there are one or more of the first measurement spacings that are smaller than the corresponding first target spacings, the corresponding first exposure pattern and the second exposure pattern are the first defect pattern and the second defect pattern.

[0011] Optionally, the method for obtaining several first target spacings between adjacent first target graphics and second target graphics in the first target layout includes: virtually extending the first target graphics along the second direction until the length of the first target graphics is equal to the length of the adjacent second target graphics, thereby obtaining a virtual first target graphics; dividing the adjacent virtual first target graphics and the second target graphics into several first segments along the second direction, and the several first segments are marked with serial numbers from 1 to N along the second direction, where N is a natural number and N≥2; obtaining the distance between adjacent first segments with the same serial number as the first target spacing, and using the serial number as the serial number of the first target spacing.

[0012] Optionally, the method for obtaining a plurality of first measurement intervals between adjacent first exposure patterns and second exposure patterns in the first exposure image includes: virtually extending the first exposure pattern along the second direction until the length dimension of the first exposure pattern is equal to the length dimension of the adjacent second exposure pattern, thereby obtaining a virtual first exposure pattern; dividing the adjacent virtual first exposure pattern and the second exposure pattern into a plurality of second segments along the second direction, and the plurality of second segments are marked with serial numbers from 1 to N along the second direction, where N is a natural number and N≥2; obtaining a distance between adjacent second segments having the same serial number as the first measurement interval, and using the serial number as the serial number of the first measurement interval.

[0013] Optionally, the method for obtaining the compensation size based on the first defect pattern and the second defect pattern includes: comparing the first target spacing with the first measurement spacing having the same serial number, and obtaining one or more defect measurement spacings that are smaller than the corresponding first target spacing from a number of the first measurement spacings; and using the difference in size between the first target spacing with the same serial number and the defect measurement spacing as the compensation size.

[0014] Optionally, the first target layout is compensated and corrected according to the compensation size, and the method for obtaining the second target layout includes: obtaining the first target pattern and the second target pattern corresponding to the first defect pattern and the second defect pattern; obtaining the second segment of the second exposure pattern corresponding to the defect measurement interval; obtaining the first segment of the second target pattern corresponding to the second segment of the second exposure pattern; translating the obtained first segment by the compensation size in a direction away from the first target pattern to obtain the second target layout.

[0015] Correspondingly, the present invention also provides a method for manufacturing a mask, comprising: providing a first target layout, wherein the first target layout includes a plurality of first target graphics and a plurality of second target graphics arranged in parallel along a first direction; obtaining a first exposure image according to the first target layout, wherein the first exposure image includes a plurality of first exposure graphics and a plurality of second exposure graphics, wherein the first exposure graphics corresponds to the first target graphics, and the second exposure graphics corresponds to the second target graphics; detecting the first exposure image according to the first target layout, obtaining a first defect graphic in the plurality of first exposure graphics, and obtaining a second defect graphic in the plurality of second exposure graphics, wherein the first defect graphic and the second defect graphic are adjacent to each other, and the first defect graphic and the second defect graphic have defects; obtaining a compensation size according to the first defect graphic and the second defect graphic; performing compensation correction on the first target layout according to the compensation size to obtain a second target layout; performing optical proximity correction processing on the second target layout several times to obtain a second optical proximity correction layout; and manufacturing the mask according to the second optical proximity correction layout.

[0016] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a device layer on the substrate; providing a first target layout, wherein the first target layout includes a plurality of first target graphics and a plurality of second target graphics arranged in parallel along a first direction; obtaining a first exposure image according to the first target layout, wherein the first exposure image includes a plurality of first exposure graphics and a plurality of second exposure graphics, wherein the first exposure graphics corresponds to the first target graphics, and the second exposure graphics corresponds to the second target graphics; detecting the first exposure image according to the first target layout, obtaining a first defect graphic in the plurality of first exposure graphics, and obtaining a second defect graphic in the plurality of second exposure graphics, wherein the first defect graphic and the second defect graphic are adjacent to each other, and the first defect graphic and the second defect graphic have defects; obtaining a compensation size according to the first defect graphic and the second defect graphic; compensating and correcting the first target layout according to the compensation size to obtain a second target layout; performing optical proximity correction processing on the second target layout several times to obtain a second optical proximity correction layout; making the mask according to the second optical proximity correction layout; performing a patterning process on the device layer using the mask as a mask to form the semiconductor structure.

[0017] Optionally, the base includes: a substrate and a plurality of mutually discrete fins located on the substrate.

[0018] Optionally, the device layer includes a plurality of initial dummy gate structures arranged in parallel along a second direction, the first direction is perpendicular to the second direction, and the initial dummy gate structures span the fin.

[0019] Optionally, the initial dummy gate structure is patterned using the mask plate as a mask to form a dummy gate structure and an isolation opening within the dummy gate structure.

[0020] Optionally, after forming the dummy gate structure and the isolation opening, the method further includes: removing the dummy gate structure to form a gate opening; and forming a gate dielectric layer and a gate layer located on the gate dielectric layer in the gate opening.

[0021] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0022] In the optical proximity correction method of the technical solution of the present invention, the first exposure pattern is detected according to the first target layout to obtain the first defect pattern and the second defect pattern adjacent to each other in the first exposure image; the compensation size is obtained according to the first defect pattern and the second defect pattern; the first target layout is compensated and corrected according to the compensation size to obtain the second target layout. Since the pattern in the obtained second target layout has been compensated and corrected, the deviation of the pattern position caused by the mutual attraction between the first target pattern and the second target pattern can be reduced, the effect of the corrected pattern is improved, and then the performance of the semiconductor structure finally formed by the second target layout is improved.

[0023] In the method for making a mask of the technical solution of the present invention, the second target layout is subjected to optical proximity correction processing for several times to obtain a second optical proximity correction layout; the mask is made according to the second optical proximity correction layout. Since the mask is made based on the second target layout, the performance of the semiconductor structure finally formed by the mask can be improved.

[0024] In the method for forming a semiconductor structure of the technical solution of the present invention, the semiconductor structure is formed by the mask plate, which can effectively reduce the offset of the isolation opening formed in the pseudo gate structure, so that there is a larger distance between the cut-off point of the pseudo gate structure and the fin, and then the gate opening formed subsequently is convenient for filling with gate dielectric material, thereby improving the performance of the semiconductor structure finally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of a figure to be corrected in an optical proximity correction method;

[0026] Figure 2 It is a schematic diagram of an exposure pattern in an optical proximity correction method;

[0027] Figure 3 is a flow chart of an optical proximity correction method according to an embodiment of the present invention;

[0028] Figures 4 to 10 It is a schematic diagram of the structures of each step in an embodiment of an optical proximity correction method of the present invention;

[0029] Figure 10 to Figure 11 It is a schematic diagram of the structures of each step in an embodiment of a method for making a mask according to the present invention;

[0030] Figures 12 to 15 It is a schematic diagram of the structures of each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0031] As described in the background art, the graphic effect after optical proximity correction in the prior art still needs to be improved.

[0032] The existing optical proximity correction process is: providing a target layout; performing optical proximity correction processing on the target layout several times to obtain an optical proximity correction layout; performing simulated exposure processing on the optical proximity correction layout to obtain an exposure image. When the exposure image meets the expected placement edge error (EPE), it is considered that the acquired exposure image meets the requirements, and a mask is made using the optical proximity correction layout.

[0033] However, the target layout (such as Figure 1 As shown in FIG. 1 , during the optical proximity correction, since the target layout has long cut-off patterns 100 (long bars) and short cut-off patterns 101 (short bars), the short cut-off patterns 101 will attract the long cut-off patterns 100 to a certain extent during the optical proximity correction, so that the long exposure cut-off patterns 200 obtained after the exposure processing will be close to the short exposure cut-off patterns 201 (as shown in FIG. 1 ). Figure 2 As shown, the spacing d1 between the cut-off point of the pseudo gate structure formed by the attracted long exposure cut-off pattern 200 and the fin is smaller, and the corresponding gate opening formed when the pseudo gate structure is subsequently removed is also smaller. When the gate opening is smaller, it is not conducive to the filling of the gate dielectric material, resulting in a decrease in the performance of the semiconductor structure finally formed.

[0034] On this basis, the present invention provides an optical proximity correction method, mask production and semiconductor structure formation method, wherein the first exposure pattern is detected according to the first target layout, and the first defect pattern and the second defect pattern adjacent to each other in the first exposure image are obtained; the compensation size is obtained according to the first defect pattern and the second defect pattern; the first target layout is compensated and corrected according to the compensation size to obtain the second target layout. Since the pattern in the obtained second target layout has been compensated and corrected, the deviation of the pattern position caused by the mutual attraction between the first target pattern and the second target pattern can be reduced, the effect of the corrected pattern is improved, and then the performance of the semiconductor structure finally formed by the second target layout is improved.

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figure 3 : is a flow chart of an optical proximity correction method according to an embodiment of the present invention, comprising:

[0037] S21, providing a first target layout, wherein the first target layout includes a plurality of first target graphics and a plurality of second target graphics arranged in parallel along a first direction.

[0038] S22, acquiring a first exposure image according to the first target layout, wherein the first exposure image includes a plurality of first exposure patterns and a plurality of second exposure patterns, the first exposure patterns correspond to the first target patterns, and the second exposure patterns correspond to the second target patterns.

[0039] S23, detecting the first exposure image according to the first target layout, obtaining a first defect pattern in a number of the first exposure patterns, and obtaining a second defect pattern in a number of the second exposure patterns, wherein the first defect pattern and the second defect pattern are adjacent to each other, and the first defect pattern and the second defect pattern have defects.

[0040] S24, obtaining a compensation size according to the first defect pattern and the second defect pattern.

[0041] S25, performing compensation correction on the first target layout according to the compensation size to obtain a second target layout.

[0042] The steps of the optical proximity correction method are described in detail below with reference to the accompanying drawings.

[0043] Figures 4 to 10 , is a schematic structural diagram of each step of an optical proximity correction method according to an embodiment of the present invention.

[0044] Please refer to Figure 4, providing a first target layout 300, wherein the first target layout 300 includes a plurality of first target graphics 301 and a plurality of second target graphics 302 arranged in parallel along a first direction X.

[0045] In this embodiment, the first target pattern 301 and the second target pattern 302 are targets of optical proximity correction, that is, in an ideal state, the isolation opening subsequently formed on the wafer is consistent with the first target pattern 301 and the second target pattern 302 in the first target layout 300 .

[0046] It should be noted that although the ideal partition opening is a rectangular strip, due to the existence of the optical proximity effect, the partition opening finally formed on the wafer cannot be a regular rectangular strip, and there may be a problem of deformation and displacement of some adjacent partition openings.

[0047] In this embodiment, the first target graphic 301 and the second target graphic 302 both extend along the second direction Y, the first direction X is perpendicular to the second direction Y, and the length dimension L1 of the second target graphic 302 is greater than the length dimension L2 of the first target graphic 201, and the length dimension is along the second direction Y.

[0048] Please refer to Figure 5 , a first exposure image 400 is obtained according to the first target layout 300, wherein the first exposure image 400 includes a plurality of first exposure patterns 401 and a plurality of second exposure patterns 402, wherein the first exposure patterns 401 correspond to the first target pattern 301, and the second exposure patterns 402 correspond to the second target pattern 302.

[0049] In this embodiment, the method for obtaining the first exposure image 400 includes: performing optical proximity correction processing on the first target layout 300 for several times to obtain a first optical proximity correction layout (not shown); performing simulated exposure processing on the first optical proximity correction layout to obtain the first exposure image 400.

[0050] In other embodiments, the method for obtaining the first exposure image may further include: performing optical proximity correction processing on the first target layout several times to obtain a first optical proximity correction layout; providing a substrate; performing a patterning process on the substrate according to the first optical proximity correction layout to form a semiconductor structure; and performing actual exposure processing on the semiconductor structure to obtain the first exposure image.

[0051] After acquiring the first target layout 300 and the first exposure image 400, the first exposure image 400 is detected according to the first target layout 300, a first defect pattern is acquired from a plurality of first exposure patterns 401, and a second defect pattern is acquired from a plurality of second exposure patterns 402, wherein the first defect pattern and the second defect pattern are adjacent to each other, and the first defect pattern and the second defect pattern have defects. For the specific process, please refer to Figures 6 to 8 .

[0052] Please refer to Figure 6 , Figure 6 for Figure 4 Part A in the middle is an enlarged schematic diagram, and a plurality of first target spacings T1 between adjacent first target graphics 301 and second target graphics 302 in the first target layout 300 are obtained.

[0053] In this embodiment, the method for obtaining a plurality of first target spacings T1 between adjacent first target graphics 301 and second target graphics 302 in the first target layout 300 includes: virtually extending the first target graphics 301 along the second direction Y until the length dimension L1 of the first target graphics 301 is equal to the length dimension L2 of the adjacent second target graphics 302, and obtaining a virtual first target graphics 303; dividing the adjacent virtual first target graphics 303 and the second target graphics 302 into a plurality of first segments 304 along the second direction Y, and the plurality of first segments 304 are marked with serial numbers from 1 to N along the second direction Y, where N is a natural number and N≥2; obtaining the distance between adjacent first segments 304 with the same serial number as the first target spacing T1, and using the serial number as the serial number of the first target spacing T1.

[0054] Please refer to Figure 7 , Figure 7 for Figure 5 In the enlarged schematic diagram of part B, a plurality of first measurement intervals M1 between adjacent first exposure graphics 401 and second exposure graphics 402 corresponding to adjacent first target graphics 301 and second target graphics 302 in the first exposure image 400 are obtained, and the first measurement intervals M1 are equal in number and correspond one-to-one to the first target intervals T1.

[0055] In this embodiment, the method for obtaining a plurality of first measurement intervals M1 between adjacent first exposure patterns 401 and second exposure patterns 402 in the first exposure image 400 includes: virtually extending the first exposure pattern 401 along the second direction Y until the length of the first exposure pattern 401 is equal to the length of the adjacent second exposure pattern 402, and obtaining a virtual first exposure pattern 403; dividing the adjacent virtual first exposure pattern 403 and the second exposure pattern 402 into a plurality of second segments 404 along the second direction Y, and the plurality of second segments 404 are numbered with serial numbers from 1 to N along the second direction Y, where N is a natural number and N≥2; obtaining a distance between adjacent second segments 404 with the same serial number as the first measurement interval M1, and using the serial number as the serial number of the first measurement interval M1.

[0056] Please refer to Figure 8 , compare the corresponding first target spacing T1 with the first measurement spacing M1. If there is one or more of the first measurement spacings M1 that are smaller than the corresponding first target spacing T1, the corresponding first exposure pattern 401 and the second exposure pattern 402 are the first defect pattern 405 and the second defect pattern 406.

[0057] Please refer to Fig. 9 After obtaining the first defect pattern 405 and the second defect pattern 406 , a compensation size R1 is obtained according to the first defect pattern 405 and the second defect pattern 406 .

[0058] In this embodiment, the method for obtaining the compensation size R1 according to the first defect pattern 405 and the second defect pattern 406 includes: comparing the first target spacing T1 with the first measurement spacing M1 with the same serial number, and obtaining one or more defect measurement spacings D1 that are smaller than the corresponding first target spacing T1 from several first measurement spacings M1; and using the difference in size between the first target spacing T1 with the same serial number and the defect measurement spacing D1 as the compensation size R1.

[0059] Please refer to Fig.10 After obtaining the compensation size R1, the first target layout 300 is compensated and corrected according to the compensation size R1 to obtain the second target layout 500.

[0060] In this embodiment, the first target layout 300 is compensated and corrected according to the compensation size R1, and the method for obtaining the second target layout 500 includes: obtaining the first target graphic 301 and the second target graphic 302 corresponding to the first defect graphic 405 and the second defect graphic 406; obtaining the second segment 404 of the second exposure graphic 402 corresponding to the defect measurement interval D1; obtaining the first segment 304 of the second target graphic 302 corresponding to the second segment 404 of the second exposure graphic 402; translating the obtained first segment 304 by the compensation size R1 in a direction away from the first target graphic 301, and obtaining the second target layout 500.

[0061] In this embodiment, the first exposure image 400 is detected according to the first target layout 300 to obtain the first defect pattern 405 and the second defect pattern 406 adjacent to each other in the first exposure image 400; the compensation size R1 is obtained according to the first defect pattern 405 and the second defect pattern 406; the first target layout 300 is compensated and corrected according to the compensation size R1 to obtain the second target layout 500. Since the pattern in the obtained second target layout 500 has been compensated and corrected, the deviation of the pattern position caused by the mutual attraction between the first target pattern 301 and the second target pattern 302 can be reduced, the effect of the corrected pattern is improved, and then the performance of the semiconductor structure finally formed by the second target layout 500 is improved.

[0062] Correspondingly, an embodiment of the present invention also provides a method for making a mask. For the specific forming process, please refer to Figure 10 to Figure 11 .

[0063] Please continue to refer to Fig.10 , a second target layout 500 is obtained using the above-mentioned optical proximity correction method.

[0064] In this embodiment, the graphics in the second target layout 500 have been compensated and corrected, thereby reducing the deviation of the graphic position caused by the mutual attraction between the first target graphic 301 and the second target graphic 302, improving the effect of the corrected graphic, and further improving the performance of the semiconductor structure ultimately formed by the second target layout 500.

[0065] Please refer to Fig.11 , performing optical proximity correction processing on the second target layout 500 for several times to obtain a second optical proximity correction layout 600.

[0066] In this embodiment, after the second optical proximity correction plate 600 is obtained, the mask plate (not shown) is manufactured according to the second optical proximity correction plate 600 .

[0067] In this embodiment, the second target layout 500 is subjected to several optical proximity correction processes to obtain a second optical proximity correction layout 600; the mask is manufactured according to the second optical proximity correction layout 600. Since the mask is manufactured based on the second target layout 500, the performance of the semiconductor structure finally formed by the mask can be improved.

[0068] Accordingly, the present invention also provides a method for forming a semiconductor structure. For the specific forming process, please refer to Figures 12 to 15 .

[0069] Please refer to Fig.12 , providing a substrate 700.

[0070] In this embodiment, the base 700 includes: a substrate 701 and a plurality of fins 702 separated from each other and located on the substrate 701 .

[0071] In this embodiment, the method for forming the substrate 701 and the fin 702 includes: providing an initial base (not shown); forming a patterned layer (not shown) on the initial base; and etching the initial base using the patterned layer as a mask to form the substrate 701 and the fin 702.

[0072] In this embodiment, the material of the substrate 701 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0073] In this embodiment, the material of the fin 702 is silicon; in other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0074] Referring to FIG. 13 , an isolation layer 703 is formed on the substrate 700 , and the isolation layer 703 covers a portion of the sidewall of the fin 702 , and a top surface of the isolation layer 703 is lower than a top surface of the fin 702 .

[0075] In this embodiment, the method for forming the isolation layer 703 includes: forming an initial isolation layer (not shown) on the substrate 700 ; etching and removing a portion of the initial isolation layer to form the isolation layer, wherein the top surface of the isolation layer 703 is lower than the top surface of the fin 702 .

[0076] The material of the isolation layer 703 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride. In this embodiment, the material of the isolation layer 703 is silicon oxide.

[0077] Please refer to Fig.14After forming the isolation layer 703 , a device layer is formed on the substrate 700 .

[0078] In this embodiment, the device layer includes a plurality of initial dummy gate structures 704 arranged in parallel along a second direction Y, and the initial dummy gate structures 704 span across the fin 702 .

[0079] Please refer to Fig.15 , providing a mask plate obtained by the above-mentioned mask plate manufacturing method, using the mask plate as a mask, performing a patterning process on the device layer to form the semiconductor structure.

[0080] In this embodiment, the initial dummy gate structure 704 is patterned using the mask plate as a mask to form a dummy gate structure 705 and an isolation opening 706 located in the dummy gate structure 705 .

[0081] In this embodiment, after forming the dummy gate structure 705 and the isolation opening 706, it also includes: removing the dummy gate structure 705 to form a gate opening (not marked); forming a gate dielectric layer in the gate opening and a gate layer (not marked) located on the gate dielectric layer.

[0082] In this embodiment, the semiconductor structure is formed by the mask plate, which can effectively reduce the offset of the isolation opening 706 formed in the pseudo gate structure 705, so that there is a larger distance between the cut-off point of the pseudo gate structure 705 and the fin 702, and then after the gate opening is formed, it is convenient to fill the gate dielectric material, thereby improving the performance of the semiconductor structure finally formed.

[0083] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. An optical proximity correction method, characterized in that: include: Providing a first target layout, wherein the first target layout includes a plurality of first target graphics and a plurality of second target graphics arranged in parallel along a first direction; Acquire a first exposure image according to the first target layout, wherein the first exposure image includes a plurality of first exposure patterns and a plurality of second exposure patterns, wherein the first exposure patterns correspond to the first target patterns, and the second exposure patterns correspond to the second target patterns; The first exposure image is detected according to the first target layout, a first defect pattern is obtained from a plurality of the first exposure patterns, and a second defect pattern is obtained from a plurality of the second exposure patterns, the first defect pattern and the second defect pattern are adjacent to each other, and the first defect pattern and the second defect pattern have defects; wherein, The first target pattern and the second target pattern both extend along a second direction, the first direction is perpendicular to the second direction, and a length dimension of the second target pattern is greater than a length dimension of the first target pattern, and the length dimension is along the second direction; The method for obtaining adjacent first defective patterns and second defective patterns includes: obtaining a plurality of first target spacings between adjacent first target patterns and second target patterns in the first target layout; obtaining a plurality of first measurement spacings between adjacent first exposure patterns and second exposure patterns corresponding to the adjacent first target patterns and second target patterns in the first exposure image, wherein the first measurement spacings are equal in number and correspond one to one with the first target spacings; comparing the corresponding first target spacings with the first measurement spacings, and if there are one or more of the first measurement spacings that are smaller than the corresponding first target spacings, the corresponding first exposure pattern and the second exposure pattern are the first defective pattern and the second defective pattern; The method for obtaining a plurality of first target spacings between adjacent first target graphics and second target graphics in the first target layout includes: virtually extending the first target graphics along the second direction until the length of the first target graphics is equal to the length of the adjacent second target graphics, and obtaining a virtual first target graphics; dividing the adjacent virtual first target graphics and the second target graphics into a plurality of first segments along the second direction, and the plurality of first segments are marked with serial numbers from 1 to N along the second direction, where N is a natural number and N≥2; obtaining the distance between adjacent first segments with the same serial number as the first target spacing, and using the serial number as the serial number of the first target spacing; Acquire a compensation size according to the first defect pattern and the second defect pattern; The first target layout is compensated and corrected according to the compensation size to obtain the second target layout; wherein, The method for obtaining the compensation size according to the first defect pattern and the second defect pattern includes: comparing the first target spacing with the first measurement spacing having the same serial number, obtaining one or more defect measurement spacings smaller than the corresponding first target spacing from a plurality of the first measurement spacings; using the difference between the first target spacing and the defect measurement spacing having the same serial number as the compensation size; The method for obtaining the second target layout by compensating and correcting the first target layout according to the compensation size includes: obtaining the first target pattern and the second target pattern corresponding to the first defect pattern and the second defect pattern; obtaining the second segment of the second exposure pattern corresponding to the defect measurement interval; obtaining the first segment of the second target pattern corresponding to the second segment of the second exposure pattern; translating the obtained first segment by the compensation size in a direction away from the first target pattern to obtain the second target layout.

2. The optical proximity correction method according to claim 1, wherein: The method for acquiring the first exposure image includes: performing optical proximity correction processing on the first target layout several times to acquire a first optical proximity correction layout; and performing simulated exposure processing on the first optical proximity correction layout to acquire the first exposure image.

3. The optical proximity correction method according to claim 1, wherein: The method for obtaining the first exposure image includes: performing optical proximity correction processing on the first target layout several times to obtain a first optical proximity correction layout; providing a substrate; performing a patterning process on the substrate according to the first optical proximity correction layout to form a semiconductor structure; and performing actual exposure processing on the semiconductor structure to obtain the first exposure image.

4. The optical proximity correction method according to claim 1, wherein: The method for obtaining a plurality of first measurement intervals between adjacent first exposure patterns and second exposure patterns in the first exposure image includes: virtually extending the first exposure pattern along the second direction until the length of the first exposure pattern is equal to the length of the adjacent second exposure pattern, thereby obtaining a virtual first exposure pattern; dividing the adjacent virtual first exposure pattern and the second exposure pattern into a plurality of second segments along the second direction, and the plurality of second segments are marked with serial numbers from 1 to N along the second direction, where N is a natural number and N≥2; obtaining a distance between adjacent second segments having the same serial number as the first measurement interval, and using the serial number as the serial number of the first measurement interval.

5. A method for making a mask, characterized in that: include: Providing a first target layout, wherein the first target layout includes a plurality of first target graphics and a plurality of second target graphics arranged in parallel along a first direction; Acquire a first exposure image according to the first target layout, wherein the first exposure image includes a plurality of first exposure patterns and a plurality of second exposure patterns, wherein the first exposure pattern corresponds to the first target pattern, and the second exposure pattern corresponds to the second target pattern; detect the first exposure image according to the first target layout, acquire a first defect pattern in the plurality of first exposure patterns, acquire a second defect pattern in the plurality of second exposure patterns, wherein the first defect pattern and the second defect pattern are adjacent to each other, and the first defect pattern and the second defect pattern have defects; acquire a compensation size according to the first defect pattern and the second defect pattern; The first target layout is compensated and corrected according to the compensation size to obtain the second target layout; wherein, The first target pattern and the second target pattern both extend along a second direction, the first direction is perpendicular to the second direction, and a length dimension of the second target pattern is greater than a length dimension of the first target pattern, and the length dimension is along the second direction; The method for obtaining adjacent first defective patterns and second defective patterns includes: obtaining a plurality of first target spacings between adjacent first target patterns and second target patterns in the first target layout; obtaining a plurality of first measurement spacings between adjacent first exposure patterns and second exposure patterns corresponding to the adjacent first target patterns and second target patterns in the first exposure image, wherein the first measurement spacings are equal in number and correspond one to one with the first target spacings; comparing the corresponding first target spacings with the first measurement spacings, and if there are one or more of the first measurement spacings that are smaller than the corresponding first target spacings, the corresponding first exposure pattern and the second exposure pattern are the first defective pattern and the second defective pattern; The method for obtaining the compensation size according to the first defect pattern and the second defect pattern includes: comparing the first target spacing with the first measurement spacing having the same serial number, obtaining one or more defect measurement spacings smaller than the corresponding first target spacing from a plurality of the first measurement spacings; using the difference between the first target spacing and the defect measurement spacing having the same serial number as the compensation size; The method for compensating and correcting the first target layout according to the compensation size to obtain the second target layout includes: obtaining the first target pattern and the second target pattern corresponding to the first defect pattern and the second defect pattern; obtaining the second segment of the second exposure pattern corresponding to the defect measurement interval; obtaining the first segment of the second target pattern corresponding to the second segment of the second exposure pattern; translating the obtained first segment in a direction away from the first target pattern by the compensation size to obtain the second target layout; The method for obtaining a plurality of first target spacings between adjacent first target graphics and second target graphics in the first target layout includes: virtually extending the first target graphics along the second direction until the length of the first target graphics is equal to the length of the adjacent second target graphics, and obtaining a virtual first target graphics; dividing the adjacent virtual first target graphics and the second target graphics into a plurality of first segments along the second direction, and the plurality of first segments are marked with serial numbers from 1 to N along the second direction, where N is a natural number and N≥2; obtaining the distance between adjacent first segments with the same serial number as the first target spacing, and using the serial number as the serial number of the first target spacing; Performing optical proximity correction processing on the second target layout several times to obtain a second optical proximity correction layout; The mask is manufactured according to the second optical proximity correction pattern.

6. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a device layer on the substrate; A first target layout is provided, wherein the first target layout includes a plurality of first target patterns and a plurality of second target patterns arranged in parallel along a first direction; a first exposure image is acquired according to the first target layout, wherein the first exposure image includes a plurality of first exposure patterns and a plurality of second exposure patterns, wherein the first exposure pattern corresponds to the first target pattern, and the second exposure pattern corresponds to the second target pattern; the first exposure image is detected according to the first target layout, and a first defect pattern is acquired in the plurality of first exposure patterns, and a second defect pattern is acquired in the plurality of second exposure patterns, wherein the first defect pattern and the second defect pattern are adjacent to each other, and the first defect pattern and the second defect pattern have defects; and a compensation size is acquired according to the first defect pattern and the second defect pattern; The first target layout is compensated and corrected according to the compensation size to obtain the second target layout; wherein, The first target pattern and the second target pattern both extend along a second direction, the first direction is perpendicular to the second direction, and a length dimension of the second target pattern is greater than a length dimension of the first target pattern, and the length dimension is along the second direction; The method for obtaining adjacent first defective patterns and second defective patterns includes: obtaining a plurality of first target spacings between adjacent first target patterns and second target patterns in the first target layout; obtaining a plurality of first measurement spacings between adjacent first exposure patterns and second exposure patterns corresponding to the adjacent first target patterns and second target patterns in the first exposure image, wherein the first measurement spacings are equal in number and correspond one to one with the first target spacings; comparing the corresponding first target spacings with the first measurement spacings, and if there are one or more of the first measurement spacings that are smaller than the corresponding first target spacings, the corresponding first exposure pattern and the second exposure pattern are the first defective pattern and the second defective pattern; The method for obtaining the compensation size according to the first defect pattern and the second defect pattern includes: comparing the first target spacing with the first measurement spacing having the same serial number, obtaining one or more defect measurement spacings smaller than the corresponding first target spacing from a plurality of the first measurement spacings; using the difference between the first target spacing and the defect measurement spacing having the same serial number as the compensation size; The method for compensating and correcting the first target layout according to the compensation size to obtain the second target layout includes: obtaining the first target pattern and the second target pattern corresponding to the first defect pattern and the second defect pattern; obtaining the second segment of the second exposure pattern corresponding to the defect measurement interval; obtaining the first segment of the second target pattern corresponding to the second segment of the second exposure pattern; translating the obtained first segment in a direction away from the first target pattern by the compensation size to obtain the second target layout; The method for obtaining a plurality of first target spacings between adjacent first target graphics and second target graphics in the first target layout includes: virtually extending the first target graphics along the second direction until the length of the first target graphics is equal to the length of the adjacent second target graphics, and obtaining a virtual first target graphics; dividing the adjacent virtual first target graphics and the second target graphics into a plurality of first segments along the second direction, and the plurality of first segments are marked with serial numbers from 1 to N along the second direction, where N is a natural number and N≥2; obtaining the distance between adjacent first segments with the same serial number as the first target spacing, and using the serial number as the serial number of the first target spacing; Performing optical proximity correction processing on the second target layout several times to obtain a second optical proximity correction layout; manufacturing a mask according to the second optical proximity correction pattern; The device layer is patterned using the mask plate as a mask to form the semiconductor structure.

7. The method for forming a semiconductor structure according to claim 6, wherein: The base comprises: a substrate and a plurality of fins separated from each other and located on the substrate.

8. The method for forming a semiconductor structure according to claim 7, wherein: The device layer includes a plurality of initial dummy gate structures arranged in parallel along a second direction, the first direction is perpendicular to the second direction, and the initial dummy gate structures span the fins.

9. The method for forming a semiconductor structure according to claim 8, wherein: The initial dummy gate structure is patterned using the mask plate as a mask to form a dummy gate structure and an isolation opening in the dummy gate structure.

10. The method for forming a semiconductor structure according to claim 9, wherein: After forming the dummy gate structure and the isolation opening, the method further includes: removing the dummy gate structure to form a gate opening; and forming a gate dielectric layer and a gate layer located on the gate dielectric layer in the gate opening.

Images