Delay model determination method, layout and routing method, device, equipment and medium

Abstract

The application discloses a delay model determination method, a layout and wiring method, a device, equipment and a medium. The method comprises the following steps: determining a fitting direction; selecting test data in a plurality of untraversed actual use cases corresponding to an FPGA chip; selecting a fitting model in an untraversed model corresponding to the fitting direction; obtaining an initial model based on the test data and the fitting model; determining a fitting value of the initial model; and if the fitting value is less than a preset threshold, taking the initial model as a delay model of the FPGA chip. In this way, delay estimation is performed by using the delay model, space can be saved, memory consumption can be reduced, and the delay estimation result is continuous and gradual according to the delay model determined according to the actual use case, and the delay estimation result is more in line with actual layout and wiring needs.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and more particularly, to a delay model determination method, a placement and routing method, an apparatus, a device and a medium. BACKGROUND

[0002] With the rapid development of integrated circuits, the technology involved in FPGA (Field Programmable Gate Array) chips has also made rapid development and breakthrough. FPGA chips have programmability, which can effectively simplify the digital circuit design process and become the mainstream software for circuit design.

[0003] However, with the development of technology, the scale of FGPA chips is becoming larger and larger, and the circuit design is becoming more and more complex, and the development time using FPGA is becoming longer and longer. In order to ensure the development efficiency, the algorithm performance of the supporting software is also required to be higher and higher. Among them, the placement algorithm and the routing algorithm are very important parts of the FPGA software algorithm, and in order to improve the software algorithm performance, the placement and routing efficiency must be improved, and accurate and reasonable delay estimation will determine the placement and routing efficiency.

[0004] Usually, a delay estimation method based on a lookup table method is adopted, that is, a delay table is generated and stored in advance, and a delay estimation value is obtained by using the lookup table method, however, the delay table needs to occupy a certain memory, and with the expansion of the scale of FPGA chips, the required memory is larger, and the data obtained according to the delay table is discrete and has mutations, which cannot match the actual placement and routing result. SUMMARY

[0005] In view of the above problems, the present application provides a delay model determination method, a placement and routing method, an apparatus, a device and a medium to improve the above problems.

[0006] In a first aspect, the embodiments of the present application provide a delay model determination method of an FPGA chip, the method comprising: determining a fitting direction; selecting test data in a plurality of actual use cases corresponding to the FPGA chip which have not been traversed; selecting a fitting model in a model corresponding to the fitting direction which has not been traversed; obtaining an initial model based on the test data and the fitting model; determining a fitting value of the initial model; and if the fitting value is less than a preset threshold, taking the initial model as the delay model of the FPGA chip.

[0007] In a second aspect, the embodiments of the present application further provide a layout and wiring method of an FPGA chip, which comprises: determining a to-be-set position of a to-be-set unit in the FPGA chip; determining a node distance value between the to-be-set position and surrounding nodes; and determining a delay value of the to-be-set position according to a delay model of the FPGA chip and the node distance. The delay model is determined by using the delay model determination method of the FPGA chip in the first aspect. A preset position with a delay value less than a preset delay threshold is selected as the setting position of the to-be-set unit.

[0008] In a third aspect, the embodiments of the present application further provide a layout and wiring device of an FPGA chip, which comprises: a to-be-set position determination module, a node distance value determination module, a delay value determination module and a setting position determination module. Specifically, the to-be-set position determination module is configured to determine a to-be-set position of a to-be-set unit in the FPGA chip; the node distance value determination module is configured to determine a node distance value between the to-be-set position and surrounding nodes; the delay value determination module is configured to determine a delay value of the to-be-set position according to a delay model of the FPGA chip and the node distance; the delay model is determined by using the delay model determination method of the FPGA chip in the first aspect; and the setting position determination module is configured to select a preset position with a delay value less than a preset delay threshold as the setting position of the to-be-set unit.

[0009] In a fourth aspect, the embodiments of the present application further provide an electronic device, which comprises: one or more processors; a memory; and one or more application programs. The one or more application programs are stored in the memory and configured to be executed by the one or more processors. The one or more application programs are configured to execute the delay model determination method of the FPGA chip in the first aspect and / or the layout and wiring method of the FPGA chip in the second aspect.

[0010] In a fifth aspect, the embodiments of the present application further provide a computer readable storage medium, which stores program codes. The program codes can be invoked by a processor to execute the delay model determination method of the FPGA chip in the first aspect and / or the layout and wiring method of the FPGA chip in the second aspect.

[0011] The technical scheme provided by the present application comprises the following steps: determining a fitting direction; selecting test data in a plurality of untraversed actual use cases corresponding to the FPGA chip; selecting a fitting model in an untraversed model corresponding to the fitting direction; obtaining an initial model based on the test data and the fitting model; determining a fitting value of the initial model; and if the fitting value is less than a preset threshold, taking the initial model as the delay model of the FPGA chip. In this way, the delay model is used for delay estimation, which can save space and reduce memory consumption. Moreover, the delay estimation result is continuous and gradual according to the delay model determined based on the actual use case, and is more consistent with the actual layout and wiring needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following is a brief introduction to the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments and drawings obtained by ordinary technicians in this field without creative work are within the scope of protection of this invention.

[0013] Figure 1 A flow chart of a method for determining a delay model of an FPGA chip proposed in one embodiment of the present application is shown.

[0014] Figure 2 The distance-delay scatter plot of test set A and test set B in one embodiment of the present application is shown.

[0015] Figure 3 A flow chart of a method for layout and routing of an FPGA chip proposed in one embodiment of the present application is shown.

[0016] Figure 4 A flow chart of another FPGA chip layout and routing method proposed in one embodiment of the present application is shown.

[0017] Figure 5 A schematic structural diagram of a delay model determination device for an FPGA chip proposed in one embodiment of the present application is shown.

[0018] Figure 6 A schematic structural diagram of a layout and routing device for an FPGA chip proposed in one embodiment of the present application is shown.

[0019] Figure 7 A structural block diagram of an electronic device proposed in an embodiment of the present application is shown.

[0020] Figure 8 A structural block diagram of a computer-readable storage medium proposed in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0022] With the rapid development of integrated circuits, the technology involved in FPGA (Field Programmable Gate Array) chips has also made rapid development and breakthrough. FPGA chips have programmability, which can effectively simplify the digital circuit design process and become the mainstream software of circuit design.

[0023] However, with the development of technology, the size of FGPA chips is getting larger and larger, and the circuit design is getting more and more complex, and the development time using FPGA is getting longer and longer. In order to ensure the development efficiency, the algorithm performance of the supporting software is also getting higher and higher. Among them, the layout algorithm and the routing algorithm are very important parts of the FPGA software algorithm. In order to improve the software algorithm performance, it is necessary to improve the layout and routing efficiency, and accurate and reasonable delay estimation will determine the layout and routing efficiency.

[0024] In the related art, the timing_slack of the layout algorithm can be obtained by formula one.

[0025] timing_slack = require_time - arrival_time (Formula one)

[0026] Among them, require_time is the demand value set by the user, which is set according to the actual design demand of the user; arrival_time is the actual value, and the layout algorithm needs to rely on reliable timing analysis results to obtain ideal layout results. However, there is no actual delay data in the layout stage, and the actual value arrival_time can only be obtained by delay estimation, and whether the delay estimation result is reasonable will determine whether the timing analysis result of the layout algorithm is reliable.

[0027] Usually, the A* algorithm is commonly used in the routing algorithm to search for the best routing path, and its cost function can be obtained by formula two.

[0028] f(n) = g(n) + h(n) (Formula two)

[0029] Among them, n is the intermediate node; f(n) is the estimated cost from the initial node to the target node; g(n) is the actual cost from the initial node to the n node; h(n) is the estimated cost from the n node to the target node.

[0030] Among them, g(n) can be measured by the actual wiring result, while h(n) can only be obtained by delay estimation, and h(n) can only be obtained by delay estimation, and whether the delay estimation result is reasonable determines whether h(n) is reasonable, and further determines whether the routing algorithm is reasonable.

[0031] In the related art, a delay estimation method based on a lookup table method is usually used, delay values between all ports of each unit in a chip logic array and minimum delay values between units are extracted in advance, and a delay table is generated. The delay table generated in advance is loaded by the router when starting routing, and is parsed and stored in a hash table, and then the required delay estimation value is extracted directly from the delay table.

[0032] The delay estimation method based on the lookup table method has the following defects:

[0033] (1) Occupying memory space. The delay estimation method based on the lookup table method needs to load and save the delay table for use, and with the increase of the chip size, the data of the delay table is more and more, and the occupied memory space is more and more large.

[0034] (2) Data is discrete and mutated, and does not meet the actual demand. In fact, the layout algorithm pays more attention to the relationship between the units of the port, and expects smooth and continuous timing change. The delay table is mainly generated according to the routing delay estimation demand, and records the delay values between the ports. The data is discrete and mutated, and does not meet the actual demand.

[0035] (3) Unable to adapt to the changeable chip structure. In the delay table, the optimal delay of the regular routing is recorded, and it is more suitable for regular FPGA architecture, but with the change of the chip size, the chip architecture presents the trend of irregularity, and the delay table cannot completely fit the actual routing effect.

[0036] In order to improve the above problems, the inventors propose the delay model determination method, the layout and routing method, the device, the equipment and the medium provided in the application. The method determines the fitting direction, selects the test data in the untraversed multiple actual use cases corresponding to the FPGA chip, selects the fitting model in the untraversed model corresponding to the fitting direction, obtains the initial model based on the test data and the fitting model, determines the fitting value of the initial model, and if the fitting value is less than a preset threshold, the initial model is used as the delay model of the FPGA chip. In this way, the delay estimation is performed by using the delay model, the space can be saved, the memory consumption can be reduced, and according to the delay model determined according to the actual use case, the delay estimation result is continuous and gradual, and is more in line with the actual layout and routing needs.

[0037] The specific embodiments will be described below.

[0038] In this embodiment, the delay model determination device of the FPGA chip will be described from the perspective of the delay model determination device of the FPGA chip. The delay model determination device can be integrated in a terminal device.

[0039] Please refer to Figure 1The embodiment of the present application provides a delay model determination method of an FPGA chip, which can be applied to the method characterized in that the method comprises steps 110 to 160.

[0040] Step 110: Determine a fitting direction.

[0041] Please refer to Figure 2 , Figure 2 Distance-delay scatter diagrams of test set A and test set B are shown. In the embodiment of the present application, the inventors find that the delay value is positively correlated with the distance between the starting point and the ending point through analysis of a large amount of delay data, and the data with the positive correlation can be fitted to obtain a mathematical model in which one party is the independent variable and the other party is the dependent variable.

[0042] In the embodiment of the present application, in order to obtain the relationship between the path distance and the delay value, the actual use case data on the FPGA chip can be analyzed, the appropriate fitting direction can be selected, and then a reasonable and reliable delay model that can be applied to the FPGA chip can be fitted.

[0043] In the embodiment of the present application, since the parameters of different FPGA chips are different, in order to obtain an accurate delay model, different FPGA chips can be fitted respectively to obtain a delay model suitable for each FPGA chip.

[0044] In the embodiment of the present application, the fitting direction can include but is not limited to selecting a fitting mode. It can be understood that selecting different fitting modes corresponds to different models that can be used for fitting.

[0045] In some embodiments, the fitting mode can include but is not limited to a curve fitting mode, a least square method fitting mode and the like. Preferably, the curve fitting mode is used.

[0046] In some embodiments, the user can select the fitting direction on the interactive interface of the delay model determination device, and the delay model determination device can further determine the fitting direction selected by the user in response to the selection operation of the user.

[0047] In some embodiments, the user can also select the fitting direction on the terminal, and the terminal and the delay model determination device can be connected through a wired or wireless manner, and then the terminal responds to the selection operation of the user to further determine the fitting direction selected by the user.

[0048] In some embodiments, the fitting direction can be adjusted according to the actual use. It can be understood that after the fitting direction is selected, if the subsequent fitting effect does not meet the expected effect, this step can be returned to adjust the fitting direction again.

[0049] Step 120: selecting test data in the untraversed actual use cases corresponding to the FPGA chip.

[0050] In the embodiments of the present application, the delay model is fitted by using the wiring data corresponding to the actual use cases of the FPGA chip, so that the fitted delay model is more suitable for the estimation of the delay value of the FPGA chip, and the estimated data is closer to the actual data, which can effectively improve the efficiency of the layout and wiring of the FPGA chip.

[0051] It can be understood that, in order to reasonably and reliably estimate the delay value of different FPGA chips, the fitting of the delay model corresponding to each FPGA chip uses the actual use cases corresponding to each FPGA chip, so as to obtain a fitting model more suitable for each FPGA chip.

[0052] In some embodiments, the actual use cases include, but are not limited to, one or more of actual circuit design cases actually designed on the FPGA chip, simulation circuit design cases designed by the developer, etc.

[0053] In some embodiments, the selected actual use cases can be adjusted according to the actual use needs. It can be understood that if the subsequent fitting effect does not meet the expected effect, this step can be returned to, and the test data used for fitting can be selected from the untraversed actual use cases.

[0054] In some embodiments, the actual use cases include all wiring data of the circuit involved. In actual layout and wiring, part of the network data in the wiring data does not need to consider the timing problem, and this part of the network data does not need to consider the delay problem. Therefore, when selecting the test data, the wiring data that does not need to consider the delay problem can be filtered out.

[0055] In some embodiments, due to faults, deviations, etc., part of the wiring data in the wiring data may be abnormal and have large deviations. In order to obtain a reasonable and reliable delay model, when selecting the test data, the wiring data with large deviations can be filtered out. Specifically, according to the distance between the actual wiring data and the standard value, if the distance is greater than a preset distance threshold, the wiring data can be filtered out. For example, the wiring data includes a first distance value and a first delay value, the first distance value corresponds to a first standard value, and if the distance between the first delay value and the first standard value is greater than the preset distance threshold, the wiring data needs to be filtered out to avoid the influence of deviation data on the fitting effect.

[0056] Optionally, the distance between the actual wiring and the standard value can be confirmed by Euclidean distance, Manhattan distance, etc.

[0057] In some embodiments, after determining the test data, the test data can be printed and integrated to meet the needs of the user fitting model. Alternatively, the test data can be obtained by adding a print function in the PDS (Pango Design Suit, large-scale FPGA development software) tool, running the selected actual use case, and the print function will print the running results.

[0058] In some embodiments, step 120 can include:

[0059] (1) selecting a preset number of actual use cases from the plurality of actual use cases corresponding to the FPGA chip and not traversed as test cases.

[0060] The preset number can be determined according to actual use needs. If the actual use case is a small case, i.e., involves less data, the preset number can be increased, which can be selected according to actual use needs, which is not limited in the present application.

[0061] (2) determining test data from the wiring data corresponding to the test cases.

[0062] After determining the test cases, the data related to the timing problem in the wiring data corresponding to the test cases is further selected as the test data. Alternatively, the selected data can be further filtered to remove data with deviations, thereby improving the reliability of the data.

[0063] Step 130: selecting a fitting model in the untraversed model corresponding to the fitting direction.

[0064] In an embodiment of the present application, each fitting direction can correspond to a plurality of fitting models that can be used for fitting. For example, the fitting models corresponding to the curve fitting method include: polynomial model, exponential model, etc.

[0065] In an embodiment of the present application, the fitting direction can be determined according to actual use needs, and then the fitting model can be selected from the plurality of fitting models corresponding to the fitting direction.

[0066] In some embodiments, the selected fitting model can be adjusted according to actual use needs. It can be understood that after selecting the fitting model, if the subsequent fitting effect does not meet the expected effect, the fitting model can be returned to this step and adjusted again.

[0067] In some embodiments, a plurality of fitting models can be fitted one by one, and then the fitting model with the best fitting effect can be selected as the delay model.

[0068] Step 140: obtaining an initial model based on the test data and the fitting model.

[0069] In the embodiments of the present application, an initial model can be obtained according to the selected test data and the fitting model. For example, the fitting model adopts a polynomial fitting model, for example: y(x) = k1x + k2x 2 + b, where k1 is a first delay coefficient, k2 is a second delay coefficient, and b is a delay constant.

[0070] The test data z(x, y) includes: first test data z1(x1, y1), second test data z2(x2, y2), third test data z3(x3, y3), fourth test data z4(x4, y4), and Nth test data z n (x n , y n ), where x represents a distance value, and y represents a test delay value.

[0071] Further, the test data z(x, y) is substituted into the fitting model y(x) = k1x + k2x 2 + b, i.e., the first test data z1(x1, y1), the first test data z2(x2, y2), the second test data z3(x3, y3), the third test data z4(x4, y4), and the Nth test data z n (x n , y n ) are substituted into the fitting model y(x) = k1x + k2x 2 + b, respectively, to obtain a plurality of equations to be solved, and the values of the first delay coefficient k1, the second delay coefficient k2, and the delay constant b are solved. The values of the first delay coefficient k1, the second delay coefficient k2, and the delay constant b are substituted into the fitting model y(x) = k1x + k2x 2 + b, thereby obtaining an initial model.

[0072] Step 150: Determine the fitting value of the initial model.

[0073] In the embodiments of the present application, in order to determine the fitting effect of the initial model, the fitting value of the initial model can be determined to determine the gap between the delay value obtained by the initial model and the actual wiring delay value.

[0074] Specifically, the step of determining the fitting value of the initial model can include:

[0075] (1) determining a first delay value of the preset path according to the distance value of the preset path and the initial model.

[0076] It can be understood that different evaluation criteria can be used to evaluate the fitting effect of the initial model according to different requirements. In the embodiments of the present application, the fitting effect of the initial model can be determined by determining the consistency of the layout timing and the routing timing, that is, the higher the consistency of the layout timing and the routing timing, the more the layout planning can reflect the actual routing result, and the stronger the timing stability.

[0077] In some embodiments, the critical path of the layout and the routing can be selected as the preset path, and the layout and the routing delay result of the preset path are determined and compared respectively, so as to determine the fitting effect of the initial model.

[0078] In some embodiments, the delay value corresponding to the preset path can be determined as the first delay value according to the distance value of the preset path and the initial model, and the first delay value is an estimated result according to the initial model.

[0079] (2) Routing the preset path on the FPGA chip, and detecting the second delay value of the preset path on the FPGA chip.

[0080] In the embodiments of the present application, in order to determine the delay value of the actual routing of the preset path, the preset path can be actually routed on the FPGA chip, and the second delay value of the preset path can be run and detected on the FPGA chip, and the second delay value is a test result of the actual routing.

[0081] (3) Determining the fitting value of the initial model according to the first delay value and the second delay value.

[0082] In the embodiments of the present application, the fitting value of the initial model can be determined by the difference between the first delay value and the second delay value.

[0083] Step 160: If the fitting value is less than the preset threshold, the initial model is taken as the delay model of the FPGA chip.

[0084] In the embodiments of the present application, the preset threshold can be set according to the actual chip design accuracy requirement, and the present application does not limit this. It can be understood that the smaller the value of the preset threshold, the higher the accuracy requirement of the delay model, and the more accurate the delay estimation result of the delay model.

[0085] In some embodiments, the delay model determination method provided by the embodiments of the present application can further include the step of: if the fitting value is less than or equal to the preset threshold, determining whether to replace the fitting model.

[0086] In the embodiments of the present application, if the fitting value is greater than or equal to the preset threshold, the fitting effect of the initial model does not meet the expected requirement, and the initial model needs to be adjusted again.

[0087] Specifically, the step of determining whether to replace the fitting model can comprise:

[0088] (1.1) determining fitting data based on the test data and the initial model.

[0089] In embodiments of the present application, the test data can be, for example, distance values and first delay values corresponding to the distance values, and second delay values estimated by the initial model can be obtained according to the distance values of the test data and the initial model, the second delay values being corresponding fitting data.

[0090] (1.2) determining a fitting value of the test data and the fitting data.

[0091] In embodiments of the present application, the mean square error of the test data and the fitting data can be calculated as the fitting value of the test data and the fitting data.

[0092] For example, the test data is test data z(x, y) including: first test data z1(x1, y1), first test data z2(x2, y2), second test data z3(x3, y3), third test data z4(x4, y4)……Nth test data zN(xN, yN), where x represents a distance value, and y represents a test delay value. n n n

[0093] Further, according to the distance values of the test data and the initial model, corresponding fitting delay values can be obtained in turn: a first fitting delay value corresponding to the first test data a second fitting delay value corresponding to the second test data a third fitting delay value corresponding to the third test data a second fitting delay value corresponding to the fourth test data ……an Nth fitting delay value corresponding to the Nth test data

[0094] Thus, the mean square error of the test data and the fitting data, i.e., the fitting value D of the test data and the fitting data, can be calculated according to Formula Three.

[0095]

[0096] (1.3) if the fitting value is greater than or equal to a preset fitting threshold, it is determined to replace the fitting model, otherwise it is determined not to replace the fitting model.

[0097] In embodiments of the present application, if the fitting value is greater than or equal to the preset fitting threshold, it indicates that the result of delay estimation does not meet the expected effect, and the fitting model does not fit the test data of the actual use case.

[0098] ​​​(1.4) If it is determined to replace the fitting model, return to perform the step of selecting the fitting model in the unselected model corresponding to the fitting direction.

[0099] In the embodiments of the present application, the delay model determination method provided by the embodiments of the present application can further include:

[0100] (1) If it is determined not to replace the fitting model, determine whether to update the test data.

[0101] (2) If it is determined to update the test data, return to perform the step of selecting the test data in the untraversed multiple actual use cases corresponding to the FPGA chip.

[0102] In the embodiments of the present application, if it is determined not to replace the fitting model, and the fitting effect cannot meet the expected effect, it may be due to the fact that the number of trace data corresponding to the selected actual use case is small, the coverage is small, or part of the selected actual use case is designed by the developer, and the trace data obtained under ideal conditions, so that the initial model obtained by using these actual use cases cannot meet the delay estimation requirement under actual conditions. Therefore, the test data used for fitting can be updated, that is, the test data is reselected in the untraversed multiple actual use cases corresponding to the FPGA chip for fitting. Thus, by adjusting and updating the test data, a delay model more in line with actual needs can be obtained.

[0103] The delay model determination method provided by the embodiments of the present application determines the fitting direction, selects the test data in the untraversed multiple actual use cases corresponding to the FPGA chip, selects the fitting model in the untraversed model corresponding to the fitting direction, obtains the initial model based on the test data and the fitting model, determines the fitting value of the initial model, and if the fitting value is less than a preset threshold, the initial model is used as the delay model of the FPGA chip. In this way, the delay model is used for delay estimation, without loading an additional delay table, which can greatly save space and reduce memory consumption. Moreover, according to the delay model determined based on the actual use case, the delay estimation result is continuous and gradual, which is more in line with the actual layout and wiring needs, and can adapt to the variable chip architecture, and has stronger universality.

[0104] In the embodiments, the layout and wiring device of the FPGA chip will be described from the perspective of the layout and wiring device of the FPGA chip, which can be integrated in a terminal device.

[0105] Please refer to Figure 3 , Figure 3 is a flowchart of the layout and wiring method of the FPGA chip provided by the embodiments of the present application. The layout and wiring method of the FPGA chip includes steps 410 to 440.

[0106] Step 210: Determine the to-be-set position of the to-be-set unit in the FPGA chip.

[0107] Step 220: determining a node distance value between the to-be-set position and surrounding nodes.

[0108] Step 230: determining a delay value of the to-be-set position according to the delay model of the FPGA chip and the node distance. The delay model is determined by using the delay model determination method of the FPGA chip.

[0109] Step 240: selecting the to-be-set position with a delay value less than a preset delay threshold as the setting position of the to-be-set unit.

[0110] In the embodiments of the present application, a layout and routing method of an FPGA chip is provided, i.e., the layout and routing is performed by using the delay model of the FPGA chip obtained by using the delay model determination method of the FPGA chip. Specifically, the to-be-set unit can have multiple to-be-set positions that can be set, the node distance value between each to-be-set position and surrounding nodes can be determined, the delay value of each to-be-set position can be determined by using the node distance value and the delay model, and the to-be-set position with a delay value less than a preset delay threshold can be selected as the setting position of the to-be-set unit.

[0111] In some embodiments, when there are multiple to-be-set positions with a delay value less than a preset delay threshold, the to-be-set position with the minimum delay value can be selected as the setting position of the to-be-set unit, so as to obtain an optimal setting position.

[0112] In some embodiments, as shown in Figure 4 , the layout and routing method of the FPGA chip can further include:

[0113] Step 310: determining a to-be-set path of the to-be-set node.

[0114] Step 320: determining a path distance value of the to-be-set path.

[0115] Step 330: determining a delay value of the to-be-set path according to the delay model and the path distance value.

[0116] Step 340: selecting the to-be-set path with the minimum delay value as the setting path of the to-be-set node.

[0117] In the embodiments of the present application, the delay values of multiple to-be-set paths can also be determined by using the delay model, specifically, the delay value corresponding to the to-be-set path can be determined according to the distance value of the to-be-set path, the to-be-set path with the minimum delay value can be selected as the setting path of the to-be-set node, and thus an optimal setting path can be obtained.

[0118] Please refer to Figure 5 , Figure 5The delay model determination device 400 for an FPGA chip is provided for an embodiment of the present application, and is applied to a terminal device. The delay model determination device 400 comprises a direction determination module 410, a data selection module 420, a model selection module 430, a model fitting module 440, a fitting value determination module 450, and a delay model determination module 460.

[0119] The direction determination module 410 is configured to determine a fitting direction.

[0120] The data selection module 420 is configured to select test data from untraversed actual use cases corresponding to the FPGA chip.

[0121] The model selection module 430 is configured to select a fitting model from untraversed models corresponding to the fitting direction.

[0122] The model fitting module 440 is configured to obtain an initial model based on the test data and the fitting model.

[0123] The fitting value determination module 450 is configured to determine a fitting value of the initial model.

[0124] The delay model determination module 460 is configured to, if the fitting value is greater than a preset threshold value, take the initial model as a delay model of the FPGA chip.

[0125] Please refer to Figure 6 , Figure 6 The layout and routing device 500 for an FPGA chip is provided for an embodiment of the present application, and is applied to a terminal device. The layout and routing device 500 comprises a to-be-set position determination module 510, a node distance value determination module 520, a delay value determination module 530, and a set position determination module 540.

[0126] The to-be-set position determination module 510 is configured to determine a to-be-set position of a to-be-set unit on the FPGA chip.

[0127] The node distance value determination module 520 is configured to determine a node distance value between the to-be-set position and surrounding nodes.

[0128] The delay value determination module 530 is configured to determine a delay value of the to-be-set position according to a delay model of the FPGA chip and the node distance. The delay model is determined by the above delay model determination method for the FPGA chip.

[0129] The set position determination module 540 is configured to select a preset position with a delay value less than a preset delay threshold value as a set position of the to-be-set unit.

[0130] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0131] In several embodiments provided in this application, the coupling between modules may be electrical, mechanical or other forms of coupling.

[0132] In addition, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The above-mentioned integrated modules may be implemented in the form of hardware or software functional modules.

[0133] See also Figure 6 An embodiment of the present application provides an electronic device 600, which can be an electronic device 600 such as a tablet computer or a desktop computer capable of running applications. The electronic device 600 in the present application may include one or more of the following components: a processor 610, a memory 620, and one or more applications, wherein the one or more applications may be stored in the memory 620 and configured to be executed by one or more processors 610, and the one or more programs are configured to execute the method described in the aforementioned method embodiment.

[0134] The processor 610 may include one or more processing cores. The processor 610 utilizes various interfaces and circuits to connect various components within the electronic device. It executes instructions, programs, code sets, or instruction sets stored in memory, and accesses data stored in memory to perform various functions of the electronic device and process data. Optionally, the processor 610 may be implemented using at least one hardware form of a digital signal processing (DSP), a field-programmable gate array (FPGA), or a programmable logic array (PLA). The processor 10 may integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. The CPU primarily processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing display content; and the modem handles wireless communications. It is understood that the modem may not be integrated into the processor and may be implemented separately via a communication chip.

[0135] The memory 620 can include a random access memory (RAM) and can also include a read-only memory (ROM). The memory can be used to store instructions, programs, codes, code sets, or instruction sets. The memory can include a program storage area and a data storage area, where the program storage area can store instructions for implementing an operating system, instructions for implementing at least one function (such as a fitting value determination function, an initial model determination function, etc.), instructions for implementing each of the method embodiments described below, and the like. The data storage area can also store data created by the terminal in use (such as test data, fitting values, etc.), and the like.

[0136] Reference is made to Figure 7 which shows a structural block diagram of a computer readable storage medium 600 provided by an embodiment of the present application. The computer readable medium 600 stores program code 610 therein, which can be invoked by a processor to execute the methods described in the above method embodiments.

[0137] The computer readable storage medium 600 can be an electronic storage such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer readable storage medium includes a non-transitory computer readable medium. The computer readable storage medium 600 has a storage space for program codes for executing any of the method steps described above. These program codes can be read from or written to one or more computer program products. The program codes can be compressed in an appropriate form, for example.

[0138] The embodiments of the present application also provide a computer program product or a computer program, which includes computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the methods provided in the various optional implementation manners provided by the above embodiments.

[0139] The specific implementation of each of the above operations can refer to the previous embodiments, which will not be described here again.

[0140] The computer readable storage medium can include a read only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0141] Due to the instructions stored in the computer readable storage medium, the steps in any of the delay model determination methods or the layout and routing methods provided in the embodiments of the present application can be performed, thus the beneficial effects of any of the delay model determination methods or the layout and routing methods provided in the embodiments of the present application can be achieved, which are described in detail in the foregoing embodiments and will not be described here.

[0142] To sum up, the embodiments of the present application provide a delay model determination method, a layout and routing method, an apparatus, a device and a medium. The method selects test data in a plurality of actual use cases that are not traversed corresponding to the FPGA chip, selects a fitting model in a model corresponding to the fitting direction that is not traversed, obtains an initial model based on the test data and the fitting model, determines a fitting value of the initial model, and if the fitting value is less than a preset threshold, takes the initial model as a delay model of the FPGA chip. In this way, delay estimation is performed by using the delay model, which can save space and reduce memory consumption, and the delay estimation result is continuous and gradual according to the delay model determined according to the actual use case, which is more in line with the actual layout and routing needs.

[0143] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not drive the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for determining a delay model of an FPGA chip, characterized in that: The method comprises: Determining a fitting direction; wherein determining the fitting direction includes selecting a fitting method; wherein different fitting methods correspond to different models to be fitted; Selecting test data from a plurality of untraversed actual use cases corresponding to the FPGA chip; Selecting a fitting model from the untraversed models corresponding to the fitting direction; Obtaining an initial model based on the test data and the fitting model; Determining a fitting value of the initial model; wherein, if the consistency between the layout timing and the routing timing corresponding to the initial model is higher, the fitting value of the initial model is smaller; If the fitting value is less than a preset threshold, the initial model is used as the delay model of the FPGA chip.

2. The method according to claim 1, characterized in that The method further comprises: If the fitting value is greater than or equal to the preset threshold, determining whether to replace the fitting model; If it is determined to replace the fitting model, the process returns to the step of selecting a fitting model from the unselected models corresponding to the fitting direction.

3. The method according to claim 2, characterized in that The determining whether to replace the fitting model includes: determining fitting data based on the test data and the initial model; Determining a fit value between the test data and the fitted data; If the fit value is less than or equal to a preset fit threshold, it is determined that the fitting model is replaced; otherwise, it is determined that the fitting model is not replaced.

4. The method according to claim 2, characterized in that The method further comprises: If it is determined not to replace the fitted model, then determine whether to update the test data; If it is determined to update the test data, the process returns to the step of selecting test data from a plurality of untraversed actual use cases corresponding to the FPGA chip.

5. The method according to claim 1, wherein The selecting test data from a plurality of untraversed actual use cases corresponding to the FPGA chip includes: Selecting a preset number of actual use cases from a plurality of unselected actual use cases corresponding to the FPGA chip as test cases; Determine the test data from the routing data corresponding to the test case.

6. The method according to claim 1, characterized in that Determining the fitting value of the initial model includes: Determining a first delay value of the preset path according to the distance value of the preset path and the initial model; Routing the preset path on the FPGA chip, and detecting a second delay value of the preset path on the FPGA chip; A fitting value of the initial model is determined according to the first delay value and the second delay value.

7. A layout and routing method for an FPGA chip, characterized in that: The method comprises: Determine the location of the unit to be set on the FPGA chip; Determine the node distance value between the to-be-set position and surrounding nodes; Determining the delay value of the position to be set according to the delay model of the FPGA chip and the node distance; wherein the delay model is determined by the delay model determination method of the FPGA chip according to any one of claims 1 to 5; The to-be-set position having the delay value smaller than the preset delay threshold is selected as the setting position of the to-be-set unit.

8. The method according to claim 7, characterized in that The method further comprises: Determine the path to be set for the node to be set; Determining a path distance value of the path to be set; Determining a delay value of the path to be set according to the delay model and the path distance value; The to-be-set path with the smallest delay value is selected as the setting path of the to-be-set node.

9. A device for determining a delay model of an FPGA chip, characterized in that: The device comprises: A direction determination module is used to determine the fitting direction; the determination of the fitting direction includes selecting a fitting method; wherein different fitting methods correspond to different models to be fitted; A data selection module, configured to select test data from a plurality of untraversed actual use cases corresponding to the FPGA chip; A model selection module, configured to select a fitting model from the untraversed models corresponding to the fitting direction; A model fitting module, configured to obtain an initial model based on the test data and the fitting model; A fitting value determination module, configured to determine a fitting value of the initial model; wherein the higher the consistency between the layout timing and the routing timing corresponding to the initial model, the smaller the fitting value of the initial model; The delay model determination module is used to use the initial model as the delay model of the FPGA chip if the fitting value is greater than a preset threshold.

10. A layout and routing device for an FPGA chip, characterized in that: The device comprises: A module for determining a position to be set, used to determine a position to be set of a unit to be set on the FPGA chip; A node distance value determination module is used to determine the node distance value between the position to be set and the surrounding nodes; a delay value determination module, configured to determine the delay value of the to-be-set position based on the delay model of the FPGA chip and the node distance; wherein the delay model is determined using the delay model determination method for the FPGA chip according to any one of claims 1 to 6; The setting position determining module is used to select a preset position where the delay value is less than a preset delay threshold as the setting position of the unit to be set.

11. An electronic device, characterized in that: include: one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the delay model determination method of the FPGA chip as described in any one of claims 1 to 6 and / or the layout and routing method of the FPGA chip as described in claim 7 or 8.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, which can be called by a processor to execute the delay model determination method of the FPGA chip as described in any one of claims 1-6 and / or the layout and routing method of the FPGA chip as described in claim 7 or 8.

Images