Method and system for repairing layout violations

Abstract

The present application relates to a method and system for repairing layout violations. The method includes the following operations: receiving a design rule violation of a first layout; classifying the first violation of the design rule violation into a first category of a predefined category based on a first chip feature of the first layout; generating a first vector array associated with the first violation for at least one first chip feature of the first layout; selecting a first operation from prestored operations based on the first vector array; and generating a second layout based on the first layout and the first operation.

Description

Technical Field

[0001] The present disclosure relates to methods and systems for repairing layout violations. Background Art

[0002] Design rule checking (DRC) violations in layout patterns are fixed through manual ad hoc analysis. Users rely solely on electronic design automation (EDA) tools to fix violations. Violations are fixed using a trial-and-error approach. To gain an overall picture of violations and layout patterns, each violation type is examined individually. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: receiving a design rule violation of a first layout; classifying a first violation of the design rule violation into a first category of a predefined category based on a first chip feature of the first layout; generating a first vector array associated with the first violation for at least one first chip feature of the first chip feature of the first layout; selecting a first operation from prestored operations based on the first vector array; and generating a second layout based on the first layout and the first operation.

[0004] According to a second aspect of the present disclosure, a system for manufacturing a semiconductor device is provided, comprising: a memory configured to store computer program code; and a processor configured to execute the computer program code in the memory to perform the following operations: classify the design rule violations into predefined categories based on data of design rule violations of a first layout of a chip; automatically assign a first operation of a prestored operation to each of the design rule violations based on the data of the design rule violations of the first layout; and generate a second layout based on the first layout and the first operation.

[0005] According to a third aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: classifying each of the design rule violations of a first layout of the chip into a predefined category based on chip features of the first layout, the chip features including at least one of a structural feature, an environmental feature, a violation type, or a circuit problem of the first layout; assigning a first operation of a prestored operation to the design rule violation based on a predefined category in the predefined categories and at least one chip feature of the chip features associated with each of the design rule violations; modifying the first layout based on the first operation to generate a second layout; and manufacturing the chip based on the second layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a flowchart of a method 100 of generating a layout according to some embodiments of the present disclosure.

[0008] Figure 2 is a flowchart of a method 200 of generating a layout according to various embodiments of the present disclosure.

[0009] Figure 3 is a block diagram of an electronic design automation (EDA) system 300 for designing an integrated circuit layout, according to some embodiments of the present disclosure.

[0010] Figure 4 is a flow chart of a method of identifying violations corresponding to routing congestion according to some embodiments of the present disclosure.

[0011] Figure 5 is an illustration 500 of repairing violations corresponding to routing congestion according to some embodiments of the present disclosure.

[0012] Figure 6 is a lookup table 600 configured to search for strategies to repair violations not associated with routing congestion, according to some embodiments of the present disclosure.

[0013] Figure 7 is an illustration 700 of adding a routing block according to some embodiments of the present disclosure.

[0014] Figure 8A is an illustration 800a of repairing violations associated with pin accesses according to some embodiments of the present disclosure.

[0015] Figure 8B is an illustration 800b of repairing violations associated with pin accesses according to some embodiments of the present disclosure.

[0016] Figure 9 is a flow chart of a method 900 of generating and evaluating repair strategies corresponding to violations of a layout, according to some embodiments of the present disclosure.

[0017] Figure 10 is a diagram illustrating the number of violations corresponding to different layouts according to some embodiments of the present disclosure.

[0018] Figure 11is a block diagram of an integrated circuit manufacturing system and an associated integrated circuit manufacturing flow according to some embodiments. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate the relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature relative to another element or feature(s) illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0021] The terms used throughout the following description and claims generally have their ordinary meanings in the art or in the specific context in which each term is used. One of ordinary skill in the art will understand that a component or process may be referred to by different names. The many different embodiments described in detail in this specification are merely illustrative and in no way limit the scope and spirit of the present disclosure or any exemplary term.

[0022] It is noteworthy that the terms used herein to describe various elements or processes (e.g., "first" and "second") are intended to distinguish one element or process from another. However, elements, processes, and their order should not be limited by these terms. For example, a first element may be referred to as a second element, and a second element may be similarly referred to as a first element, without departing from the scope of this disclosure.

[0023] In the following discussion and in the claims, the terms "including," "having," "comprising," "having," "involving," and the like should be construed as open ended, i.e., to include, but not be limited to. As used herein, the term "and / or" is not mutually exclusive, but rather includes any associated listed items and all combinations of one or more associated listed items.

[0024] Figure 1 FIG. 1 is a flow chart of a method 100 for generating a layout according to some embodiments of the present disclosure. Figure 1 As shown, method 100 includes operations 102, 104, 106, 108, and 110. In some embodiments, method 100 is performed to generate layout L2 based on layout L1. In some embodiments, method 100 is implemented during an engineer change order (ECO) phase of a chip manufacturing process.

[0025] like Figure 1 As shown, at operation 102, a design rule check (DRC) violation VL1 associated with a layout L1 and an automatic placement and routing (APR) database are received. In some embodiments, the DRC violation VL1 corresponds to a physical verification (PV) error of the layout L1. Examples of PV errors include, but are not limited to, violations due to missing redundant vias, metal spacing violations, antenna violations, well spacing violations, metal geometry violations (e.g., minimum area of ​​a particular metal layer), and the like.

[0026] At operation 104, the DRC violation VL1 is classified into categories CL11-CL13 according to chip features associated with the DRC violation VL1. Figure 1 As shown, the illegal FVs that can be repaired by ADF (Auto route DRC Fix) in the DRC violation VL1 belong to category CL11, the illegal NFVs that cannot be repaired by ADF and MDF (Manual DRC layout Fix) in the DRC violation VL1 belong to category CL12, and the illegal MFVs that cannot be repaired by ADF in the DRC violation VL1 but can be repaired by MDF belong to category CL13. In some embodiments, the operation of repairing the illegal FVs by ADF corresponds to operation 106, as will be discussed below.

[0027] At operation 106, a plurality of strategies STG are generated to repair the violation FV. In other words, a strategy STG is generated for a corresponding violation FV in the violation FV. In some embodiments, by Figure 3The strategy STG is generated by selecting an operation corresponding to the strategy STG from pre-stored operations in the memory 360 in the memory. In some embodiments, the strategy STG is applied to the layout L1 to fix the illegal FV of the layout L1, thereby generating the layout L2. In some embodiments, the strategy STG includes operations for generating, removing, and / or modifying at least one chip feature of the layout L1.

[0028] At operation 108, the layout L2 is diagnosed or evaluated. In some embodiments, in operation 108, a reduction ratio of a corresponding one of the violation types of the violating FVs associated with the layout L2 and a repair rate of the strategy STG are evaluated. The reduction ratio depends on the number of violations of the corresponding one of the violation types of the violating FVs before and after applying the strategy STG. The repair rate depends on the number of violating FVs, the number of violations repaired by the strategy STG, and the number of violations generated by the strategy STG. In some embodiments, the strategy STG is adjusted according to the reduction ratio and the repair rate. Further details of the reduction ratio and the repair rate are provided below in reference to Figure 9 is described in the embodiments of the present invention.

[0029] In some embodiments, after operation 108, operations 102, 104, 106, 108, and 110 are repeated while providing layout L2. For example, in operation 102, DRC violations associated with layout L2 and an APR (automatic place and route) database are received, and in operation 104, the DRC violations associated with layout L2 are classified into categories CL11-CL13.

[0030] At operation 110, a repair guide is generated based on the offending NVF. In some embodiments, the repair guide includes operations for repairing the offending NVF at a stage earlier than the ECO stage.

[0031] Figure 2 FIG. 2 is a flow chart of a method 200 for generating a layout according to various embodiments of the present disclosure. Figure 2 As shown, method 200 includes operations 202, 204, 206, 208, 210, and 212. In some embodiments, method 200 is performed to generate layout L2 (e.g., Figure 1 ), and method 200 includes comparing Figure 1 The operations of method 100 are described in more detail.

[0032] refer to Figure 1 right Figure 2To illustrate, at operation 202, the DRC violation VL1 is classified into categories CL21-CL23 based on the chip features of the layout L1 associated with the DRC violation VL1. In some embodiments, the classification includes generating a vector array for one of the DRC violations VL1 based on the chip features, and classifying the one of the DRC violations VL1 into one of the three categories CL21-CL23 based on the vector array. In some other embodiments, each DRC violation VL1 has a corresponding vector array as a reference for classification. In other words, the DRC violation VL1 is classified into CL21-CL23 based on the corresponding vector array. In some embodiments, each parameter in the vector array corresponds to an aspect of the corresponding violation. For example, Figure 6 As shown, row R62 is a vector array corresponding to violation V61. Referring to row R61, row R62 includes parameters at different levels corresponding to different aspects of violation V61, including, for example, violation type, shape, environmental conditions, and category of violation V61.

[0033] In some embodiments, the hardware of an electronic design automation (EDA) system (e.g., Figure 3 In some embodiments, the classification is performed by a processor that performs a classification algorithm on the DRC violation VL1. For example, Figure 3 As shown, the classification is performed by processor 320 of EDA system 300, which implements a classification algorithm stored in memory 360 of EDA system 300. In some embodiments, the classification algorithm corresponds to Figure 1 and / or Figure 2 Operations 104 and / or 202 are shown.

[0034] In some embodiments, category CL21 corresponds to a violation CV in DRC violation VL1 that is associated with routing congestion of layout L1, category CL22 corresponds to a violation NCV in DRC violation VL1 that is not associated with routing congestion, and category CL23 corresponds to a violation NFV2 in DRC violation VL1 that cannot be fixed by ADF method 200. In some embodiments, the violation CV and NCV are selected from Figure 1 The violation FV in , and therefore, the violation CV and NCV correspond to Figure 1 In some embodiments, the offending NFV2 corresponds to Figure 1 Violated NFVs and MFVs that cannot be fixed by ADF in the system.

[0035] In various embodiments, violations NFV2 are identified from DRC violations VL1 based on various conditions. In some embodiments, the conditions relate to input / output pins of layout L1. For example, the conditions include: pins not being placed, pin-to-pin spacing violations, pin NDR (non-default rule) width violations, pin short violations, pins not centered on a wire trace, pins with pin locations outside the die boundary, or clock pin layers below the preferred minimum layer constraint. In some embodiments, the conditions relate to routing blockages of layout L1. For example, the conditions include: violations or shorts in cluster areas due to routing blockages taking up too many routing resources, non-preferred routing mode violations due to routing blockages taking up too many routing resources, violations on macro pins due to routing blockages blocking pin access, or shorts with routing blockages. In some embodiments, the conditions relate to violations on repaired metal shapes.

[0036] At operation 204, based on the chip features associated with the illegal CV and NCV, a strategy STG2 for repairing the illegal CV and NCV is generated. In some embodiments, the strategy STG2 is customized for the illegal CV and NCV. In some embodiments, the strategy STG2 is selected from a repair strategy pool stored in a memory. In some embodiments, the illegal CV and NCV correspond to different repair strategy pools. Therefore, for the illegal CV, it is only necessary to select the strategy STG2 from the repair strategy pool corresponding to the illegal CV, and thus save the time of selecting STG in the repair strategy pool corresponding to the illegal NCV. Reference Figure 1 right Figure 2 For explanation, the policy STG2 is an example of the policy STG described above.

[0037] At operation 206, the repair rate and reduction rate associated with the violations CV, NCV, and strategy STG2 are evaluated. In some embodiments, violations associated with pin access are identified and repaired by a strategy that includes operations selected from pre-stored operations. Further details of violations associated with pin access are described below in conjunction with Figure 8A and Figure 8B In some embodiments, at operation 206 , the reduction ratio of the strategy STG2 corresponding to the respective violation types of the violation CV and NCV is quantified.

[0038] At operation 208, a database is generated based on the correction between the APR and PV associated with layout L1, the marking of the correctable violation of DRC violation VL1, and the violation newly created or retained after the strategy STG2 is executed. In some embodiments, the database is a Calibre result database (RDB).

[0039] At operation 210 , violations of different layouts are tracked. For example, an engineering change order (ECO) DRC tracking is performed to track the number of violations of different layouts (eg, layouts L1 and L2 ).

[0040] At operation 212 , data DT2 associated with the pattern and surroundings of DRC violations VL1 are accumulated for use in adjusting the repair strategy pool. In some embodiments, appropriate strategies for violations not stored in the strategy pool of method 200 are predicted and generated based on the violations CV, NCV, and strategy STG2 .

[0041] Figure 3 is a block diagram of an electronic design automation (EDA) system 300 for designing an integrated circuit layout according to some embodiments of the present disclosure. The EDA system 300 is configured to implement Figure 1 Method 100 disclosed in Figure 2 In some embodiments, the EDA system 300 includes an APR system.

[0042] In some embodiments, EDA system 300 is a general-purpose computing device that includes a hardware processor 320 and a non-transitory computer-readable storage medium 360. Storage medium 360 is encoded with (i.e., stores) computer program code (instructions) 361 (i.e., a set of executable instructions). Hardware processor 320 executes instructions 361 (at least in part) on behalf of an EDA tool that implements a portion or all of a method, including, for example, method 100 and / or method 200.

[0043] The processor 320 is electrically coupled to a computer-readable storage medium 360 via a bus 350. The processor 320 is also electrically coupled to an I / O interface 310 and a manufacturing tool 370 via the bus 350. The network interface 330 bus 320 is also electrically connected to the processor 320 via the bus 350. The network interface 330 is connected to a network 340, and thus, the processor 320 and the computer-readable storage medium 360 can be connected to external components via the network 340. The processor 320 is configured to execute computer program code 361 encoded in the computer-readable storage medium 360 to enable the EDA system 300 to perform part or all of the processes and / or methods described. In one or more embodiments, the processor 320 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0044] In one or more embodiments, the computer-readable storage medium 360 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or component). For example, the computer-readable storage medium 360 includes semiconductor or solid-state memory, magnetic tape, a removable computer disk, random access memory (RAM), read-only memory (ROM), a rigid disk, and / or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 360 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disk (DVD).

[0045] In one or more embodiments, the storage medium 360 stores computer program code 361 configured to enable the EDA system 300 (where such execution (at least in part) represents an EDA tool) to perform some or all of the processes and / or methods described. In one or more embodiments, the storage medium 360 also stores information that facilitates the execution of some or all of the processes and / or methods described. In one or more embodiments, the storage medium 360 stores a library 362 of standard cells, including standard cells of the type disclosed herein, including, for example, the following references to Figure 7 The unit of the wiring barrier 716 discussed, or including the following reference Figure 10 The cells of the active areas AA1-AA4 are discussed.

[0046] In one or more embodiments, the storage medium 360 stores a layout 364, which corresponds to, for example, layouts L1 and L2. In one or more embodiments, the storage medium 360 stores a pattern data field 365, which is configured to accumulate and Figure 2 Operation 212 schematically illustrates the data DT2 associated with the pattern of DRC violation VL1 and its surroundings. In some embodiments, pattern data field 365 is configured to form a large data database for strategic design improvement. In some embodiments, pattern data field 365 is configured to perform at least one test on data DT2 to identify areas for improvement. In some embodiments, pattern data field 365 is configured to extract chip features from data DT2, including, for example, numerical and image-based attributes of layouts L1 and L2.

[0047] In one or more embodiments, the storage medium 360 is a memory storing computer program code. The computer program code corresponds to the above Figure 1 and Figure 2and is configured to be executed by the processor 320. In one or more embodiments, the processor 320 is configured to execute the computer program code in the memory to perform the following operations: according to the data (e.g., Figure 6 ), classifying the design rule violations into predefined categories (e.g., categories CL11-CL13) based on the data of the design rule violations of the first layout; automatically assigning a first operation (e.g., an operation corresponding to a box in column C67) of prestored operations (e.g., an operation corresponding to a box in column C67 of the lookup table 600) to each design rule violation based on the data of the design rule violations of the first layout; and generating a second layout (e.g., layout L2) based on the first layout and the first operation.

[0048] EDA system 300 includes an I / O interface 310. I / O interface 310 is coupled to external circuitry. In one or more embodiments, I / O interface 310 includes a keyboard, keypad, mouse, trackball, touchpad, touch screen, and / or cursor direction keys for communicating information and commands to processor 320.

[0049] EDA system 300 also includes a network interface 330 coupled to processor 320. Network interface 330 allows EDA system 300 to communicate with a network 340 connecting one or more other computer systems. Network interface 330 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods (including, for example, method 100 and / or method 200) described are implemented in two or more systems, including EDA system 300.

[0050] The EDA system 300 also includes a fabrication tool 370 coupled to the processor 320. The fabrication tool 370 is configured to fabricate and layout (including, for example, Figure 1 、 Figure 8A and Figure 8B The chip corresponding to the layout L2, L82a, L82b) shown.

[0051] The EDA system 300 is configured to receive information via an I / O interface 310. The information received via the I / O interface 310 includes one or more of instructions, data, design rules, a library of standard cells, and / or other parameters for processing by the processor 320. This information is transmitted to the processor 320 via a bus 350. The EDA system 300 is configured to receive information related to a UI via the I / O interface 310. This information is stored in a computer-readable medium 360 as a user interface (UI) 363.

[0052] In some embodiments, part or all of the processes and / or methods described are implemented as standalone software applications for execution by a processor. In some embodiments, part or all of the processes and / or methods described are implemented as software applications that are part of an add-on software application. In some embodiments, part or all of the processes and / or methods described are implemented as plug-ins to a software application. In some embodiments, at least one of the processes and / or methods described is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods described are implemented as software applications used by the EDA system 300. In some embodiments, software such as those available from CADENCE DESIGN SYSTEMS, Inc. is used. or other suitable layout generation tools to generate a layout including standard cells.

[0053] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, for example, one or more of an optical disk such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as a ROM, RAM, a memory card, and the like.

[0054] Figure 4 FIG. 4 is a flow chart of a method 400 for identifying violations corresponding to routing congestion according to some embodiments of the present disclosure. Figure 4 As shown, method 400 includes operations 402, 404, 406, 408, 410, and 412. In some embodiments, method 400 is performed to Figure 1 In some embodiments, the violation CV associated with the routing congestion is located in a corresponding cluster box area, including, for example, the cluster box area associated with operation 410 .

[0055] At operation 402, a position value LV4 of a corresponding one of the violating FVs is received. In other words, a plurality of position values ​​LV4 of the violating FVs are received. In some embodiments, one of the violating FVs is generated on layer LY of layout L1. In other words, the violating FVs are correspondingly generated on a plurality of layers LY of layout L1. In some embodiments, the layer LY of the one of the violating FVs is identified based on the position value LV4 of the one of the violating FVs.

[0056] At operation 404 , a DBSCAN (Density-based spatial clustering of applications with noise) algorithm is executed based on the location value LV4 associated with the offending FV and the chip features. In some embodiments, the DBSCAN algorithm is executed to identify cluster box regions of the layout L1.

[0057] At operation 406, an equivalent metal density value EMD associated with the offending FV is generated. In some embodiments, the equivalent metal density value EMD is given by EMD=∑ LY1∈LY RT(LY1)×MD(LY1) is defined, where layer LY1 is one of the layers LY, ratio RT(LY1) is the ratio of the number of violations on layer LY1 to the total number of DRC violations VL1 of layout L1, and metal density MD(LY1) is the metal density of layer LY1.

[0058] At operation 408, a violation V41 is identified from the violation FV according to the equivalent metal density value EMD. In some embodiments, the violation V41 is identified when the equivalent metal density value EMD meets the filtering criteria. Figure 4 As shown, the filtering criteria include an equivalent metal density value EMD being greater than or equal to a value in the range of 0.25-0.3. In some embodiments, violation V41 is considered a cluster candidate for layout L1.

[0059] At operation 410, violations V41 are processed by a cluster block filter. In some embodiments, the cluster block filter evaluates a number N4 of violations in a cluster block region surrounding a corresponding one of the violations V41. In other words, the number N4 of violations in cluster block regions surrounding a corresponding plurality of violations V41 is evaluated. In some embodiments, each cluster block region has a size greater than or equal to 1.0 μm×1.0 μm.

[0060] At operation 412, a violating CV is identified from the violating V41 based on the number N4 of violating V41. In some embodiments, the violating CV is identified when the number N4 is greater than or equal to 10. In some embodiments, cluster box regions where the number N4 is greater than or equal to 10 are considered valid cluster boxes. When the violating CV is located in a valid cluster box, the violating CV corresponds to routing congestion.

[0061] Figure 5 FIG5 is a diagram 500 of repairing violations corresponding to routing congestion according to some embodiments of the present disclosure. Figure 5 As shown, diagram 500 includes states S51 and S52 of the layout. Violation V51 associated with routing congestion (shown in state S51) is fixed, and thus routing is modified (shown in state S52). In some embodiments, violation V51 is associated with routing congestion. Figure 4 The operation 412 shown in FIG. 4 corresponds to one of the violating CVs.

[0062] At state S51, the wire 514 that passes through the congested area 512 to connect the points P51 and P52 is detected as a violation V51. Therefore, a corresponding strategy STG5 is generated to repair the violation V51. In some embodiments, the strategy STG5 includes an operation of guiding the wire 514 to bypass the congested area 512.

[0063] At state S52, wire 516 connects points P51 and P52 and does not pass through congested area 512. Furthermore, in some embodiments, wire 516 does not contact congested area 512. Therefore, by replacing wire 514 with wire 516 according to policy STG5, violation V51 is fixed.

[0064] The strategy for fixing violations associated with routing congestion is not limited to strategy STG5. For example, in some other embodiments, the strategy includes relocating buffers associated with congested areas to alleviate the congestion, such as corresponding to congested area 512.

[0065] Figure 6 is a lookup table 600 according to some embodiments of the present disclosure, which is configured to search for strategies to repair violations that are not associated with routing congestion. In some embodiments, the lookup table 600 corresponds to Figure 1 Operation 106 and / or Figure 2 In some embodiments, the operation 204 in the embodiment corresponds to generating a policy for remediating the violation. Figure 9 Operations S91 and S92 of the method 900 shown in FIG. 9 obtain the contents of the lookup table 600 , which will be discussed in more detail below.

[0066] like Figure 6As shown, the lookup table 600 includes rows R61-R66 and columns C61-C67. Row R61 includes descriptions corresponding to columns C61-C67. One of rows R62-R66 corresponds to one of the violation NCVs in the DRC violation VL1 that is not associated with routing congestion, such as Figure 2 In other words, the five rows R62-R66 correspond to five violations in the NCV violation that are not associated with routing congestion.

[0067] like Figure 6 The description shown in row R61 of , column C61 corresponds to the technology nodes of the offending manufacturing processes, for example, technology nodes n6, n7, and n22.

[0068] like Figure 6 As shown, columns C62-C66 correspond to the classification conditions for NCV violations. Column C62 corresponds to the violation type for violations with only a rule name. Column C63 corresponds to the violation type for violations with some explanation. For example, the violation type corresponds to antenna violations, cut spacing, and metal shorts. Column C64 corresponds to the shape of the violation. For example, the shape corresponds to operating signals only, clock signals only, and operating signals to clock signals. In some embodiments, operating signals include, but are not limited to, control signals and data signals of the chip corresponding to lookup table 600. Column C65 corresponds to the surrounding environment associated with the NCV violation. For example, the surrounding environment of the violation corresponds to fat pins, local congestion, and violations under macros. Column C66 corresponds to the category of the violation. For example, the category of the violation corresponds to short circuit issues, pin access issues, bad via issues, and other circuit issues. In summary, columns C62-C66 are classification conditions corresponding to the structural characteristics, environmental characteristics, violation type, or circuit issues of the NCV violation of layout L1.

[0069] like Figure 6 As shown, column C67 corresponds to a strategy generated based on the classification conditions in columns C62-C66 of the violation NCV. In some embodiments, the generation of the strategy includes selecting an operation from pre-stored operations. For example, the violation condition of violation V61 is shown by the box at the intersection of row R62 and columns C62-C66. According to the box in row R62, the violation type of violation V61 corresponds to adjacent cuts of the same mask pitch, the shape of violation V61 corresponds to only operating signals, the surrounding environment of violation V61 corresponds to violation V61 being blocked by polysilicon gate (PG), and the category of violation V61 corresponds to a short circuit problem. Therefore, based on the violation condition associated with violation V61 as described above, a corresponding strategy for the mobile unit is generated, which is shown at the intersection of column C67 and row R62. In some embodiments, the strategy is selected from Figure 2 The repair strategy pool described in method 200.

[0070] Figure 7FIG. 700 is a diagram of adding a routing barrier according to some embodiments of the present disclosure. Figure 7 As shown, diagram 700 includes states S71 and S72. Figure 6 right Figure 7 For illustration, the strategy STG7 for adding a routing barrier corresponding to the violation V62 of row R63 is described in further detail below. The violation V62 shown in state S71 needs to be repaired by adding a routing barrier 716, and thus the routing barrier 716 is added in state S72.

[0071] like Figure 7 As shown, at state S71, strategy STG7 is generated to repair violation V62. Mark 712 marks the location of violation V62. The edge of region 714 extends to points P71-P74. In some embodiments, marking is made at operation 208, such as Figure 2 shown.

[0072] At state S72, routing barrier 716 is added to region 714 and covers marker 712. Figure 7 As shown, the edge of routing barrier 716 extends to points P71, P74 and the edge of region 714. In some embodiments, shapes and vias in region 714 are removed according to strategy STG7.

[0073] Figure 8A FIG. 8 is an illustration 800a of fixing a violation associated with a pin access according to some embodiments of the present disclosure. Figure 8A As shown, diagram 800a includes states S81a and S82a. Layouts L81a and L82a correspond to states S81a and S82a, respectively. In some embodiments, diagram 800a corresponds to fixing a violation of a short circuit problem associated with pin accesses of layout L81a. A violation of a short circuit problem is fixed in layout L82a. In some embodiments, the operation corresponding to diagram 800a corresponds to Figure 1 Operation 106 and / or Figure 2 Operation 204 in.

[0074] like Figure 8A As shown, the layout L81a is modified according to the strategy STG8a to generate the layout L82a. In some embodiments, the strategy STG8a is generated according to the layout L81a to fix the short circuit problem associated with the pin access of the layout L81a.

[0075] like Figure 8A As shown, both layouts L81a and L82a include power supply lines VDD, VSS and active areas AA1-AA4. Compared with layout L81a, layout L82a also includes blockers BK1-BK8.

[0076] At state S81a, active areas AA1-AA4 are configured to serve as pin accesses for layout L81a.A short circuit problem associated with active areas AA1 and AA2 is detected, and strategy STG8a is generated accordingly.

[0077] At state S82a, according to strategy STG8a, blockers BK1-BK8 are generated to fix the short circuit issue. Layout L82a is generated by method 800a based on the violations associated with the short circuit issue in layout L81a and strategy STG8a. In some embodiments, blockers BK1-BK8 block other components on layout L81a from contacting power lines VDD and VSS and active areas AA1-AA4, thereby preventing the short circuit issue.

[0078] Figure 8B FIG8 is an illustration 800b of fixing a violation associated with a pin access according to some embodiments of the present disclosure. Figure 8B As shown, diagram 800b includes states S81b and S82b. Layouts L81b and L82b correspond to states S81b and S82b, respectively. In some embodiments, diagram 800b corresponds to fixing a violation of a short circuit problem associated with pin accesses of layout L81b. The violation of the short circuit problem is fixed in layout L82b. In some embodiments, the operation corresponding to diagram 800b corresponds to Figure 1 Operation 106 and / or Figure 2 Operation 204 in.

[0079] like Figure 8B As shown, the layout L81b is modified according to the strategy STG8b to generate the layout L82b. In some embodiments, the strategy STG8b is generated according to the layout L81b to fix the short circuit problem. Figure 8B The layouts L81b and L82b have the same Figure 8A The layouts L81a and L82a are similar in structure, so Figure 8B Follow and Figure 8A Similar markup conventions.

[0080] like Figure 8B As shown, both layouts L81b and L82b include power lines VDD and VSS and active areas AA1-AA4. Compared to layout L81b, layout L82b also includes pin blocks MP1-MP4. In some embodiments, pin blocks MP1-MP4 and active areas AA1-AA4 are located in different layers of layout L82b. For example, active areas AA1-AA4 are located in the metal zero (M0) layer of layout L82b, while pin blocks MP1-MP4 are located in the metal one (M1) layer of layout L82b.

[0081] At state S81b, active areas AA1-AA4 are configured to serve as pin accesses for layout L81b.A short circuit issue associated with active areas AA3 and AA2 is detected, and strategy STG8b is generated accordingly.

[0082] At state S82b, according to strategy STG8b, pin barriers MP1-MP4 are generated for use as pin accesses for layout L82b, and active areas AA1-AA4 are not configured for use as pin accesses for layout L82b, thereby fixing the short circuit issue. Layout L82b is generated by method 800b according to the violations associated with the short circuit issue in layout L81b and strategy STG8b.

[0083] Figure 9 FIG. 9 is a flow chart of a method 900 for generating and evaluating a repair strategy corresponding to a layout violation according to some embodiments of the present disclosure. Figure 9 As shown, method 900 includes operations S91-S94. In the following description, for the purpose of illustration and not limitation, reference is made to Figure 1 、 Figure 2 and Figure 6 In some embodiments, method 900 corresponds to Figure 1 Operation 108 and / or Figure 2 Operation 206 in.

[0084] At operation S91, data associated with the DRC violation VL1 of the layout L1 is received and analyzed to obtain corresponding classification conditions, such as the violation type, shape, surrounding environment, and category of the DRC violation VL1. Figure 6 shown.

[0085] At operation S92, based on the data associated with the DRC violation VL1, a strategy STG is generated for repairing the violating FVs that the ADF can repair. In some embodiments, at operation S92, violating FVs, violating NFVs that neither the ADF nor the MDF can repair, and violating MFVs that the ADF cannot repair but the MDF can repair are identified from the DRC violation VL1.

[0086] At operation S93, a repair rate FR for the strategy STG is generated. In some embodiments, the repair rate FR is associated with a number N91-N93. The number N91 is the number of violations FV for layout L1. The number N92 is the number of violations repaired by the strategy STG. The number N93 is the number of violations generated after applying the strategy STG to layout L1. For example, the repair rate FR is equal to (N91-N92+N93) / N91.

[0087] At operation S94, a reduction ratio RR for a corresponding one of the violation types is generated. In other words, a plurality of reduction ratios RR are generated to correspond to each of the violation types. In some embodiments, the reduction ratio RR1 for one of the violation types is associated with numbers N94 and N95. Number N94 is the number of violations of the one of the violation types before strategy STG is applied to layout L1. Number N95 is the number of violations of the one of the violation types after strategy STG is applied to layout L1. For example, reduction ratio RR1 is equal to 1-(N95 / N94).

[0088] In some embodiments, at least one of the above methods 100, 200, 400, 500, 700, 800a, 800b, and 900 is performed by Figure 3 The EDA system 300 is implemented in.

[0089] Figure 10 FIG. 1 is a schematic diagram showing the number of violations corresponding to different layouts according to some embodiments of the present disclosure. Figure 10 As shown, graph 1000 includes a horizontal axis corresponding to layouts L101-L104 and a vertical axis corresponding to the number of total violations and the number of repairable violations of the respective layouts L101-L104. For example, graph 1000 shows that the number of total violations and the number of repairable violations of layout L101 are both greater than 30. For example, graph 1000 shows that the number of total violations of layout L103 is greater than the number of repairable violations of layout L103.

[0090] like Figure 10 As shown, point P101 corresponds to the total violations of layouts L101-L104 (including e.g. Figure 1 Point P102 corresponds to the number of repairable violations of layout L101-L104 that can be automatically repaired by ADF (including, for example, Figure 1 The number of violations FV).

[0091] In some embodiments, layout L101 is modified using at least one of the above-described methods 100, 200, 400, 500, 700, 800a, 800b, and 900 for repairing violations to generate layout L102. Therefore, the total number of violations and the number of repairable violations in layout L102 are less than the total number of violations and the number of repairable violations in layout L101. Similarly, in some embodiments, layout L103 is generated by modifying layout L102, and layout L104 is generated by modifying layout L103.

[0092] In some embodiments, the total violations correspond to Figure 1 The DRC violation in VL1, and the fixable violation corresponds to Figure 1 In some embodiments, layout L101 corresponds to layout L1, and layout L102 corresponds to the violation FV in FIG. Figure 1 The method 100 modifies the layout L1 and generates the layout L2.

[0093] like Figure 10 As shown, at layout L103 , the number of total violations is greater than the number of repairable violations, which means that layout L103 has at least one violation that cannot be repaired by ADF and thus requires manual repair.

[0094] exist Figure 11 In the present invention, IC manufacturing system 1100 includes entities that interact with each other in the design, development, and manufacturing cycles and / or services related to manufacturing IC devices 1140, such as design room 1110, mask room 1120, and IC manufacturer / fabricator ("fab") 1130. The entities in IC manufacturing system 1100 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of design room 1110, mask room 1120, and IC fab 1130 are owned by a single larger company. In some embodiments, two or more of design room 1110, mask room 1120, and IC fab 1130 coexist in a common facility and use common resources.

[0095] The design office (or design team) 1110 generates an IC design layout 1111. The IC design layout 1111 includes various geometric patterns, such as those discussed above. Figure 8A and / or Figure 8B 11. The IC layout design depicted in FIG. The geometric pattern corresponds to the pattern of the metal, oxide or semiconductor layers of the various components that make up the IC device 1140 to be manufactured. The various layers are combined to form various IC functions. For example, a portion of the IC design layout 1111 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate, such as active areas, gate electrodes, source and drain electrodes, conductive segments or through-holes for interconnecting layers. The design room 1110 implements an appropriate design process to form the IC design layout 1111. The design process includes one or more of logic design, physical design, or layout and routing. The IC design layout 1111 is presented in one or more data files having geometric pattern information. For example, the IC design layout 1111 can be expressed in a GDSII file format or a DFII file format.

[0096] The mask chamber 1120 includes data preparation 1121 and mask fabrication 1122. The mask chamber 1120 uses the IC design layout 1111 to fabricate one or more masks 1123 for fabricating various layers of an IC device 1140 according to the IC design layout 1111. The mask chamber 1120 performs mask data preparation 1121, wherein the IC design layout 1111 is converted into a representative data file ("RDF"). The mask data preparation 1121 provides the RDF for mask fabrication 1122. The mask fabrication 1122 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1123 or a semiconductor wafer 1133. The IC design layout 1111 is processed by the mask data preparation 1121 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1130. In Figure 11 , data preparation 1121 and mask fabrication 1122 are shown as separate elements. In some embodiments, data preparation 1121 and mask fabrication 1122 may be collectively referred to as mask data preparation.

[0097] In some embodiments, data preparation 1121 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other processing effects, etc. OPC adjusts the IC design layout 1111. In some embodiments, data preparation 1121 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or a combination thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0098] In some embodiments, data preparation 1121 includes a mask rule checker (MRC) that checks an IC design layout 1111 that has been processed in OPC using a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1111 to compensate for the constraints during mask fabrication 1122, which may undo a portion of the modifications performed by the OPC to satisfy the mask creation rules.

[0099] In some embodiments, data preparation 1121 includes a lithography process check (LPC), which simulates the process that will be implemented by IC fab 1130 to manufacture IC device 1140. LPC simulates the process based on IC design layout 1111 to create a simulated manufactured device, such as IC device 1140. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as projection contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or a combination thereof. In some embodiments, after the simulated manufactured device is created by LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 1111.

[0100] It should be understood that the above description of data preparation 1121 has been simplified for clarity. In some embodiments, data preparation 1121 includes additional features, such as logic operations (LOPs), to modify IC design layout 1111 according to manufacturing rules. In addition, the processes applied to IC design layout 1111 during data preparation 1121 can be performed in a variety of different orders.

[0101] After data preparation 1121 and during mask manufacturing 1122, a mask 1123 or a mask set 1123 is manufactured based on the modified IC design layout 1111. In some embodiments, mask manufacturing 1122 includes performing one or more photolithographic exposures based on the IC design layout 1111. In some embodiments, a pattern is formed on a mask (photomask or reticle) 1123 based on the modified IC design layout 1111 using an electron beam (e-beam) or a plurality of electron beams. Mask 1123 can be formed using various techniques. In some embodiments, binary technology is used to form mask 1123. In some embodiments, the mask pattern includes opaque areas and transparent areas. The radiation beam (e.g., an ultraviolet (UV) beam) used to expose the image sensitive material layer (e.g., photoresist) already coated on the wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of mask 1123 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 1123 is formed using phase shift technology. In a phase shift mask (PSM) version of mask 1123, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask(s) generated by mask manufacturing 1122 are used in various processes. For example, such mask(s) are used in ion implantation processes to form various doped regions in semiconductor wafer 1133, in etching processes to form various etched regions in semiconductor wafer 1133, and / or in other suitable processes.

[0102] IC fab 1130 includes wafer fabrication 1132. IC fab 1130 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC Fab 1130 is a semiconductor foundry. For example, one fabrication facility may be used for front-end-of-line (FEOL) fabrication of multiple IC products, while a second fabrication facility may provide back-end-of-line (BEOL) fabrication for interconnection and packaging of IC products, and a third fabrication facility may provide other services for the foundry business.

[0103] IC fab 1130 uses mask(s) 1123 manufactured by mask chamber 1120 to manufacture IC devices 1140. Thus, IC fab 1130 at least indirectly uses IC design layout 1111 to manufacture IC devices 1140. In some embodiments, IC fab 1130 uses mask(s) 1123 to manufacture semiconductor wafer 1133 to form IC devices 1140. In some embodiments, IC fabrication includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1111. Semiconductor wafer 1133 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 1133 also includes one or more of various doped regions, dielectric features, multi-layer interconnects, etc. (formed in subsequent fabrication steps).

[0104] In methods 100 and 200 for automatically classifying DRC violations and generating corresponding repair strategies, DRC violations are systematically repaired. Users can understand DRC violations based on the classification. Violations associated with routing congestion are identified to avoid unnecessary attempts at non-congestion strategies. Compared to manually repairing DRC violations, the number of DRC violations after ADF is reduced. Furthermore, repair time is also reduced.

[0105] A method is also disclosed, including: receiving a design rule violation of a first layout; classifying a first violation of the design rule violation into a first category of a predefined category based on a first chip feature of the first layout; generating a first vector array associated with the first violation for at least one first chip feature of the first layout; selecting a first operation from prestored operations based on the first vector array; and generating a second layout based on the first layout and the first operation.

[0106] Also disclosed is a system including a memory and a processor. The memory is configured to store computer program code. The processor is configured to execute the computer program code in the memory to perform the following operations: classify the design rule violations into predefined categories based on data of design rule violations of a first layout of a chip; automatically assign a first pre-stored operation to each of the design rule violations based on the data of design rule violations of the first layout; and generate a second layout based on the first layout and the first operation.

[0107] A method is also disclosed, including: classifying each of the design rule violations of the first layout into a predefined category based on chip characteristics of the first layout of the chip, the chip characteristics including at least one of a structural feature, an environmental feature, a violation type, or a circuit problem of the first layout; assigning a first operation of a prestored operation to the design rule violation based on a predefined category in the predefined categories and at least one chip feature in the chip characteristics associated with each of the design rule violations; modifying the first layout based on the first operation to generate a second layout; and manufacturing the chip based on the second layout.

[0108] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0109] Example 1. A method for manufacturing a semiconductor device, comprising: receiving a design rule violation of a first layout; classifying a first violation of the design rule violation into a first category of a predefined category based on a first chip feature of the first layout; generating a first vector array associated with the first violation for at least one first chip feature of the first chip feature of the first layout; selecting a first operation from prestored operations based on the first vector array; and generating a second layout based on the first layout and the first operation.

[0110] Example 2. The method of Example 1, further comprising evaluating a repair rate of the first operation corresponding to the first layout by comparing a number of design rule violations of the first layout with a number of design rule violations of the second layout.

[0111] Example 3. The method of Example 1, further comprising: identifying the first violation for which the pre-stored operation is not performed based on at least one first chip feature of the first layout.

[0112] Example 4. The method of Example 1, wherein classifying the first violation comprises identifying the first violation corresponding to routing congestion based on a metal density of a layer in the first layout where the first violation is generated, and a ratio of the number of violations on the layer to the total number of design rule violations of the first layout.

[0113] Example 5. The method of Example 4, wherein selecting the first operation from the pre-stored operations comprises: when the first violation corresponds to the routing congestion, selecting the first operation from among the pre-stored operations that correspond to the routing congestion.

[0114] Example 6. The method of Example 1, wherein generating the first vector array comprises generating the first vector array based on at least one environmental feature in the first chip features, wherein the at least one environmental feature is associated with the first violation.

[0115] Example 7. The method according to Example 1 further includes: accumulating a first value corresponding to the design rule violation and a second value corresponding to the surrounding environment associated with the design rule violation; and generating at least one of the pre-stored operations based on the first value and the second value.

[0116] Example 8. The method according to Example 1 further includes: receiving a design rule violation of the second layout; classifying a second violation of the design rule violation of the second layout into a second category of the predetermined category based on a second chip feature of the second layout; generating a second vector array associated with the second violation for at least one second chip feature of the second layout; selecting a second operation from the pre-stored operations based on the second vector array; and generating a third layout based on the second layout and the second operation.

[0117] Example 9. The method according to Example 1 further includes: determining whether the first violation belongs to a category corresponding to a pin access; wherein, when the first violation belongs to a category corresponding to the pin access, the first operation includes at least one of the following: adding a blockage on the first cell where the first violation is generated; assigning a layer other than the layer of the first cell to at least one pin access in the pin access; or determining a fill value between the first cell and a second cell adjacent to the first cell.

[0118] Example 10. The method of Example 1, wherein the pre-stored operation comprises at least one of: generating at least one chip feature; removing at least one chip feature; or modifying at least one chip feature.

[0119] Example 11. The method of Example 1, wherein selecting the first operation comprises automatically selecting, by a processor of a computer, the first operation from the pre-stored operations stored in a memory of the computer.

[0120] Example 12. A system for manufacturing a semiconductor device, comprising: a memory configured to store computer program code; and a processor configured to execute the computer program code in the memory to perform the following operations: classify the design rule violations into predefined categories based on data of design rule violations of a first layout of a chip; automatically assign a first operation of a prestored operation to each of the design rule violations based on the data of the design rule violations of the first layout; and generate a second layout based on the first layout and the first operation.

[0121] Example 13. The system of Example 12, wherein the processor is further configured to compare the number of design rule violations of the first layout with the number of design rule violations of the second layout to generate a repair rate for the first operation corresponding to the first layout, and the processor is further configured to adjust the first operation based on the repair rate.

[0122] Example 14. The system of Example 12, wherein the memory is further configured to store data associated with at least one of a structural characteristic, an environmental characteristic, a violation type, or a circuit problem.

[0123] Example 15. The system of Example 12, wherein the processor is further configured to classify each of the design rule violations into a category of routing congestion, a category of non-congestion, or a category where the pre-stored operation is not performed on the design rule violation.

[0124] Example 16. The system of Example 12, wherein the processor is further configured to add blocking on the first layout or rearrange the pin access according to the data when the design rule violation is associated with the pin access of the first layout.

[0125] Example 17. A method for manufacturing a semiconductor device, comprising: classifying each of the design rule violations of a first layout of the chip into a predefined category based on chip characteristics of the first layout, the chip characteristics including at least one of a structural feature, an environmental feature, a violation type, or a circuit problem of the first layout; assigning a first operation of a prestored operation to the design rule violation based on a predefined category in the predefined categories and at least one chip feature of the chip characteristics associated with each of the design rule violations; modifying the first layout based on the first operation to generate a second layout; and manufacturing the chip based on the second layout.

[0126] Example 18. A method according to Example 17, wherein classifying each of the design rule violations of the first layout into the predefined category includes: identifying the first violation corresponding to a category in the predefined category in which the pre-stored operation is not performed based on at least one chip feature of the chip features associated with the first violation of the design rule violations; and identifying the first violation corresponding to a category in the predefined category corresponding to wiring congestion based on a metal density of a layer in the first layout in which the first violation is generated and a ratio of the number of violations on the layer to the total number of design rule violations of the first layout, when the first violation does not correspond to a category in which the pre-stored operation is not performed.

[0127] Example 19. The method of Example 18, wherein when the first violation corresponds to the category of the routing congestion, the method further comprises: routing a metal line to bypass the routing congestion; or relocating a buffer in the area of ​​the routing congestion.

[0128] Example 20. A method according to Example 18, wherein assigning the first operation to the design rule violation includes: automatically assigning, by a processor of the computer, at least one of the first operations stored in a memory of the computer to the first violation based on at least one of the chip features associated with the first violation, wherein the at least one of the first operations includes at least one of the following: generating at least one chip feature; removing at least one chip feature; or modifying at least one chip feature.

Claims

1. A method for manufacturing a semiconductor device, comprising: receiving a design rule violation for a first layout; classifying a first violation of the design rule violation into a first category of predefined categories based on a first chip feature of the first layout; generating a first vector array associated with the first violation for at least one first chip feature of the first layout; selecting a first operation from pre-stored operations according to the first vector array; as well as generating a second layout based on the first layout and the first operation, Classifying the first violation includes: identifying the first violation corresponding to wiring congestion based on the metal density of the layer in the first layout where the first violation is generated, and the ratio of the number of violations on the layer to the total number of design rule violations of the first layout.

2. The method according to claim 1, further comprising: A repair rate of the first operation corresponding to the first layout is evaluated by comparing the number of design rule violations of the first layout with the number of design rule violations of the second layout.

3. The method according to claim 1, further comprising: The first violation for which the pre-stored operation is not performed is identified based on at least one first chip feature of the first layout.

4. The method according to claim 1, wherein Selecting the first operation from the pre-stored operations includes: When the first violation corresponds to the routing congestion, the first operation is selected from among the pre-stored operations that correspond to the routing congestion.

5. The method according to claim 1, wherein Generating the first vector array includes: The first vector array is generated according to at least one environmental feature among the first chip features, wherein the at least one environmental feature is associated with the first violation.

6. The method according to claim 1, further comprising: accumulating a first value corresponding to the design rule violation and a second value corresponding to surrounding circumstances associated with the design rule violation; as well as At least one of the pre-stored operations is generated according to the first value and the second value.

7. The method according to claim 1, further comprising: receiving a design rule violation for the second layout; classifying a second violation of the design rule violation of the second layout into a second category of the predetermined category based on a second chip feature of the second layout; generating a second vector array associated with the second violation for at least one second chip feature of the second layout; selecting a second operation from the pre-stored operations according to the second vector array; as well as A third layout is generated based on the second layout and the second operation.

8. The method according to claim 1, further comprising: determining whether the first violation belongs to a category corresponding to a pin access; Wherein, when the first violation belongs to a category corresponding to the pin access, the first operation includes at least one of the following: adding a block on the first cell generating the first violation; assigning a layer other than a layer of the first unit to at least one of the pin accesses; or A padding value between the first cell and a second cell adjacent to the first cell is determined.

9. The method according to claim 1, wherein The pre-stored operation includes at least one of the following: generating at least one chip feature; Removing at least one chip feature; or At least one chip feature is modified.

10. The method according to claim 1, wherein Selecting the first operation includes: The first operation is automatically selected by a processor of a computer from among the pre-stored operations stored in a memory of the computer.

11. A system for manufacturing a semiconductor device, comprising: a memory configured to store computer program code; as well as a processor configured to execute the computer program code in the memory to perform the following operations: classifying the design rule violations into predefined categories based on the data of the design rule violations of the first layout of the chip; automatically assigning a first operation of a pre-stored operation to each of the design rule violations based on the data of the design rule violations of the first layout; as well as Generate a second layout based on the first layout and the first operation The processor is further configured to compare the number of design rule violations of the first layout with the number of design rule violations of the second layout to generate a repair rate of the first operation corresponding to the first layout.

12. The system according to claim 11, wherein The processor is further configured to adjust the first operation based on the repair rate.

13. The system according to claim 11, wherein: The memory is further configured to store data associated with at least one of a structural characteristic, an environmental characteristic, a violation type, or a circuit problem.

14. The system according to claim 11, wherein: The processor is further configured to classify each of the design rule violations into a category of routing congestion, a category of non-congestion, or a category where the pre-stored operation is not performed on the design rule violation.

15. The system according to claim 11, wherein The processor is further configured to, when the design rule violation is associated with a pin access of the first layout, add blocking on the first layout or rearrange the pin access according to the data.

16. A method for manufacturing a semiconductor device, comprising: classifying each of the design rule violations of a first layout of a chip into a predefined category based on chip characteristics of the first layout, the chip characteristics comprising at least one of a structural characteristic, an environmental characteristic, a violation type, or a circuit problem of the first layout; assigning a first operation of pre-stored operations to the design rule violations based on one of the predefined categories and at least one of the chip characteristics associated with each of the design rule violations; modifying the first layout according to the first operation to generate a second layout; as well as manufacturing the chip based on the second layout, Classifying each of the design rule violations of the first layout into the predefined category includes: based on a metal density of a layer in the first layout where the first violation is generated, and a ratio of the number of violations on the layer to the total number of design rule violations of the first layout, identifying the first violation as corresponding to a category in the predefined categories corresponding to routing congestion when the first violation does not correspond to a category in which the pre-stored operation is not performed.

17. The method according to claim 16, wherein Categorizing each of the design rule violations of the first layout into the predefined category further comprises: The first violation corresponding to a category in the predefined categories in which the pre-stored operation is not performed is identified according to at least one chip feature among the chip features associated with the first violation of the design rule violations.

18. The method according to claim 17, wherein When the first violation corresponds to the category of routing congestion, the method further includes: routing metal lines around the routing congestion; or Relocate buffers in the area of ​​routing congestion.

19. The method according to claim 17, wherein Assigning the first operation to the design rule violation includes: automatically assigning, by a processor of a computer, at least one of the first operations stored in a memory of the computer to the first violation based on at least one of the chip characteristics associated with the first violation, At least one of the first operations includes at least one of the following: generating at least one chip feature; Removing at least one chip feature; or At least one chip feature is modified.

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