Storage device using time-interleaved sample page buffers to perform read operations

Abstract

A memory device that performs a read operation by using a time-interleaved page buffer is provided. The memory device controls a sensing time point of a bit line of an even page buffer circuit and a sensing time point of a bit line of an odd page buffer circuit with a certain time difference, and performs an even-odd sensing (EOS) operation in the order of even sensing and odd sensing. The memory device performs a two-step EOS operation, and performs a main sensing operation on a selected memory cell according to a result of the two-step EOS operation.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0120310, filed on September 18, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor memory device, and more specifically, to a memory device that performs read operations using a time-interleaved sampling page buffer and a method of operating the memory device. Background Technology

[0004] Many companies and their computer systems host data processing systems such as data centers. Data centers are used to distribute hosted applications and / or transactions and include networked computing resources (e.g., servers, disks, and virtual machines). In such a configuration, the enterprise is the customer of the data center. Data centers provide customers with many services that can reduce costs and alleviate management burdens.

[0005] Data centers can use Dynamic Random Access Memory (DRAM) to store data or instructions used by hosts within the data center and / or to perform computational operations. Data centers can also include storage devices with non-volatile memory. As the capacity of storage devices increases, the number of memory cells and word lines stacked three-dimensionally on the substrate of non-volatile memory increases, and the number of bits of data stored in a given memory cell also increases.

[0006] Non-volatile memory can degrade over time due to various reasons. Degradation can be overcome by changing the operating conditions of the non-volatile memory. These modified operating conditions can be pre-set in the storage device based on the average usage pattern and the usage environment. However, such techniques are unsuitable when the threshold voltage distribution of the memory cells shifts.

[0007] Therefore, the operating conditions need to be dynamically changed depending on the degree of degradation of the non-volatile memory. Summary of the Invention

[0008] According to an exemplary embodiment of the present invention, a method for reading a non-volatile memory device is provided, the method comprising: performing a first sensing operation on selected memory cells connected to a selected word line and applying a first read voltage to the selected word line, wherein the first sensing operation is performed by dividing a plurality of memory cells connected to the selected word line into a first group and a second group; determining a first valley search operation and a target read level of the first read voltage based on the result of performing the first sensing operation; performing a second sensing operation on the selected memory cells and applying a second read voltage to the selected word line, wherein the target read level of the second read voltage is different from the target read level of the first read voltage, wherein the second sensing operation is performed by dividing the plurality of memory cells into the first group and the second group; performing a second valley search operation based on the result of performing the second sensing operation; determining a target generation time point of a sensing node connected to the selected memory cells based on the result of performing the second valley search operation; and performing a main read operation on the selected memory cells using the target read level and the target generation time point.

[0009] According to an exemplary embodiment of the present invention, a method for reading data from selected memory cells of a non-volatile storage device is provided, the method comprising: performing a two-step parity sensing (EOS) operation on the selected memory cells; performing a first master sensing operation on the selected memory cells based on the result of the two-step EOS operation; performing a one-step EOS operation on the selected memory cells; and performing a second master sensing operation on the selected memory cells based on the result of the one-step EOS operation; wherein the two-step EOS operation is performed to identify, from the programming states of the plurality of memory cells, a programming state that has deviated by more than a first threshold amount corresponding to retention degradation, and the one-step EOS operation is performed to identify, from the programming states of the plurality of memory cells, a programming state that has deviated by less than a second threshold amount corresponding to the retention degradation.

[0010] According to an exemplary embodiment of the present invention, a method for operating a storage device including a non-volatile storage device and a controller for controlling the non-volatile storage device is provided. The method includes: sending a read command from the controller to the non-volatile storage device; performing a read operation on the non-volatile storage device according to the read command and sending read data of the read operation to the controller; the controller performing an error correction code (ECC) operation on the read data; performing a two-step parity sensing (EOS) operation on the non-volatile storage device when the result of the ECC operation indicates that an error in the read data is uncorrectable; and determining an optimal read level for reading a valley of data stored in the non-volatile storage device based on the result of performing the two-step EOS operation.

[0011] According to an exemplary embodiment of the present invention, an operating method for a storage device comprising multiple storage blocks is provided. The method includes: when a sudden power failure of the storage device is detected while first data is being written to a first storage block among the multiple storage blocks, and writing the first data to the first storage block cannot continue, selecting a second storage block as a power failure protection (PLP) region, and migrating the first data written on the first storage block to the second storage block, which is the PLP region. The migration includes: performing a two-step parity sensing (EOS) operation on the selected storage cell, and performing a main sensing operation on the selected storage cell to read the first data based on the result of performing the two-step EOS operation. Attached Figure Description

[0012] The embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a conceptual block diagram of a system according to an exemplary embodiment of the present invention;

[0014] Figure 2 yes Figure 1 A block diagram of an example of a non-volatile storage device;

[0015] Figure 3 yes Figure 2 A structural diagram of an NVM device;

[0016] Figure 4 yes Figure 2 The equivalent circuit diagram of the storage block;

[0017] Figure 5 Including showing Figure 4 A graph showing the offset of the threshold voltage distribution of the memory cells;

[0018] Figure 6 It shows Figure 2 Example of a page buffer;

[0019] Figure 7 and Figure 8 yes Figure 6 A diagram of the page buffer circuit;

[0020] Figure 9 and Figure 10 This is a flowchart of a method for reading non-volatile memory according to an exemplary embodiment of the present invention;

[0021] Figures 11A to 11C It is used to explain the basis Figure 10The graph of valley search operation read by two-step Even Odd Sensing (EOS);

[0022] Figure 12 and Figure 13 This is a diagram illustrating a method for reading non-volatile memory according to an exemplary embodiment of the present invention;

[0023] Figure 14 and Figure 15 This is a flowchart illustrating an operation method of a storage device according to an exemplary embodiment of the present invention;

[0024] Figure 16 yes Figure 1 A flowchart illustrating an example of how to operate a storage device;

[0025] Figures 17 to 19 yes Figure 16 A diagram illustrating an example of the Power Loss Protection (PLP) operation in the S1640; and

[0026] Figure 20 This is a block diagram illustrating an example of applying non-volatile memory to an SSD system according to an exemplary embodiment of the present invention. Detailed Implementation

[0027] Figure 1 This is a conceptual block diagram of a system according to an exemplary embodiment of the present invention.

[0028] Reference Figure 1 System 100 may be a data center comprising dozens of hosts or servers running hundreds of virtual machines. According to some embodiments, system 100 may be, for example, a computing device such as a laptop computer, desktop computer, server computer, workstation, portable communication terminal, personal digital assistant (PDA), portable multimedia player (PMP), smartphone, tablet computer, virtual machine, or virtual computing device of a virtual machine. Alternatively, system 100 may be a component included in a computing system such as a graphics card.

[0029] System 100 may include the following references Figure 1The hardware components described in detail are not limited thereto, but one or more embodiments of the inventive concept are not limited thereto. System 100 may include other components. In an embodiment, system 100 includes a host device 110 and a storage device 120. Host device 110 and storage device 120 may communicate with each other using various protocols. For example, host device 110 and storage device 120 may communicate with each other using interface protocols such as Fast Peripheral Component Interconnect (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). Additionally, other interface protocols such as Universal Flash Memory (UFS), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE) may be used as the interface protocol between host device 110 and storage device 120.

[0030] Host device 110 can control data processing operations to be performed on storage device 120. For example, data processing operations may be data read operations, data write operations, or data erase operations. Host device 110 may be a data processor that processes data. For example, a data processor may be processor 112, a central processing unit (CPU), a microprocessor, or an application processor (AP). Host device 110 may execute an operating system (OS) and / or various applications. In an embodiment, system 100 may be included in a mobile device, and host device 110 may be implemented as an AP. In an embodiment, host device 110 may be implemented as a system-on-a-chip (SoC) and therefore may be embedded in system 100.

[0031] Examples can be described using expressions such as “connection” and / or “coupling” and their derivatives. These terms are not necessarily used as synonyms for each other. For example, a description using the terms “connection” and / or “coupling” can refer to two or more elements being in direct physical or electrical contact with each other. The terms “connection” and / or “coupling” can also mean that two or more elements cooperate or interact with each other even if they are not in direct contact.

[0032] For example, processor 112 may include a CPU, a graphics processing unit (GPU), a neural processing unit (NPU), or a digital signal processor (DSP). The number of processors 112 may be at least one, i.e., a multi-core processor. Processor 112 may be configured to execute one or more machine-executable commands or software, firmware, or combinations thereof. Figure 1 A system 100 including a processor 112 is shown, but according to an embodiment, the system 100 may include multiple processors.

[0033] Storage device 120 may include controller 130, non-volatile memory 140, and buffer memory 150. For example, storage device 120 may include solid-state drive or solid-state disk (SSD), universal flash memory (UFS), memory card, micro SD card, or embedded multimedia (eMMC) card, but the scope of the present invention is not limited thereto.

[0034] Controller 130 can process requests from host device 110. Controller 130 can perform write (or programming), read, and erase operations on non-volatile memory 140 based on requests from host device 110. Controller 130 can control non-volatile memory 140 and buffer memory 150. Controller 130 can be implemented using a SoC, application-specific integrated circuit (ASIC), or field-programmable gate array (FPGA).

[0035] The non-volatile memory 140 can perform write, read, and erase operations under the control of the controller 130. The non-volatile memory 140 may include non-volatile memory devices (hereinafter referred to as "NVM devices") connected to channels CH1 to CH4 respectively. Each NVM device may include NAND flash memory.

[0036] NVM devices can be connected to controller 130 via channels CH1 to CH4. Figure 1 The diagram shows four channels, but one or more embodiments of the present invention are not limited to this. Each NVM device can receive a write command, address, and data from controller 130 and write the data to the memory cell corresponding to that address. Each NVM device can receive a read command and address from controller 130, read data from the memory cell corresponding to that address, and output the read data back to controller 130. Each NVM device can receive an erase command and address from controller 130 and erase the data in the memory cell corresponding to that address. (Refer to...) Figure 2 A more detailed description of NVM devices.

[0037] The controller 130 can drive each memory block included in the NVM device in one of the following modes: single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), and quad-level cell (QLC). The controller 130 may include an error correction code (ECC) unit 131 and a power-loss protection (PLP) unit 133. The ECC unit 131 may be referred to as an ECC engine or an ECC circuit block.

[0038] ECC unit 131 can detect and correct errors in data input from host device 110 or data output from each NVM device, and can provide accurate data.

[0039] When storage device 120 experiences a sudden power failure, PLP unit 133 can perform PLP operations to fulfill a request from host device 110 by using the auxiliary power supply of storage device 120. The components described herein as units can be implemented as circuits or processors.

[0040] Buffer memory 150 may include static random access memory (SRAM), dynamic random access memory (DRAM), or tightly coupled memory (TCM). Figure 1 As shown, buffer memory 150 may be contained within controller 130. In an embodiment, the capacity of buffer memory 150 is smaller than that of non-volatile memory 140. In an embodiment, buffer memory 150 is better than non-volatile memory 140 in at least one aspect: latency, access time, and operating speed. Buffer memory 150 may store information or programs for controlling or managing non-volatile memory 140, a mapping table indicating the relationship between logical addresses of the host and physical addresses of non-volatile memory 140, data to be stored in non-volatile memory 140, or data output from non-volatile memory 140.

[0041] Figure 2 yes Figure 1 A block diagram of an example NVM device. (Refer to...) Figure 2 This will describe one of the NVM devices, NVM device 141.

[0042] Reference Figure 2 The NVM device 141 includes a memory cell array 122, a row decoder 394 (e.g., decoder circuitry), control circuitry 124, a page buffer 393, input / output circuitry 126, and a voltage generator 127. Although not shown, the NVM device 141 may also include an input / output interface.

[0043] The memory cell array 122 can be connected to the word line WL, the serial select line SSL, the ground select line GSL, and the bit line BL. The memory cell array 122 can be connected to the row decoder 394 via the word line WL, the serial select line SSL, and the ground select line GSL, and can also be connected to the page buffer 393 via the bit line BL. The memory cell array 122 can include memory blocks BLK1 to BLKn.

[0044] Each of the memory blocks BLK1 to BLKn may include memory cells and select transistors. Memory cells may be connected to word lines WL, and select transistors may be connected to either the string select line SSL or the ground select line GSL. Under the control of controller 130, the memory cells of each of the memory blocks BLK1 to BLKn may be SLC, MLC, TLC, or QLC. In the following description, embodiments of the inventive concept will be described with reference to examples where the memory cells are NAND flash memory cells. Memory cell array 122 may include a three-dimensional memory cell array with cell strings, as will be described with reference to… Figure 3 and Figure 4 Describe this three-dimensional storage cell array.

[0045] A three-dimensional memory cell array is monolithically formed on at least one physical level of the memory cell array. Each memory cell array includes an active region on a silicon substrate and circuitry formed on or in the substrate for operation of the memory cell. The term "monolithic" may indicate that the layers forming each level of the array are directly stacked on top of the layers of the next lower level of the array. In embodiments, the three-dimensional memory cell array includes a string of cells arranged vertically such that at least one memory cell is located on top of another memory cell. At least one memory cell may include a charge trapping layer. US 7,679,133, US 8,553,466, US 8,654,587, US 8,559,235, and US 2011 / 0233648 disclose three-dimensional memory cell arrays configured in a hierarchical manner, sharing word lines and / or bit lines between these levels, the disclosures of which are incorporated herein by reference.

[0046] The line decoder 394 can select one of the memory blocks BLK1 to BLKn of the memory cell array 122, select one of the word lines WL of the selected memory block, and select one of the string selection lines SSL.

[0047] Control circuit 124 can output various internal control signals for performing programming, reading, and erasing operations on memory cell array 122 based on the command CMD, address ADDR, and control signal CTRL sent from controller 130. Control circuit 124 can provide row address R_ADDR to row decoder 394, column address to input / output circuit 126, and voltage control signal CTRL_VOL to voltage generator 127.

[0048] In an exemplary embodiment, the control circuit 124 includes a counter 125 (e.g., a counting circuit) that counts the number of memory cells sensed according to the two-step EOS read operation to search for valleys in the threshold voltage of the memory cells. The counter 125 may count mass bits and may be referred to as a mass bit counter (MBC). In the following embodiments, the terms counter 125 and MBC are used interchangeably.

[0049] Page buffer 393 can be used as a write driver or a sense amplifier depending on the operating mode. During a read operation, page buffer 393 can sense the bit line BL of the selected memory cell under the control of control circuit 124. The sensed data can be stored in a latch included in page buffer 393. Page buffer 393 can provide the data stored in the latch to MBC 125 under the control of control circuit 124. In addition, page buffer 393 can dump the data stored in the latch to input / output circuit 126 via data line DL under the control of control circuit 124.

[0050] The input / output circuit 126 can temporarily store commands (CMD), addresses (ADDR), and data (DATA) provided from the outside of the NVM device 141 via input / output lines I / O. The input / output circuit 126 can also temporarily store data read from the NVM device 141 and output the read data to the outside via the input / output lines I / O at a specified time.

[0051] Voltage generator 127 can generate various voltages for performing programming, reading, and erasing operations on memory cell array 122 in response to voltage control signal CTRL_VOL. Specifically, voltage generator 127 can generate word line voltages VWL (e.g., programming voltage, read detection voltage, read voltage, pass voltage, erase voltage, or erase verification voltage).

[0052] Figure 3 This illustrates an example embodiment. Figure 2 Figure 141 of the storage device.

[0053] Reference Figure 3The memory device 141 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by: fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer separate from the second wafer, and then bonding the upper and lower chips together. Here, the bonding process may include a method of electrically connecting bonding metal formed on the topmost metal layer of the upper chip to bonding metal formed on the topmost metal layer of the lower chip. For example, the bonding metal may include copper (Cu) using Cu-Cu bonding. However, embodiments of the inventive concept are not limited thereto. For example, the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0054] The peripheral circuit region PERI and cell region CELL of the storage device 141 may each include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0055] The Peripheral Circuit Region (PERI) may include a first substrate 210, an interlayer insulating layer 215, a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210, first metal layers 230a, 230b, and 230c respectively connected to the plurality of circuit elements 220a, 220b, and 220c, and second metal layers 240a, 240b, and 240c formed on the first metal layers 230a, 230b, and 230c. In an example embodiment, the first metal layers 230a, 230b, and 230c may be formed of tungsten, which has a relatively high resistivity, and the second metal layers 240a, 240b, and 240c may be formed of copper, which has a relatively low resistivity.

[0056] exist Figure 3 In the example embodiments shown, although only the first metal layers 230a, 230b, and 230c and the second metal layers 240a, 240b, and 240c are shown and described, the embodiments of the present invention are not limited thereto. For example, one or more additional metal layers may also be formed on the second metal layers 240a, 240b, and 240c. At least a portion of the one or more additional metal layers formed on the second metal layers 240a, 240b, and 240c may be formed of aluminum or other metals with a resistivity lower than that of copper, which forms the second metal layers 240a, 240b, and 240c.

[0057] Interlayer insulating layer 215 may be disposed on first substrate 210 and cover multiple circuit elements 220a, 220b and 220c, first metal layers 230a, 230b and 230c and second metal layers 240a, 240b and 240c. Interlayer insulating layer 215 may include insulating material such as silicon oxide or silicon nitride.

[0058] Lower bonding metals 271b and 272b can be formed on the second metal layer 240b in the word line bonding area (WLBA). In the word line bonding area (WLBA), the lower bonding metals 271b and 272b in the peripheral circuit area (PERI) can be electrically bonded to the upper bonding metals 371b and 372b in the cell area (CELL). The lower bonding metals 271b and 272b, as well as the upper bonding metals 371b and 372b, can be formed of aluminum, copper, or tungsten. Furthermore, the upper bonding metals 371b and 372b in the cell area (CELL) can be referred to as first metal pads, and the lower bonding metals 271b and 272b in the peripheral circuit area (PERI) can be referred to as second metal pads.

[0059] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 310 and a common source line 320. Multiple word lines 331 to 338 (i.e., 330) may be stacked on the second substrate 310 in a direction perpendicular to the upper surface of the second substrate 310 (Z-axis direction). At least one string select line and at least one ground select line may be arranged on and below the multiple word lines 330, respectively, and the multiple word lines 330 may be positioned between the at least one string select line and the at least one ground select line.

[0060] In the bit line bonding area BLBA, the channel structure CHS can extend in a direction perpendicular to the upper surface of the second substrate 310 (Z-axis direction) and pass through multiple word lines 330, at least one string select line, and at least one ground select line. The channel structure CHS may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may be a bit line contact, and the second metal layer 360c may be a bit line. In an example embodiment, the bit line 360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0061] exist Figure 3 In the example embodiment shown, the region where the channel structure CHS and bit line 360c are provided can be defined as the bit line bonding region BLBA. In the bit line bonding region BLBA, bit line 360c can be electrically connected to circuit element 220c, which includes page buffer 393 in the peripheral circuit region PERI. Bit line 360c can be connected to upper bonding metals 371c and 372c in the cell region CELL, and upper bonding metals 371c and 372c can be connected to lower bonding metals 271c and 272c connected to the circuit element 220c of page buffer 393.

[0062] In the word line bonding area (WLBA), multiple word lines 330 can extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 310 and perpendicular to the first direction, and can be connected to multiple cell contact plugs 341 to 347 (i.e., 340). The multiple word lines 330 and the multiple cell contact plugs 340 can be connected to each other in pads provided by at least a portion of the multiple word lines 330 extending at different lengths along the second direction. A first metal layer 350b and a second metal layer 360b can be sequentially connected to the upper portion of the multiple cell contact plugs 340 connected to the multiple word lines 330. The multiple cell contact plugs 340 can be connected to the peripheral circuit region PERI in the word line bonding area (WLBA) via upper bonding metals 371b and 372b of the cell region CELL and lower bonding metals 271b and 272b of the peripheral circuit region PERI.

[0063] Multiple unit contact plugs 340 may be electrically connected to circuit element 220b forming a row decoder 394 in the peripheral circuitry region PERI. In an example embodiment, the operating voltage of circuit element 220b forming the row decoder 394 is different from the operating voltage of circuit element 220c forming the page buffer 393. For example, the operating voltage of circuit element 220c forming the page buffer 393 may be greater than the operating voltage of circuit element 220b forming the row decoder 394.

[0064] A common source line contact plug 380 can be disposed in the external pad bonding region PA. The common source line contact plug 380 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 320. A first metal layer 350a and a second metal layer 360a can be sequentially stacked on the upper part of the common source line contact plug 380. For example, the region in which the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed can be defined as the external pad bonding region PA.

[0065] Input and output pads 205 and 305 can be set in the external pad bonding area PA. (See reference...) Figure 3 A lower insulating film 201 covering the lower surface of the first substrate 210 can be formed below the first substrate 210, and a first input / output pad 205 can be formed on the lower insulating film 201. The first input / output pad 205 can be connected to at least one of a plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit region PERI via a first input / output contact plug 203, and can be separated from the first substrate 210 by the lower insulating film. In addition, a side insulating film can be disposed between the first input / output contact plug 203 and the first substrate 210 to electrically separate the first input / output contact plug 203 from the first substrate 210.

[0066] Reference Figure 3 An upper insulating film 301 covering the upper surface of the second substrate 310 can be formed on the second substrate 310, and a second input / output pad 305 can be disposed on the upper insulating layer 301. The second input / output pad 305 can be connected to at least one of a plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit region PERI via a second input / output contact plug 303. In an example embodiment, the second input / output pad 305 is electrically connected to circuit element 220a. For example, the second input / output pad 305 can be electrically connected to circuit element 220a via metal patterns 272a and 271a via the second input / output contact plug 303.

[0067] According to the example embodiment, the second substrate 310 and the common source line 320 are not disposed in the region where the second input / output contact plug 303 is disposed. Additionally, the second input / output pad 305 does not overlap with the word line 330 in the third direction (Z-axis direction). See also... Figure 3 The second input / output contact plug 303 can be separated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310, and can pass through the interlayer insulating layer 315 of the cell region to connect to the second input / output pad 305.

[0068] According to the example embodiment, the first input / output pad 205 and the second input / output pad 305 are selectively formed. For example, the storage device 141 may include only the first input / output pad 205 disposed on the first substrate 210 or the second input / output pad 305 disposed on the second substrate 310. Alternatively, the storage device 141 may include both the first input / output pad 205 and the second input / output pad 305.

[0069] In each of the external pad bonding area PA and bit line bonding area BLBA included in the cell region CELL and the peripheral circuit region PERI respectively, the metal pattern set on the top metal layer can be set as a dummy pattern, or the top metal layer can be absent.

[0070] In the external pad bonding region PA, the storage device 141 may include a lower metal pattern 273a in the uppermost metal layer of the peripheral circuit region PERI, which corresponds to the upper metal pattern 372a formed in the uppermost metal layer of the cell region CELL and has the same cross-sectional shape as the upper metal pattern 372a of the cell region CELL, for interconnection. The upper metal pattern 372a may be connected to the second metal layer 360a via its protruding structure 371a. In the peripheral circuit region PERI, in an embodiment, the lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit region PERI is not connected to a contact. Similarly, in the external pad bonding region PA, an upper metal pattern 372a may be formed in the uppermost metal layer of the cell region CELL, which corresponds to the lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit region PERI and has the same shape as the lower metal pattern 273a of the peripheral circuit region PERI.

[0071] Lower bonding metals 271b and 272b can be formed on the second metal layer 240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 271b and 272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 371b and 372b of the cell region CELL via Cu-Cu bonding.

[0072] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 392 can be formed in the uppermost metal layer of the cell region CELL. This upper metal pattern 392 corresponds to the lower metal pattern 252 formed in the uppermost metal layer of the peripheral circuit region PERI and has the same cross-sectional shape as the lower metal pattern 252 of the peripheral circuit region PERI. In this embodiment, no contact is formed on the upper metal pattern 392 formed in the uppermost metal layer of the cell region CELL. The lower metal pattern 252 can be connected to the second metal layer 240c through its protruding structure 251.

[0073] In an example embodiment, corresponding to the metal pattern formed in the uppermost metal layer of one of the cell region (CELL) and the peripheral circuit region (PERI), a reinforcing metal pattern with the same cross-sectional shape can be formed in the uppermost metal layer of the other of the cell region (CELL) and the peripheral circuit region (PERI). In this embodiment, no contacts are formed on the reinforcing metal pattern.

[0074] Figure 4 yes Figure 2 The equivalent circuit diagram of the storage block. Figure 4 The storage block is a reference Figure 2The description refers to an example of one of the memory blocks BLK1 to BLKn, specifically the first memory block BLK1. Hereinafter, one or more embodiments of the inventive concept will be described using the first memory block BLK1 as an example. The first memory block BLK1 is a three-dimensional memory block having a three-dimensional structure on a substrate. The strings of memory cells included in the first memory block BLK1 can be formed in a direction perpendicular to the substrate.

[0075] Reference Figure 4 The first storage block BLK1 may include NAND strings NS11 to NS33, word lines WL1 to WL8, bit lines BL1 to BL3, ground select lines GSL1 to GSL3, string select lines SSL1 to SSL3, and common source line CSL. Figure 4 The NAND strings NS11 to NS33 are shown to each include eight memory cells MC connected to eight word lines WL1 to WL8, but one or more embodiments of the present invention are not limited thereto.

[0076] Each NAND string (e.g., NS11) may include a series-connected string select transistor (SST), a memory cell (MC), and a ground select transistor (GST). The string select transistor (SST) is connected to the corresponding string select line (SSL1). The memory cells (MC) are connected to the corresponding word lines (WL1 through WL8). The ground select transistor (GST) is connected to the corresponding ground select line (GSL1). The string select transistor (SST) is connected to the corresponding bit lines (BL1 through BL3), and the ground select transistor (GST) is connected to the common source line (CSL).

[0077] According to embodiments, in each cell string, one or more dummy memory cells may be provided between the string select transistor SST and the memory cell MC. In each cell string, one or more dummy memory cells may be provided between the ground select transistor GST and the memory cell MC. In each cell string, one or more dummy memory cells may be provided between the memory cells MC. The dummy memory cells may have the same structure as the memory cells MC but are not programmed (e.g., to prevent programming), or they may be programmed differently from the memory cells MC. For example, when the memory cells MC are programmed to have two or more threshold voltage distributions, the dummy memory cells may be programmed to have a threshold voltage distribution range or a number less than the number of threshold voltage distributions of the memory cells MC.

[0078] Figure 5 Includes showing Figure 4 A graph showing the offset of the threshold voltage distribution of the memory cells. Figure 5The graphs G1 and G2 represent the distribution of threshold voltages of memory cells connected to a specific word line. For example, this specific word line could be the first word line in the first memory block BLK1. The horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the cell count, i.e., the number of memory cells.

[0079] Reference Figure 5 One or more bits can be programmed into a memory cell connected to the first word line. Depending on the number of bits stored in the memory cell, the memory cell can be classified as SLC, MLC, TLC, or QLC. Depending on the number of bits stored in the memory cell, the memory cell can have one of several states. The state can be defined as a range of threshold voltages. (See reference...) Figure 5 The storage cell can be a QLC, and the threshold voltage of the storage cell can be programmed to one of 16 states S1 to S16.

[0080] After data is programmed into a memory cell, interference degradation or retention degradation may occur within the cell. Interference degradation indicates that the threshold voltage of the memory cell changes due to programming, reading, erasing, or coupling occurring around the cell. Retention degradation indicates that after charge is trapped in the charge trapping layer of the memory cell and the cell is programmed, the threshold voltage of the cell changes due to leakage of the trapped charge over time. Because the threshold voltage of a memory cell changes when degradation occurs, the data in the cell may not be readable when using the initially set read level (i.e., the data is corrupted).

[0081] exist Figure 5 In the context of graph G1, when the distribution of threshold voltages for the memory cells is as shown, the optimal read level for reading data stored in the memory cells can be VR1 to VR15. Due to degradation, graph G1 may change to graph G2 or may shift. When the distribution of threshold voltages for the memory cells is as shown in graph G2, the optimal read level for reading data stored in the memory cells may change to VR1' to VR15', instead of VR1 to VR15.

[0082] During the read operation, the control circuit 124 can perform a two-step EOS operation to obtain the target read level and the target develop time point as the result of the two-step EOS operation, and perform a main read operation on the selected memory cell by using the target read level and the target develop time point, thereby performing a read operation on the selected memory cell connected to the first word line with a changed read level VR1' to VR15'.

[0083] Figure 6 It shows Figure 2 An example of a page buffer. Figure 6The selected memory cell MC_S of the first memory block BLK1 is conceptually shown. Figure 6 It shows the reference Figure 4 Page buffer circuits 601 to 608 are described for some memory cells connected to the selected word line WL_S in the described cell string. For clarity of the figures, the memory cells connected to the selected word line WL_S are respectively connected between bit lines BL1 to BL8 and the common source line CSL, while transistors and memory cells connected to the string select line, ground select line, and unselected word line are not shown.

[0084] Reference Figure 6 Bit lines BL1 to BL8, connected to the memory cell of the selected word line WL_S, are respectively connected to page buffer circuits 601 to 608. During a read operation, page buffer circuits 601 to 608 can sense the voltage levels of bit lines BL1 to BL8 and can acquire (or latch) the voltage levels. Page buffer circuits 601 to 608 can send sensed and latched data to control circuit 124 or input / output circuit 126.

[0085] When page buffer circuits 601 to 608 sense the voltage levels of bit lines BL1 to BL8, page buffer circuits 601 to 608 can be divided into odd-numbered page buffer circuits 601, 603, 605, and 607 and even-numbered page buffer circuits 602, 604, 606, and 608 for operation. Odd-numbered page buffer circuits 601, 603, 605, and 607 can be connected to odd-numbered bit lines BL1, BL3, BL5, and BL7, and even-numbered page buffer circuits 602, 604, 606, and 608 can be connected to even-numbered bit lines BL2, BL4, BL6, and BL8.

[0086] For example, even-numbered page buffer circuits 602, 604, 606, and 608 can sense and latch the voltage levels of even-numbered bit lines BL2, BL4, BL6, and BL8 in response to a first control signal SET and a second control signal RESET applied sequentially. Odd-numbered page buffer circuits 601, 603, 605, and 607 can sense and latch the voltage levels of odd-numbered bit lines BL1, BL3, BL5, and BL7 in response to a first control signal SET and a second control signal RESET applied sequentially. In this case, the timing at which the first control signal SET is applied to odd-numbered page buffer circuits 601, 603, 605, and 607 can differ from the timing at which the first control signal SET is applied to even-numbered page buffer circuits 602, 604, 606, and 608. That is, the first control signal SET can be applied to odd-numbered page buffer circuits 601, 603, 605, and 607 and even-numbered page buffer circuits 602, 604, 606, and 608 with a certain time difference. In an exemplary embodiment, the multiplexer is configured to apply a first control signal SET to the odd-numbered page buffer circuits 601, 603, 605, and 607 at a first time, and then apply the first control signal SET to the even-numbered page buffer circuits 602, 604, 606, and 608 at a second time different from the first time. For example, a first-level control signal may be applied to the multiplexer at the first time to cause the multiplexer to output the first control signal SET to the odd-numbered page buffer circuits 601, 603, 605, and 607, and a second control signal of a different level may be applied to the multiplexer at the second time to cause the multiplexer to output the first control signal SET to the even-numbered page buffer circuits 602, 604, 606, and 608.

[0087] Here, sending the first control signal SET to the odd-numbered page buffer circuits 601, 603, 605, and 607 and the even-numbered page buffer circuits 602, 604, 606, and 608 with a time difference can mean that the memory cells are sensed at different time points when the page buffer circuits 601 to 608 sense whether the memory cells are on or off. The sensing operation of the even-numbered page buffer circuits 602, 604, 606, and 608 can be referred to as even-numbered sensing (E_Sensing), and the sensing operation of the odd-numbered page buffer circuits 601, 603, 605, and 607 can be referred to as odd-numbered sensing (O_Sensing). Therefore, the page buffer 393 can perform EOS operations in the order of even-numbered sensing and odd-numbered sensing. According to an embodiment, EOS operations can be performed in the order of odd-numbered sensing followed by even-numbered sensing. During a read operation, the sensing operations on even-numbered page buffer circuits 602, 604, 606, and 608 during a first time period and the sensing operations on odd-numbered page buffer circuits 601, 603, 605, and 607 during a second, other time period can be referred to as performing time-interleaved sensing or sampling.

[0088] Figure 7 and Figure 8 It is used for explanation Figure 6 The diagram shows the page buffer circuit. Figure 7 This is the circuit diagram of the page buffer circuit PB. Figure 8 This is a timing diagram used to illustrate the operation of the page buffer circuit PB. Note that the timing diagram in this invention is not necessarily a uniform ratio.

[0089] Reference Figure 7 The page buffer circuit PB includes a sensing latch 710, a selection circuit 720, a precharge circuit 730, a latch circuit 740, a transmission circuit 750, a first transistor 760, a second transistor 770, and a reset circuit 780.

[0090] The sensing latch 710 may include a cross-coupled inverter located between the first node N1 and the second node N2. The sensing latch 710 may store the detection result of the voltage level of the bit line BL. The selection circuit 720 may, in response to the selection signal SEL, electrically connect the sensing node SO to the bit line BL or disconnect the sensing node SO from the bit line BL. The precharge circuit 730 may, in response to the precharge signal PRE, apply a precharge voltage to the sensing node SO. The latch circuit 740 may be connected to the sensing node SO and, in response to the latch signal LAT, transmits the voltage level of the sensing node SO to the first transistor 760 and the second transistor 770. The transmission circuit 750 may be connected to the first transistor 760 and the second transistor 770 and, in response to the transmit signal TRS, transmits the detection result stored in the sensing latch 710 to the control circuit 124 or the input / output circuit 126. The first transistor 760 may be controlled by a first control signal SET, and the second transistor 770 may be controlled by a second control signal RESET.

[0091] Reference Figure 8 At time T1, a reset signal RST and a first control signal SET are sent as a logic high pulse. For example, the reset signal RST and the first control signal SET can transition to a logic high state at time T1. In this case, the first node N1 of the sensing latch 710 can be initialized to, for example, a ground voltage level, and the second node N2 of the sensing latch 710 can be initialized to a power supply voltage level.

[0092] At time T2, bit line BL and sensing node SO are precharged to the precharge voltage (e.g., power supply voltage).

[0093] At time T3, a read voltage RDi is applied to the selected word line WL_S. Depending on the level to be compared with the threshold voltage of the selected memory cell MC_S, the read voltage RDi can have the following characteristics: Figure 12 The voltage levels shown are one of VRD1 to VRD15. When the threshold voltage of the selected memory cell MC_S is higher than the read voltage RDi, the selected memory cell MC_S is turned off. Therefore, the voltage level of the bit line BL can be maintained at the precharge level. In contrast, when the threshold voltage of the selected memory cell MC_S is less than or equal to the read voltage RDi, the selected memory cell is turned on. Therefore, the voltage level of the bit line BL can be discharged to the ground level.

[0094] At time point T3a, the selection signal SEL is applied at a logic high level, and the bit line BL and the sensing node SO are electrically connected to each other. Therefore, the voltage level of the sensing node SO can be generated or set according to the voltage level of the bit line BL.

[0095] At time point T4, after applying the latch signal LAT and the second control signal RESET to the even-numbered page buffer circuits 602, 604, 606, and 608 with a logic high pulse, at time point T5, the latch signal LAT and the first control signal SET are applied to the even-numbered page buffer circuits 602, 604, 606, and 608 with a logic high pulse. At times T4 and T5, even-numbered sensing E_Sensing of the even-numbered page buffer circuits 602, 604, 606, and 608 is performed, and times T4 and T5 can be considered as the times when the sensing nodes SO of the even-numbered page buffer circuits 602, 604, 606, and 608 are generated.

[0096] At time point T5, after applying a latch signal LAT and a second control signal RESET to the odd-page buffer circuits 601, 603, 605, and 607 with a logic high pulse, at time point T6, the latch signal LAT and the first control signal SET are applied to the odd-page buffer circuits 601, 603, 605, and 607 with a logic high pulse. At times T5 and T6, odd-page sensing O_Sensing of the odd-page buffer circuits 601, 603, 605, and 607 is performed, and times T5 and T6 can be considered as the times when the sensing nodes SO of the odd-page buffer circuits 601, 603, 605, and 607 are generated.

[0097] Figure 9 and Figure 10 This is a flowchart of a method for reading non-volatile memory according to an exemplary embodiment of the present invention.

[0098] Reference Figure 2 as well as Figures 6 to 9 The method for reading S900 from non-volatile memory (NVM) includes performing a two-step EOS read in operation S910, and then performing a main read operation in operation S920.

[0099] During operation of S910, two EOS reads of page buffer 393 are performed.

[0100] In operation S920, a primary read is performed on the selected memory cell.

[0101] Reference Figure 10 During the two-step EOS reading in operation S910, the operation of performing a first EOS reading to find the first valley position is executed (S912), and the target reading level of the reading voltage RDi can be found by using the first valley position EOS found during the first EOS reading. Then, the operation of changing the target reading level of the reading voltage RDi is executed (S914) to find the target generation time point of the sensing node SO.

[0102] The first EOS read in operation S912 is an operation that roughly (or coarsely) searches for the location of the first valley, and can be referred to as a C-EOS read. In the following embodiments, the terms "first EOS operation," "first EOS read," and "C-EOS operation" can be used interchangeably.

[0103] In operation S914, the target read level of the read voltage RDi obtained as a result of the first EOS read can be slightly increased or decreased. According to the embodiment, the target read level of the read voltage RDi of the selected word line WL_S is changed n times. For example, when n is 3, this change is performed approximately 3 times.

[0104] The two-step EOS read in operation S910 includes the operation of performing a second EOS read to search for the second valley position (S916) and the operation of determining the time point for sending the first control signal SET and the second control signal RESET (i.e., the target generation time point) based on the second valley position (S918).

[0105] The second EOS read in operation S916 is an operation performed based on the target read level RDi modified three times according to the selected word line WL_S, to accurately (or precisely) search for the second valley position compared to the first valley position, and this second EOS read can be referred to as an F-EOS read. In the following embodiments, the terms "second EOS operation", "second EOS read" and "F-EOS operation" can be used interchangeably.

[0106] In operation S920, a primary read is performed on the selected memory cell using the target read level and the target generation time point. In the following embodiments, the terms "primary read operation" and "primary read" are used interchangeably.

[0107] Figures 11A to 11C It is based on Figure 10 A diagram illustrating the two-step valley search operation for EOS reading. (Refer to...) Figures 11A to 11C This allows modeling of the threshold voltage levels used to identify the two states Si and Si+1 (e.g., the programming state) of a memory cell. Figures 11A to 11C In the diagram, the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells.

[0108] Valley search can be performed by detecting levels near the predicted valley level and counting the number of memory cells based on the detection results. For example, a non-volatile memory (NVM) can perform a two-step EOS read using a first voltage V1 and a second voltage V2, and can count the number nC1 of memory cells having a threshold voltage between the first voltage V1 and the second voltage V2 using the MBC 125 of the control circuit 124. A NVM can also perform a two-step EOS read using a second voltage V2 and a third voltage V3, and can count the number nC2 of memory cells having a threshold voltage between the second voltage V2 and the third voltage V3 using the MBC 125 of the control circuit 124. The NVM can identify valleys V based on the counting results. For example, valleys can be identified from the counting results of nC1 and nC2.

[0109] Reference Figure 11A When it is determined that the number of memory cells nC1 obtained through two-step EOS reading is greater than the number of memory cells nC2, and when the difference |nC1-nC2| is equal to or greater than the reference value, the control circuit 124 can determine that the third voltage V3 is the optimal reading level for the valley.

[0110] Reference Figure 11B When it is determined that the number of memory cells nC2 obtained through two-step EOS reading is greater than the number nC1, and when the difference |nC1-nC2| is equal to or greater than the reference value, the control circuit 124 can determine that the first voltage V1 is the optimal reading level of the valley.

[0111] exist Figure 11C In the process, when it is determined that the number of memory cells nC1 obtained through two-step EOS reading is equal to the number nC2, or when the difference |nC1-nC2| is less than the reference value, the control circuit 124 can determine that the second voltage V2 is the optimal reading level of the valley.

[0112] Figure 12 and Figure 13 This is a diagram illustrating a method for reading a non-volatile memory according to an exemplary embodiment of the present invention. Figure 12 This is a graph showing the threshold voltage distribution of the memory cells. Although Figure 12 This is a graph showing the threshold voltage distribution when the memory cell is a QLC, but... Figure 12 The description can be similarly applied to storage units that store different numbers of bits. Figure 13 A method for reading the most significant bit (MSB) page is shown. The method for reading the MSB page can be equivalently applied to the method for reading the least significant bit (LSB) page, the first middle significant bit (CSB1), and the second middle significant bit (CSB2).

[0113] When each memory cell is a QLC, the state of each memory cell can correspond to one of 16 states S1 to S16. A memory cell connected to a word line can include an LSB page, a CSB1 page, a CSB2 page, and an MSB page. The state determined during the operation of reading each page can be different.

[0114] For example, in the operation of reading an LSB page, a non-volatile memory (NVM) can determine the eleventh state S11 and the twelfth state S12 by applying an eleventh read voltage RD11 to the selected word line WL_S, and can determine the sixth state S6 and the seventh state S7, the fourth state S4 and the fifth state S5, and the first state S1 and the second state S2 by sequentially applying a sixth read voltage RD6, a fourth read voltage RD4, and a first read voltage RD1 to the selected word line WL_S. The eleventh read voltage RD11 can be referred to as the highest read voltage for the LSB page.

[0115] During the operation of reading the CSB1 page, the non-volatile memory (NVM) can determine the thirteenth state S13 and the fourteenth state S14, the ninth state S9 and the tenth state S10, the seventh state S7 and the eighth state S8, and the third state S3 and the fourth state S4 by sequentially applying the thirteenth read voltage RD13, the ninth read voltage RD9, the seventh read voltage RD7, and the third read voltage RD3 to the selected word line WL_S. The thirteenth read voltage RD13 can be referred to as the highest read voltage for the CSB1 page.

[0116] During the operation of reading the CSB2 page, the non-volatile memory (NVM) can determine the fourteenth state S14 and the fifteenth state S15, the eighth state S8 and the ninth state S9, and the second state S2 and the third state S3 by sequentially applying the fourteenth read voltage RD14, the eighth read voltage RD8, and the second read voltage RD2 to the selected word line WL_S. The fourteenth read voltage RD14 can be referred to as the highest read voltage of the CSB2 page.

[0117] During the operation of reading MSB pages, the non-volatile memory (NVM) can determine the fifteenth state S15 and the sixteenth state S16, the twelfth state S12 and the thirteenth state S13, the tenth state S10 and the eleventh state S11, and the fifth state S5 and the sixth state S6 by applying the fifteenth read voltage RD15, the twelfth read voltage RD12, the tenth read voltage RD10 and the fifth read voltage RD5 to the selected word line WL_S. The fifteenth read voltage RD15 can be referred to as the highest read voltage of the MSB page.

[0118] Reference Figure 10 , Figure 12 and Figure 13The method for reading the MSB page may include: a first read operation based on the fifteenth read voltage RD15, which is the highest read voltage, in interval TA (or within a first time period); a second read operation based on the twelfth read voltage RD12, which is the second highest read voltage, in interval TB (or within a second time period); a third read operation based on the tenth read voltage RD10, which is the second lowest read voltage, in interval TC (or within a third time period); and a fourth read operation based on the fifth read voltage RD5, which is the lowest read voltage, in interval TD (or within a fourth time period).

[0119] In the first read operation within the interval TA, a C-EOS read can be performed by applying the fifteenth read voltage RD15 to the selected word line WL_S. The number of memory cells obtained from the C-EOS read can be stored in the MBC 125 of the control circuit 124, thus allowing a coarse search for the fifteenth valley position. An F-EOS read can be performed by changing the level of the fifteenth read voltage RD15 based on the approximate fifteenth valley position. The target read level of the fifteenth read voltage RD15 can be determined based on the precise fifteenth valley position searched as a result of the F-EOS read, and the target generation time point for providing the first control signal SET can be determined. Then, the main read operation performed on the selected memory cell can be executed using the target read level of the fifteenth read voltage RD15 and the target generation time point.

[0120] In the second read operation within interval TB, a C-EOS read can be performed by applying a twelfth read voltage RD12 to the selected word line WL_S, and the number of memory cells obtained from the C-EOS read is stored in the MBC 125 of the control circuit 124, thereby approximating the twelfth valley location. An F-EOS read can be performed by changing the level of the twelfth read voltage RD12 according to the approximate twelfth valley location. The target read level of the twelfth read voltage RD12 can be determined based on the precise twelfth valley location found as a result of the F-EOS read, and the target generation time point for sending the first control signal SET can be determined. Then, a main read operation of the selected memory cell can be performed using the target read level of the twelfth read voltage RD12 and the target generation time point.

[0121] In the third read operation within interval TC, a C-EOS read can be performed by applying a tenth read voltage RD10 to the selected word line WL_S, and the number of memory cells obtained as a result of the C-EOS read can be stored in the MBC 125 of the control circuit 124, thereby approximating the tenth valley position. An F-EOS read can be performed by changing the level of the tenth read voltage RD10 according to the approximate tenth valley position. The target read level of the tenth read voltage RD10 can be determined based on the precise tenth valley position found as a result of the F-EOS read, and the target generation time point for sending the first control signal SET can be determined. Then, a main read operation on the selected memory cell can be performed using the target read level of the tenth read voltage RD10 and the target generation time point.

[0122] Reference Figure 12 Of the 16 states S1 to S16 of the described memory cell, states S1 to S7 of the memory cell read with a lower level read voltage (e.g., the first to seventh read voltages RD1 to RD7) show minimal changes in maintaining degradation, thus the threshold voltage shift of the memory cell can be small. In contrast, states S8 to S16 of the memory cell read with a higher level read voltage (e.g., the eighth to fifteenth read voltages RD8 to RD15) show significant changes due to maintaining degradation, thus the threshold voltage shift of the memory cell can be large. Therefore, a read operation using a higher level voltage (e.g., the eighth to fifteenth read voltages RD8 to RD15) can be performed using a two-step EOS read, while a read operation using a lower level voltage (e.g., the first to seventh read voltages RD1 to RD7) can be performed using a one-step EOS read.

[0123] In the fourth read operation within interval TD, an EOS read can be performed by applying a fifth read voltage RD5 to the selected word line WL_S. The fifth valley position can be searched by storing the number of memory cells obtained as a result of the EOS read in the MBC 125 of the control circuit 124. The target read level of the fifth read voltage RD5 can be determined based on the fifth valley position, and the target generation time point for sending the first control signal SET can be determined. Then, a main read operation on the selected memory cell can be performed using the target read level of the fifth read voltage RD5 and the target generation time point.

[0124] Figure 14 and Figure 15 This is a flowchart illustrating an operational method of a storage device according to an exemplary embodiment of the present invention. Figure 14 and Figure 15 In the middle, it will be described Figure 1 The operation of the controller 130 and NVM device 141 in the storage device 120.

[0125] Reference Figure 14 In operation S1410, the controller 150 issues a read command and sends it to the NVM device 141. The NVM device 141 performs a read operation according to the read command.

[0126] In operation S1420, NVM device 141 performs a two-step EOS read on the selected memory cell, as shown in reference... Figures 6 to 13 As described. In operation S1422, NVM device 141 performs a main read on a selected memory cell using a target read level and target generation time determined as a result of a two-step EOS read. NVM device 141 sends the result of the two-step EOS read to controller 130.

[0127] In operation S1412, controller 130 performs an ECC operation on the data output from NVM device 141 to detect and correct errors. When the ECC operation can correct the error, or when no error needs correction, controller 130 performs ECC (S1414). When the error cannot be corrected or error correction is impossible, controller 130 determines that ECC has failed (S1416). For example, if the number of errors in the data exceeds the correction capability of the ECC operation, error correction cannot be performed. Controller 130 can use ECC unit 131 to perform the ECC operation.

[0128] Reference Figure 15 In operation S1510, the controller 130 issues a read command and sends the read command to the NVM device 141.

[0129] In operation S1520, NVM device 141 performs a read operation according to the read command. NVM device 141 sends the result of the read operation to controller 130.

[0130] In operation S1512, controller 130 performs an ECC operation on the data output from NVM device 141 to detect and correct errors in the data output from NVM device 141. Controller 130 can perform the ECC operation using ECC unit 131. In operation S1514, controller 130 performs ECC when the ECC operation can correct the error or when no error needs to be corrected. When controller 130 or ECC unit 131 cannot perform error correction, operation S1530 is executed.

[0131] In operation S1530, controller 130 performs a two-step EOS read on NVM device 141, as shown in reference... Figures 6 to 13Described. Controller 130 can derive an optimal read voltage based on the location of a valley obtained as a result of a two-step EOS read. In an embodiment, the location of the valley is obtained from the result of the two-step EOS read, the read voltage is determined from the location of the valley, and subsequent reads are performed on NVM device 141 using the determined read voltage.

[0132] Figure 16 This is an exemplary embodiment of the concept of the present invention. Figure 1 A flowchart of the operation method of the storage device. Figure 16 The method of operating the storage device involves performing a PLP operation during a write operation requested from a host device 110 due to a sudden power outage.

[0133] Reference Figure 1 and Figure 15 In operation S1610, the controller 130 of storage device 120 receives a write request from host device 110. Host device 110 may send a request to store data in storage device 120.

[0134] In operation S1620, controller 130 performs a write operation to write (or program) data to a target block (e.g., the first memory block BLK1), corresponding to a write request from host device 110. Controller 130 executes a programming cycle until the data is programmed according to Incremental Step Pulse Programming (ISPP). As the number of programming cycles increases, the programming voltage of the selected memory cell can be gradually increased.

[0135] In operation S1630, controller 130 detects a sudden power failure during a write operation. Even if the power is suddenly turned off, controller 130 must retain the data being written.

[0136] In operation S1640, when the power is suddenly turned off in operation S1630, the controller 130 performs a PLP operation. The PLP operation refers to the following operation: when the power is restored, a determination is made on whether to continue writing data that has not yet been fully written on the same block of data that has already been written, that is, to determine whether writing can continue and to complete the data writing operation expected by the host device 110.

[0137] For example, controller 130 can locate the last page on which data was written during a write operation from the block on which data is being written. Controller 130 can examine the time from the point when the last page was written to the current time (i.e., the programming time). Controller 130 can compare the programming time with a reference value and determine whether writing can continue. When the reference value equals a minimum reference value, controller 130 can determine that writing can continue if the programming time is greater than the minimum reference value, and can determine that writing cannot continue if the programming time is less than the minimum reference value. Conversely, when the reference value equals a maximum reference value, controller 130 can determine that writing can continue if the programming time is less than the maximum reference value, and can determine that writing cannot continue if the programming time is greater than the maximum reference value. Figure 17 and Figure 18 Describe PLP operations.

[0138] Figures 17 to 19 It is used for explanation Figure 16 The diagram shows the PLP operation in the S1640. Figure 17 and Figure 18 In the NVM device 141, there are a first storage block BLK1 and a second storage block BLK2. The first storage block BLK1 may be a storage block on which data received from the host device 110 is written, and the second storage block BLK2 may be an empty storage block on which no data is written. Figure 17 This indicates that writing can continue. Figure 18 This indicates that the write operation cannot be continued.

[0139] Reference Figure 17 When power is suddenly cut off during a write operation, only a portion of the data DATA is written to the first storage block BLK1, while the remainder of the data DATA is not written to the first storage block BLK1. The PLP unit 133 of the controller 130 can save the unwritten segment of data DATA as first data D1 using auxiliary power. The segment of data DATA written to the first storage block BLK1 can be second data D2 and can be located in the first storage block BLK1. During PLP operation, the data DATA of the host device 110 can be divided into first data D1 and second data D2.

[0140] In PLP operation, when the controller 130 determines that writing can continue, the first data D1 is written to the first storage block BLK1. Therefore, the data DATA, including the first data D1 and the second data D2, is written to the first storage block BLK1 as expected by the host device 110. This achieves the purpose of power failure protection. In PLP operation, the first storage block BLK1 can be referred to as the PLP area.

[0141] Reference Figure 18 In PLP operation, when controller 130 determines that continued writing cannot be performed, PLP unit 133 of controller 130 uses auxiliary power to write the first data D1 to an empty second storage block BLK2 instead of writing it to the first storage block BLK1. PLP unit 133 then migrates the existing second data D2 from the first storage block BLK1 to the second storage block BLK2. Here, the term "migration" can refer to data being copied and moved; therefore, the data can still remain in the existing first storage block BLK1 and can also be in the new second storage block BLK2. Then, an erase operation can be performed on the first storage block BLK1.

[0142] Since the first data D1 and the second data D2 included in the data DATA of host device 110 are migrated to the second storage block BLK2, power failure protection can be achieved. During PLP operation, the first storage block BLK1 can be referred to as the PLP region. In this case, contrary to the expectations of host device 110, due to PLP, data DATA is written to the second storage block BLK2 and not to the first storage block BLK1. Controller 130 can include a mapping table in the Flash Translation Layer (FTL) for managing the mapping between logical addresses used by host device 110 and physical addresses used by the NVM device 141 of non-volatile memory. The mapping table can be written such that the physical addresses of the first storage block BLK1 are mapped to the physical addresses of the second storage block BLK2. Then, commands referencing the first storage block BLK1 specified by host device 110 can be executed on the second storage block BLK2 by referring to the mapping table. For example, if data is associated with a logical address, and that logical address is initially mapped to the first physical address of the first block BLK1 in the mapping table, then after the data is migrated to the location of the second block BL2 with the second physical address, the mapping table can be updated to map that logical address to the second physical address of the second block BLK2.

[0143] exist Figure 19 In this context, storage device 120 can be referred to as an SSD.

[0144] In operation S1910, the operation of SSD 120 begins. In operation S1920, SSD 120 experiences a sudden power outage. When SSD 120 does not experience a sudden power outage, SSD 120 continues to execute operation S1910, but when SSD 120 experiences a sudden power outage, SSD 120 executes operation S1930.

[0145] In operation S1930, SSD 120 performs the actions described above. Figure 16The S1640 operates under PLP (Power Loss Protection) mode. During PLP operation, the SSD 120 can achieve power-loss protection by: using auxiliary power and continuing writing to the first storage block BLK1 as expected by the host when writing is possible; or writing or migrating data to the second storage block BLK2 instead of as expected by the host when writing is not possible. In PLP operation, either the first storage block BLK1 or the second storage block BLK2 can be a PLP region.

[0146] In operation S1940, when the second data D2 in the existing first storage block BLK1 is moved to the second storage block BLK2, the SSD 120 can execute the reference... Figures 6 to 13 The description includes two steps: EOS read and main read.

[0147] During operation S1950, SSD 120 is powered off, and operation of SSD 120 is terminated.

[0148] Figure 20 This is a block diagram illustrating an example of applying non-volatile memory to an SSD system according to an exemplary embodiment of the present invention.

[0149] Reference Figure 20 The SSD system 2000 includes a host 2100 and an SSD 2200. The SSD 2200 exchanges signals with the host 2100 via a signal connector and receives power via a power connector. The SSD 2200 includes an SSD controller 2210, an auxiliary power supply 2220, and non-volatile memory 2230, 2240, and 2250. The non-volatile memory 2230, 2240, and 2250 can be vertically stacked NAND flash memory devices. In this case, the SSD 2200 can be configured using a reference... Figures 1 to 19 The described embodiments are implemented.

[0150] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for reading a non-volatile storage device, the method comprising: A first sensing operation is performed on a selected memory cell connected to a selected word line and a first read voltage is applied to the selected word line. The first sensing operation is performed by dividing a plurality of memory cells connected to the selected word line into a first group and a second group. The first group of the plurality of memory cells is connected to a plurality of even-numbered page buffers through a plurality of even-numbered bit lines of the plurality of memory cells, and the second group of the plurality of memory cells is connected to a plurality of odd-numbered page buffers through a plurality of odd-numbered bit lines of the plurality of memory cells. The first sensing operation searches for a first valley location. The target read level is determined based on the location of the first valley. A second sensing operation is performed on the selected memory cell and a second read voltage is applied to the selected word line, wherein the second sensing operation is performed by dividing the plurality of memory cells into a first group and a second group, wherein a second valley position is searched through the second sensing operation; Based on the location of the second valley, determine the target generation time point of the sensing node connected to the selected storage unit; and A main read operation is performed on the selected memory cell by using the target read level and the target generation time point.

2. The method according to claim 1, wherein, Performing the first sensing operation and performing the second sensing operation includes performing an even-number read operation and then performing an odd-number read operation, wherein the even-number read operation latches the voltage level of the sensing nodes connected to the plurality of even-number page buffers, and the odd-number read operation latches the voltage level of the sensing nodes connected to the plurality of odd-number page buffers.

3. The method according to claim 1, wherein, Performing the first sensing operation and performing the second sensing operation includes performing an odd-number read operation and then performing an even-number read operation, wherein the odd-number read operation latches the voltage level of the sensing nodes connected to the plurality of odd-number page buffers, and the even-number read operation latches the voltage level of the sensing nodes connected to the plurality of even-number page buffers.

4. The method according to claim 1, wherein, In the execution of the second sensing operation, the second read voltage applied to the selected word line is changed n times, and the second sensing operation is performed n times, where n is a number equal to or greater than 3.

5. A method for reading data from a selected memory cell of a non-volatile storage device comprising a plurality of memory cells, the method comprising: Perform a two-step parity sensing operation on the selected memory cell; Based on the results of the two-step parity sensing operation, a first main sensing operation is performed on the selected memory cell; Perform a parity sensing operation on the selected memory cell; as well as Based on the result of the first-step parity sensing operation, a second main sensing operation is performed on the selected memory cell; Specifically, the two-step parity sensing operation is performed to identify programming states from the programming states of the plurality of memory cells that have shifted by more than a first threshold amount corresponding to the degradation, and the one-step parity sensing operation is performed to identify programming states from the programming states of the plurality of memory cells that have shifted by less than a second threshold amount corresponding to the degradation.

6. The method according to claim 5, wherein, Performing the two-step parity sensing operation includes: A first sensing operation is performed on the selected memory cell and a first read voltage is applied to the selected word line connected to the selected memory cell. The first sensing operation is performed by dividing a plurality of memory cells connected to the selected word line into a first group and a second group. The first group of the plurality of memory cells is connected to a plurality of even-numbered page buffers through a plurality of even-numbered bit lines of the plurality of bit lines of the plurality of memory cells, and the second group of the plurality of memory cells is connected to a plurality of odd-numbered page buffers through a plurality of odd-numbered bit lines of the plurality of bit lines of the plurality of memory cells. The first valley location is searched through the first sensing operation. The target read level of the first read voltage is determined based on the location of the first valley. A second sensing operation is performed on the selected memory cell and a second read voltage is applied to the selected word line, wherein the second sensing operation is performed by dividing the plurality of memory cells into a first group and a second group, wherein a second valley location is searched through the second sensing operation; and Based on the location of the second valley, the target generation time point of the sensing node connected to the selected storage unit is determined.

7. The method according to claim 6, wherein, Performing the first primary sensing operation includes: performing a read operation on the selected storage unit by using the target read level and the target generation time point.

8. The method according to claim 6, wherein, Performing the first sensing operation and performing the second sensing operation includes performing an even-number read operation and then performing an odd-number read operation, wherein the even-number read operation latches the voltage level of the sensing nodes connected to the plurality of even-number page buffers, and the odd-number read operation latches the voltage level of the sensing nodes connected to the plurality of odd-number page buffers.

9. The method according to claim 6, wherein, Performing the first sensing operation and performing the second sensing operation includes performing an odd-number read operation and then performing an even-number read operation, wherein the odd-number read operation latches the voltage level of the sensing nodes connected to the plurality of odd-number page buffers, and the even-number read operation latches the voltage level of the sensing nodes connected to the plurality of even-number page buffers.

10. The method according to claim 6, wherein, In the execution of the second sensing operation, the second read voltage applied to the selected word line is changed n times, and the second sensing operation is performed n times, where n is a number equal to or greater than 3.

11. A method of operating a storage device including a non-volatile storage device and a controller for controlling the non-volatile storage device, the method comprising: Send a read command from the controller to the non-volatile storage device; The non-volatile storage device is read according to the read command, and the read data of the read operation is sent to the controller. The controller performs an error correction code operation on the read data; When the result of the error correction code operation indicates that the error in the read data is uncorrectable, a two-step parity sensing operation is performed on the non-volatile storage device. as well as Based on the results of the two-step parity sensing operation, the optimal read level for reading data stored in multiple memory cells of the non-volatile storage device is determined.

12. The operating method according to claim 11, wherein, Performing the two-step parity sensing operation includes: A first sensing operation is performed on a selected memory cell among the plurality of memory cells, and a first read voltage is applied to a selected word line connected to the selected memory cell. The first sensing operation is performed by dividing the plurality of memory cells connected to the selected word line into a first group and a second group. The first group of the plurality of memory cells is connected to a plurality of even-numbered page buffers through a plurality of even-numbered bit lines among the plurality of bit lines of the plurality of memory cells, and the second group of the plurality of memory cells is connected to a plurality of odd-numbered page buffers through a plurality of odd-numbered bit lines among the plurality of bit lines of the plurality of memory cells. The first valley location is searched through the first sensing operation. Based on the location of the first valley, determine the target read level of the first read voltage; A second sensing operation is performed on the selected memory cell, and a second read voltage is applied to the selected word line, wherein the second sensing operation is performed by dividing the plurality of memory cells into a first group and a second group, wherein a second valley location is searched through the second sensing operation; and Based on the location of the second valley, the target generation time point of the sensing node connected to the selected storage unit is determined.

13. The operating method according to claim 12, wherein, Performing the first sensing operation and performing the second sensing operation includes performing an even-number read operation and then performing an odd-number read operation, wherein the even-number read operation latches the voltage level of the sensing nodes connected to the plurality of even-number page buffers, and the odd-number read operation latches the voltage level of the sensing nodes connected to the plurality of odd-number page buffers.

14. The operating method according to claim 12, wherein, Performing the first sensing operation and performing the second sensing operation includes performing an odd-number read operation and then performing an even-number read operation, wherein the odd-number read operation latches the voltage level of the sensing nodes connected to the plurality of odd-number page buffers, and the even-number read operation latches the voltage level of the sensing nodes connected to the plurality of even-number page buffers.

15. The operating method according to claim 12, wherein, In the execution of the second sensing operation, the second read voltage applied to the selected word line is changed n times, and the second sensing operation is performed n times, where n is a number equal to or greater than 3.

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