Magnetic storage device and method for manufacturing the same

Abstract

The present invention provides a magnetic storage device and a method for manufacturing the same. The magnetic storage device includes a first switching element and a second switching element, a first stack and a second stack disposed on the first switching element and the second switching element, respectively, a first insulator disposed on a side surface of the first stack, and a second insulator disposed on a side surface of the second stack. The first switching element and the second switching element each contain a variable resistance material. The first stack and the second stack each include a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first and second ferromagnetic layers. The narrowest distance between the first insulator and the second insulator is narrower than the narrowest distance between the first switching element and the second switching element.

Description

Technical Field

[0001] Embodiments generally relate to magnetic storage devices and methods of manufacturing magnetic storage devices. Background Art

[0002] A storage device using a magnetoresistive element is known. Summary of the Invention

[0003] A magnetic storage device comprises: a first switching element and a second switching element, each of which contains a variable resistance material; a first stack and a second stack, which are respectively arranged on the first switching element and the second switching element, and the first stack and the second stack each include a first ferromagnetic layer, a second ferromagnetic layer and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer; a first insulator on a side surface of the first stack; and a second insulator on a side surface of the second stack, the narrowest distance between the first insulator and the second insulator being narrower than the narrowest distance between the first switching element and the second switching element. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 Functional blocks of the magnetic storage device according to the first embodiment are shown.

[0005] Figure 2 This is a circuit diagram of the memory cell array according to the first embodiment.

[0006] Figure 3 The structure of a portion of a cross section of the memory cell array according to the first embodiment is shown.

[0007] Figure 4 The structure of a portion of a cross section of the memory cell array according to the first embodiment is shown.

[0008] Figure 5 A cross section showing an example of the memory cell structure according to the first embodiment is shown.

[0009] Figure 6 The structure of the magnetic storage device according to the first embodiment at a certain point in time during a portion of the manufacturing process is shown.

[0010] Figure 7 Indicates next Figure 6 The construction of the time point.

[0011] Figure 8 Indicates next Figure 7 The construction of the time point.

[0012] Figure 9 Indicates next Figure 8 The construction of the time point.

[0013] Figure 10 Indicates next Figure 9 The construction of the time point.

[0014] Figure 11 Indicates next Figure 10 The construction of the time point.

[0015] Figure 12 Indicates next Figure 11 The construction of the time point.

[0016] Figure 13 A state during a reference manufacturing process of a magnetic storage device is shown.

[0017] Figure 14 Indicates next Figure 13 The construction of the time point.

[0018] Figure 15 Indicates next Figure 14 The construction of the time point. DETAILED DESCRIPTION

[0019] A magnetic storage device according to one embodiment includes a first switching element and a second switching element, a first stack and a second stack provided on the first switching element and the second switching element, respectively, a first insulator provided on a side surface of the first stack, and a second insulator provided on a side surface of the second stack. The first switching element and the second switching element each contain a variable resistance material. The first stack and the second stack each include a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first and second ferromagnetic layers. The narrowest distance between the first and second insulators is narrower than the narrowest distance between the first and second switching elements.

[0020] The following describes the embodiments with reference to the accompanying drawings. In the following description, components having substantially the same function and structure are sometimes denoted by the same reference numeral, and duplicate descriptions are sometimes omitted. In order to distinguish multiple components having substantially the same function and structure from each other, numbers or letters may be added to the end of the reference numerals.

[0021] The accompanying drawings are schematic, and the relationship between thickness and plane dimensions, the ratio of thickness of each layer, etc. may be different from the actual ones. In addition, the drawings may also include parts with different dimensional relationships and ratios. For the description of a certain embodiment, as long as it is explicitly or self-evidently excluded, it is also appropriate to describe all of them as other embodiments. Each embodiment is an example of an embodiment of an apparatus or method for concretizing the technical idea of ​​the embodiment. The technical idea of ​​the embodiment does not specify the material, shape, structure, configuration, etc. of the constituent parts to the following materials, shapes, structures, configurations, etc.

[0022] Hereinafter, the embodiments will be described using the xyz orthogonal coordinate system. In the following description, the term "lower" and its derivatives and related terms refer to the smaller coordinate position on the z-axis, and the term "upper" and its derivatives and related terms refer to the larger coordinate position on the z-axis.

[0023] 1. First Implementation

[0024] 1.1. Construction (Structure)

[0025] 1.1.1. Overall structure

[0026] Figure 1 1 shows the functional blocks of the magnetic storage device of the first embodiment. Figure 1 As shown, the magnetic memory device 1 includes a memory cell array 11 , an input / output circuit 12 , a control circuit 13 , a row selection circuit 14 , a column selection circuit 15 , a write circuit 16 , and a read circuit 17 .

[0027] The memory cell array 11 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL. The memory cells MC can store data in a nonvolatile manner. Each memory cell MC is connected to a word line WL and a bit line BL. Word lines WL are associated with rows. Bit lines BL are associated with columns. Selecting a row and one or more columns determines the location of one or more memory cells MC.

[0028] The input / output circuit 12 receives various control signals CNT, various commands CMD, address signals ADD, and data (write data) DAT from the memory controller 2 , and transmits data (read data) DAT to the memory controller 2 .

[0029] The row selection circuit 14 receives the address signal ADD from the input / output circuit 12 and sets one word line WL associated with the row specified by the received address signal ADD to a selected state.

[0030] The column selection circuit 15 receives the address signal ADD from the input / output circuit 12 and sets the plurality of bit lines BL associated with the column identified by the received address signal ADD to a selected state.

[0031] The control circuit 13 receives a control signal CNT and a command CMD from the input / output circuit 12. Based on the control signal CNT and the command CMD, the control circuit 13 controls the write circuit 16 and the read circuit 17. Specifically, the control circuit 13 supplies a voltage used for writing data to the write circuit 16 while data is being written to the memory cell array 11. Furthermore, the control circuit 13 supplies a voltage used for reading data to the read circuit 17 while data is being read from the memory cell array 11.

[0032] The write circuit 16 receives write data DAT from the input / output circuit 12 , and supplies a voltage used for data writing to the column selection circuit 15 based on the control of the control circuit 13 and the write data DAT.

[0033] The read circuit 17 includes a sense amplifier and uses a voltage used for data reading to obtain data held in the memory cell MC under the control of the control circuit 13. The obtained data is supplied to the input / output circuit 12 as read data DAT.

[0034] 1.1.2. Circuit Structure of Memory Cell Array

[0035] Figure 2 FIG. 1 is a circuit diagram of the memory cell array 11 according to the first embodiment. Figure 2 As shown, the memory cell array 11 includes M+1 (M is a natural number) word lines WLa (WLa<0>, WLa<1>, ..., WLa<M>) and M+1 word lines WLb (WLb<0>, WLb<1>, ..., WLb<M>). In addition, the memory cell array 11 includes N+1 (N is a natural number) bit lines BL (BL<0>, BL<1>, ..., BL<N>).

[0036] Each memory cell MC (MCa and MCb) has two nodes: the first node is connected to a word line WL, and the second node is connected to a bit line BL. More specifically, for all combinations of α being an integer from 0 to M and β being an integer from 0 to N, memory cell MCa includes memory cells MCa<α, β>, and memory cells MCa<α, β> are connected between word line WLa<α> and bit line BL<β>. Similarly, for all combinations of α being an integer from 0 to M and β being an integer from 0 to N, memory cell MCb includes memory cells MCb<α, β>, and memory cells MCb<α, β> are connected between word line WLb<α> and bit line BL<β>.

[0037] Each memory cell MC includes a magnetoresistive element VR (VRa or VRb) and a switching element SE (SEa or SEb). More specifically, for all combinations of cases where α is an integer between 0 and M and all combinations of cases where β is an integer between 0 and N, the memory cell MCa<α, β> includes the magnetoresistive element VRa<α, β> and the switching element SEa<α, β>. Furthermore, for all combinations of cases where α is between 0 and M and all combinations of cases where β is an integer between 0 and N, the memory cell MCb<α, β> includes the magnetoresistive element VRb<α, β> and the switching element SEb<α, β>.

[0038] In each memory cell MC, a magnetoresistive element VR and a switch element SE are connected in series. The magnetoresistive element VR is connected to one word line WL, and the switch element SE is connected to one bit line BL.

[0039] The magnetoresistive element VR can switch between a low resistance state and a high resistance state, and can store 1 bit of data by utilizing the difference between these two resistance states.

[0040] The switching element SE can be, for example, a switching element as described below. The switching element has two terminals, and when a voltage less than a first threshold value is applied between the two terminals in a first direction, the switching element is in a high resistance state, for example, an electrically non-conductive state (off state). On the other hand, when a voltage greater than a first threshold value is applied between the two terminals in the first direction, the switching element is in a low resistance state, for example, an electrically conductive state (on state). The switching element further has the same function as the switching function between a high resistance state and a low resistance state based on the magnitude of the voltage applied in the first direction in a second direction opposite to the first direction. The switching element is a bidirectional switching element. By turning the switching element on or off, it is possible to control whether or not current is supplied to the magnetoresistance effect element VR connected to the switching element, that is, whether the magnetoresistance effect element VR is selected or not.

[0041] 1.1.3. Memory Cell Array Structure

[0042] Figure 3 and Figure 4 FIG. 1 shows a partial cross-sectional structure of the memory cell array 11 according to the first embodiment. Figure 3 represents the cross section along the xz plane, Figure 4 represents the cross section along the yz plane.

[0043] like Figure 3 and Figure 4 As shown, a plurality of conductors 21 are provided above a semiconductor substrate (not shown). The conductors 21 extend along the y-axis and are arranged along the x-axis. Each conductor 21 functions as a word line WL.

[0044] Each conductor 21 is connected on its top surface to the bottom surface of each of the multiple memory cells MCb. The memory cells MCb have, for example, a circular shape in the xy plane. The memory cells MCb are arranged along the y-axis on each conductor 21. This arrangement forms a matrix arrangement of the memory cells MCb in the xy plane. Each memory cell MCb includes a structure that functions as a switching element SEb and a structure that functions as a magnetoresistive element VRb. As described below, the structure that functions as the switching element SEb and the structure that functions as the magnetoresistive element VRb each include one or more layers.

[0045] Multiple conductors 22 are provided above the memory cells MCb. The conductors 22 extend along the x-axis and are arranged along the y-axis. The bottom surface of each conductor 22 contacts the top surface of each of the multiple memory cells MCb arranged along the x-axis. Each conductor 22 functions as a bit line BL.

[0046] Each conductor 22 is connected on its top surface to the bottom surface of each of the multiple memory cells MCa. The memory cells MCa have, for example, a circular shape in the xy plane. The memory cells MCa are arranged along the x-axis on each conductor 22. This arrangement forms a matrix arrangement of the memory cells MCa in the xy plane. Each memory cell MCa includes a structure that functions as a switching element SEa and a structure that functions as a magnetoresistive element VRa. As described below, the structure that functions as the switching element SEa and the structure that functions as the magnetoresistive element VRa each include one or more layers.

[0047] A conductor 21 is further provided on the upper surface of each of the plurality of memory cells MCa arranged along the y-axis.

[0048] By repeatedly setting along the z axis Figure 3 and Figure 4 The structure from the bottom conductor 21 layer to the memory cell MCa layer can achieve the following Figure 2 The memory cell array 11 is shown.

[0049] The memory cell array 11 further includes a conductor 21 , a conductor 22 , and an interlayer insulator in a region where no memory cells MC are provided.

[0050] 1.1.4. Storage Unit Structure

[0051] Figure 5 A cross section showing an example of the structure of the memory cell according to the first embodiment. Figure 5 It represents the structure of the layer where a certain conductor 22 is located and the layer from this layer to the layer where the previous conductor 21 is located along the z-axis. Figure 5 The memory cell MC shown corresponds to the memory cell MCa.

[0052] like Figure 5 As shown, an interlayer insulator 23 is provided above a semiconductor substrate (not shown). Conductors 22 are provided in the interlayer insulator 23. Memory cells MC are located on the upper surfaces of the conductors 22. Each memory cell MC includes a switching element SE, a magnetoresistive element VR, a hard mask 35, and sidewall insulators 36. Memory cells MC may also include other layers.

[0053] Each switching element SE is located on the upper surface of one conductor 22 and has a tapered side surface. Each switching element SE may have a truncated cone shape, for example. When the switching element SE has a truncated cone shape, the switching element SE is Figure 5 The structure in the cross section is different from the cross section shown Figure 5 The structure shown and described below is the same.

[0054] The switching element SE includes at least a variable resistance material (layer) 25. The switching element SE may further include a lower electrode 24 and an upper electrode 26. In this case, the lower electrode 24 is located on the upper surface of the conductor 22, the variable resistance material 25 is located on the upper surface of the lower electrode 24, and the upper electrode 26 is located on the upper surface of the variable resistance material 25. The following description is based on an example in which the switching element SE includes the lower electrode 24 and the upper electrode 26.

[0055] Lower electrode 24 is located on the upper surface of conductor 22 and comprises, for example, titanium nitride (TiN) or consists essentially of TiN. In this specification and claims, "consisting essentially of" and similar expressions including "essentially" mean that the elements "consisting essentially of" are allowed to contain unintentional impurities.

[0056] The variable resistor material 25 is, for example, a two-terminal switching element, wherein the first terminal of the two terminals corresponds to one of the upper surface and the bottom surface of the variable resistor material 25, and the second terminal of the two terminals corresponds to the other of the upper surface and the bottom surface of the variable resistor material 25. When the voltage applied between the two terminals is less than the threshold value, the switching element is in a "high resistance" state, such as an electrically non-conductive state. When the voltage applied between the two terminals is greater than the threshold value, the switching element changes to a "low resistance" state, such as an electrically conductive state. The variable resistor material 25 is formed of a material including an insulator and contains a dopant introduced by ion implantation. The insulator includes, for example, an oxide, including SiO2 or a material substantially composed of SiO2. The dopant includes, for example, arsenic (As) and germanium (Ge).

[0057] The upper electrode 26 is located on the upper surface of the variable resistance material 25 and includes, for example, TiN or is substantially composed of TiN.

[0058] One magnetoresistance effect element VR is located on the upper surface of each upper electrode 26. The magnetoresistance effect element VR is tapered on the side. Each magnetoresistance effect element VR may have a truncated cone shape, for example. When the magnetoresistance effect element VR has a truncated cone shape, the magnetoresistance effect element VR is Figure 5 The structure in the cross section is different from the cross section shown. Figure 5 The structure shown and described below is the same.

[0059] Each magnetoresistance effect element VR exhibits a tunnel magnetoresistance effect. In this embodiment and the modified examples described below, the elements are described as including a magnetic tunnel junction (MTJ). Specifically, the magnetoresistance effect element VR includes a ferromagnetic layer 31, an insulating layer 32, and a ferromagnetic layer 33. As an example, Figure 5As shown, the insulating layer 32 is located on the upper surface of the ferromagnetic layer 31 , and the ferromagnetic layer 33 is located on the upper surface of the insulating layer 32 .

[0060] The ferromagnetic layer 31 has an easy magnetization axis that extends along the interface between the ferromagnetic layer 31, the insulating layer 32, and the ferromagnetic layer 33. For example, the easy magnetization axis has an angle of at least 45° and not more than 90° relative to the interface, or, for example, has an easy magnetization axis that extends perpendicularly to the interface. The magnetization direction of the ferromagnetic layer 31 is intended to remain unchanged even during data reading and writing in the magnetic storage device 1. The ferromagnetic layer 31 can function as a so-called reference layer. The ferromagnetic layer 31 may also include multiple layers.

[0061] The insulating layer 32 contains, for example, magnesium oxide (MgO) or consists essentially of MgO, and functions as a so-called tunnel barrier.

[0062] The ferromagnetic layer 33 includes, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or is substantially composed of CoFeB or FeB. The ferromagnetic layer 33 has an easy magnetization axis that extends along the interface between the ferromagnetic layer 31, the insulating layer 32, and the ferromagnetic layer 33. For example, the easy magnetization axis has an angle of at least 45° and no greater than 90° relative to the interface, or is perpendicular to the interface. The magnetization direction of the ferromagnetic layer 33 is variable due to data writing, enabling the ferromagnetic layer 33 to function as a so-called storage layer.

[0063] When the magnetization direction of the ferromagnetic layer 33 is parallel to the magnetization direction of the ferromagnetic layer 31, the magnetoresistive element VR has a relatively low resistance. When the magnetization direction of the ferromagnetic layer 33 is antiparallel to the magnetization direction of the ferromagnetic layer 31, the magnetoresistive element VR has a higher resistance than when the magnetization directions of the ferromagnetic layers 31 and 33 are antiparallel.

[0064] When a write current of a certain magnitude flows from the ferromagnetic layer 33 to the ferromagnetic layer 31, the magnetization direction of the ferromagnetic layer 33 becomes parallel to the magnetization direction of the ferromagnetic layer 31. On the other hand, when a write current of another certain magnitude flows from the ferromagnetic layer 31 to the ferromagnetic layer 33, the magnetization direction of the ferromagnetic layer 33 becomes antiparallel to the magnetization direction of the ferromagnetic layer 31.

[0065] The hard mask 35 is located on the upper surface of the magnetoresistive element VR, for example, the upper surface of the ferromagnetic layer 33. The hard mask 35 is formed of a conductor, for example, contains TiN, or consists essentially of TiN.

[0066] The side surfaces of the magnetoresistive element VR are covered by a sidewall insulator 36. As described below, the sidewall insulator 36 has an etching rate for reactive ion etching (RIE) that is lower than the etching rate of at least one component included in the switching element SE. Hereinafter, the etching rate for RIE is sometimes referred to as the RIE etching rate. As a more specific example, the sidewall insulator 36 has an RIE etching rate that is lower than the RIE etching rate of all components included in the switching element SE. When based on the current example, the sidewall insulator 36 has an RIE etching rate that is lower than the RIE etching rate of each of the upper electrode 26, the variable resistance material 25, and the lower electrode 24.

[0067] In order to have such an RIE etching rate, the sidewall insulator 36 may include a first material having the characteristics described below, or may be substantially composed of the first material. The first material is an oxide having a bond dissociation energy with oxygen that is higher than the bond dissociation energy with oxygen of the materials of one, more, or all of the components included in the switching element SE. For example, the first material has a bond dissociation energy with oxygen exceeding 500 kJ / mol. More specific examples of the first material include oxides of hafnium (Hf), aluminum (Al), scandium (Sc), gadolinium (Gd), tantalum (Ta), and yttrium (Y). That is, examples of the first material include hafnium oxide (HfO2), aluminum oxide (Al2O3), scandium oxide (Sc2O3), gadolinium oxide (Gd2O3), tantalum oxide (Ta2O5), and yttrium oxide (Y2O3).

[0068] The conductor 21 is located on the upper surface of the hard mask 35 of each of the plurality of memory cells MC arranged along the y-axis.

[0069] The area PA between the switching elements SE of two adjacent memory cells MC has the dimensions described below. The minimum spacing D1 between the magnetoresistance elements VR of two adjacent memory cells MC is smaller than the minimum spacing D2 between the switching elements SE of the two memory cells MC. The spacing is, for example, the distance between the two closest positions of two elements of interest. Since the side surfaces of the magnetoresistance elements VR and the switching elements SE are tapered, the spacing D1 is, for example, the spacing between the respective edges (ends) of the upper ends of the magnetoresistance elements VR of the two adjacent memory cells MC. Furthermore, the spacing D2 is, for example, the spacing between the respective edges of the lower ends of the switching elements SE of the two adjacent memory cells MC.

[0070] In the region from the upper surface of the interlayer insulator 23 to the upper surface of the hard mask 35 , an interlayer insulator 37 is provided in a portion where no elements are provided.

[0071] Manufacturing method

[0072] Figures 6 to 11 The structure of the magnetic storage device according to the first embodiment during a portion of the manufacturing process will be sequentially shown. Figures 6 to 11 Represents Figure 5 The cross-section shown is the same cross-section.

[0073] like Figure 6 As shown, conductor 22, interlayer insulator 23, lower electrode 24A, variable resistance material 25A, upper electrode 26A, ferromagnetic layer 31A, insulating layer 32A, ferromagnetic layer 33A, and hard mask 35A are formed. Specifically, multiple conductors 22 are formed within interlayer insulator 23. Next, lower electrode 24A, variable resistance material 25A, upper electrode 26A, ferromagnetic layer 31A, insulating layer 32A, ferromagnetic layer 33A, and hard mask 35A are deposited in this order on the upper surface of interlayer insulator 23 and the upper surface of conductor 22. Examples of deposition methods include chemical vapor deposition (CVD) and sputtering. The lower electrode 24A, variable resistance material 25A, upper electrode 26A, ferromagnetic layer 31A, insulating layer 32A, and ferromagnetic layer 33A are elements that will be formed into the lower electrode 24, variable resistance material 25, upper electrode 26, ferromagnetic layer 31, insulating layer 32, and ferromagnetic layer 33, respectively, in subsequent steps. The hard mask 35A remains directly above the region where the magnetoresistive element VR is to be formed, and has openings 35A1 in other regions. The openings 35A1 extend from the top surface of the hard mask 35A to the bottom surface.

[0074] The interval between memory cells MC depends on the area of ​​opening 35A1. In order to arrange memory cells MC at a high density, the area of ​​opening 35A1 is very narrow.

[0075] like Figure 7As shown, multiple groups of ferromagnetic layers 31, insulating layers 32, and ferromagnetic layers 33 are formed. Specifically, the structure obtained through the steps thus far is partially removed by ion beam etching (IBE). The ion beam is angled relative to the z-axis. This ion beam penetrates into opening 35A1 of hard mask 35A, partially removing the elements exposed within opening 35A1. A portion of the ion beam is blocked by hard mask 35A, meaning that due to the shielding effect provided by hard mask 35A, it does not reach the deep areas within opening 35A1. However, hard mask 35A is also partially removed by IBE, and as IBE proceeds, the upper surface of hard mask 35A gradually lowers. As a result, as IBE proceeds, the ion beam reaches deeper areas within opening 35A1. IBE continues at least until the ferromagnetic layer 31A, the insulating layer 32A, and the ferromagnetic layer 33A are partially removed, forming multiple sets of ferromagnetic layer 31, insulating layer 32, and ferromagnetic layer 33. IBE is performed while the target structure is rotated about the z-axis. Therefore, as IBE progresses, the edges of the exposed elements in the xy plane move evenly toward the center of the element. IBE partially exposes the top surface of the upper electrode 26A between the structures (sometimes referred to as unit stacks) consisting of the sets of hard mask 35A, ferromagnetic layer 31, insulating layer 32, and ferromagnetic layer 33.

[0076] As mentioned above, in order to arrange the memory cells MC at a high density, the area of ​​the opening 35A1 is very small. Therefore, the area of ​​the region VA between adjacent unit stacks on the xy plane is also very small, and the width or diameter of the region VA on the xy plane is very small. In other words, the aspect ratio of the region VA is very high. Hereinafter, "width" refers to, for example, the length of a straight line passing through the center on the xy plane. Due to the very high aspect ratio of the region VA and the shielding effect achieved by the hard mask 35A, the unit stack has a tapered shape on the side. That is, the unit stack has a width greater at the lower end than at the upper end. Therefore, the width of the bottom surface of the region VA, that is, the distance between the ends of the bottom surfaces of adjacent unit stacks, is smaller than the width of the top surface of the region VA, that is, the distance between the ends of the top surfaces of adjacent unit stacks. In other words, the side surface of the region VA is inverted tapered. Due to the narrow spacing between the unit stacks, the bottom surface of the region VA is very narrow.

[0077] like Figure 8As shown, an insulator 36A is deposited over the entire upper surface of the structure obtained through the steps thus far. Insulator 36A is an element that will be formed into sidewall insulator 36 in a subsequent step. Insulator 36A covers the exposed portion of the upper surface of upper electrode 26A, the side surfaces of the unit stack (the side surfaces of ferromagnetic layer 31, insulating layer 32, ferromagnetic layer 33, and hard mask 35A), and the upper surface of hard mask 35A.

[0078] like Figure 9 As shown, insulator 36A is etched back. This etch back removes portions of insulator 36A above the exposed portion of the upper surface of upper electrode 26A and portions of the upper surface of hard mask 35A. As a result, portions of the upper surface of upper electrode 26A between the unit stacks are exposed. Furthermore, portions of the side surfaces of insulator 36A, including ferromagnetic layer 31, insulating layer 32, ferromagnetic layer 33, and hard mask 35A, are thinned by the etch back.

[0079] like Figure 10 As shown, multiple groups of upper electrodes 26B, variable resistor material 25B, and lower electrodes 24B are formed. That is, RIE is performed on the structure obtained through the processes thus far. Ions from RIE enter the region VA between the unit stacks, thereby removing the upper surface of the upper electrode 26A. As RIE proceeds, RIE further removes portions of the upper electrode 26A, variable resistor material 25A, and lower electrode 24A below region VA. During RIE, the unit stacks and insulator 36A function as masks. RIE continues until an opening is formed in the lower electrode 24A below region VA, extending from the upper surface of the lower electrode 24A to the bottom surface. Through RIE, the upper electrode 26A, variable resistor material 25A, and lower electrode 24A are formed. As a result of this formation, region PA1 is formed below region VA, and multiple groups of upper electrodes 26B, variable resistor material 25B, and lower electrodes 24B are formed. The set of the upper electrode 26B, the variable resistance material 25B, and the lower electrode 24B is sometimes referred to as a switching element stack below. The switching element stack is located below the unit stack.

[0080] The width or diameter of the opening in region PA1 (i.e., the width or diameter at the same height as the upper surface of upper electrode 26B) is equal to the distance between the lower ends of adjacent unit stacks (or the width or diameter of the lower end of region VA). As described above, the distance between the lower ends of adjacent unit stacks is very narrow. Therefore, the opening in region PA1 is very narrow.

[0081] RIE is isotropic. However, due to the extremely narrow opening of region PA1 and the large ratio of the opening to the thickness of the group of upper electrode 26B, variable resistor material 25B, and lower electrode 24B that are the subject of RIE, the side surfaces of the switching element stack are tapered. Specifically, the width of the bottom surface of region PA1, or the distance between the ends of the bottom surfaces of adjacent switching element stacks, is smaller than the width of the bottom surface of region VA, or the distance between the ends of the top surfaces of adjacent switching element stacks. In other words, the side surfaces of region PA1 are tapered. Due to the extremely narrow opening of region PA1 and the tapered side surfaces of region PA1, the width or diameter of the bottom surface of region PA1 is extremely small. As a result, the spacing between the lower ends of adjacent unit stacks is extremely small.

[0082] like Figure 11 As shown, ongoing Figure 10 The RIE in the process of forming multiple sets of upper electrodes 26, variable resistor materials 25, and lower electrodes 24 is performed. Specifically, as the RIE progresses, the side surfaces of upper electrodes 26B, variable resistor materials 25B, and lower electrodes 24B are further removed, and the widths or diameters of upper electrodes 26B, variable resistor materials 25B, and lower electrodes 24B are further reduced. As a result, multiple sets of upper electrodes 26, variable resistor materials 25, and lower electrodes 24 are formed, and region PA1 becomes region PA.

[0083] in addition, Figure 10 and Figure 11 The RIE thinned insulator 36A is shown. Figure 5 As described, the insulator 36A (sidewall insulator 36) has an RIE etching rate lower than the RIE etching rate of at least one component included in the switching element SE, for example, an RIE etching rate lower than the RIE etching rate of each of the upper electrode 26, the variable resistance material 25, and the lower electrode 24. Therefore, the thickness of the insulator 36A is not significantly reduced by RIE. At least, it will not be completely removed until the end of RIE, that is, until the formation of multiple groups of upper electrodes 26, variable resistance materials 25, and lower electrodes 24 originating from the upper electrode 26A, the variable resistance material 25A, and the lower electrode 24A. In other words, considering the need to continue the period of performing RIE until the upper electrode 26, the variable resistance material 25, and the lower electrode 24 are formed, Figure 8 The insulator 36A formed in the step has a thickness such that the sidewall insulator 36 remains even after RIE. Thus, as a result of RIE, the sidewall insulator 36 is formed from the insulator 36A.

[0084] like Figure 12As shown, in the region from the upper surface of the interlayer insulator 23 to the upper surface of the hard mask 35 , an interlayer insulator 37 is formed in a portion where no elements are provided.

[0085] like Figure 5 As shown, the conductor 21 is formed on the upper surface of the interlayer insulator 37 and the upper surface of the hard mask 35 .

[0086] 1.3. Effect

[0087] According to the first embodiment, as described below, it is possible to provide a magnetic memory device that can suppress dielectric breakdown and deterioration of magnetic characteristics of memory cells MC.

[0088] Figure 5 The structure shown can be considered to be formed through the steps described below. Figures 13 to 15 A state during the manufacturing process of the magnetic storage device for reference is shown, and the magnetic storage device 1 is shown. Figure 5 The parts are equivalent to the parts of the structure.

[0089] like Figure 13 As shown, the first embodiment is carried out Figure 9 The steps to this end are the same as those in the reference manufacturing process. Insulator 136A is deposited instead of insulator 36A in the first embodiment. Insulator 136A is an element intended to have the same function as insulator 36A and is intended to be formed into a sidewall insulator having the same function as sidewall insulator 36 through subsequent steps. Insulator 136A does not have the low RIE etching rate of sidewall insulator 36 and is formed of, for example, silicon nitride (Si3N4).

[0090] like Figure 14 As shown, by the first embodiment Figure 10 and Figure 11In the same process as shown, the upper electrode 26B, the variable resistance material 25B, and the lower electrode 24B are formed by RIE. The insulator 136A does not have a low RIE etching rate, so the insulator 136A will be thinned in a short time by RIE. RIE needs to be stopped before the insulator 136A is completely etched. The insulator 136A thins quickly, so the time available for RIE is short. Therefore, at the time when RIE is completed, the spacing between the upper electrode 26B, the spacing between the variable resistance material 25B, and the spacing between the lower electrode 24B is very narrow. As a result, insulation breakdown is likely to occur at these spacings. Depending on the situation, the formation of the upper electrode 26B, the variable resistance material 25B, and the lower electrode 24B may not be fully completed. In this case, the upper electrodes 26B, the variable resistance material 25B, and / or the lower electrodes 24B may be connected across adjacent memory cells MC. Such a structure cannot be used as a memory cell.

[0091] In order to suppress and / or prevent such dielectric breakdown and / or inability to form a memory cell, it is conceivable to continue performing RIE. Figure 15 express Figure 14 The subsequent state of the state. Figure 15 As shown, continued RIE may completely remove insulator 136A. The disappearance of insulator 136A exposes the side surfaces of the magnetoresistive element VR. The exposed side surfaces are damaged by RIE, degrading the magnetic properties of the damaged magnetoresistive element VR. A magnetoresistive element VR with degraded magnetic properties may fail to exhibit the expected performance.

[0092] Reference Figures 13 to 15 The phenomenon described above is caused by the insulator 136A being formed of silicon nitride. The reason for using silicon nitride is that it has high performance as the sidewall of the magnetoresistive element VR. When a transistor is used in the memory cell MC instead of the switching element SE, which enables high-density configuration of the memory cell MC, RIE for forming the switching element SE is not required. Therefore, no reference is generated. Figures 13 to 15 However, it was found that due to the use of the switching element SE, a reference Figures 13 to 15 Therefore, it is desirable to use the switching element SE and suppress or avoid Figures 13 to 15 The phenomenon shown.

[0093] According to the first embodiment, the sidewall insulator 36 has an RIE etching rate lower than the RIE etching rate of at least one component included in the switching element SE, for example, an RIE etching rate lower than the RIE etching rate of each of the upper electrode 26, the variable resistance material 25, and the lower electrode 24. As a result, the sidewall insulator 36 can be sufficiently left, and RIE can be continued for a long time on the upper electrode 26A, the variable resistance material 25A, and the lower electrode 24A. Therefore, the spacing between the upper electrodes 26, the spacing between the variable resistance material 25, and (or) the spacing between the lower electrodes 24 can be wide. This makes it difficult to cause insulation breakdown between the upper electrodes 26, between the variable resistance material 25, and (or) between the lower electrodes 24. At the same time, the presence (remaining) of the sidewall insulator 36 can suppress or avoid degradation of the magnetic properties of the magnetoresistive element VR. Thus, a magnetic storage device can be provided that can suppress insulation breakdown and suppress degradation of the magnetic properties of the memory cell MC.

[0094] 1.4. Modifications

[0095] The description thus far has been directed to an example in which the ferromagnetic layer 33, which can function as a so-called storage layer, is located above the ferromagnetic layer 31, which can function as a so-called reference layer. The first embodiment is not limited to this example. That is, the magnetoresistive element VR may also include the ferromagnetic layer 31, which can function as a so-called reference layer, above the ferromagnetic layer 33, which can function as a so-called storage layer.

[0096] While several embodiments have been described above, these embodiments are provided merely as examples and are not intended to limit the scope of the invention. These new embodiments may be implemented in a variety of other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be within the scope and spirit of the invention, and are also intended to be within the scope of the invention as set forth in the claims and their equivalents.

Claims

1. A magnetic storage device comprising: The first switching element and the second switching element each include a variable resistance material; a first laminate and a second laminate, each provided on the first switching element and the second switching element, wherein the first laminate and the second laminate each include a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer; a first insulator on a side surface of the first stack; and a second insulator on the side surface of the second stack, The narrowest distance between the first insulator and the second insulator is narrower than the narrowest distance between the first switching element and the second switching element. The first insulator and the second insulator are made of a material having a lower etching rate than the first switching element and the second switching element.

2. The magnetic storage device according to claim 1, The first insulator covers the side surface of the first stack. The second insulator covers the side surface of the second stack.

3. The magnetic storage device according to claim 1, Each of the first switching element and the second switching element includes a bidirectional switching element.

4. The magnetic storage device according to claim 1, The variable resistance material includes silicon oxide containing arsenic or germanium.

5. The magnetic storage device according to claim 1, Each of the first insulator and the second insulator includes an oxide having a bond dissociation energy with respect to oxygen exceeding 500 kJ / mol.

6. The magnetic storage device according to claim 1, Each of the first insulator and the second insulator includes hafnium oxide, aluminum oxide, scandium oxide, gadolinium oxide, tantalum oxide, or yttrium oxide.

7. The magnetic storage device according to claim 1, The narrowest distance between the first insulator and the second insulator is the distance between the lower end of the first insulator and the lower end of the second insulator. The narrowest distance between the first switching element and the second switching element is a distance between a lower end of the first switching element and a lower end of the second switching element.

8. The magnetic storage device according to claim 1, The first switching element and the second switching element each include: a first conductor; the variable resistance material on the first conductor; and A second conductor is provided on the variable resistance material.

9. A magnetic storage device comprising: a switching element comprising a variable resistance material; a laminated body on the switching element, each of the laminated bodies including a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer; and Hafnium oxide, aluminum oxide, scandium oxide, gadolinium oxide, tantalum oxide, or yttrium oxide on the side surface of the stacked body.

10. The magnetic storage device according to claim 9, The hafnium oxide, aluminum oxide, scandium oxide, gadolinium oxide, tantalum oxide, or yttrium oxide covers the side surfaces of the stacked body.

11. The magnetic storage device according to claim 9, The variable resistance material includes silicon oxide containing arsenic or germanium.

12. The magnetic storage device according to claim 9, The switching element comprises: a first conductor; the variable resistance material on the first conductor; and A second conductor is provided on the variable resistance material.

13. A method for manufacturing a magnetic storage device, comprising: forming a first stacked body including a variable resistance material; forming a second stack and a third stack on the first stack, wherein each of the second stack and the third stack includes a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer; forming a first insulator on a side surface of the second stack, the first insulator comprising a first material having a lower etching rate than the first stack in a first etching process; forming a second insulator made of the first material on a side surface of the third stack; as well as The first stack is partially removed by the first etching using the second stack, the third stack, the first insulator, and the second insulator as masks.

14. The method for manufacturing a magnetic storage device according to claim 13, Forming the first stacked body includes: forming a first conductor; forming the variable resistance material on the first conductor; as well as forming a second conductor on the variable resistance material, The first material has an etching rate lower than each of the first conductor, the variable resistance material, and the second conductor in the first etching.

15. The method for manufacturing a magnetic storage device according to claim 14, Forming the variable resistance material includes: Silicon oxide containing arsenic or germanium is formed.

16. The method for manufacturing a magnetic storage device according to claim 13, The first etching comprises: The first insulator and the second insulator are left.

17. The method for manufacturing a magnetic storage device according to claim 13, The first etching includes reactive ion etching.

18. The method for manufacturing a magnetic storage device according to claim 13, Each of the first insulator and the second insulator includes an oxide having a bond dissociation energy with respect to oxygen exceeding 500 kJ / mol.

19. The method for manufacturing a magnetic storage device according to claim 13, Each of the first insulator and the second insulator includes hafnium oxide, aluminum oxide, scandium oxide, gadolinium oxide, tantalum oxide, or yttrium oxide.

20. The method for manufacturing a magnetic storage device according to claim 13, Forming the second stack and the third stack includes: forming a third ferromagnetic layer on the first stack; forming a second insulating layer above the third ferromagnetic layer; forming a fourth ferromagnetic layer on the second insulating layer; and The third ferromagnetic layer, the second insulating layer, and the fourth ferromagnetic layer are ion beam etched.

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